Semiconductor Device and Method

Abstract

In one embodiment, a method may include forming a multilayer stack over a substrate. The multilayer stack comprises alternating layers of first semiconductor layers and second semiconductor layers. The method may also include removing the first semiconductor layers. Furthermore, the method may include forming a disposable material between the second semiconductor layers. Additionally, the method may include performing a first implantation process on the disposable material and the second semiconductor layers. The method may also include forming source / drain regions adjacent to the second semiconductor layers and the disposable material. Finally, the method may include replacing the disposable material with a metal gate structure.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over the preliminary US patent application No. 63 / 645,512, filed on May 10, 2024, entitled “Sheet Formation Approach Via Implant Under DOI Scheme”, which is incorporated by reference into the present application. BACKGROUND

[0002] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers onto a semiconductor substrate, and by structuring the various material layers using lithography to form circuit components and elements.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thus enabling the integration of more components within a given area. However, reducing the minimum element dimensions introduces additional problems that need to be addressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 illustrates an example of a nanostructured field-effect transistor (nano-FET) in a three-dimensional view according to some embodiments. The Fig. 2, Fig. 3, Fig. 4, Fig. 5A, Fig. 5B, Fig. 6A, Fig. 6B, Fig. 7A, Fig. 7B, Fig. 7C, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 9C, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 10E, Fig. 11A, Fig. 11B, Fig. 11C, Fig. 11D, Fig. 12A, Fig. 12B, Fig. 12C, Fig. 12D, Fig. 12E, Fig. 12F, Fig. 13A, Fig. 13B, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 16C, Fig. 17A, Fig. 17B, Fig. 17C, Fig. 18A, Fig. 18B, Fig. 18C, Fig. 19A, Fig. 19B and Fig. Figure 19C illustrates various views of intermediate steps in the fabrication of a nano-FET transistor according to some embodiments. Fig. Figure 20 illustrates a cross-sectional view of an intermediate step in the fabrication of a nano-FET transistor according to some embodiments. The Fig. 21, Fig. 22A, Fig. 22B and Fig. Figure 22C illustrates cross-sectional views of an intermediate step in the fabrication of a nano-FET transistor according to some embodiments. Fig. Figure 23 illustrates a cross-sectional view of an intermediate step in the fabrication of a nano-FET transistor according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and also embodiments in which additional elements may be formed between the first and second elements, such that the first and second elements may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or symbols in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself dictate a relationship between the various described embodiments and / or configurations.

[0006] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein to facilitate discussion and describe the relationship of one element or feature to one or more other elements or features as illustrated in the figures. These spatially relative terms are intended to encompass, in addition to the orientation shown in the figures, various orientations of the device during its use or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0007] The present disclosure relates to a method for the formation of nano-FETs using a disposable oxide interposer (DOI) scheme. This method may involve inclined implantation or a plasma doping approach to increase the DOI oxide etch rate. By increasing the etch rate, the method can reduce the likelihood of residual oxide remaining after the DOI removal step, which is a common challenge in conventional layer-by-layer processes.

[0008] In some embodiments, the method can also mitigate the risk of over-etching the layer during the DOI oxide etching process. Over-etching can potentially lead to source / drain epitaxy damage and changes in channel strain and layer height, which is generally undesirable in the layer formation process.

[0009] Furthermore, the process allows for heavier doping in the extension region. This increased doping can potentially address the transition underlap problem and increase the silicon etch rate. Dopant concentration, energy, dosage, tilt angle, and temperature can all be adjusted to achieve the desired results, providing a level of flexibility and control not typically found in conventional methods.

[0010] The disclosure also provides several embodiments of the method, each exhibiting different doping strategies and potential results. In some embodiments, for example, the corners of the layer can be doped to prevent DOI residue, while in others, the center can be doped to prevent over-etching. Other embodiments may involve different doping sequences and the use of a hard mask for shallow trench isolation (STI) to prevent doping of the STI.

[0011] Overall, the method described in this disclosure offers a potential solution to the problem of residual material from the DOI process and provides a more efficient and precise approach to nano-FET formation using a DOI scheme.

[0012] The embodiments are described below in a specific context, namely a die featuring nano-FETs. However, various embodiments can be applied to dies featuring other transistor types (e.g., stacked transistors or the like) instead of, or in combination with, the nano-FETs.

[0013] Fig. Figure 1 illustrates an example of nano-FETs (e.g., nanowire FETs, nanosheet FETs (nano-FETs), or the like) in a three-dimensional view according to some embodiments. Fig. For clarity, certain features have been simplified and / or omitted. The nanoFETs have nanostructures 54 (e.g., nanosheets, nanowires, or the like) over the fins 66 on a substrate 50 (e.g., a semiconductor substrate), with the nanostructures 54 serving as channel regions for the nanoFETs. The nanostructure 54 can be p-nanostructures, n-nanostructures, or a combination thereof. The STI regions 68 (also referred to as STI structures or STI regions) are arranged between the adjacent fins 66, which can project over and between adjacent STI regions 68. Although the STI regions 68 are described / illustrated as separate from the substrate 50, the term "substrate" as used herein can refer to the semiconductor substrate alone or to a combination of the semiconductor substrate and the isolation regions.Although a lower section of the fins 66 is illustrated as a single, continuous material with the substrate 50, the lower section of the fins 66 and / or the substrate 50 may also consist of a single material or multiple materials. In this context, the fins 66 refer to the section extending between the adjacent STI regions 68.

[0014] The gate dielectric layers 100 are located above the upper surfaces of the fins 66 and along the upper surfaces, sidewalls, and lower surfaces of the nanostructures 54. The gate electrodes 102 are located above the gate dielectric layers 100. The epitaxial source / drain regions 92 are arranged on the fins 66 on opposite sides of the gate dielectric layers 100 and the gate electrodes 102. The source / drain region(s) 92 can refer to a source or a drain individually or collectively, depending on the context.

[0015] Fig. Figure 1 further illustrates reference cross-sections used in later figures. Cross-section AA' runs along a longitudinal axis of a gate electrode 102 and, for example, in a direction perpendicular to the current flow direction between the epitaxial source / drain regions 92 of a nanoFET. Cross-section BB' runs perpendicular to cross-section AA' and parallel to the longitudinal axis of a fin 66 of the nanoFET and, for example, in a direction of current flow between the epitaxial source / drain regions 92 of the nanoFET. Cross-section CC' runs parallel to cross-section AA' and extends through the epitaxial source / drain regions of the nanoFETs. For clarity, the following figures refer to these reference cross-sections.

[0016] Some of the embodiments described herein are related to nanoFETs fabricated using a gate-last process. Other embodiments may employ a gate-first process. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs or fin field-effect transistors (FinFETs).

[0017] The Fig. Figures 2 to 19C are cross-sectional views of intermediate stages in the fabrication of nano-FETs according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A and Fig. 19A illustrates the in Fig. 1 illustrated reference cross-section A-A'. The Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 9C, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B and Fig. 19B illustrates the in Fig. 1 illustrated reference cross-section B-B'. The Fig. 7C, Fig. 12E, Fig. 12F, Fig. 17C, Fig. 18C and Fig. 19C illustrate the in Fig. 1 illustrated reference cross-section C-C'. The Fig. 10E, Fig. 12C and Fig. Figure 12D illustrates top views of intermediate stages in the fabrication of nano-FETs according to some embodiments.

[0018] In Fig. 2. A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate and is typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of the substrate 50 may comprise silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0019] Substrate 50 features an n-region 50N and a p-region 50P. The n-region 50N can be used to form n-type devices such as NMOS transistors, like n-nanoFETs, and the p-region 50P can be used to form p-type devices such as PMOS transistors, like p-nanoFETs. The n-region 50N can be physically separated from the p-region 50P (as illustrated by the divider 20), and any number of elements (e.g., other active devices, doped regions, isolation structures, etc.) can be placed between the n-region 50N and the p-region 50P. Although one n-region 50N and one p-region 50P are illustrated, any number of n-regions 50N and p-regions 50P can be provided. The following figures describe processing steps that can be performed either in the n-regions 50N or the p-regions 50P, unless otherwise specified.

[0020] Furthermore, in Fig. 2 A multilayer stack 64 is formed on top of the substrate 50. The multilayer stack 64 has alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustrative purposes and as described in more detail below, the first semiconductor layers 51 are removed and the second semiconductor layers 53 are structured to form channel regions of nanoFETs in both the n-region 50N and the p-region 50P. However, in some embodiments, the second semiconductor layers 53 can be removed and the first semiconductor layers 51 structured to form channel regions of nanoFETs in both the n-region 50N and the p-region 50P. The channel regions can, for example, have the same material composition (e.g.,silicon or another semiconductor material) and are formed simultaneously.

[0021] In other embodiments, the first semiconductor layers 51 can be removed and the second semiconductor layers 53 structured to form channel regions of nano-FETs in the p-region 50P, and the second semiconductor layers 53 can be removed and the first semiconductor layers 51 structured to form channel regions of nano-FETs in the n-region 50N. In still further embodiments, the first semiconductor layers 51 can be removed and the second semiconductor layers 53 structured to form channel regions of nano-FETs in the n-region 50N, and the second semiconductor layers 53 can be removed and the first semiconductor layers 51 structured to form channel regions of nano-FETs in the p-region 50P. In such embodiments, the channel regions of the n-region 50N can have a different material composition than the channel regions of the p-region 50P.The first semiconductor layers 51 and the second semiconductor layers 53 can be selectively removed from each of the n-region 50N and the p-region 50P by additional masking and etching steps. The channel regions of the n-region 50N can be silicon channel regions, for example, while the channel regions of the p-region 50P can be silicon germanium channel regions.

[0022] The multilayer stack 64 is illustrated as having three layers of each of the first semiconductor layers 51 and the second semiconductor layers 53. In some embodiments, the multilayer stack 64 can have any number of first semiconductor layers 51 and second semiconductor layers 53. Each of the layers of the multilayer stack 64 can be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor deposition (VDE), molecular beam epitaxy (MBE), or the like.

[0023] In various embodiments, the first semiconductor layers 51 can be formed from a first semiconductor material, such as silicon germanium or the like, and the second semiconductor layers 53 from a second semiconductor material, such as silicon, silicon carbon, or the like. The first and second semiconductor materials can be materials with high etch selectivity towards each other. As such, the first semiconductor layers 51 of the first semiconductor material can be removed without substantially removing the second semiconductor layers 53 of the second semiconductor material, thereby enabling the structuring of the second semiconductor layers 53 to form channel regions of the nano-FETs.

[0024] With reference to Fig. 3. According to some embodiments, the fins 66 are formed in the substrate 50 and nanostructures 55 in the multilayer stack 64. In some embodiments, the nanostructures 55 and the fins 66 in the multilayer stack 64 and the substrate 50 can be formed accordingly by etching trenches 58 in the multilayer stack 64 and the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic. During the etching process, a hard mask 56 can be used to define a structure of the fins 66 and the nanostructures 55. The hard mask 56 can comprise any suitable insulating material, such as an oxide, a nitride, an oxynitride, an oxycarbonitride, or the like. In some embodiments (not illustrated separately), the hard mask 56 can be a multilayer structure.The hard mask 56 can be formed over the nanostructures 55 using an acceptable process or processes, such as thermal oxidation, physical vapor deposition (PVD), CVD, ALD, combinations thereof or the like.

[0025] The fins 66 and the nanostructures 55 can be structured by any suitable method. For example, the fins 66 and the nanostructures 55 can be structured using one or more photolithography processes, including dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-alignment processes, which makes it possible to produce structures with, for example, spacings that are smaller than what is otherwise achievable using a single direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacer elements are formed along the structured sacrificial layer using a self-alignment process.The sacrificial layer is then removed and the remaining spacer elements can then be used to structure the fins 66 and the nanostructures 55.

[0026] The formation of the nanostructures 55 by etching the multilayer stack 64 can further define first nanostructures 52A-C (collectively referred to as the first nanostructures 52) from the first semiconductor layers 51 and second nanostructures 54A-C (collectively referred to as the second nanostructures 54) from the second semiconductor layers 53. The first nanostructures 52 and the second nanostructures 54 can furthermore be collectively referred to as the nanostructures 55.

[0027] Fig. Figure 3 illustrates the fins 66, which for illustrative purposes have essentially the same widths. In some embodiments, the widths of the fins 66 in the n-region 50N may be greater or thinner than the fins 66 in the p-region 50P. While Fig. 3. As illustrated, each of the fins 66 and the nanostructures 55 has a uniform width throughout. In other embodiments, the fins 66 and / or the nanostructures 55 may have tapered sidewalls, such that the width of each of the fins 66 and / or the nanostructures 55 increases continuously towards the substrate 50. In such embodiments, each of the nanostructures 55 may have a different width and be trapezoidal.

[0028] In Fig. 4. The shallow trench insulation regions (STI regions) 68 are formed adjacent to the fins 66. The STI regions 68 can be formed by depositing an insulating material over the substrate 50, the fins 66, and the nanostructures 55, as well as between adjacent fins 66, to fill the trenches 58. The insulating material can be an oxide such as silicon dioxide, a nitride, the like, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon dioxide formed by an FCVD process. An annealing process can be performed once the insulating material has been formed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructures 55.Although the insulating material is illustrated as a single layer, several layers can be used in some embodiments. For example, in some embodiments, a lining (not shown separately) can first be formed along a surface of the substrate 50, the fins 66, and the nanostructures 55. A filler material such as that described above can then be formed over the lining.

[0029] Subsequently, a removal process is applied to the insulating material to remove excess insulating material covering the nanostructures 55. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. The planarization process exposes the nanostructures 55 so that, after completion of the planarization process, the top surfaces of the nanostructures 55 and the insulating material are at the same level.

[0030] The insulating material is then recessed to form the STI regions 68. The insulating material is recessed such that upper sections of the fins 66 protrude between adjacent STI regions 68. Furthermore, the upper surfaces of the STI regions 68 can be flat, convex, concave (such as a hollow section), or a combination thereof, as illustrated. The upper surfaces of the STI regions 68 can be formed flat, convex, and / or concave by a suitable etching process. The STI regions 68 can be recessed using an acceptable etching process, such as one that is selective for the insulating material (e.g., one that etches the insulating material faster than the material of the fins 66 and the nanostructures 55). For example, oxide removal using dilute hydrofluoric acid (dHF acid) can be employed.

[0031] Furthermore, in Fig. Four suitable wells (not illustrated separately) are formed in the fins 66 and / or the nanostructures 55. In embodiments with different well types, different implantation steps for the n-region 50N and the p-region 50P can be achieved using a photoresist or other masks (not illustrated separately). For example, a photoresist can be formed over the fins 66 and the nanostructures 55 in the n-region 50N and the p-region 50P. The photoresist is patterned to expose the p-region 50P. The photoresist can be formed using a spin-coating technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-doping is implanted in the p-region 50P, and the photoresist can act as a mask to essentially prevent n-dopers from being implanted into the n-region 50N.The n-doping agents can be phosphorus, arsenic, antimony, or the like, which are present in the region at a concentration in the range of approximately 10. 13 atoms / cm² 3 up to about 10 14 atoms / cm² 3 The photoresist is implanted. After implantation, it is removed, for example, by an acceptable ashing process.

[0032] Prior to or following the implantation of the p-region 50P, a photoresist or other mask (not shown separately) is formed in the p-region 50P and the n-region 50N over the fins 66 and the nanostructures 55. The photoresist is patterned to expose the n-region 50N. The photoresist can be formed using a spin-casting technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-doping can be implanted in the n-region 50N, and the photoresist can act as a mask to essentially prevent p-dopers from being implanted into the p-region 50P. The p-dopers can be boron, boron fluoride, indium, or the like, present in the region at a concentration in the range of approximately 10 13 atoms / cm² 3 up to about 10 14 atoms / cm² 3It can be implanted. After implantation, the photoresist can be removed, for example, by an acceptable ashing process.

[0033] After implantation of the n-region 50N and the p-region 50P, annealing can be performed to repair implantation damage and activate the implanted p- and / or n-doping agents. In some embodiments, the grown materials can be doped in situ by epitaxial fins during growth, which may eliminate the need for implantation, although in-situ and implantation doping can be used together.

[0034] In the Fig. 5A and Fig. In 5B, dummy gates are formed over and along the sidewalls of the nanostructures 55 and the fin 66. To form the dummy gates, a dummy dielectric layer is first formed on the fins 66 and / or the nanostructures 55. The dummy dielectric layer can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer is formed over the dummy dielectric layer, and a mask layer is formed over the dummy gate layer. The dummy gate layer can be deposited over the dummy dielectric layer and then planarized, for example, by a CMP. The mask layer can be deposited over the dummy gate layer.The dummy gate layer can be a conductive or non-conductive material and can be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metal oxides, and metals. The dummy gate layer can be deposited by physical vapor deposition (PVD), continuous vapor deposition (CVD), sputtering, or other techniques for depositing the selected material. Alternatively, the dummy gate layer can be made from materials that exhibit high etch selectivity for etching insulating regions. For example, the dummy gate layer can be silicon nitride, silicon oxynitride, or similar materials.

[0035] Subsequently, the mask layer can be structured using acceptable photolithography and etching techniques to form masks 78. The structure of the masks 78 can then be transferred to the dummy gate layer and the dummy dielectric layer to form the dummy gates 76 and dummy gate dielectrics 70, respectively. The dummy gates 76 cover corresponding channel regions of the fins 66. The structure of the masks 78 can be used to physically separate each dummy gate 76 from adjacent dummy gates 76. The dummy gates 76 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the corresponding fins 66. It is noted that the dummy gate dielectrics 70 are shown, for illustrative purposes, as covering only the fins 66 and the nanostructures 55.In some embodiments, the dummy gate dielectrics 70 can be deposited such that the dummy gate dielectrics 70 cover the STI regions 68, so that the dummy gate dielectrics 70 extend between the dummy gates 76 and the STI regions 68.

[0036] In the Fig. 6A and Fig. 6B, gate spacer elements 81 are formed over the nanostructures 55 and the STI regions 68, on exposed sidewalls of the masks 78 (if present), the dummy gates 76, and the dummy gate dielectrics 70. The spacer elements 81 can be formed by conformal forming of one or more dielectric materials and subsequent etching of the dielectric material(s). Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which can be formed by a deposition process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. Other insulating materials formed by any acceptable process may be used. Any acceptable etching process, such as dry etching, wet etching, or a combination thereof, may be performed to pattern the dielectric material(s).The etching process can be anisotropic. When the dielectric material(s) are etched, sections remain on the sidewalls of the dummy gates 76 (and thus form the gate spacer elements 81). As described in more detail below, when the dielectric material(s) are etched, sections can also remain on the sidewalls of the fins 66 and / or the nanostructures 55 (and thus form the fin spacer elements 83, see Figure 1). Fig. 7C). After etching, the fin spacer elements 83 and / or the gate spacer elements 81 can have straight side walls (as illustrated) or curved side walls (not illustrated separately).

[0037] Furthermore, implantations for lightly doped source / drain regions (LDD regions) (not illustrated separately) can be performed. The LDD implantations can be performed before the gate spacer elements 81 are formed. In embodiments with different device types, similar to the implantations for the previously described wells, a mask such as a photoresist can be formed over the n-region 50N while the p-region 50P is exposed, and suitable types of dopants (e.g., type p) can be implanted into the fins 66 and the nanostructures 55 exposed in the p-region 50P. The mask can then be removed. Subsequently, a mask such as a photoresist can be formed over the p-region 50P while the n-region 50N is exposed, and suitable dopants (e.g., type n) can be implanted into the fins 66 and the nanostructures 55 exposed in the n-region 50N.The mask can then be removed. The n-dopers can be any of the previously described n-dopers, and the p-dopers can be any of the previously described p-dopers. The lightly doped source / drain regions can have an impurity concentration in the range of 10. 15 atoms / cm² 3 up to 10 19 atoms / cm² 3 They exhibit certain characteristics. Tempering can be used to repair implant damage and to activate the implanted dopants.

[0038] It should be noted that the preceding disclosure generally describes a process for forming spacer elements and LDD regions. However, other processes and sequences can also be used. For example, fewer or additional spacer elements can be used, a different sequence of steps can be used, additional spacer elements can be formed and removed, and / or the like. Furthermore, the n- and p-devices can be formed using different structures and steps.

[0039] In the Fig. In some embodiments, as described in 7A to 7C, the first recesses 86 are formed in the fins 66, the nanostructures 55, and the substrate 50. Epitaxial source / drain regions are subsequently formed in the first recesses 86. The first recesses 86 can extend through the first nanostructures 52 and the second nanostructures 54 and into the substrate 50. As shown in Fig. As illustrated in Figure 7C, the upper surfaces of the STI regions 68 can be at the same level as the lower surfaces of the first recesses 86. In other embodiments, the fins 66 can be etched such that the lower surfaces of the first recesses 86 are positioned above or below the upper surfaces of the STI regions 68. The first recesses 86 can be formed by etching the fins 66, the nanostructures 55, and the substrate 50 using anisotropic etching processes such as RIE, NBE, or the like. The gate spacer elements 81, the fin spacer elements 83, and the masks 78 mask sections of the fins 66, the nanostructures 55, and the substrate 50 during the etching processes used to form the first recesses 86. A single etching process or multiple etching processes can be used to etch each layer of the nanostructures 55 and / or the fins 66.Time-controlled etching processes can be used to stop the etching of the first recesses 86 after the first recesses 86 have reached a desired depth.

[0040] In the Fig. In steps 8A to 9C, the first nanostructures 52 are replaced by a sacrificial material 72 (also referred to as a disposable interposer (DOI) 72). Replacing the first nanostructures 52 can involve etching them away using a suitable etching process, such as an isotropic etching process, carried out through the first recesses 86, as described in the Fig. Figures 8A to 8B illustrate this. The etching process can be selective for the material of the first nanostructures 52 and remove the first nanostructures 52 without substantially removing the second nanostructures 54 or the fins 66. In an embodiment where the first nanostructures 52 comprise, for example, SiGe and the second nanostructures 54 comprise, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to remove the first nanostructures 52.

[0041] Subsequently, a sacrificial material layer 71 is deposited in the first recesses 86 and in the spaces where the first nanostructures 52 were removed. The sacrificial material layer 71 can be deposited by a conformal deposition process, such as CVD, ALD, or the like. The sacrificial material layer 71 can comprise an insulating material, such as silicon oxide (e.g., SiO2), silicon oxynitride, aluminum oxide, or the like, which can be selectively etched by the second nanostructures 54.

[0042] In the Fig. In steps 9A to 9C, the sacrificial layer 71 can then be etched to form the sacrificial material 72. The etching can be isotropic or anisotropic. The sacrificial layer can, for example, be etched by a wet etching process using dilute HF or the like as an etchant. In some embodiments, the etching is carried out until the sidewalls of the sacrificial material 72 are recessed over the sidewalls of the nanostructures 54. Although the sidewalls of the sacrificial material 72 are recessed over the sidewalls of the nanostructures 54, Fig. 9B and Fig. As illustrated in 9C, the side walls can be concave or convex (see e.g. Fig. 11C).

[0043] The Fig. 9B and Fig. Figure 9C illustrates similar cross-sectional views according to different embodiments. Fig. Figure 9B illustrates a configuration of the structure similar to the previous figures and shows the nanostructures 54, gate structures 76 / 78, spacer elements 81 and the sacrificial material 72 with planar surfaces and right-angled corners. Fig. In contrast, 9C illustrates a configuration of the structure showing the nanostructures 54, the gate structures 76 / 78, the spacer elements 81 and the sacrificial material 72 with non-planar surfaces and rounded corners. Fig. Figure 9C illustrates, for example, the second nanostructures 54, which are thicker in the middle and thinner towards the edges, with rounded corners in the cross-sectional view. Furthermore, it illustrates Fig. 9C, that the fins / substrate 66 / 50, which are exposed on the underside of the recesses 86, have a depression in the central region of the recess 86. Furthermore, the gate spacer elements 81 are in Fig. 9C illustrates that they have multiple layers of spacer elements. Although most of the figures in this revelation illustrate the structures with flat surfaces and right-angled corners, the scope of the revelation is not limited to this, since this revelation also considers the structures with non-flat surfaces and rounded corners and profiles.

[0044] Replacing the first nanostructures 52 with the sacrificial material 72 can offer advantages. In subsequent source / drain formation steps, for example, one or more high-temperature processes can be performed to activate the dopants in the source / drain regions. If the material of the first nanostructures 52 (e.g., SiGe) is exposed to high temperatures, germanium mixing and increased roughness at interfaces between the nanostructures 52 and 54 can occur. Such fabrication defects can impair the performance of the resulting transistor devices. For example, if germanium diffuses into the second nanostructures 74, germanium residues can remain in the channel regions of the resulting transistor devices, negatively affecting the performance of the channel regions. Replacing the first nanostructures 52 with an insulating material before the high-temperature processes (e.g., SiGe) can prevent this.Source / drain tempering can reduce manufacturing defects and improve device performance (e.g., increased current control, reduced capacitance, and improved short-channel effect).

[0045] The Fig. Figures 10A-D illustrate an implantation process 88 that forms doped regions 89 in the second nanostructures 54 and the sacrificial material 72 in the first recesses 86 to modify the etch rate of the structure. Similar to the preceding Fig. 9C illustrate the Fig. 10C and Fig. 10D embodiments of the structure with non-planar surfaces and rounded corners. The implantation process 88 is designed to selectively modify the etch rate or etch selectivity of the second nanostructures 54 relative to the sacrificial material 72. This process can involve introducing implantation types into the second nanostructures 54 and the sacrificial material 72 to create different etch characteristics, which facilitates the subsequent removal of the sacrificial material 72 without adversely affecting the second nanostructures 54. The implantation process 88 can be performed using an inclined implantation technique in which the implantation angle is controlled to optimize the distribution of the implantation types within the target regions. In some embodiments, a mask 91 (see, e.g., Figure 1) is used. Fig. 10D) formed to cover one of the regions (either 50P or 50N) while the implantation process 88 is performed on the other region. As in Fig. As illustrated in Figure 10C, the doped regions 89 may not be continuous across the underside of the recesses 86 due to the non-planar surface of the fins / substrate 66 / 50 on the underside of the recesses 86 and the inclination angle of the implantation process 88. In some embodiments, the doped regions 89 are not formed in the depression on the underside of the recesses 86.

[0046] In some embodiments, n-doping agents, such as phosphorus, arsenic, or antimony, or other types, such as germanium, xenon, argon, silicon, or nitrogen, can be used in the implantation process to improve the etch rate of the sacrificial material 72. Alternatively, p-doping agents, such as boron, boron fluoride, indium, or other types such as carbon, can be used to slow down the etch rate and thereby prevent over-etching of the sacrificial material 72. The choice of implantation method may depend on the desired outcome of the etching process and the materials involved.

[0047] The implantation process 88 can be characterized by a number of parameters that can be adjusted to achieve the desired modification of the etch rate or etch selectivity. The implantation inclination angle can range from 0 to 60 degrees, allowing for precise control of the implantation profile. The implantation energy can range from 1 keV to 50 keV, which, together with the dose in the range of 5E 13 up to 1E 16 atoms / cm² 2 The depth and concentration of the implanted species are determined. The temperature during the implantation process can be maintained in a range from -100 °C to 500 °C to accommodate different material properties and implantation outcomes.

[0048] In some embodiments, the implantation process 88 can generate an implantation-induced damage layer on the sacrificial material 72, which can improve the efficiency of cleaning and etching during these processes. This improvement can lead to increased etch selectivity, enabling the sacrificial material 72 to be completely removed without leaving residues and without damaging the source / drain regions 92. As a result, the interface of the second nanostructures 54 can be smoother, which promotes improved channel mobility in the semiconductor device.

[0049] By carefully selecting and controlling these parameters, the implantation process 88 can be tailored to modify the etch rate or etch selectivity of the second nanostructures 54 and the sacrificial material 72 in a controlled manner. This enables a more efficient and precise etching process, reducing the likelihood of residual material and improving the overall quality of the semiconductor device.

[0050] The doped regions 89 in the second nanostructures 54 can be attributed to a concentration in the range of approximately 1E 18 up to 1E 19 atoms / cm² 3The doping concentration helps to control the shape of the second nanostructures during the subsequent etching process, which removes the sacrificial material 72. Additionally, the abruptness of the doping profile within this concentration range can be controlled to lie within approximately 1 to 5 nm / decade, indicating a sharp transition between doped and undoped regions.

[0051] The doped regions 89 in the sacrificial material 72 can be compared to the second nanostructures 54 with a range of approximately 5E 17 up to 5E 18 atoms / cm² 3The dopant is applied at a lower concentration. This concentration is selected to optimize etch selectivity during the removal of the sacrificial material 72 and to ensure that the second nanostructures 54 remain intact and undamaged. The abruptness of the dopant profile in the sacrificial material 72 is also controlled to facilitate a controlled etching process, which contributes to the overall efficiency of the device fabrication.

[0052] In some embodiments, the upper second nanostructure 54C has a higher dopant concentration than the middle and lower second nanostructures 54B and 54A, because during the implantation process 88, the spacer elements 81 and overlying structures block some of the dopants. As shown in the Fig. 10B and Fig. As can be seen in Figure 10C, the upper second nanostructure 54C has a doped region 89 formed on two surfaces (e.g., side surfaces and bottom surfaces), while the middle and lower second nanostructures 54B and 54A have doped regions 89 formed on three surfaces (e.g., upper, side, and bottom surfaces).

[0053] Adjusting the dopant concentrations and profile abruptness in both the second nanostructures 54 and the sacrificial material 72 improves the etching process and ensures the formation of a semiconductor device with enhanced channel mobility and reduced electrical resistance. This approach allows for the precise tailoring of the semiconductor device properties to specific performance requirements.

[0054] Fig. Figure 10E illustrates a top view of a second nanostructure 54 with doped regions 89 within the second nanostructure 54 according to some embodiments. The doped regions 89 are configured to modify the etch rate of the second nanostructures 54, which is a strategic step in the fabrication process. The implantation process 88 introduces dopants into the second nanostructures 54 in a manner that produces a different etch characteristic between the second nanostructures 54 and the sacrificial material 72. This different etch characteristic is advantageous for the subsequent removal of the sacrificial material 72, as it allows for the selective etching of the sacrificial material 72 without adversely affecting the second nanostructures 54.

[0055] The configuration of the doped regions 89 is such that it can be tailored to the specific requirements of the semiconductor device to be manufactured. By adjusting the parameters of the implantation process 88, such as the inclination angle, energy, dosage, and temperature, the etch rate or etch selectivity of the second nanostructures 54 can be controlled.

[0056] Although the doped regions 89 are illustrated with clearly defined boundaries in the following figures, the boundaries of the doped regions 89 are more fluid in some embodiments and may shift or change due to the distribution of the dopants as a result of further processing, such as thermal processes, etching processes or the like.

[0057] In the Fig. 11A and Fig. In section 11B, the inner spacer elements 90 are formed in the first recesses 86 on the side walls of the sacrificial material 72 and / or the doped regions 89. The inner spacer elements 90 act as insulating elements between subsequently formed source / drain regions and a gate structure. As described in more detail below, source / drain regions are formed in the first recesses 86, while the sacrificial material 72 is replaced by corresponding gate structures. The inner spacer elements 90 can also be used to prevent damage to subsequently formed source / drain regions by subsequent etching processes, such as those used to form gate structures.

[0058] The inner spacer elements 90 can be formed by depositing an inner spacer element layer (not illustrated separately) over the area in the Fig. 10A and Fig. The structures illustrated in Figure 10B can be formed. The inner spacer element layer can be deposited by a conformal deposition process, such as CVD, ALD, or the like. The inner spacer element layer can be made of a material such as silicon nitride or silicon oxynitride, although any suitable material, such as materials with a low dielectric constant (low-k materials) with a k-value of less than approximately 3.5, can be used. The inner spacer element layer can then be anisotropically etched to form the inner spacer elements shown in Figure 90. The inner spacer element layer can be etched by an anisotropic etching process, such as RIE, NBE, or the like.

[0059] Although the outer sidewalls of the inner spacer elements 90 are illustrated to be flush with the sidewalls of the second nanostructures 54, the outer sidewalls of the inner spacer elements 90 may extend beyond the sidewalls of the second nanostructures 54 or be recessed from them (see e.g. Fig. 11C). Although the outer side walls of the inner spacer elements are 90° in Fig. As illustrated in Figure 11B, the outer side walls of the inner spacer elements 90 can be concave or convex. Fig. Figure 11C illustrates, for example, an embodiment in which the side walls of the sacrificial material 72 are concave, the outer side walls of the inner spacer elements 90 are concave, and the inner spacer elements 90 are recessed from the side walls of the second nanostructures 54. Other configurations are also possible. Fig. Figure 11D illustrates, for example, an embodiment in which the side walls of the sacrificial material 72 are concave, the outer side walls of the inner spacer elements 90 are straight, and the inner spacer elements 90 are flush with the side walls of the second nanostructures 54.

[0060] In the Fig. Epitaxial source / drain regions 92 are formed in the first recesses 86 at 12A to 12F. In some embodiments, the source / drain regions 92 can exert a stress on the second nanostructures 54 in the n-region 50N and / or on the first nanostructures 52 in the p-region 50P, thereby improving performance. As shown in Fig. As illustrated in Figure 12B, the epitaxial source / drain regions 92 in the first recesses 86 are formed such that each dummy gate 76 is arranged between corresponding adjacent pairs of epitaxial source / drain regions 92. In some embodiments, the gate spacer elements 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76, and the inner spacer elements 90 are used to separate the epitaxial source / drain regions 92 from the sacrificial material 72 by a suitable lateral distance, so that the epitaxial source / drain regions 92 are not short-circuited with the subsequently formed gates of the resulting nano-FETs.

[0061] The epitaxial source / drain regions 92 in the n-region 50N, such as the NMOS region, can be formed by masking the p-region 50P, such as the PMOS region. Subsequently, the epitaxial source / drain regions 92 are epitaxially grown in the first recesses 86 in the n-region 50N. The epitaxial source / drain regions 92 can consist of any suitable material appropriate for n-nanoFETs. For example, if the second nanostructures 54 are made of silicon, the epitaxial source / drain regions 92 in the n-region 50N can consist of materials that exert a tensile stress on the second nanostructures 54, such as Si, SiP, SiAs, SiP+SiAs / SiSb, SiSb, SiP+SiAs+SiSb, or the like.

[0062] The epitaxial source / drain regions 92 in the p-region 50P, such as the PMOS region, can be formed by masking the n-region 50N, such as the NMOS region. Subsequently, the epitaxial source / drain regions 92 are epitaxially grown in the first recesses 86 in the p-region 50P. The epitaxial source / drain regions 92 can consist of any suitable material appropriate for p-nanoFETs. For example, if the second nanostructures 54 are made of silicon, the epitaxial source / drain regions 92 in the p-region 50P can consist of materials that exert a compressive stress on the second nanostructures 54, such as SiGe, Ge, GeSn, SiB, SiGe:B, SiGe:Ga, or the like.

[0063] The epitaxial source / drain regions 92, the second nanostructures 54, and / or the substrate 50 can be implanted with dopants to form source / drain regions similar to the previously described method for forming lightly doped source / drain regions, followed by annealing. The source / drain regions can have an impurity concentration of approximately 1 × 10 19 atoms / cm² 3 and approximately 1x10 21 atoms / cm² 3 exhibit. The n- and / or p-dopers for source / drain regions can be any of the dopers described above. In some embodiments, the epitaxial source / drain regions 92 can be doped in situ during growth.

[0064] Fig. Figure 12C illustrates a top view of a second nanostructure 54 and epitaxial source / drain regions 92 according to some embodiments. In some embodiments, the wafer is tilted during the implantation process 88, thereby enabling selective doping of the corners of the second nanostructure 54, which can be advantageous to prevent the presence of sacrificial material 72 during subsequent removal. In some embodiments, not only the corners (see, e.g., Figure 12C) can be selectively doped. Fig. 10E), but the entire sides (including the central regions in addition to the corners) of the second nanostructure 54 are doped, which can be advantageous to prevent over-etching. This selective doping results in a tailored dopant distribution that can be used to modify the etch rate of the second nanostructure 54, thereby improving the etching process and the overall device performance. For example, by controlling the etch rate in this way, the rounding of the sides of the second nanostructure 54 can be configured. Fig. Figure 12C illustrates the rounding of the sides of the second nanostructure 54 by a distance D1, which represents the difference between the innermost and outermost points of the side of the second nanostructure 54 in this top view. In some embodiments, the distance D1 in this configuration is less than 1 nm. This configuration is advantageous for achieving a uniform interface between the second nanostructure 54 and the epitaxial source / drain regions 92, which is desirable for improved transition uniformity and device performance.

[0065] Fig. Figure 12D illustrates a top view of a second nanostructure 54 and the epitaxial source / drain regions 92 according to some embodiments. In this embodiment, the wafer is not tilted during the implantation process 88, resulting in a uniform dopant distribution across the entire sides (e.g., from the top corner to the bottom corner on both sides) of the second nanostructure 54. Due to the faster etch rate in the center compared to the edge, the uniform distribution of the dopants leads to a curved profile between the second nanostructure 54 and the epitaxial source / drain regions 92. Fig. Figure 12D illustrates the rounding of the sides of the second nanostructure 54 by a distance D2, which represents the difference between the innermost and outermost points of the side of the second nanostructure 54 in this top view. In some embodiments, the distance D2 in this configuration is 3 nm or more.

[0066] The use of different implantation methods not only improves the etch rates for the sacrificial material 72 and the second nanostructures 54, but also deepens the transition. The dopant concentration in the sacrificial material 72 is lower relative to that in the source / drain regions 92. During the formation of the source / drain regions 92, defects can be introduced into these regions by the implantation process, which can promote the diffusion of dopants from the source / drain regions 92 into the adjacent channel regions. This diffusion of dopants can result in a reduction of the electrical resistance of the channels of the subsequently formed transistor structure.

[0067] In the inclined implantation embodiment, the distribution of the doped regions 89 can be selectively controlled. For example, the STI regions 68, the fins 66, and the lower sections of the second nanostructures 54, as well as the sacrificial material 72, can remain undoped, while upper sections of the structure are doped. Consequently, different dopant concentrations can be achieved in different layers of the second nanostructures 54. In a configuration with three layers of second nanostructures 54, for example, dopants can be introduced into all three layers in an initial implantation process 88, while a subsequent implantation process 88 targets only the upper two layers. Various other doping sequences are also possible. In addition, the gate spacer elements 81, located next to the dummy gates 76, can be doped.This doping may reduce the dielectric constant (k-value) of the gate spacer elements 81, which may also lead to a reduction in electrical leakage.

[0068] In the plasma doping configuration, the STI regions 68, the fins 66, the spacer elements 81 adjacent to the dummy gates 76, the second nanostructures 54, and the sacrificial material 72 are all doped during the implantation process 88. If the doping reaches the lower portion of the fins 66, it can influence the growth of the source / drain regions 92 from bottom to top. The introduction of dopants can, for example, potentially damage the crystal lattice, which could impair the quality of the epitaxial source / drain regions 92.

[0069] Additionally, by doping the STI regions 68, the etch rate of the STI regions 68 can be modulated during subsequent etching processes (see e.g. Fig. 20). Consequently, this allows the adjustment of the height of the upper surface of the STI regions 68, as described with reference to Fig. 20 is described in more detail. To prevent doping of the STI regions 68, as described in the Fig. Figures 21 to 22C show that an optional hard mask structure is used.

[0070] The doped regions 89, formed by the implantation process 88, particularly in the source / drain extension region adjacent to the second nanostructures 54, can improve the etch rate of these structures. This improvement facilitates the modulation of the convex pressure magnitude of the source / drain regions 92 into channel regions (e.g., the second nanostructures 54), a technique used to control short-channel effects in semiconductor devices. By adjusting the dopant distribution, the shape of the interface between the second nanostructures 54 and the source / drain regions 92 can be fine-tuned, contributing to improved device performance.

[0071] As a result of the epitaxial processes used to form the epitaxial source / drain regions 92 in the n-region 50N and the p-region 50P, the upper surfaces of the epitaxial source / drain regions 92 exhibit facets that extend laterally outward beyond the sidewalls of the nanostructures 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of an identical nanoFET to merge, as described in Fig. Figure 12E illustrates this. In other embodiments, adjacent epitaxial source / drain regions 92 remain separate after the epitaxial process is complete, as shown by Fig. 12F is illustrated. In the Fig. 12E and Fig. In the embodiments illustrated in Figure 12F, the fin spacer elements 83 can be formed on the upper surfaces of the STI regions 68, thereby blocking epitaxial growth. In some other embodiments, the fin spacer elements 83 can cover sections of the sidewalls of the nanostructures 55, further blocking epitaxial growth. In some other embodiments, the spacer element etching process used to form the gate spacer elements 83 can be modified to remove the spacer element material, allowing the epitaxially grown region to extend to the surface of the STI regions 68.

[0072] The epitaxial source / drain regions 92 can comprise one or more semiconductor material layers. For example, the epitaxial source / drain regions 92 can comprise a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers can be used for the epitaxial source / drain regions 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C can be formed from different semiconductor materials and doped with different dopant concentrations. In some embodiments, the first semiconductor material layer 92A can have a dopant concentration that is lower than that of the second semiconductor material layer 92B and higher than that of the third semiconductor material layer 92C.In embodiments in which the epitaxial source / drain regions 92 have three semiconductor material layers, the first semiconductor material layer 92A can be deposited, the second semiconductor material layer 92B can be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C can be deposited over the second semiconductor material layer 92B.

[0073] In the Fig. 13A and Fig. 13B will have a first interlayer dielectric (ILD) 96 accordingly over the one in the Fig. 18A and Fig. The structure illustrated in Figure 19B is deposited. The first ILD 96 can consist of a dielectric material and can be deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials can be phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 94 is arranged between the first ILD 96 and the epitaxial source / drain regions 92, the masks 78, and the gate spacer elements 81. The CESL 94 can be a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which has a different etch rate than the material of the overlying first ILD 96.

[0074] After the first ILD 96 has been deposited, a planarization process, such as a CMP, can be performed to align the top surface of the first ILD 96 with the top surfaces of the dummy gates 76 or the masks 78. The planarization process can also remove the masks 78 on the dummy gates 76 and sections of the gate spacer elements 81 along the side walls of the masks 78. After the planarization process, the top surfaces of the dummy gates 76, the gate spacer elements 81, and the first ILD 96 are at the same level within the process variations. Accordingly, the top surfaces of the dummy gates 76 are exposed through the first ILD 96. In some embodiments, the masks 78 can remain, in which case the planarization process levels the top surface of the first ILD 96 with the top surfaces of the masks 78 and the gate spacer elements 81.

[0075] In the Fig. 14A and Fig. In 14B, the dummy gates 76 and the masks 78, if present, are removed in one or more etching steps, forming the second recesses 98. Sections of the dummy gate dielectrics 70 and sections of the protective lining 118 in the second recesses 98 can also be removed. In some embodiments, the dummy gates 76 and the dummy gate dielectrics 70 are removed by an anisotropic dry etching process. The etching process can, for example, include a dry etching process using reactive gas(es) that selectively etch the dummy gates 76 at a faster rate than the first ILD 96 or the gate spacer elements 81. Each second recess 98 exposes and / or lies above sections of nanostructures 55 that function as channel regions in subsequently completed nanoFETs.Sections of the nanostructures 55, which function as channel regions, are arranged between adjacent pairs of the epitaxial source / drain regions 92. During removal, the dummy gate dielectrics 70 can be used as etch stop layers when the dummy gates 76 are etched. The dummy gate dielectrics 70 can then be removed after the dummy gates 76 have been removed.

[0076] In the Fig. 15A and Fig. In 15B, the sacrificial material 72 is removed, which enlarges the second recesses 98. In some embodiments, removing the sacrificial material 72 also removes portions of the doped regions 89 in or adjacent to the sacrificial material. Removing the sacrificial material 72 may involve an isotropic etching process, such as wet etching using dilute hydrofluoric acid (HF) or chemical oxide removal dry etching (COR dry etching). These etchants are selective for the materials of the sacrificial material 72, ensuring that the second nanostructures 54 remain relatively unetched compared to the sacrificial material 72. The sacrificial material 72 may be completely removed, or a residue of the sacrificial material 72 may remain on sidewalls of the inner spacer elements in the second recesses 98 (see, for example, Figure 15B). Fig. 16C).

[0077] In some embodiments, the STI regions 68 can be etched while the sacrificial material 72 is removed, but the overall material loss in the STI regions 68 can be reduced by controlling the etching parameters (e.g., timing) during the removal of the sacrificial material 72. In other embodiments, the STI regions 68 can form a hard mask (see, e.g., the Fig. 21 to 22C) on an upper surface to protect the underlying STI regions 68 from etching while the sacrificial material 72 is structured and removed. In such embodiments, the hard mask may, for example, comprise a nitride.

[0078] The residual doping substances from the implantation process 88, which are present after the etching process (e.g., after etching the Fig. The remaining 15A-B molecules in the second nanostructures 54 can be used to reduce the electrical resistance of the channel. This resistance reduction has a positive effect on the overall electrical performance of the device, as it can lead to increased current flow and improved switching characteristics of the transistors. Precise control of the dopant concentration and distribution is therefore a valuable tool for optimizing semiconductor device fabrication.

[0079] In the Fig. In sections 16A to 16C, the gate dielectric layers 100 and the gate electrodes 102 for exchange gates are formed. The gate dielectric layers 100 are conformally deposited in the second recesses 98. The gate dielectric layers 100 can be formed on the upper surfaces and sidewalls of the substrate 50 and on the upper surfaces, sidewalls, and lower surfaces of the second nanostructures 54. The gate dielectric layers 100 can also be deposited on the upper surfaces of the first ILD 96, the CESL 94, the spacer elements 81, and the STI regions 68.

[0080] According to some embodiments, the gate dielectric layers 100 have one or more dielectric layers, such as an oxide, a metal oxide, the like, or combinations thereof. In some embodiments, the gate dielectrics may, for example, have a silicon oxide layer and a metal oxide layer over the silicon oxide layer. In some embodiments, the gate dielectric layers 100 have a high-k dielectric material, and in these embodiments, the gate dielectric layers 100 may have a k-value greater than approximately 7.0 and may comprise a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The structure of the gate dielectric layers 100 may be the same or different in the n-region 50N and the p-region 50P.The formation processes of the gate dielectric layers 100 can include molecular beam deposition (MBD), ALD, PECVD and the like.

[0081] The gate electrodes 102 are deposited accordingly over the gate dielectric layers 100 and fill the remaining sections of the second recesses 98. The gate electrodes 102 can comprise a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Although in the Fig. As illustrated in Figures 16A to 16C, single-layer gate electrodes 102 can have any number of lining layers, any number of exit working layers, and a filler material. Any combination of the layers comprising the gate electrodes 102 can be deposited in the n-region 50N between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50, and can be deposited in the p-region 50P between adjacent first nanostructures 52.

[0082] The formation of the gate dielectric layers 100 in the n-region 50N and the p-region 50P can occur simultaneously, so that the gate dielectric layers 100 in each region are formed from the same materials, and the formation of the gate electrodes 102 can also occur simultaneously, so that the gate electrodes 102 in each region are formed from the same materials. In some embodiments, the gate dielectric layers 100 in each region can be formed by different processes, so that the gate dielectric layers 100 can be made of different materials and / or have a different number of layers, and / or the gate electrodes 102 in each region can be formed by different processes, so that the gate electrodes 102 can be made of different materials and / or have a different number of layers.Various masking steps can be used to mask and expose suitable regions when using different processes.

[0083] After filling the second recesses 98, a planarization process such as a CMP can be performed to remove the excess sections of the gate dielectric layers 100 and the material of the gate electrodes 102, with the excess sections located above the top surface of the first ILD 96. The remaining material sections of the gate electrodes 102 and the gate dielectric layers 100 therefore form exchange gate structures of the resulting nano-FETs. The gate electrodes 102 and the gate dielectric layers 100 can be collectively referred to as the “gate structures”.

[0084] Fig. 16C illustrates a detailed view of various elements of Fig. 16B including the epitaxial source / drain regions 92, the gate dielectric layers 100, the gate electrodes 102, the second nanostructures 54 and the internal spacer elements 90. In some embodiments, which are characterized by Fig. As illustrated in Figure 15C, a residue of the sacrificial material 72 may remain on the inner spacer elements 90, for example, between the inner spacer elements 90 and the gate dielectric layers 100 / gate electrodes 102. For example, the sacrificial material 72 may not be completely removed, and the gate dielectric layers 100 may form on the remaining sacrificial material 72. Since the sacrificial material 72 is an insulating material (e.g., silicon dioxide), the remaining residue may not significantly affect the electrical performance of the resulting device.

[0085] In the Fig. In sections 17A to 17C, the gate structure (including the gate dielectric layers 100 and the corresponding overlying gate electrodes 102) is recessed, forming a cavity directly above the gate structure and between opposing sections of the gate spacer elements 81. A gate mask 104, comprising one or more layers of dielectric material such as silicon nitride, silicon oxynitride, or the like, is filled into the cavity, followed by a planarization process to remove excess sections of the dielectric material extending over the first ILD 96. Subsequently formed gate contacts (such as the gate contacts 114, described below with reference to the Fig. 19A to 19C) penetrate the gate mask 104 so that they contact the upper surface of the recessed gate electrodes 102.

[0086] As in the Fig. As further illustrated in Figures 17A to 17C, a second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In other embodiments, the second ILD 106 is formed from a dielectric, such as PSG, BSG, BPSG, USG, or the like, and can be deposited by any suitable method, such as CVD, PECVD, or the like.

[0087] In the Fig. In processes 18A to 18C, the second ILD 106, the first ILD 96, the CESL 94, and the gate masks 104 are etched to form third recesses 108 that expose the surfaces of the epitaxial source / drain regions 92 and / or the gate structure. The third recesses 108 can be formed by etching using an anisotropic etching process, such as RIE, NBE, or the like. In some embodiments, the third recesses 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; they can be etched through the gate masks 104 using a second etching process; and can then be etched through the CESL 94 in a third etching process. A mask, such as a photoresist, can be formed and structured over the second ILD 106 to protect sections of the second ILD 106 before the first etching process and the second etching process.In some embodiments, the etching process can over-etch, causing the third recesses 108 to extend into the epitaxial source / drain regions 92 and / or the gate structure, and a bottom surface of the third recesses 108 may be at the same level (e.g., at the same level or at the same distance from the substrate) or deeper (e.g., closer to the substrate) than the epitaxial source / drain regions 92 and / or the gate structure. Although the . Fig. 18B illustrates the third recesses 108 as exposing the epitaxial source / drain regions 92 and the gate structure in the same cross-section. In different embodiments, the epitaxial source / drain regions 92 and the gate structure can be exposed in different cross-sections, thereby reducing the risk of short-circuiting subsequently formed contacts.

[0088] After the third recesses 108 have been formed, the silicide regions 110 are formed over the epitaxial source / drain regions 92. In some embodiments, the silicide regions 110 are formed by first depositing a metal (not shown) capable of reacting with the semiconductor materials of the underlying epitaxial source / drain regions 92 (e.g., silicon, silicon germanium, germanium) to form silicide or germanide regions, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other high-melting-point metals, rare-earth metals, or their alloys, over the exposed portions of the epitaxial source / drain regions 92, and then performing an annealing process to form the silicide regions 110. The unreacted portions of the deposited metal are then removed, for example, by an etching process.Although silicide regions 110 are referred to as silicide regions, they can also be germanide regions or silicon germanide regions (e.g., regions containing both silicide and germanide). In one embodiment, the silicide region 110 contains TiSi and has a thickness in the range of approximately 2 nm to approximately 10 nm.

[0089] Next, in the Fig. In 19A to 19C, contacts 112 and 114 (which can also be referred to as contact plugs) are formed in the third recesses 108. Contacts 112 and 114 can each have one or more layers, such as barrier layers, diffusion layers, and filler materials. For example, in some embodiments, contacts 112 and 114 each have a barrier layer and a conductive material and are electrically coupled to the underlying conductive element (e.g., the gate electrode 102 and / or silicide region 110 in the illustrative embodiment). Contacts 114 are electrically coupled to the gate electrode 102 and can be referred to as gate contacts 114, and contacts 112 are electrically coupled to the silicide regions 110 and can be referred to as source / drain contacts 112. The barrier layer can be titanium, titanium nitride, tantalum, tantalum nitride, or the like.The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as CMP can be performed to remove excess material from a surface of the second ILD 106.

[0090] Fig. Figure 20 illustrates a cross-sectional view of an intermediate step in the fabrication of a nano-FET transistor according to some embodiments. Fig. 20 illustrates the in Fig. 1 illustrated reference cross-section C-C'. In Fig. 20 indicate identical reference symbols for identical elements, which are processed by the same processes as above in the Fig. 2 to 19C are formed as described, unless otherwise specified. Fig. Figure 20 illustrates a similar processing step to the Fig. 10A-C and the description is not repeated herein.

[0091] In this embodiment, the implantation process 88 also forms the doped regions 89 within the upper surface of the STI regions 68. This allows the etch rate of the STI to be modified during subsequent etching and structuring steps (e.g., etching internal spacer elements or removing sacrificial material 72). By adjusting the etch rate, the height of the upper surface of the STI can be controlled.

[0092] The doped regions 89 in the STI regions 68 can be formed simultaneously with the doped regions in the second nanostructures 54 and the sacrificial material 72. The type and concentration of the dopants, as well as the implantation conditions, can be controlled to achieve the desired modification of the etch rate.

[0093] The ability to adjust the height of the upper STI surface can offer several advantages. For example, it can help achieve a more uniform device structure, which can lead to improved device performance. It can also help reduce manufacturing defects and increase the overall yield of the manufacturing process. Furthermore, the ability to control the STI height can provide flexibility in the design and fabrication of the semiconductor device, allowing the device characteristics to be tailored to specific performance requirements.

[0094] The Fig. Figure 20-C illustrates cross-sectional views of intermediate steps in the fabrication of a nano-FET transistor according to some embodiments. Fig. 21 illustrates the in Fig. 1 illustrated reference cross-section C-C'. Fig. 22A illustrates the in Fig. 1 illustrated reference cross-section A-A'. Fig. 22B illustrates the in Fig. 1 illustrated reference cross-section B-B'. Fig. 22C illustrates the in Fig. 1 illustrated reference cross-section C-C'. In the Fig. Sections 20 to 21C use the same reference symbols to indicate the same elements, which are processed by the same processes as described above. Fig. 2 to 19C are formed as described, unless otherwise specified.

[0095] In this embodiment, hard mask layers can be formed on an upper surface of the STI regions 68 to reduce insulation region loss during subsequent cleaning and / or etching processes performed to manufacture the transistor. Fig. Figure 21 illustrates a similar processing step to the Fig. 4 and the description is not repeated here. Fig. 22A-C illustrate a similar processing step to the Fig. 7A-C, and the description is not repeated herein.

[0096] As in Fig. As illustrated in Figure 21, a hard mask structure 120 is formed on the upper surface of the STI regions 68. In some embodiments, the hard mask structure 120 is a multilayer structure, comprising, for example, a nitride hard mask and a silicon hard mask over the nitride hard mask. In some embodiments, an optional protective lining 118 is deposited over and along the sidewalls of the nanostructures 55 and on exposed upper sidewalls of the fins 66 prior to the formation of the hard mask structure 120.

[0097] The optional protective lining 118 can be formed, for example, downstream of the STI regions 68 and upstream of the dummy gates. In some embodiments, the protective lining 118 is produced by growing a silicon layer using an epitaxial process such as CVD, ALD, VPE, MBE, or the like. In some embodiments, the protective lining 118 is selectively deposited onto a semiconductor material of the nanostructures 55 and the fin 66, without depositing it on the exposed surfaces of the STI regions 68. The deposition process used to form the protective lining 118 can enable the formation of a relatively high-quality material. For example, if the protective lining 118 is a silicon layer deposited by an ALD process, the protective lining 118 can exhibit improved coverage and be more crystalline than the second nanostructures 54.The higher-quality material of the protective lining 118 can be more resistant to etching and reduce undesirable thinning of the second nanostructures 54 during subsequent processing steps. As a result, the protective lining 118 can enable the formation of higher-quality channel regions in the resulting device. The protective lining 118 can be omitted in some embodiments.

[0098] After the formation of the optional protective lining 118 and before the formation of the dummy gates, a first hard mask 120A is deposited over and along the sidewalls of the nanostructures 55, on the upper sidewalls of the fins 66, and on the upper surfaces of the STI regions 68. The first hard mask 120A can be a nitride layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxycarbonitride layer, or the like. The nitrogen concentration of the first hard mask 120A can be higher than the nitrogen concentration of the STI regions 68. In some embodiments, the first hard mask 120A is deposited by a non-conforming deposition process, such as a plasma-enhanced CVD process (PECVD process) or the like. The non-conforming deposition process can form sidewall sections of the first hard mask 120A with a thickness that is less than the thickness of side sections of the first hard mask 120A.The non-conforming deposition process can support the structuring and selective removal of the sidewall sections of the first hard mask 120A.

[0099] The top and sidewall sections of the first hard mask 120A can be removed before the second hard mask 120B is formed. The top sections of the first hard mask 120A may include sidewall sections arranged over the nanostructures 55. Removing the top sections of the first hard mask 120A may involve depositing a mask layer (not shown) over the first hard mask 120A followed by one or more etching processes to remove the top sections. Removing the sidewall sections of the first hard mask 120A may involve an etching process such as an isotropic etching process.

[0100] Furthermore, a second hard mask 120B is deposited over the first hard mask 120A. The second hard mask 120B can be deposited over the top surfaces of the nanostructures 55, along sidewalls of the nanostructures 55, and over top surfaces of the first hard mask 120A. The second hard mask 120B can be formed from a material with a higher etch selectivity to the STI regions 68 than the first hard mask 120A relative to the same etching process. In some embodiments, the second hard mask 120B is a semiconductor material. For example, the second hard mask 120B can be made of silicon or the like if the first hard mask 120A is made of a nitride material and the STI regions 68 are made of an oxide material.

[0101] The second hard mask 120B can be formed by a non-conforming deposition process, such as an FCVD process. Once the second hard mask 120B is formed, an annealing process can be performed. Furthermore, the non-conforming deposition process can deposit a material of lower quality than the material of the protective liner 118. For example, the second hard mask 120B may exhibit poorer coverage, particularly on the sidewalls and upper surfaces of the nanostructures 55, and may be less crystalline compared to the protective liner 118. Consequently, the second hard mask 120B may be more easily etched away in subsequent processes than the protective liner 118. Other non-conforming deposition processes, such as a PECVD process, can be used in other embodiments to deposit the second hard mask 120B.

[0102] The sidewall sections and upper sections of the second 120B hard mask are then removed, while the lower sections of the second 120B hard mask remain (see the Fig. 20-21C). Removing the side and top sections of the second hard mask 120B may involve an etching process such as an isotropic etching process. The optional protective liner 118 may be removed during the gate replacement process.

[0103] The hard mask structure 120 has a multilayer structure comprising the first hard mask 120A (e.g., a nitride) and the second hard mask 120B (e.g., a silicon hard mask). The hard mask structure 120 protects the underlying STI regions 68 during subsequent processing steps (e.g., subsequent etching and / or cleaning processes). Furthermore, the parasitic capacitance in the resulting device can be reduced by combining materials in the first hard mask 120A and the second hard mask 120B.

[0104] Fig. Figure 22 illustrates cross-sectional views of an intermediate step in the fabrication of a nano-FET transistor according to some embodiments. Fig. 22 illustrates the in Fig. 1 illustrated reference cross-section C-C'. In Fig. 22 indicate identical reference numbers for identical elements, which are processed through the same processes as above in the Fig. 2 to 19C are formed as described, unless otherwise stated. Fig. Figure 22 illustrates a similar processing step to the Fig. 19A-C and the description is not repeated herein.

[0105] In this embodiment, the adjacent epitaxial source / drain regions 92 remain separated after completion of the epitaxial process (similar to in Fig.12F) and the source / drain contacts 112 can extend between the adjacent epitaxial source / drain regions 92 such that their lower surface is deeper than the upper surface of the epitaxial source / drain regions 92. Although the contacts 112 are shown to extend between the adjacent epitaxial source / drain regions 92 into the STI regions 68, using the embodiments of the present disclosure, the contacts 112 do not extend as far as in conventional devices, since the distance and loss of the STI regions 68 are reduced with the present disclosure. This can improve the yield and reduce the parasitic capacity in the resulting device.

[0106] The disclosed method offers an approach to nano-FET formation in semiconductor manufacturing that addresses challenges such as the presence of residual oxide after removal of the disposable oxide interposer (DOI) and the problem of over-etching during the DOI oxide etching process. By employing an inclined implantation or plasma doping technique, the method increases the etch rate of the DOI, thereby minimizing the presence of residual oxide and reducing the likelihood of source / drain epitaxy damage as well as changes in channel strain and layer height.

[0107] The method also allows for increased doping in the extension region, thereby addressing the problem of transition overlap and improving the silicon etch rate. This control over doping enhances the interface between the layers and the source / drain regions, potentially leading to improved channel mobility and device performance. The dopant distribution can be selectively tailored in specific areas, such as the corners or the center of the nanostructure, to modulate the etch rate and dopant profile.

[0108] This method is adaptable to various doping strategies and results, which can be tailored based on manufacturing requirements. It enables the control of dopant concentrations across different layers of the nanostructures, which can be adjusted through a multi-tilt implantation design. Furthermore, the method can reduce the dielectric constant of adjacent gate spacer elements, potentially reducing electrical leakage currents and improving device reliability.

[0109] In summary, this method provides an approach to the fabrication of semiconductor nanoFETs that increases efficiency and precision, offering a solution that addresses some of the limitations of previous methods. It allows for the adjustment of etch rates and dopant profiles, thereby reducing the risks associated with residual materials and over-etching, making it a useful technique in the fabrication of semiconductor devices.

[0110] In one embodiment, a method may include forming a multilayer stack over a substrate. The multilayer stack comprises alternating layers of first semiconductor layers and second semiconductor layers. The method may also include removing the first semiconductor layers. Furthermore, the method may include forming a disposable material between the second semiconductor layers. Additionally, the method may include performing a first implantation process on the disposable material and the second semiconductor layers. The method may also include forming source / drain regions adjacent to the second semiconductor layers and the disposable material. Finally, the method may include replacing the disposable material with a metal gate structure.

[0111] The described embodiments may also have one or more of the following features. The method may employ a disposable material selected from the group consisting of silicon oxide, silicon oxynitride, and aluminum oxide. Additionally, the method may include performing a second implantation process to introduce n-dopers into the source / drain regions between the second semiconductor layers after the disposable material has been formed. The first implantation process on the disposable material and the second semiconductor layers may include an inclined implantation process. The first implantation process may include a plasma. Phosphorus, arsenic or antimony, germanium, xenon, argon, silicon, nitrogen, boron, boron fluoride, indium, and carbon may be used in the first implantation process on the disposable material and the second semiconductor layers.The initial implantation process on the disposable material and the second semiconductor layers can alter the etch selectivity between the second semiconductor layers and the disposable material. The process for replacing the disposable material with the metal gate structure can further include removing the disposable material using an etching process that is selective for the disposable material across the second semiconductor layers. Following the initial implantation process, the process can include forming internal spacer elements on the sidewalls of the disposable material. The internal spacer elements can be composed of silicon nitride, silicon oxynitride, or a combination thereof. The internal spacer elements can have a convex shape facing the disposable material.

[0112] In one embodiment, a method may include forming a multilayer stack over a substrate. The multilayer stack has alternating layers of first semiconductor layers and second semiconductor layers. The method may also include structuring the multilayer stack to define a fin. Furthermore, the method may include forming a recess adjacent to the fin. Additionally, the method may include selectively removing the first semiconductor layers. Furthermore, the method may include forming a sacrificial material between the second semiconductor layers. The method may also include performing a doping process on the sacrificial material and the second semiconductor layers to modify the etch selectivity. Finally, the method may include growing epitaxial source / drain regions in the recess adjacent to the second semiconductor layers.The procedure may also include replacing the sacrificial material with a metal gate structure.

[0113] The described embodiments may also have one or more of the following features. The doping process may include the introduction of dopants such as phosphorus, arsenic or antimony, germanium, xenon, argon, silicon, nitrogen, boron, boron fluoride, indium, and carbon. The sacrificial material may be selected from the group consisting of silicon dioxide, silicon oxynitride, and aluminum oxide. The doping process may be a plasma doping process. The method may include the formation of internal spacer elements on the sidewalls of the sacrificial material after the doping process. The method may include an implantation process to introduce dopants into the epitaxial source / drain regions after the epitaxial source / drain regions have grown.

[0114] In one embodiment, a method may include forming fins of a multilayer stack over a substrate. The multilayer stack comprises alternating layers of first semiconductor layers and second semiconductor layers. The method may also include forming a first gate structure over the fins. Furthermore, the method may include etching first recesses into the fins. Additionally, the method may include removing the first semiconductor layers from the fins. The method may also include forming a dielectric material between the second semiconductor layers and in the first recesses. Finally, the method may include removing sidewalls of the dielectric material in the first recesses to form second recesses between adjacent second semiconductor layers.Furthermore, the method can include performing a doping process in the first and second recesses of the dielectric material and the second semiconductor layers. Additionally, the method can include forming internal spacer elements on the recessed sidewalls of the dielectric material. The method can also include forming source / drain regions in the first recesses alongside the internal spacer elements and the second semiconductor layers. The method can further include performing an ion implantation process to introduce dopants into the source / drain regions. Finally, the method can include replacing the first gate structure and the dielectric material with a metal gate structure.

[0115] The described embodiments may also have one or more of the following features. The doping process may comprise a plasma doping process or an inclined ion implantation process.

[0116] The foregoing describes features of several embodiments so that the person skilled in the art may better understand the aspects of the present disclosure. A person skilled in the art should recognize that he can readily use the present disclosure as a basis for the design or modification of other methods and structures to achieve the same purposes and / or to obtain the same advantages as the embodiments presented herein. The person skilled in the art should also recognize that such equivalent designs do not deviate from the spirit and scope of the present disclosure, and that he can make various changes, substitutions, and modifications without deviating from the spirit and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 645.512

[0001]

Claims

[1] Procedure, encompassing: Forming a multilayer stack over a substrate, wherein the multilayer stack has alternating layers of first semiconductor layers and second semiconductor layers; Removal of the first semiconductor layers; Formation of a disposable material between the second semiconductor layers; Performing a first implantation process on the disposable material and the second semiconductor layers; Formation of source / drain regions adjacent to the second semiconductor layers and the disposable material; and Replacing the disposable material with a metal gate structure. [2] Method according to claim 1, wherein the disposable material is selected from the group consisting of silicon oxide, silicon oxynitride and aluminium oxide. [3] Method according to claim 1 or 2, further comprising: Performing a second implantation process to introduce n-dopers into the source / drain regions after forming the disposable material between the second semiconductor layers. [4] Method according to one of the preceding claims, wherein the execution of the first implantation process on the disposable material and the second semiconductor layers comprises an inclined implantation process. [5] Method according to any of the preceding claims, wherein the first implantation process comprises a plasma. [6] Method according to any of the preceding claims, wherein carrying out the first implantation process on the disposable material and the second semiconductor layers comprises implanting phosphorus, arsenic or antimony, germanium, xenon, argon, silicon, nitrogen, boron, boron fluoride, indium and carbon. [7] Method according to any of the preceding claims, wherein performing the first implantation process on the disposable material and the second semiconductor layers changes the etch selectivity between the second semiconductor layers and the disposable material. [8] Method according to any of the preceding claims, wherein replacing the disposable material with the metal gate structure further comprises: Removal of the disposable material using an etching process that is selective for the disposable material above the second semiconductor layers. [9] Method according to any of the foregoing claims, further comprising: After performing the first implantation process on the disposable material and the second semiconductor layers, forming internal spacer elements on the side walls of the disposable material. [10] Method according to claim 9, wherein the inner spacer elements comprise silicon nitride, silicon oxynitride or a combination thereof. [11] Method according to claim 9, wherein the inner spacer elements have a convex shape facing the disposable material. [12] Procedures, including: Forming a multilayer stack over a substrate, wherein the multilayer stack has alternating layers of first semiconductor layers and second semiconductor layers; Structuring the multi-layer stack to define a fin; Forming a recess next to the fin; selective removal of the first semiconductor layers; Formation of sacrificial material between the second semiconductor layers; Performing a doping process on the sacrificial material and the second semiconductor layers to change the etch selectivity; Growth of epitaxial source / drain regions in the recess adjacent to the second semiconductor layers; and Replacing the sacrificial material with a metal gate structure. [13] Method according to claim 12, wherein the doping process comprises the introduction of dopants comprising phosphorus, arsenic or antimony, germanium, xenon, argon, silicon, nitrogen, boron, boron fluoride, indium and carbon. [14] Method according to claim 12 or 13, wherein the sacrificial material comprises a material selected from the group consisting of silicon oxide, silicon oxynitride and aluminum oxide. [15] Method according to any one of the preceding claims 12 to 14, wherein the doping process is a plasma doping process. [16] Method according to any one of claims 12 to 15 above, further comprising: Forming internal spacer elements on the side walls of the sacrificial material after the doping process has been carried out. [17] Method according to any one of claims 12 to 16 above, further comprising: Performing an implantation process to introduce dopants into the epitaxial source / drain regions after the epitaxial source / drain regions have grown. [18] Procedures, including: Forming fins of a multilayer stack over a substrate, wherein the multilayer stack has alternating layers of first semiconductor layers and second semiconductor layers; Forming an initial gate structure over the fin; Etching of initial recesses into the fins; Removal of the first semiconductor layers from the fins; Formation of a dielectric material between the second semiconductor layers and in the first recesses; Recesses of side walls of the dielectric material in the first recesses to form second recesses between adjacent second semiconductor layers; Performing a doping process in the first and second recesses on the dielectric material and the second semiconductor layers; Forming internal spacer elements on the recessed side walls of the dielectric material; Formation of source / drain regions in the first recesses next to the inner spacer elements and the second semiconductor layers; Performing an ion implantation process to introduce dopants into the source / drain regions; and Replacing the first gate structure and dielectric material with a metal gate structure. [19] Method according to claim 18, wherein the doping process comprises a plasma doping process. [20] Method according to claim 18, wherein the doping process comprises an inclined ion implantation process.

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