semiconductor device

Abstract

A semiconductor device with high field-effect mobility is provided. The semiconductor device comprises an oxide semiconductor; a first conductor and a second conductor above the oxide semiconductor, which are separated from each other; a first insulator placed over the first conductor and the second conductor and including an opening overlapping with a region between the first conductor and the second conductor; a second insulator placed in the opening in the first insulator and in contact with the top surface of the oxide semiconductor, a side surface of the first conductor, a side surface of the second conductor, and a side surface of the first insulator; and a third conductor placed over the second insulator in the opening in the first insulator and including a region overlapping with the oxide semiconductor, with the second insulator interposed therebetween.The oxide semiconductor comprises a first layer, a second layer over the first layer, and a third layer over the second layer in an area overlapping the third layer. The first layer contains gallium. The second layer contains indium oxide. The third layer contains indium, gallium, and oxygen. The indium content of the second layer is higher than the indium content of the third layer.

Description

Background of the invention 1. Field of the invention

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device, each comprising an oxide semiconductor. Another embodiment of the present invention also relates to a method for manufacturing the semiconductor device.

[0002] Note that an embodiment of the present invention is not limited to the above technical field. Examples of the technical field of an embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch screen), operating methods thereof, and manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device generally refers to a device that can operate by utilizing semiconductor properties. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are each an embodiment of a semiconductor device. A display device (e.g., a liquid crystal display device and a light-emitting display device), a projection device, an illumination device, an electro-optical device, an energy storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, and the like may comprise a semiconductor device. 2. Description of the state of the art

[0004] In recent years, semiconductor devices have been developed, and large-scale integrations (LSIs), central processing units (CPUs), memories, and the like are mainly used in semiconductor devices. A CPU is an aggregate of semiconductor elements; the CPU includes a semiconductor integrated circuit (including at least one transistor and one memory) formed into a chip by processing a semiconductor wafer and provided with an electrode that serves as a connection terminal.

[0005] A semiconductor circuit (IC chip) of an LSI, a CPU, a memory, or the like is mounted on a circuit board such as a printed circuit board to be used as one of the components of various electronic devices.

[0006] A technique in which a transistor is formed using a semiconductor thin film formed over a substrate with an insulating surface has attracted attention. The transistor is used in a variety of electronic devices, such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a semiconductor thin film material that can be used in a transistor. Another material that has attracted attention is an oxide semiconductor.

[0007] It is known that a transistor including an oxide semiconductor has a very low leakage current in the off state. For example, Patent Document 1 discloses a low-power CPU that utilizes a low leakage current characteristic of a transistor including an oxide semiconductor. As another example, Patent Document 2 discloses a memory device that can retain stored data for a long time by utilizing a low leakage current characteristic of a transistor including an oxide semiconductor. [References][Non-Patent Document] [Patent Document 1] Japanese Patent Laid-Open No. 2012-257187 [Patent Document 2] Japanese Patent Laid-Open No. 2011-151383 Summary of the invention

[0008] An object of an embodiment of the present invention is to provide a semiconductor device with high field effect mobility. Another object of an embodiment of the present invention is to provide a semiconductor device with advantageous electrical characteristics. Another object of an embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of an embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of an embodiment of the present invention is to provide a semiconductor device that operates at high speed. Another object of an embodiment of the present invention is to provide a semiconductor device with low power consumption.Another object of an embodiment of the present invention is to provide a semiconductor device with small variations in the electrical characteristics of transistors. Another object of an embodiment of the present invention is to provide a novel semiconductor device. Another object of an embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Another object of an embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device. Another object of an embodiment of the present invention is to provide a novel display device.

[0009] It should be noted that the description of these objects does not preclude the existence of further objects. An embodiment of the present invention does not necessarily have to fulfill all of these objects. Further objects may be derived from the explanation of the description, the drawings, and the claims.

[0010] An embodiment of the present invention is a semiconductor device comprising an oxide semiconductor; a first conductor and a second conductor above the oxide semiconductor, which are separated from each other; a first insulator placed over the first conductor and the second conductor and including an opening overlapping with a region between the first conductor and the second conductor; a second insulator placed in the opening and in contact with the top surface of the oxide semiconductor, a side surface of the first conductor, a side surface of the second conductor, and a side surface of the first insulator; and a third conductor placed over the second insulator in the opening and including a region overlapping with the oxide semiconductor with the second insulator therebetween.The oxide semiconductor comprises a first layer, a second layer over the first layer, and a third layer over the second layer in a region overlapping the third layer. The first layer comprises gallium and oxygen. The second layer comprises indium oxide. The third layer comprises indium, gallium, and oxygen. The indium content of the second layer is higher than the indium content of the third layer.

[0011] In the above semiconductor device, the conduction band minimum of the first layer is preferably closer to the vacuum level than the conduction band minimum of the second layer, and the conduction band minimum of the third layer is preferably closer to the vacuum level than the conduction band minimum of the second layer.

[0012] In the above semiconductor device, the first layer preferably comprises indium, and the indium content is preferably lower than the gallium content in the first layer.

[0013] In the above semiconductor device, in a plan view, a side surface of a part of the first insulator is preferably aligned or substantially aligned with the side surface of the first conductor and the side surface of the second conductor.

[0014] The above semiconductor device preferably comprises a third insulator in contact with the top surface of the third conductor, an upper end portion of the second insulator, and the top surface of the first insulator; and a fourth insulator in contact with the top surface of the third insulator.

[0015] In the above semiconductor device, the third insulator preferably comprises alumina.

[0016] In the above semiconductor device, the fourth insulator preferably comprises silicon nitride.

[0017] In the above semiconductor device, the first conductor and the second conductor each preferably comprise a first conductive layer and a second conductive layer over the first conductive layer, and the shortest distance between the first conductive layer of the first conductor and the first conductive layer of the second conductor is preferably smaller than the shortest distance between the second conductive layer of the first conductor and the second conductive layer of the second conductor.

[0018] In the above semiconductor device, in a plan view, a side surface of a part of the first insulator is preferably aligned or substantially aligned with a side surface of the second conductive layer of the first conductor and a side surface of the second conductive layer of the second conductor.

[0019] In the above semiconductor device, the first conductive layer of the first conductor and the first conductive layer of the second conductor each preferably comprise tantalum nitride.

[0020] The above semiconductor device preferably includes a fifth insulator. The fifth insulator is preferably placed in the opening and in contact with the top surface of the first conductive layer of the first conductor, the side surface of the second conductive layer of the first conductor, the top surface of the first conductive layer of the second conductor, and the side surface of the second conductive layer of the second conductor. The fifth insulator preferably includes an opening that overlaps with a region between the first conductive layer of the first conductor and the first conductive layer of the second conductor.

[0021] In the above semiconductor device, the fifth insulator preferably comprises silicon nitride.

[0022] In the above semiconductor device, the second insulator preferably comprises a first insulating layer, and the first insulating layer preferably comprises a hafnium-containing oxide.

[0023] In the above semiconductor device, the first insulating layer preferably comprises hafnium zirconium oxide.

[0024] In the above semiconductor device, the second insulator preferably comprises a second insulating layer over the first insulating layer, and the second insulating layer preferably comprises silicon nitride.

[0025] One embodiment of the present invention can provide a semiconductor device with high field-effect mobility. Another embodiment of the present invention can provide a semiconductor device with advantageous electrical characteristics. Another embodiment of the present invention can provide a highly reliable semiconductor device. Another embodiment of the present invention can provide a semiconductor device that can be miniaturized or highly integrated. One embodiment of the present invention can provide a semiconductor device that operates at high speed. Another embodiment of the present invention can provide a semiconductor device with low power consumption.Another embodiment of the present invention can provide a semiconductor device with small variations in the electrical characteristics of transistors. Another embodiment of the present invention can provide a novel semiconductor device. Another embodiment of the present invention can provide a method for manufacturing a semiconductor device with high productivity. Another embodiment of the present invention can provide a method for manufacturing a novel semiconductor device. Another embodiment of the present invention can provide a novel display device.

[0026] It should be noted that the description of these effects does not preclude the existence of further effects. An embodiment of the present invention may not necessarily exhibit all of these effects. Further effects may be derived from the explanation of the description, the drawings, and the claims. Short description of the drawings

[0027] In the accompanying drawings: Fig. 1A is a plan view showing an example of a semiconductor device, and Fig. 1B to Fig. 1D are cross-sectional views illustrating an example of the semiconductor device; Fig. 2A and Fig. 2B are cross-sectional views illustrating an example of a semiconductor device; Fig. 3A to Fig. 3E are cross-sectional views illustrating examples of a semiconductor device; Fig. 4A is a plan view showing an example of a semiconductor device, and Fig. 4B to Fig. 4D are cross-sectional views illustrating an example of the semiconductor device; Fig. 5A is a plan view showing an example of a semiconductor device, and Fig. 5B to Fig. 5D are cross-sectional views illustrating an example of the semiconductor device; Fig. 6A to Fig. 6C are cross-sectional views illustrating examples of a semiconductor device; Fig. 7A is a plan view showing an example of a semiconductor device, and Fig. 7B to Fig. 7D are cross-sectional views illustrating an example of the semiconductor device; Fig. 8 is a cross-sectional view illustrating an example of a semiconductor device; Fig. 9A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 9B to Fig. 9D are cross-sectional views illustrating the example of the method for manufacturing the semiconductor device; Fig. 10A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 10B to Fig. 10D are cross-sectional views illustrating the example of the method for manufacturing the semiconductor device; Fig. 11A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 11B to Fig. 11D are cross-sectional views illustrating the example of the method for manufacturing the semiconductor device; Fig. 12A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 12B to Fig. 12D are cross-sectional views illustrating the example of the method for manufacturing the semiconductor device; Fig. 13A1 to Fig. 13D2 are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device; Fig. 14A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 14B to Fig. 14D are cross-sectional views illustrating the example of the method for manufacturing the semiconductor device; Fig. 15A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 15B to Fig. 15D are cross-sectional views illustrating the example of the method for manufacturing the semiconductor device; Fig. 16A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 16B to Fig. 16D are cross-sectional views illustrating the example of the method for manufacturing the semiconductor device; Fig. 17 is a band diagram of an oxide semiconductor; Fig. 18 is a diagram showing an example of hysteresis characteristics; Fig. 19A to Fig. 19C are equivalent circuit diagrams of a semiconductor device, and Fig. Figure 19D shows an example of Id-Vg characteristics of a transistor; Fig. 20A is a timing chart for explaining the operation of a semiconductor device, and Fig. 20B is a circuit diagram for explaining the operation of the semiconductor device; Fig. 21A is a timing chart for explaining the operation of a semiconductor device, and Fig. Fig. 21B is a circuit diagram for explaining the operation of the semiconductor device; Fig. 22A is a timing chart for explaining the operation of a semiconductor device, and Fig. Fig. 22B is a circuit diagram for explaining the operation of the semiconductor device; Fig. 23 is a block diagram illustrating a structural example of a semiconductor device; Fig. 24A to Fig. 24H each represents an example of a circuit structure of a memory cell; Fig. 25 is a cross-sectional view illustrating an example of a semiconductor device; Fig. 26A and Fig. 26B are perspective views each illustrating a structural example of a semiconductor device; Fig. 27 is a cross-sectional view illustrating an example of a semiconductor device; Fig. 28 is a cross-sectional view illustrating an example of a semiconductor device; Fig. 29 is a block diagram illustrating a CPU; Fig. 30A and Fig. 30B are perspective views illustrating a structural example of a semiconductor device; Fig. 31A and Fig. 31B are perspective views each illustrating a structural example of a semiconductor device; Fig. 32A and Fig. 32B each represent a hierarchy of different types of storage devices; Fig. 33A and Fig. 33B are examples of electronic devices, and Fig. 33C to Fig. 33E represents an example of a large computer; Fig. 34 shows an example of a room furnishing; Fig. Figure 35 shows an example of a storage system that can be used in a data center; Fig. 36A and Fig. 36B illustrates a structural example of a display device; Fig. 37 shows a structural example of a display device; Fig. 38 shows a structural example of a display device; Fig. 39 shows a structural example of a display device; Fig. 40A to Fig. 40D illustrate structural examples of a display device; Fig. 41A and Fig. 41B illustrate structural examples of display devices; Fig. 42A and Fig. 42B illustrates a structural example of a display device; Fig. 43A to Fig. 43D illustrate structural examples of a display device; Fig. 44A to Fig. 44D illustrate structural examples of a display device; Fig. 45 shows a structural example of a display device; Fig. 46A to Fig. 46F show structural examples of electronic devices; Fig. 47A to Fig. 47F show structural examples of electronic devices; and Fig. 48A to Fig. 48G represent structural examples of electronic devices. Detailed description of the invention

[0028] Embodiments will be described in detail with reference to the drawings. It should be noted that the present invention is not limited to the following description, and it will be readily apparent to those skilled in the art that modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as limited to the description of the following embodiments.

[0029] Note that in the structures of the invention described below, the same portions or portions with similar functions are designated by the same reference numerals in different drawings, and the description thereof will not be repeated. The same hatching pattern is used for portions with similar functions, and in some cases, the portions are not designated by specific reference numerals.

[0030] The position, size, area, or the like of each component shown in drawings may not represent the actual position, size, area, or the like in some cases for easy understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, area, or the like disclosed in the drawings.

[0031] It should be noted that ordinal numbers such as "first" and "second" are used in this specification and the like for convenience and do not limit the number or order (e.g., the order of steps or the order of arrangement) of components. The ordinal number assigned to a component in one part of this specification may be different from the ordinal number assigned to the component in another part of this specification or the scope of the claims.

[0032] It should be noted that the terms "film" and "layer" can be used interchangeably depending on the situation or circumstances. For example, the term "conductive layer" can be replaced with the term "conductive film". The term "insulating film" can be replaced with the term "insulating layer". The term "oxide semiconductor film" can be replaced with the term "oxide semiconductor layer". The term "conductor" can be replaced with the term "conductive layer" or "conductive film" depending on the situation or circumstances. The term "insulator" can be replaced with the term "insulating layer" or "insulating film" depending on the situation or circumstances. The term "oxide semiconductor" can be replaced with the term "oxide semiconductor layer" or "oxide semiconductor film" depending on the situation or circumstances.

[0033] In this specification and the like, the term "parallel" indicates that the angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°. Therefore, the case where the angle is greater than or equal to -5° and less than or equal to 5° is also included. The term "substantially parallel" indicates that the angle formed between two straight lines is greater than or equal to -20° and less than or equal to 20°. The term "perpendicular" indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°. Therefore, the case where the angle is greater than or equal to 85° and less than or equal to 95° is also included. The term "substantially perpendicular" indicates that the angle formed between two straight lines is greater than or equal to 70° and less than or equal to 110°.

[0034] The term "opening" includes, for example, a groove and a slot. An area in which an opening is formed is sometimes referred to as an opening section.

[0035] In the drawings used in this specification and the like, a sidewall of an insulator in an opening is perpendicular or substantially perpendicular to a substrate surface or a forming surface; however, the sidewall may be tapered.

[0036] In this specification and the like, a tapered shape refers to a shape in which at least a part of a side surface of a component is inclined with respect to a substrate surface or a formation surface. For example, the tapered shape preferably includes a region where the angle between the inclined side surface and the substrate surface or the formation surface (the angle will be referred to as a taper angle in some cases hereinafter) is less than 90°. Note that the side surface of the component and the substrate surface are not necessarily completely flat and may be substantially flat and have a slight curvature or a slight unevenness.

[0037] In this specification and the like, in some cases, a transistor containing an oxide semiconductor or a metal oxide in its semiconductor layer and a transistor containing an oxide semiconductor or a metal oxide in its channel formation region are each referred to as an OS transistor. A transistor containing silicon in its channel formation region is referred to as an Si transistor in some cases. (Embodiment 1)

[0038] In this embodiment, a semiconductor device comprising an oxide semiconductor and a method of manufacturing the semiconductor device are described based on Fig. 1A to Fig. 1D to Fig. 16A to Fig. 16D described. <Strukturbeispiel der Halbleitervorrichtung>

[0039] A structural example of a semiconductor device is shown using Fig. 1A to Fig. 1D and Fig. 2A and Fig. 2B. Fig. 1A to Fig. 1D are a plan view and cross-sectional views of a semiconductor device (a transistor 200). Fig. 1A is the plan view of the semiconductor device. Fig. 1B to Fig. 1D are the cross-sectional views of the semiconductor device. Fig. Figure 1B shows a cross section along the dotted line A1-A2 in Fig. 1A, which corresponds to a cross-sectional view of the transistor 200 in the channel longitudinal direction. Fig. Figure 1C shows a cross section along the dotted line A3-A4 in Fig. 1A, which corresponds to a cross-sectional view of the transistor 200 in the channel width direction. Fig. Figure 1D shows a cross section along the dotted line A5-A6 in Fig. 1A, which corresponds to a cross-sectional view of the transistor 200 in the channel width direction. It should be noted that for simplicity, some components in the plan view are Fig. 1A cannot be shown. Fig. 2A and Fig. 2B are enlarged cross-sectional views of the transistor 200 in the channel longitudinal direction.

[0040] Transistor 200 includes a conductor 205 embedded in an insulator 216, an insulator 221 over insulator 216 and conductor 205, an insulator 222 over insulator 221, an insulator 224 over insulator 222, an oxide semiconductor 230 over insulator 224, conductors 242a and 242b over oxide semiconductor 230, an insulator 271a over conductor 242a, an insulator 271b over conductor 242b, an insulator 250 over oxide semiconductor 230, and a conductor 260 over insulator 250.

[0041] The oxide semiconductor 230 includes a region serving as a channel formation region of the transistor 200. The conductor 260 includes a region serving as a first gate electrode (also referred to as an upper gate electrode or top gate electrode) of the transistor 200. The insulator 250 includes a region serving as a first gate insulator of the transistor 200. The conductor 205 includes a region serving as a second gate electrode (also referred to as a lower gate electrode or bottom gate electrode) of the transistor 200. Each of the insulators 224, 222, and 221 includes a region serving as a second gate insulator of the transistor 200. The conductor 242a includes a region serving as one of a source electrode and a drain electrode of the transistor 200. The conductor 242b includes a region that serves as the other of the source electrode and the drain electrode of the transistor 200.

[0042] An insulator 275 is provided over the insulators 271a and 271b, and an insulator 280 is provided over the insulator 275. An opening reaching the insulator 222 and the oxide semiconductor 230 is formed in the insulators 280 and 275, and the opening overlaps with a region between the conductor 242a and the conductor 242b. In a plan view (also referred to as a plan view), the side surface of the insulator 280 in the opening is aligned or substantially aligned with the side surface of the conductor 242a and the side surface of the conductor 242b. The insulator 250 and the conductor 260 are provided in an opening formed in the insulator 280 and the insulator 275. An insulator 282 is provided in contact with the top surface of the insulator 280, the upper end portion of the insulator 250, and the top surface of the conductor 260. An insulator 283 is provided over the insulator 282. An insulator 285 is provided over the insulator 283.An insulator 214 is provided under the insulator 216 and the conductor 205. An insulator 212 is provided under the insulator 214. The insulators 212, 214, 280, 282, 283, and 285 each serve as an interlayer film.

[0043] An opening reaching the conductor 242a is formed in the insulators 285, 283, 282, 280, 275, and 271a, and a conductor 240a and an insulator 241a are provided in the opening. The insulator 241a is provided in contact with a side wall of the opening, and the conductor 240a is provided further inside than the insulator 241a. An opening reaching the conductor 242b is formed in the insulators 285, 283, 282, 280, 275, and 271b, and a conductor 240b and an insulator 241b are provided in the opening. The insulator 241b is provided in contact with a side wall of the opening, and the conductor 240b is provided further inside than the insulator 241b. Conductors 240a and 240b serve as vias that connect a line or the like provided across transistor 200 to a terminal of the source and drain of transistor 200.

[0044] The oxide semiconductor 230 includes a channel formation region. The oxide semiconductor 230 also includes a source region and a drain region. The source region and the drain region are n-type (low-resistance) regions that have a higher carrier concentration than the channel formation region. The oxide semiconductor 230 may have a single-layer structure or a multilayer structure composed of two or more layers.

[0045] There is no particular limitation on the crystallinity of a semiconductor material used for the oxide semiconductor 230, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor with crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor partially including crystal regions) can be used. Preferably, a single-crystal semiconductor or a semiconductor with crystallinity is used, in which case, deterioration of transistor characteristics can be suppressed.

[0046] The band gap of a metal oxide serving as a semiconductor is preferably greater than or equal to 2.0 eV, more preferably greater than or equal to 2.5 eV. Using a wide band gap metal oxide for the oxide semiconductor 230 can reduce the off-state current of the transistor 200. The off-state current of the OS transistor is low, so the power consumption of the semiconductor device can be sufficiently reduced. The OS transistor has high frequency characteristics, enabling the semiconductor device to operate at high speed.

[0047] For the oxide semiconductor that can be used for the semiconductor layer of the transistor of one embodiment of the present invention, reference may be made to the description in Embodiment 2. Here, the detailed description is omitted.

[0048] Note that a transistor containing a different semiconductor material in a channel formation region may be used for the semiconductor device of this embodiment. Examples of a different semiconductor material include a single-element semiconductor and a compound semiconductor.

[0049] Examples of single-element semiconductors that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor materials include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS).

[0050] Examples of the compound semiconductor that can be used as the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride, which can be used for the semiconductor layer, preferably has an amorphous structure. Boron arsenide, which can be used for the semiconductor layer, preferably comprises a crystal with a cubic structure. Other examples of the compound semiconductor include an organic semiconductor and a nitride semiconductor. Note that the oxide semiconductor described above is also a type of compound semiconductor. These semiconductor materials may include an impurity as a dopant.

[0051] Here, the oxide semiconductor 230 used in the semiconductor device preferably contains an indium-containing oxide. For example, indium oxide, indium gallium oxide, indium zinc oxide, indium gallium zinc oxide, or indium gallium tin zinc oxide can be used as the oxide semiconductor 230. Furthermore, the oxide semiconductor 230 may have a multilayer structure. For example, the oxide semiconductor 230 may have a multilayer structure of indium oxide and indium gallium zinc oxide over the indium oxide. Furthermore, as shown in Fig. 2A, the oxide semiconductor 230 may include an oxide semiconductor 230a over the insulator 224, an oxide semiconductor 230b over the oxide semiconductor 230a, and an oxide semiconductor 230c over the oxide semiconductor 230b. For example, indium oxide may be used as the oxide semiconductor 230b, and indium gallium zinc oxide may be used as the oxide semiconductors 230a and 230c. When the oxide semiconductor 230 includes an indium-containing oxide as described above, a semiconductor device with high field-effect mobility can be provided. It is also possible to provide a semiconductor device having at least one of favorable electrical characteristics, high frequency characteristics, and high reliability. For a specific structure of the oxide semiconductor 230, reference may be made to the description in Embodiment 2.

[0052] In the oxide semiconductor 230, a channel formation region and source and drain regions of the transistor 200 are formed. The channel formation region is located between the source and drain regions. At least a portion of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged.

[0053] The channel formation region has a lower amount of oxygen vacancies or a lower concentration of impurities than the source and drain regions, and is therefore a high-resistance region with a low carrier concentration. The channel formation region can therefore be considered an i-type (intrinsic) or essentially i-type region.

[0054] The source and drain regions have a large number of oxygen vacancies or a high concentration of impurities such as hydrogen, nitrogen, and a metal element, and are therefore low-resistance regions with a high carrier concentration. In other words, the source and drain regions are n-type (low-resistance) regions with a higher carrier concentration than the channel formation region.

[0055] It should be noted that the carrier concentration in the channel formation region is preferably lower than or equal to 1 × 10 16 cm -3 , lower than 1 × 10 17 cm -3 , lower than 1 × 10 16 cm -3 , lower than 1 × 10 15 cm -3 , lower than 1 × 10 14 cm -3 , lower than 1 × 10 13 cm -3 , lower than 1 × 10 12 cm -3 , lower than 1 × 10 11 cm -3or lower than 1 × 10 10 cm -3 The lower limit of the carrier concentration of the channel formation region is not particularly limited and can be, for example, 1 × 10 -9 cm -3 be.

[0056] To reduce the carrier concentration of the oxide semiconductor 230, the concentration of impurities in the oxide semiconductor 230 is reduced, so that the density of defect states is reduced. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic state or a substantially high-purity intrinsic state. Note that an oxide semiconductor (or a metal oxide) with a low carrier concentration may be referred to as a high-purity intrinsic state or a substantially high-purity intrinsic oxide semiconductor (or metal oxide).

[0057] To maintain stable electrical characteristics of the transistor 200, it is effective to reduce the concentration of impurities in the channel formation region of the oxide semiconductor 230. To reduce the concentration of impurities in the oxide semiconductor 230, it is preferable to reduce the concentration of impurities in a film adjacent to the oxide semiconductor 230. Examples of the impurities include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel, and silicon. Note that impurities in the oxide semiconductor 230 refer to, for example, elements other than the main components of the oxide semiconductor 230. For example, an element with a concentration lower than 0.1 atomic % can be considered an impurity.

[0058] In the oxide semiconductor 230, it is sometimes difficult to clearly observe the boundaries between regions. The concentrations of a metal element and an impurity element, such as hydrogen or nitrogen, detected in each region may not only change gradually between regions, but also change continuously within each region. That is, the region closer to a channel formation region may preferentially have lower concentrations of a metal element and an impurity element, such as hydrogen or nitrogen.

[0059] When impurities and oxygen vacancies are present in a channel formation region in an oxide semiconductor, a transistor comprising the oxide semiconductor may exhibit variable electrical characteristics and poor reliability. In some cases, hydrogen forms a defect in the vicinity of an oxygen vacancy, which is an oxygen vacancy into which hydrogen has penetrated (hereinafter referred to as V in some cases). o H), which creates an electron that serves as a charge carrier. Therefore, when the channel formation region in the oxide semiconductor includes oxygen vacancies, the transistor tends to exhibit self-conducting properties (with which the channel is created even when no voltage is applied to the gate electrode and a current flows through the transistor). Therefore, impurities, oxygen vacancies, and V oH in the channel formation region in the oxide semiconductor is preferably reduced as much as possible. In other words, the channel formation region in the oxide semiconductor is preferably an i-type (intrinsic) or substantially i-type region with a reduced carrier concentration.

[0060] As a countermeasure against the above, an oxygen-containing insulator which releases oxygen by heating (hereinafter referred to as excess oxygen in some cases) is provided in the vicinity of the oxide semiconductor, and a heat treatment is carried out so that oxygen is supplied from the insulator to the oxide semiconductor to form oxygen vacancies and V oH. However, supplying an excessive amount of oxygen to the source region or the drain region could cause a reduction in the forward current or the field-effect mobility of the transistor 200. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region in the substrate plane result in variations in the properties of the semiconductor devices including the transistors. An excessive amount of oxygen supplied to the oxide semiconductor from the insulator adversely affects the electrical properties and reliability of the transistor in some cases. In addition, oxygen diffuses into a conductor, such as a gate electrode, a source electrode, or a drain electrode, to oxidize the conductor, which could impair conductivity.

[0061] First, an insulator having a barrier property against hydrogen is preferably formed in the vicinity of the transistor 200 to V o H in the channel formation region of the oxide semiconductor 230 and in the vicinity thereof.

[0062] At least one of insulators 212, 214, 221, 222, 275, 282, and 283 preferably serves as a hydrogen barrier insulator. At least one of insulators 212, 214, 221, 222, 275, 282, and 283 preferably serves as a contaminant barrier insulator. At least one of insulators 212, 214, 221, 222, 275, 282, and 283 preferably serves as an oxygen barrier insulator. It should be noted that not all of insulators 212, 214, 221, 222, 275, 282, and 283 need to be provided. If the barrier properties against hydrogen, impurities, oxygen, and the like are sufficient, any of the insulators 212, 214, 221, 222, 275, 282, and 283 may be formed appropriately selectively. For example, the insulator 216 and the conductor 205 may be formed without providing the insulator 214 in contact with the top surface of the insulator 212.

[0063] It should be noted that in this specification and the like, a barrier insulator refers to an insulator having a barrier property. In this specification and the like, the term "having a barrier property" means having a property that does not easily allow diffusion of a target substance (also referred to as a property that does not easily allow passage of a target substance, a low-permeability property of a target substance, or a function of preventing diffusion of a target substance). As another example, the term "having a barrier property" means having a function of capturing or fixing (also referred to as gettering) a target substance in the insulator. It should be noted that hydrogen described as a target substance includes, for example, at least one of a hydrogen atom, a hydrogen molecule, and a substance that bonds to hydrogen, such as a water molecule and OH.- Unless otherwise specified, an impurity described as a target substance refers to an impurity in a channel formation region or a semiconductor layer, and refers, for example, to at least one of a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N2O, NO, and NO2), and a copper atom. Oxygen described as a target substance refers, for example, to at least one of an oxygen atom and an oxygen molecule.

[0064] As an insulator having a hydrogen diffusion-preventing function, silicon nitride or silicon nitride oxide, for example, is preferably used. As another example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, indium gallium zinc oxide, or the like may be used in some cases.

[0065] For insulators 212, 221, 275, and 283, insulators with a hydrogen diffusion prevention function are preferably used. For example, silicon nitride, which has a higher hydrogen barrier property, is used for insulators 212, 221, 275, and 283.

[0066] A part of the insulator having a function of preventing hydrogen diffusion has a function of capturing or fixing hydrogen. Preferred examples of a material for an insulator having a function of capturing or fixing hydrogen include metal oxides such as an oxide containing hafnium, an oxide containing aluminum, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), and a manganese oxide. The insulator having a function of capturing or fixing hydrogen preferably has an amorphous structure. In such a metal oxide having an amorphous structure, an oxygen atom in some cases has an open bond, which is used to capture or fix hydrogen. That is, the metal oxide having an amorphous structure has a high ability to capture or fix hydrogen.When silicon is added to the above metal oxide, the metal oxide is prevented from polycrystallizing and easily becomes amorphous. Therefore, such a metal oxide to which silicon is added (e.g., hafnium silicate or aluminum silicate) is preferably used.

[0067] An insulator having a hydrogen trapping or fixing function is preferably used for insulators 214, 222, and 282. For example, aluminum oxide is used for insulators 214 and 282. For example, hafnium oxide, which is a high-permittivity (high-k) material, is preferably used for insulator 222 serving as the second gate insulator.

[0068] Such inorganic insulators, which are exemplified as insulator having a function of preventing the diffusion of hydrogen and insulator having a function of trapping or fixing hydrogen, also have a barrier property against oxygen.

[0069] As in Fig. 2A, the insulator 212 having a function of preventing hydrogen diffusion and the insulator 214 having a function of trapping or fixing hydrogen are preferably provided below the transistor 200. When the insulator 212 is provided below the transistor 200, hydrogen can be prevented from diffusing from a layer below the transistor 200. When the insulator 214 is provided above the insulator 212, hydrogen contained in the insulator 216 or the like can be trapped or fixed by the insulator 214. Therefore, the hydrogen concentration in the oxide semiconductor 230 and the surrounding area can be reduced.

[0070] As in Fig. 2A, the insulator 221 having a function of preventing hydrogen diffusion and the insulator 222 having a function of trapping or fixing hydrogen are preferably provided in a lower portion of the transistor 200. When the insulator 221 is provided in the lower portion of the transistor 200, hydrogen can be prevented from diffusing from a lower layer in the transistor 200. When the insulator 222 is provided above the insulator 221, hydrogen contained in the insulator 224 or the like can be trapped or fixed by the insulator 222. Therefore, the hydrogen concentration in the oxide semiconductor 230 and the surrounding area can be reduced.

[0071] As in Fig. As shown in FIG. 2A, the insulator 275 is preferably provided to cover the oxide semiconductor 230, the conductors 242a and 242b, and the like. By providing the insulator 275 in this manner, hydrogen can be prevented from diffusing from the insulator 275 into the oxide semiconductor 230, the conductors 242a and 242b, and the like.

[0072] As in Fig. 2A, the insulator 282 having a function of trapping or fixing hydrogen and the insulator 283 having a function of preventing hydrogen diffusion are preferably provided above the transistor 200. When the insulator 283 is provided above the transistor 200, hydrogen can be prevented from diffusing from a layer above the transistor 200. When the insulator 282 is provided below the insulator 283, hydrogen contained in the insulator 280 or the like can be trapped or fixed by the insulator 282. Therefore, the hydrogen concentration in the oxide semiconductor 230 and the surrounding area can be reduced.

[0073] If the top and bottom of the transistor 200 are surrounded by hydrogen barrier insulators in this way, the diffusion of hydrogen into the oxide semiconductor can be reduced, and V oH in the channel formation region can be reduced. Thus, the electrical characteristics and reliability of the transistor 200 can be improved.

[0074] Furthermore, oxygen released by heating is preferably contained in the insulator 280. When oxygen is supplied to the oxide semiconductor 230 through the insulator 250 by heat treatment, oxygen vacancies in the channel formation region can be reduced.

[0075] As in Fig. 2A, for example, the insulator 282 may have a multi-layer structure of an insulator 282a and an insulator 282b over the insulator 282a.

[0076] In this case, the insulator 282b is deposited by a sputtering method in an atmosphere containing an oxygen gas, allowing oxygen to be added to the insulator 280. At this time, when the insulator 282b is deposited with the insulator 282a provided, oxygen is added through the insulator 282a; thus, the amount of oxygen added to the insulator 280 can be controlled. With a greater thickness of the insulator 282a, the addition of oxygen is more likely to be prevented, and the amount of oxygen supplied to the insulator 280 decreases. With a smaller thickness of the insulator 282a, the addition of oxygen is less likely to be prevented, and the amount of oxygen supplied to the insulator 280 increases.For example, when the thickness of the insulator 282a is greater than or equal to 1 nm and less than or equal to 20 nm, preferably greater than or equal to 3 nm and less than or equal to 10 nm, an appropriate amount of oxygen can be supplied to the insulator 280.

[0077] The insulator 282a is preferably deposited by an atomic layer deposition (ALD) process to prevent oxygen from being added to the insulator 282a during the deposition of the insulator 282a. To form the insulator 282a with a small thickness like the above, an ALD process is preferably used. Examples of an ALD process include a thermal ALD process in which a precursor and a reactant react with each other using only thermal energy, and a plasma-enhanced ALD (PEALD) process in which a reactant excited by plasma is used.

[0078] A precursor used in an ALD method sometimes contains carbon or the like. For this reason, a film formed by an ALD method may contain an impurity, such as carbon, in a larger amount than a film formed by another film formation method. Therefore, in some cases, the insulator 282a has a higher carbon concentration than the insulator 282b. Note that impurities can be quantified by secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0079] For example, in the case where both the insulator 282a and the insulator 282b contain alumina, in some cases the carbon concentration of the insulator 282a is higher than that of the insulator 282b. In this case, the carbon concentration of the insulator 282a is preferably higher than or equal to 1 × 10 18 atoms / cm 3 and less than or equal to 1 × 10 21 atoms / cm 3 . The insulator 282a may include a region in which the carbon concentration is higher than or equal to 1 × 10 19 atoms / cm 3 and less than or equal to 1 × 10 21 atoms / cm 3 The carbon concentration of insulator 282b in the SIMS analysis is preferably higher than or equal to the lower detection limit and lower than or equal to 1 × 10 20 atoms / cm 3. The insulator 282b may include a region in which the carbon concentration is higher than or equal to 4.46 × 10 17 atoms / cm 3 and less than or equal to 1 × 10 19 atoms / cm 3 is.

[0080] As described above, heat treatment is performed on the insulator 280 in a state where the insulator 280 contains oxygen to be released by heating, whereby an appropriate amount of oxygen can be supplied to the oxide semiconductor 230 through the insulator 250. In the heat treatment, since the insulators 282 and 283, each having an oxygen barrier property, are placed over the insulator 280, oxygen contained in the insulator 280 can be prevented from excessively diffusing from the insulator 280. Since the insulator 275, which has an oxygen barrier property, is formed between the insulator 280 and each of the oxide semiconductor 230 and the conductors 242a and 242b, oxygen contained in the insulator 280 can be prevented from excessively diffusing from the insulator 280.The heat treatment is performed in a state where the opening is partially formed in the insulators 280, 282, and 283, whereby a part of oxygen contained in the insulator 280 can diffuse to the outside and the amount of oxygen supplied from the insulator 280 to the oxide semiconductor 230 can be regulated.

[0081] Here, the insulator 250 preferably allows diffusion of oxygen from the insulator 280 into the oxide semiconductor 230 and prevents oxidation of the conductors 242a, 242b, and 260.

[0082] As in Fig. 1B and Fig. 1C, the insulator 250 is provided in the opening formed in the insulators 280 and 275. The insulator 250 is formed in the opening in contact with the top surface of the insulator 222, a side surface of the insulator 224, a side surface and the top surface of the oxide semiconductor 230, a side surface of the conductor 242a, a side surface of the conductor 242b, a side surface of the insulator 271a, a side surface of the insulator 271b, a side surface of the insulator 275, and a side surface of the insulator 280. As shown in Fig. 2A, in the case where the oxide semiconductor 230 includes the oxide semiconductors 230a to 230c, the insulator 250 is in contact with a side surface of the oxide semiconductor 230a, a side surface of the oxide semiconductor 230b, and the top surface and a side surface of the oxide semiconductor 230c. Here, the crystallinity of the Fig. 2A is preferably high, in which case the transistor 200 can have a high charge carrier mobility in the on state because the oxide semiconductor 230c has a large contact area with the insulator 250.

[0083] As in Fig. 2A, the insulator 250 preferably has a multi-layer structure of an insulator 250a in contact with the oxide semiconductor 230, an insulator 250b over the insulator 250a, and an insulator 250c over the insulator 250b.

[0084] For the insulator 250b, silicon oxide, silicon oxynitride, or the like with high insulation withstand voltage is preferably used. To increase the insulation withstand voltage, the insulator 250b may have a greater thickness than the insulator 250a. Using the above oxide insulator, oxygen can diffuse into the insulator 250b through a high-temperature heat treatment. Therefore, the heat treatment allows oxygen contained in the insulator 250b to be supplied to the oxide semiconductor 230 through the insulator 250b. Note that in this specification and the like, an oxynitride refers to a material containing more oxygen than nitrogen, and a nitride oxide refers to a material containing more nitrogen than oxygen. For example, silicon oxynitride refers to a material containing more oxygen than nitrogen, and silicon nitride oxide refers to a material containing more nitrogen than oxygen.

[0085] To prevent oxidation of the conductors 242a, 242b, and 260, a barrier oxygen insulator is preferably provided in the vicinity of each of the conductors 242a, 242b, and 260. For example, a barrier oxygen insulator is preferably provided as insulators 250a and 250c.

[0086] The insulator 250a preferably has an oxygen barrier property. The insulator 250a preferably transmits less oxygen than at least the insulator 250b. The insulator 250a includes a region in contact with the side surface of the conductor 242a and the side surface of the conductor 242b. When the insulator 250a has an oxygen barrier property, oxidation of the side surfaces of the conductors 242a and 242b and formation of oxide films on the side surfaces can be prevented. Consequently, a reduction in the forward current or the field-effect mobility of the transistor 200 can be prevented. With such a structure, oxygen contained in the insulator 250b can be prevented from being absorbed by the conductors 242a and 242b.Therefore, an appropriate amount of oxygen can be supplied from the insulator 250b to the oxide semiconductor 230, so that oxygen vacancies in the channel formation region of the oxide semiconductor 230 can be reduced.

[0087] When the insulator 250a is provided between the insulator 280 and the insulator 250b, as well as between the insulator 250b and the oxide semiconductor 230, oxygen from the insulator 280 can be prevented from being excessively supplied to the oxide semiconductor 230, and an appropriate amount of oxygen can be supplied to the oxide semiconductor 230. Therefore, the amount of oxygen in the channel formation region of the oxide semiconductor 230 and the vicinity thereof can be controlled to an appropriate amount, thus preventing the transistor 200 from having excessively off-state characteristics and achieving high reliability. Furthermore, excessive oxidation of the source and drain regions can be prevented, and a reduction in the forward current or field-effect mobility of the transistor 200 can be prevented.

[0088] Therefore, the insulator 250a preferably has a thickness that does not excessively inhibit the diffusion of oxygen from the insulator 280 into the insulator 250b and the diffusion of oxygen from the insulator 250b into the oxide semiconductor 230. The thickness of the insulator 250a is preferably, for example, greater than or equal to 0.1 nm and less than or equal to 5.0 nm, more preferably greater than or equal to 0.5 nm and less than or equal to 5.0 nm, even more preferably greater than or equal to 0.5 nm and less than or equal to 3.0 nm, even more preferably greater than or equal to 0.5 nm and less than or equal to 2.0 nm.

[0089] As described above, preferably, the diffusion of oxygen from the insulator 280 into the insulator 250b and the diffusion of oxygen from the insulator 250b into the oxide semiconductor 230 occur appropriately, and the diffusion of oxygen from the insulator 250b into the conductors 242a and 242b is preferably prevented as much as possible. Here, in the semiconductor device of this embodiment, the contact area between the insulator 250a and the conductor 242a and the contact area between the insulator 250a and the conductor 242b are much smaller than the contact area between the insulator 250a and the oxide semiconductor 230. That is, the amount of oxygen that diffuses from the insulator 250b through the insulator 250a into the conductors 242a and 242b is expected to be smaller than the amount of oxygen that diffuses from the insulator 250b through the insulator 250a into the oxide semiconductor 230.Therefore, the amount of oxygen contained in the insulator 280 is controlled so that an appropriate amount of oxygen is supplied from the insulator 280 to the insulator 250b and the oxide semiconductor 230, whereby oxidation of the conductors 242a and 242b can be reduced.

[0090] The insulator 250a in contact with the channel formation region of the oxide semiconductor 230 preferably has a function of trapping or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide semiconductor 230. Therefore, V o H in the channel formation region, so that the channel formation region may be an i-type region or a substantially i-type region.

[0091] Furthermore, a high-permittivity (high-k) material is preferably used for the insulator 250a. An example of the high-k material is an oxide containing aluminum and / or hafnium. By using the high-k material for the insulator 250a, a gate potential applied during operation of the transistor can be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide film thickness (EOT) of the insulator serving as the gate insulator can be reduced.

[0092] As described above, an oxide containing aluminum and / or hafnium is preferably used for the insulator 250a, and an oxide containing aluminum and / or hafnium and having an amorphous structure is more preferably used. Since alumina can be relatively easily formed into an amorphous film by an ALD method, the use of alumina having an amorphous structure is more preferable. In this embodiment, an alumina film is used as the insulator 250a. Alumina has a function of capturing or fixing hydrogen and has a barrier property against oxygen; therefore, alumina can be advantageously used for the insulator 250a.

[0093] The insulator 250c also preferably has an oxygen barrier property. The insulator 250c is provided between the channel formation region of the oxide semiconductor 230 and the conductor 260, and between the insulator 280 and the conductor 260. With such a structure, oxygen contained in the channel formation region of the oxide semiconductor 230 can be prevented from diffusing into the conductor 260, and therefore, oxygen vacancies can be prevented from forming in the channel formation region of the oxide semiconductor 230. Furthermore, oxygen contained in the oxide semiconductor 230 and the oxygen contained in the insulator 280 can be prevented from diffusing into the conductor 260 and oxidizing the conductor 260. The insulator 250c preferably transmits less oxygen than at least the insulator 250b. Further, the insulator 250c preferably has a function of preventing the diffusion of hydrogen.This can prevent impurities contained in the conductor 260, such as hydrogen, from diffusing into the oxide semiconductor 230. For example, a silicon nitride film is preferably used as the insulator 250c.

[0094] As in Fig. 2B, an insulator 250d is preferably provided over the insulator 250b. In this case, an insulator that can be used for the insulator 250a and has a function of capturing or fixing hydrogen can be provided as the insulator 250d. For example, a hafnium-containing oxide is preferably used for the insulator 250d. As the hafnium-containing oxide, for example, hafnium oxide, hafnium aluminate, hafnium silicate, hafnium zirconium oxide, or hafnium zirconium oxide containing yttrium can be used. Hafnium zirconium oxide containing a lanthanide such as lanthanum can also be used for the insulator 250d. Here, when the insulator 250d is provided between the insulator 250c and the insulator 250b, hydrogen contained in the insulator 250b and the like can be more effectively trapped and fixed.The channel formation region of the oxide semiconductor 230 and the insulators 250a and 250d, each having a function of trapping and fixing hydrogen, are provided below the insulator 250c, which has a function of preventing hydrogen diffusion. For example, in a region where the diffusion of hydrogen from above is blocked by the insulator 250c, hydrogen contained in the channel formation region of the oxide semiconductor 230 can be trapped or fixed by the insulators 250a and 250d. Consequently, the hydrogen concentration in the oxide semiconductor 230 can be reduced, so that a negative shift in the initial characteristics of the transistor 200 can be prevented, and the transistor 200 can exhibit normally-off characteristics. Furthermore, negative drift deterioration in a gate bias temperature (+GBT) stress test can be prevented.

[0095] Note that the insulators 250a, 250b, and 250d may alternatively be provided without providing the insulator 250c. In this case, an insulator having a function of preventing hydrogen diffusion (e.g., silicon nitride) is preferably provided as the insulator 283 over the insulator 250. With this structure, the oxide semiconductor 230 and the insulators 250a and 250d, each having a function of trapping or fixing hydrogen, are formed in a region covered with silicon nitride having a high hydrogen barrier property. Accordingly, hydrogen contained in the channel formation region of the oxide semiconductor 230 can be trapped or fixed by, for example, the insulators 250a and 250d.

[0096] With the above structure, the i-type or substantially i-type channel formation region and the n-type source and drain regions can be formed, and therefore, a semiconductor device with favorable electrical characteristics can be provided. The semiconductor device with the above structure can have favorable electrical characteristics even when the semiconductor device is miniaturized or highly integrated. Furthermore, the miniaturization of the transistor 200 can improve the frequency characteristics. In particular, the cutoff frequency can be improved.

[0097] The hafnium-containing metal oxide used for the insulator 250d preferably serves as a high-k material. Accordingly, a gate potential applied during operation of the transistor can be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide film thickness (EOT) of the insulator serving as the gate insulator can be reduced.

[0098] The insulator 250d preferably has ferroelectricity. For example, hafnium zirconium oxide or hafnium zirconium oxide containing yttrium, each of which has ferroelectricity, can be used for the insulator 250d. The insulator 250d may have a structure in which a layer of hafnium zirconium oxide is disposed over a layer of hafnium zirconium oxide containing yttrium. Note that when a ferroelectric is used as the insulator 250d, the insulator 250d does not necessarily have a function of capturing or fixing hydrogen. For example, a material capable of exhibiting ferroelectricity, as described in Embodiment 4, can be used for the insulator 250d.

[0099] By using a ferroelectric as the insulator 250d in the above manner, the transistor 200 can serve as a ferroelectric field-effect transistor (FeFET). An FeFET itself serves as a memory element. Therefore, the size of the memory element can be smaller than that of a dynamic random access memory (DRAM) memory element including a transistor and a capacitor. Accordingly, a memory device including the transistors 200 can be miniaturized and highly integrated. Furthermore, the productivity of the memory device including the transistors 200 can be increased.

[0100] Insulators 250a to 250d serve as a part of the first gate insulator. Insulators 250a to 250d are provided together with conductor 260 in the opening formed in insulator 280 and the like. To miniaturize transistor 200, the thicknesses of each of insulators 250a, 250c, and 250d are preferably small. The thickness of each of the insulators 250a, 250c and 250d is preferably greater than or equal to 0.1 nm and less than or equal to 20 nm, more preferably greater than or equal to 0.1 nm and less than or equal to 10 nm, even more preferably greater than or equal to 0.5 nm and less than or equal to 5.0 nm, even more preferably greater than or equal to 1.0 nm and less than 5.0 nm, even more preferably greater than or equal to 1.0 nm and less than or equal to 3.0 nm.For example, 1 nm thick aluminum oxide may be used for insulator 250a, 2 nm thick silicon oxide may be used for insulator 250b, 2 nm thick hafnium oxide, hafnium zirconium oxide, or hafnium zirconium oxide containing yttrium may be used for insulator 250d, and 1 nm thick silicon nitride may be used for insulator 250c. Note that each of insulators 250a, 250c, and 250d at least partially includes a region having a thickness within the above range.

[0101] To reduce the thicknesses of the insulators 250a, 250c, and 250d as described above, an ALD method is preferably used for deposition. Furthermore, to form the insulators 250a to 250d with favorable coverage in the opening in the insulator 280 and the like, an ALD method is preferably used.

[0102] Although the case where the insulator 250 has a three-layer structure composed of the insulators 250a to 250c or a four-layer structure composed of the insulators 250a to 250d is described above, the present invention is not limited to these structures. The insulator 250 may have a single-layer structure, a two-layer structure, or a multi-layer structure composed of five or more layers. Furthermore, the insulator 250 may have a structure including at least one of the insulators 250a to 250d. For example, the insulator 250 may have a single-layer structure composed of the insulator 250c. In this case, the insulator 250 may be a single layer of hafnium zirconium oxide. When the insulator 250 is formed from one, two, or three layers of the insulators 250a to 250d, the manufacturing process of a semiconductor device can be simplified and productivity can be increased.

[0103] In the case where the insulator 250 has a four-layer structure or a five-layer structure, for example, a multi-layer structure formed in any of the Fig. 3A to Fig. 3E. Here are Fig. 3A to Fig. 3E enlarged views corresponding to an area A in Fig. 2B.

[0104] Fig. 3A illustrates an example in which the insulator 250 has a multilayer structure comprising the insulator 250a over the oxide semiconductor 230, the insulator 250d over the insulator 250a, the insulator 250b over the insulator 250d, and the insulator 250c over the insulator 250b. That is, in the Fig. 3A, the positions of the insulator 250b and the insulator 250d in the in Fig. 2B are interchanged. For example, 1 nm thick aluminum oxide may be used for insulator 250a, 2 nm thick hafnium zirconium oxide or hafnium zirconium oxide containing yttrium may be used for insulator 250d, 2 nm thick silicon oxide may be used for insulator 250b, and 1 nm thick silicon nitride may be used for insulator 250c. Insulator 250d may have a structure in which a layer of hafnium zirconium oxide is disposed over a layer of hafnium zirconium oxide containing yttrium. Without limitation to the foregoing, any of the insulating materials described above may be appropriately selected for insulators 250a to 250d, and the thicknesses of insulators 250a to 250d may also be appropriately selected. If the insulators 250a to 250d, as in Fig. 3A, the insulators 250a and 250d, each having a function of trapping or fixing hydrogen, are provided adjacent to each other, whereby hydrogen can be trapped and fixed more effectively.

[0105] As in Fig. 3B, the positions of insulator 250c and insulator 250b may be interchanged. In this case, insulator 250 has a multilayer structure including insulator 250a over oxide semiconductor 230, insulator 250d over insulator 250a, insulator 250c over insulator 250d, and insulator 250b over insulator 250c.

[0106] In Fig. 3A, the insulator 250c may be provided in contact with the top and bottom of the insulator 250b. In this case, as shown in Fig. 3C, the insulator 250 has a multilayer structure including the insulator 250a over the oxide semiconductor 230, the insulator 250d over the insulator 250a, an insulator 250c1 over the insulator 250d, the insulator 250b over the insulator 250c1, and an insulator 250c2 over the insulator 250b. Here, the insulator described above is used for the insulators 250c1 and 250c2, which can be used as the insulator 250c. For example, 1 nm thick silicon nitride can be used for each of the insulators 250c1 and 250c2.

[0107] Fig. 3D illustrates an example in which the insulator 250 has a multilayer structure comprising the insulator 250a over the oxide semiconductor 230, the insulator 250b over the insulator 250a, an insulator 250d1 over the insulator 250b, the insulator 250c over the insulator 250d1, and an insulator 250d2 over the insulator 250c. That is, the Fig. 3D has a structure in which insulators that can be used as the insulator 250d are in contact with the top and bottom of the insulator 250c in the Fig. 2B. Here, an insulator having a function of trapping or fixing hydrogen (e.g., hafnium oxide) may be used for the insulator 250d1, and an insulator having ferroelectricity (e.g., hafnium zirconium oxide or hafnium zirconium oxide containing yttrium) may be used for the insulator 250d2. The insulator 250d2 may have a structure in which a layer of hafnium zirconium oxide is disposed over a layer of hafnium zirconium oxide containing yttrium. When such a structure is employed to use a ferroelectric for the insulator 250d2, the transistor 200 may function as an FeFET. Furthermore, hydrogen can be trapped or fixed by the insulator 250d1, so that the electrical characteristics and reliability of the transistor 200 can be improved.

[0108] In the case where the insulator 250d2 is provided and formed using a ferroelectric material such as hafnium zirconium oxide, a conductor 252 may be provided in contact with the bottom of the insulator 250d2, as shown in Fig. 3E. For the conductor 252, a material that easily induces polarization in the insulator 250d2 is preferably used, and, for example, titanium nitride is preferably used. In this case, titanium nitride is also preferably used for a portion that is a lower portion of the conductor 260 and is in contact with the insulator 250d2 (e.g., for a conductor 260a). With such a structure, the insulator 250d2 can be a ferroelectric, and therefore the transistor 200 can serve as an FeFET.

[0109] In the transistor 200, the conductor 205 is provided to overlap with the oxide semiconductor 230 and the conductor 260. For the conductor 205, any of the conductive materials described in the paragraph < <leiter>> described. Here, the conductor 205 is preferably provided to be embedded in an opening formed in the insulator 216. The conductor 205 is preferably provided to extend in the channel width direction, as shown in Fig. 1A and Fig. 1C. With such a structure, the conductor 205 serves as a line when a plurality of transistors are provided.

[0110] As in Fig. As shown in Figure 2A, the conductor 205 preferably includes a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom and a side surface of the opening. The conductor 205b is provided to fill a recessed portion defined by the conductor 205a and formed along the opening. Here, the top surface of the conductor 205 is level with, or substantially level with, the top surface of the insulator 216.

[0111] Here, the conductor 205a preferably contains a conductive material having a function of preventing the diffusion of impurities, such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, and NO2), and copper atoms. Alternatively, the conductor 205a preferably contains a conductive material having a function of preventing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules).

[0112] When a conductive material having a function of preventing hydrogen diffusion is used for the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing into the oxide semiconductor 230 through the insulator 216 and the like. When a conductive material having a function of preventing oxygen diffusion is used for the conductor 205a, the conductivity of the conductor 205b can be prevented from being reduced due to oxidation of the conductor 205b. Examples of the conductive material having a function of preventing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a may have a single-layer structure or a multi-layer structure made of the above conductive material(s). For example, the conductor 205a preferably contains titanium nitride.

[0113] The conductor 205b is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. For example, the conductor 205b preferably contains tungsten.

[0114] Conductor 205 may serve as a second gate electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by changing a potential applied to conductor 205 not in conjunction with a potential applied to conductor 260, but independently. In particular, by applying a negative potential to conductor 205, Vth of transistor 200 can be increased and its off-state current can be reduced. Therefore, in the case where a negative potential is applied to conductor 205, a drain current when a potential applied to conductor 260 is 0 V can be lower than in the case where the negative potential is not applied to conductor 205.

[0115] The electrical resistivity of the conductor 205 is adjusted taking into account the potential applied to the conductor 205, and the thickness of the conductor 205 is determined according to the electrical resistivity. The thickness of the insulator 216 is substantially equal to that of the conductor 205. The conductor 205 and the insulator 216 are preferably as thin as possible within the allowable range of the design of the conductor 205. The insulator 216 with a smaller thickness contains a smaller absolute amount of impurities such as hydrogen, which prevents the impurities from diffusing into the oxide semiconductor 230.

[0116] Although the multilayer structure of the conductors 205a and 205b is Fig. 2A, the present invention is not limited to this structure. The conductor 205 may have a single-layer structure or a multilayer structure of three or more layers. For example, the conductor 205a may have a two-layer structure of tantalum nitride and titanium nitride over the tantalum nitride, and the conductor 205b containing tungsten may be provided over the conductor 205a. With such a structure, impurities such as hydrogen and metal impurities such as copper contained in the layer below the transistor 200 can be prevented from diffusing into the conductor 205.

[0117] The insulator 224, the insulator 221 and the insulator 222 serve as the second gate insulator.

[0118] For the insulator 224 in contact with the oxide semiconductor 230, any of the insulating materials described in paragraph < <isolator>> described above. For example, the insulator 224 preferably includes silicon oxide or silicon oxynitride. Accordingly, oxygen can be supplied from the insulator 224 to the oxide semiconductor 230, so that oxygen vacancies can be reduced. Note that the insulator 224 may have a multilayer structure composed of two or more layers. In these cases, without being limited to a multilayer structure formed of the same material, a multilayer structure formed of different materials may be used.

[0119] The insulator 224 is preferably processed into an island shape like the oxide semiconductor 230. Therefore, in the case where a plurality of transistors 200 are provided, the transistors 200 have the insulator 224 of substantially the same size. Consequently, the amount of oxygen supplied from the insulator 224 to the oxide semiconductor 230 is substantially the same among the transistors 200. As a result, variations in the electrical characteristics of the transistors 200 in the substrate plane can be reduced.

[0120] It should be noted that the insulator 224 is not necessarily processed into an island shape. For example, as in Fig. 4A to Fig. 4D, the insulator 224 may have a shape in which an opening is partially formed instead of an island shape. Fig. 4A to Fig. 4D correspond here to the Fig. 1A to Fig. 1D and are the same as Fig. 1A to Fig. 1D, with the exception of the shape of the insulator 224.

[0121] The Fig. 4A to Fig. The insulator 224 shown in FIG. 4D has a smaller thickness in a region that does not overlap with the oxide semiconductor 230 than in a region that overlaps with the oxide semiconductor 230. An opening is formed in a region that overlaps not with the oxide semiconductor 230 but with the insulator 250. In the case where a plurality of transistors are provided over a substrate, forming the insulator 224 in this way results in the formation of the oxide semiconductor 230 of each transistor over the same insulator 224. Consequently, variations in the amount of oxygen supplied from the insulator 224 to the oxide semiconductor 230 of each transistor can be reduced. Therefore, variations in the electrical characteristics of the transistors can be reduced.

[0122] It should be noted that in the Fig. 4A to Fig. 4D, the opening is formed in the region that overlaps not with the oxide semiconductor 230 but with the insulator 250; however, a structure without an opening may be used.

[0123] For the conductors 242a, 242b and 260, any of the conductive materials described in paragraph < <leiter>> described above. In particular, it is preferable to use a conductive material that is less likely to be oxidized or a conductive material having a function of preventing the diffusion of oxygen for the conductors 242a, 242b, and 260. Examples of such conductive materials include a conductive material containing nitrogen and a conductive material containing oxygen. The use of such conductive materials can prevent a reduction in the conductivity of the conductors 242a, 242b, and 260. In the case where a conductive material containing a metal and nitrogen is used for each of the conductors 242a, 242b, and 260, the conductors 242a, 242b, and 260 contain at least the metal and nitrogen.

[0124] For the conductors 242a and 242b, a metal nitride is preferably used; for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum is used. For example, tantalum nitride can be used for the conductors 242a and 242b. As another example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel can be used. These materials are preferred because they are conductive materials that are not easily oxidized or materials whose conductivity is maintained even after oxygen absorption.

[0125] Note that hydrogen contained in the oxide semiconductor 230 or the like may diffuse into the conductor 242a or 242b in some cases. In particular, when a nitride containing tantalum is used for the conductors 242a and 242b, hydrogen contained in the oxide semiconductor 230 or the like is likely to diffuse into the conductor 242a or 242b, and the diffused hydrogen may be bonded to nitrogen contained in the conductors 242a and 242b in some cases. That is, hydrogen contained in the oxide semiconductor 230 or the like may be absorbed by the conductor 242a or 242b in some cases.

[0126] Conductors 242a and 242b may each have a multilayer structure. In this case, the conductive material described above is used for lower layers of the multilayer structures of conductors 242a and 242b, and a conductive material with higher conductivity is used for upper layers of the multilayer structures of conductors 242a and 242b. For example, tantalum nitride may be used for the lower layers, and tungsten may be used for the upper layers.

[0127] The insulators 271a and 271b serve as etch stoppers during processing of the conductors 242a and 242b and are inorganic insulators that protect the conductors 242a and 242b. Since the insulators 271a and 271b are in contact with the conductors 242a and 242b, respectively, the insulators 271a and 271b are preferably inorganic insulators that are less likely to oxidize the conductors 242a and 242b. Therefore, as shown in Fig. 2A, the insulator 271a preferably has a multilayer structure of an insulator 271a1 and an insulator 271a2 over the insulator 271a1, and the insulator 271b preferably has a multilayer structure of an insulator 271b1 and an insulator 271b2 over the insulator 271b1. Here, the insulators 271a1 and 271b1 are preferably formed using the nitride insulator that can be used for the insulator 250c so that the conductors 242a and 242b are not easily oxidized. The insulators 271a2 and 271b2 are preferably formed using the oxide insulator that can be used for the insulator 250b to serve as an etch stopper.

[0128] Here, the insulator 271a1 is in contact with the top surface of the conductor 242a and a part of the insulator 275, and the insulator 271b1 is in contact with the top surface of the conductor 242b and another part of the insulator 275. The insulator 271a2 is in contact with the top surface of the insulator 271a1 and the bottom surface of the insulator 275, and the insulator 271b2 is in contact with the top surface of the insulator 271b1 and the bottom surface of the insulator 275. For example, silicon nitride can be used for the insulators 271a1 and 271b1, and silicon oxide can be used for the insulators 271a2 and 271b2.

[0129] An insulator to become insulators 271a and 271b serves as a mask for a conductor to become conductors 242a and 242b, and therefore, as shown in Fig. 1D, no curved surface exists between the side surface and the top surface. Accordingly, an end portion at the intersection of the side surface and the top surface of each of the conductors 242a and 242b is square. The cross-sectional area of each of the conductors 242a and 242b is larger in the case where the end portion at the intersection of the side surface and the top surface of each of the conductors 242a and 242b is square than that in the case where the end portion is rounded. Furthermore, when a nitride insulator that is less likely to oxidize a metal is used for the insulators 271a1 and 271b1, excessive oxidation of the conductors 242a and 242b can be prevented. Consequently, the resistance of the conductors 242a and 242b is reduced, so that the forward current of the transistor can be increased.

[0130] As in Fig. 1B and Fig. 1C, the conductor 260 is provided in the opening formed in the insulators 280 and 275. The conductor 260 is formed in the opening to cover the top surface of the insulator 222, the side surface of the insulator 224, and the side surface and top surface of the oxide semiconductor 230, with the insulator 250 interposed therebetween. The top surface of the conductor 260 is positioned to be level with, or substantially level with, the top end portion of the insulator 250 and the top surface of the insulator 280.

[0131] It should be noted that the sidewall of the opening in which the conductor 260 and the insulator 250 are provided may be perpendicular or substantially perpendicular to the top surface of the insulator 222, or it may be tapered. The tapered sidewall may improve coverage with the insulator 250 formed in the opening in the insulator 280, so that the number of defects, such as voids, may be reduced.

[0132] The conductor 260 serves as the first gate electrode of the transistor 200. Here, as in Fig. 1A and Fig. 1C, the conductor 260 is preferably provided to extend in the channel width direction. With such a structure, the conductor 260 serves as a wiring when a plurality of transistors are provided.

[0133] In the case where the above structure is employed, a curved surface may be provided between the side surface and the top surface of the oxide semiconductor 230 in a cross-sectional view of the transistor 200 in the channel width direction, as shown in Fig. 1C. In other words, the end portion of the side surface and the end portion of the top surface can be curved (rounded).

[0134] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the thickness of the oxide semiconductor 230 in a region overlapping with the conductors 242a and 242b, or less than half the length of a region not including the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than or equal to 20 nm, preferably greater than or equal to 1 nm and less than or equal to 15 nm, more preferably greater than or equal to 2 nm and less than or equal to 10 nm. With such a shape, the coverage of the oxide semiconductor 230 with the insulator 250 and the conductor 260 can be improved.

[0135] Note that in this specification and the like, a transistor structure in which a channel formation region is electrically surrounded by at least the electric field of the first gate electrode is referred to as a surrounded-channel structure (S-channel structure). The S-channel structure disclosed in this specification and the like is different from a fin structure or a planar structure. However, the S-channel structure disclosed in this specification and the like can be regarded as a type of fin structure. In this specification and the like, the fin structure refers to a structure in which at least two surfaces (specifically, two surfaces, three surfaces, four surfaces, or the like) of a channel are covered with a gate electrode.By using the fin structure or the S-channel structure, a transistor with high resistance to a short channel effect, that is, a transistor in which a short channel effect is less likely to occur, can be obtained.

[0136] When the transistor 200 has the S-channel structure described above, the channel formation region may be electrically enclosed. Since the S-channel structure is a structure with the electrically enclosed channel formation region, the S-channel structure is, in a sense, equivalent to a gate-all-around (GAA) structure or a lateral gate-all-around (LGAA) structure. When the transistor 200 has the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or in the vicinity of the interface between the oxide semiconductor 230 and the gate insulator may correspond to the entire bulk of the oxide semiconductor 230. Consequently, the density of a current flowing through the transistor can be increased, so that the forward current or field-effect mobility of the transistor should be increased.

[0137] In this embodiment, the insulator 224 is provided to have an island shape. Accordingly, as shown in Fig. 1C, at least a part of the bottom surface of the conductor 260 may be located at a position lower than the bottom surface of the oxide semiconductor 230. Therefore, the conductor 260 may be provided facing the top and side surfaces of the oxide semiconductor 230, so that an electric field of the conductor 260 may act on the top and side surfaces of the oxide semiconductor 230. When the insulator 224 having an island shape is provided in this way, the transistor 200 may have the S-channel structure.

[0138] It should be noted that although Fig. While FIG. 1C illustrates a transistor having an S-channel structure as transistor 200, the semiconductor device of one embodiment of the present invention is not limited thereto. For example, a transistor structure that can be used in one embodiment of the present invention is one or more selected from a planar structure, a fin structure, and a GAA structure.

[0139] As in Fig. 2A, the conductor 260 preferably has a two-layer structure. Here, the conductor 260 preferably includes the conductor 260a and a conductor 260b above the conductor 260a. For example, the conductor 260a is preferably placed to cover the bottom and side surfaces of the conductor 260b. Here, a conductive material that is less likely to be oxidized or a conductive material with a function of preventing oxygen diffusion is preferably used for the conductor 260a.

[0140] The conductor 260a is preferably formed using a conductive material having a function of preventing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, the conductor 260a is preferably formed using a conductive material having a function of preventing the diffusion of oxygen (e.g., oxygen atoms and / or oxygen molecules).

[0141] When the conductor 260a has a function of preventing oxygen diffusion, the conductivity of the conductor 260b can be prevented from being reduced due to oxidation of the conductor 260b due to oxygen contained in the insulator 280 and the like. As a conductive material having a function of preventing oxygen diffusion, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, for example, is preferably used.

[0142] The conductor 260b is preferably formed using a conductor with high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used for the conductor 260b. The conductor 260b may have a multilayer structure, for example, a multilayer structure of titanium or titanium nitride and the above conductive material.

[0143] In transistor 200, conductor 260 is formed in a self-aligned manner to fill the opening formed in insulator 280 and the like. In this way, conductor 260 can be provided in a region overlapping with a region between conductor 242a and conductor 242b without alignment.

[0144] Insulators 216, 280, and 285 each have a lower permittivity than insulator 222. Using materials with a low permittivity for the interlayer films can reduce the parasitic capacitance generated between lines.

[0145] For example, each of the insulators 216, 280, and 285 preferably includes one or more of silicon oxide, silicon oxynitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, and porous silicon oxide.

[0146] In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability. In particular, materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are preferably used, in which case a region containing oxygen released by heating can be easily formed.

[0147] Each of the top surfaces of insulators 216 and 280 can be planarized.

[0148] The concentration of impurities, such as water and hydrogen, in the insulator 280 is preferably reduced. For example, the insulator 280 preferably contains a silicon-containing oxide, such as silicon oxide or silicon oxynitride.

[0149] For the conductors 240a and 240b, any of the conductive materials described in paragraph < <leiter>> described above. The conductors 240a and 240b are preferably formed using, for example, a conductive material containing tungsten, copper, or aluminum as its main component. The conductors 240a and 240b may each have a multilayer structure.

[0150] For example, as in Fig. 2A, the conductors 240a and 240b each have a two-layer structure. The conductor 240a includes a conductor 240a1 formed along the opening and a conductor 240a2 formed on the inside of the conductor 240a1. The conductor 240b includes a conductor 240b1 formed along the opening and a conductor 240b2 formed on the inside of the conductor 240b1.

[0151] Conductors 240a1 and 240b1 are preferably formed, like conductor 205a, using a conductive material having a function of preventing passage of impurities such as water and hydrogen. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. The conductive material having a function of preventing passage of impurities such as water and hydrogen can be used as a single layer or in a layered arrangement. By providing conductors 240a1 and 240b1, impurities such as water and hydrogen can be prevented from penetrating into oxide semiconductor 230 through conductors 240a2 and 240b2. It should be noted that the conductors 240a2 and 240b2 may be formed using any of the conductive materials that may be used for the conductors 240a and 240b.

[0152] As in Fig. 1B, the conductors 240a and 240b may be formed such that their top surfaces are at the same height or substantially the same height as the top surface of the insulator 285. As shown in Fig. As shown in Figure 2A, conductor 240a may be formed such that its lower portion is embedded in conductor 242a. Similarly, conductor 240b may be formed such that its lower portion is embedded in conductor 242b.

[0153] The insulators 241a and 241b can be formed using a barrier insulator, which can be used for the insulator 275 and the like. For example, silicon nitride is used for the insulators 241a and 241b. The insulators 241a and 241b are provided in contact with the insulators 285, 283, 282, 275, 271a, and 271b. Therefore, impurities such as water and hydrogen contained in the insulator 280 or the like can be prevented from penetrating into the oxide semiconductor 230 through the conductors 240a and 240b. Silicon nitride is particularly preferred because of its high hydrogen barrier property. Furthermore, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductors 240a and 240b.

[0154] The insulators 241a and 241b may each have a multi-layer structure. In this case, a combination of an oxygen barrier insulator and a hydrogen barrier insulator is preferably used for a first insulator in contact with a side wall of the opening formed in the insulator 280 and the like, and a second insulator on the inside of the first insulator. <Variationsbeispiel 1>

[0155] In Fig. 1B and the like, the insulator 250 is in contact with the side surface of the insulator 280 in the opening portion provided in the insulator 280; however, the present invention is not limited to this structure. For example, an insulator may be provided between the insulator 250 and the insulator 280 in the opening portion.

[0156] A variation example 1 of the semiconductor device used in<Strukturbeispiel der Halbleitervorrichtung> is described using Fig. 5A to Fig. 5D and Fig. 6A to Fig. 6C. Fig. 5A to Fig. 5D are a plan view and cross-sectional views of a semiconductor device including the transistor 200 and correspond to the plan view and cross-sectional views in Fig. 1A to Fig. 1D. Fig. 6A to Fig. 6C are enlarged cross-sectional views of the transistor 200 in the channel longitudinal direction and correspond to the enlarged cross-sectional view in Fig. 2B.

[0157] The Fig. 5A to Fig. Transistor 200 shown in Figure 5D is a variation example of the transistor shown in Fig. 1A to Fig. 1D. In particular, the transistor 200 shown in Fig. 5A to Fig. 5D, the transistor 200 shown in Fig. 1A to Fig. 1D mainly by including an insulator 255. Differences from the above description of<Strukturbeispiel der Halbleitervorrichtung> are mainly described below. For the same sections, please refer to the description of<Strukturbeispiel der Halbleitervorrichtung> reference, and the description of the same section is omitted in some cases.

[0158] It should be noted that in Fig. 5A to Fig. 5D, conductors 242a and 242b each have a two-layer structure. Conductor 242a has a multi-layer structure consisting of a conductor 242a1 and a conductor 242a2 above conductor 242a1. Conductor 242b has a multi-layer structure consisting of a conductor 242b1 and a conductor 242b2 above conductor 242b1. Conductors 242a1 and 242b1 correspond to the lower layers of conductors 242a and 242b, and conductors 242a2 and 242b2 correspond to the upper layers of conductors 242a and 242b.

[0159] As in Fig. 5B and Fig. 5C, the insulator 255 is provided within the opening portion formed in the insulator 280 and the like, and is in contact with the side surface of the insulator 280, the side surface of the conductor 242a2, the side surface of the conductor 242b2, the top surface of the conductor 242a1, the top surface of the conductor 242b1, and the top surface of the insulator 222 in the opening portion. In other words, the insulator 255 is formed into a sidewall shape so as to be in contact with a sidewall of the opening portion formed in the insulator 280 and the like. Here, the sidewall of the opening portion corresponds, for example, to the side surface of the insulator 280 and the like in the opening portion.

[0160] The insulator 250 is in contact with a side surface of the insulator 255.

[0161] The insulator 255 preferably has an oxygen barrier property. When the insulator 255 has an oxygen barrier property, oxidation of the side surfaces of the conductors 242a and 242b, which forms oxide films on the side surfaces, can be prevented. Therefore, a reduction in the forward current or the field-effect mobility of the transistor 200 can be prevented. The insulator 255 can be formed using a barrier insulator, which can be used for the insulator 275 and the like. For example, silicon nitride is used for the insulator 255.

[0162] The opening portion formed in the insulator 280 overlaps with a region between the conductors 242a2 and 242b2. In a plan view, the side surface of the insulator 280 in the opening portion is aligned or substantially aligned with the side surfaces of the conductors 242a2 and 242b2. Parts of the conductors 242a1 and 242b1 are formed to extend to the inside of the opening portion. In other words, a part of the conductor 242a1 having an upper surface on which the insulator 255 is formed (hereinafter referred to in some cases as an extending portion of the conductor 242a1) is formed to extend beyond the conductor 242a2 toward the conductor 260.Similarly, a part of the conductor 242b1 having an upper surface on which the insulator 255 is formed (hereinafter referred to as an extending portion of the conductor 242b1 in some cases) is formed to extend beyond the conductor 242b2 toward the conductor 260.

[0163] A part of the top surface of the conductor 242a1 is in contact with the conductor 242a2, and a part of the top surface of the conductor 242b1 is in contact with the conductor 242b2. Consequently, the insulator 255 is in contact with another part of the top surface of the conductor 242a1, another part of the top surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2 within the opening portion. Furthermore, the insulator 250 is in contact with the top surface of the oxide semiconductor 230, a side surface of the conductor 242a1, a side surface of the conductor 242b1, and the side surface of the insulator 255.

[0164] After a conductive layer is divided into the conductor 242a2 and the conductor 242b2, the insulator 255 is formed by anisotropic etching. The insulator 255 is formed into a sidewall shape so as to be in contact with the sidewall of the opening portion provided in the insulator 280. The insulator 255 is formed in contact with the side surfaces of the conductors 242a2 and 242b2 and has a function of protecting the conductors 242a2 and 242b2.

[0165] The insulator 255 serves as a mask when dividing the conductive layer into the conductors 242a1 and 242b1. Therefore, as shown in Fig. 6A, in the cross-sectional view of transistor 200, side end portions of insulator 255 are preferably aligned with a side end portion of conductor 242a1 and a side end portion of conductor 242b1.

[0166] Note that heat treatment in an oxygen-containing atmosphere is preferably performed after dividing the conductive layer into the conductors 242a1 and 242b1 and before forming the insulator 250. At this time, since the insulator 255 is formed in contact with the side surfaces of the conductors 242a2 and 242b2, excessive oxidation of the conductors 242a2 and 242b2 can be prevented. Furthermore, even if microwave treatment is performed after dividing the conductive layer into the conductors 242a1 and 242b1, the formation of an oxide film on the side surfaces of the conductors 242a and 242b can be prevented.

[0167] Portions of the insulators 255 and 250 and the conductor 260 placed in the opening portion provided in the insulator 280 are provided to reflect the shape of the opening portion. Therefore, the insulator 255 is provided to cover the side wall of the opening portion, the insulator 250 is provided to cover the bottom portion of the opening portion and the insulator 255, and the conductor 260 is provided to fill a recessed portion defined by the insulator 250.

[0168] It should be noted that the insulator 250 may have a multi-layer structure as described above in<Strukturbeispiel der Halbleitervorrichtung> For example, as described in Fig. 6A, the insulator 250 may have a three-layer structure of the insulators 250a, 250b, and 250c. As another example, as shown in Fig. 6B, the insulator 250 may have a four-layer structure comprising the insulators 250a, 250b, 250c, and 250d. Without limitation to the Fig. 6B, one or more of the insulators 250a, 250b, 250c, and 250d may be selected to form the insulator 250. For example, the insulator 250 may have any of the Fig. 3A to Fig. 3D structures.

[0169] The thickness of the insulator 255 is preferably greater than or equal to 0.5 nm and less than or equal to 20 nm, more preferably greater than or equal to 0.5 nm and less than or equal to 10 nm, and even more preferably greater than or equal to 0.5 nm and less than or equal to 3 nm. When the insulator 255 has a thickness in the above range, excessive oxidation of the conductors 242a2 and 242b2 can be prevented. Note that at least a part of the insulator 255 includes a region having the above thickness. Since the insulator 255 is provided in contact with the sidewall of the opening formed in the insulator 280 and the like, the insulator 255 is preferably formed by a method that can form a film with good coverage, such as an ALD method.If the thickness of the insulator 255 is too large, the time for depositing the insulator 255 by an ALD method is long, which reduces productivity; therefore, the thickness of the insulator 255 is preferably within the above range. Furthermore, the insulator 255 preferably has a thickness that does not excessively inhibit the diffusion of excess oxygen from the insulator 280 into the insulator 250b and the diffusion of excess oxygen from the insulator 250b into the oxide semiconductor 230.

[0170] As in Fig. As shown in Figure 6A, in the cross-sectional view of the transistor 200 in the channel length direction, a distance L1 between the conductors 242a1 and 242b1 is smaller than a distance L2 between the conductors 242a2 and 242b2. Here, the distance L1 denotes the shortest distance between the conductors 242a1 and 242b1, and the distance L2 denotes the shortest distance between the conductors 242a2 and 242b2. With such a structure, the distance between the source and the drain can be shortened, and accordingly, the channel length can be shortened. This can improve the frequency characteristics of the transistor 200. In this way, downsizing the semiconductor device enables the semiconductor device to have higher operating speed.

[0171] At the Fig. In the structure shown in Figure 6A, the difference between the distance L2 and the distance L1 is twice the thickness of the insulator 255. In other words, the distance L2 is equal to the sum of the distance L1 and twice the thickness of the insulator 255. Here, the thickness of the insulator 255 corresponds to the width in the A1-A2 direction of at least a part of the insulator 255.

[0172] The insulator 255 may have a multilayer structure composed of two or more layers. In such a case, at least one of the stacked layers is the above-described inorganic insulator, which is less likely to be oxidized. For example, an inorganic insulator that is less likely to be oxidized is used as the first insulator of the insulator 255, and an insulator (e.g., silicon oxide) that can be used as the insulator 250b is used as the second insulator above the first insulator of the insulator 255. The second insulator of the insulator 255 preferably has a lower permittivity than the first insulator of the insulator 255. In the above manner, when the insulator 255 has a two-layer structure to have a large thickness, the distance between the conductor 260 and the conductor 242a or 242b can be increased, and therefore the parasitic capacitance can be reduced.

[0173] Although an example is described above in which the insulator 255 is formed into a sidewall shape by anisotropic etching, the present invention is not limited thereto. As shown in Fig. 6C, the insulator 255 may have an opening within the opening formed in the insulator 280 and the like. In this case, the opening of the insulator 255 may be formed by removing a portion of an insulating film to become the insulator 255 through a lithography process. The opening of the insulator 255 preferably overlaps with a region between the conductors 242a1 and 242b1.

[0174] As in Fig. 6C, protruding portions are formed in a lower portion of the insulator 255 in the cross-sectional view. The protruding portions of the insulator 255 overlap with the extending portion of the conductor 242a1 and the extending portion of the conductor 242b1. <Variationsbeispiel 2>

[0175] Although Variation Example 1 describes the structure in which the insulator 255 is provided in contact with the side wall of the opening portion formed in the insulator 280 and the like, the present invention is not limited to this structure. For example, a structure in which the insulator 255 is not provided in the opening portion may be adopted.

[0176] A variation example of the semiconductor device described in Variation Example 1 will be described with reference to Fig. 7A to Fig. 7D and Fig. 8 described. Fig. 7A to Fig. 7D are a plan view and cross-sectional views of a semiconductor device including the transistor 200 and correspond to the plan view and cross-sectional views in Fig. 5A to Fig. 5D. Fig. 8 is an enlarged cross-sectional view of the transistor 200 in the channel longitudinal direction and corresponds to the enlarged cross-sectional view in Fig. 6C.

[0177] The Fig. 7A to Fig. Transistor 200 shown in Figure 7D is a variation example of the transistor shown in Fig. 5A to Fig. 5D. In particular, the transistor 200 shown in Fig. 7A to Fig. 7D, the transistor 200 shown in Fig. 5A to Fig. 5D mainly in that the insulator 255 is not included. Differences from the above description of<Strukturbeispiel der Halbleitervorrichtung> and<Variationsbeispiel 1> are mainly described below. For the same sections, please refer to the description of<Strukturbeispiel der Halbleitervorrichtung> and<Variationsbeispiel 1> and the description of the same section is omitted in some cases.

[0178] As in Fig. As shown in Fig. 8, in the case where the insulator 255 is not provided, a part of the insulator 250 is positioned to overlap with the extending portions of the conductors 242a1 and 242b1. In some cases, a part of the conductor 260 is positioned to overlap with the extending portions of the conductors 242a1 and 242b1. Here, the extending portions of the conductors 242a1 and 242b1 are in contact with the insulator 250. The side surface of the insulator 250 is in contact with the side surfaces of the insulators 280, 275, 271a, and 271b and the side surfaces of the conductors 242a2 and 242b2.

[0179] A portion of the insulator 250 placed in the opening portion provided in the insulator 280 is formed to reflect the shape of the opening portion. Accordingly, the insulator 250 is formed to reflect the shapes of the conductors 242a1 and 242b1 extending in the opening portion.

[0180] As in Fig. As shown in Figure 8, in the cross-sectional view of transistor 200 in the channel longitudinal direction, the distance L1 between conductors 242a1 and 242b1 is smaller than the distance L2 between conductors 242a2 and 242b2. With this structure, the distance between the source and drain can be shortened, and accordingly, the channel length can be shortened. This can improve the frequency characteristics of transistor 200. Thus, downsizing the semiconductor device enables the semiconductor device to have higher operating speeds.

[0181] Furthermore, the Fig. 8, the width of the upper portion of the conductor 260 may be larger than the distance L1. This can reduce the conduction resistance of the conductor 260. Consequently, the power consumption of the semiconductor device can be reduced.

[0182] It should be noted that the insulator 250 may have a multi-layer structure as described above in<Strukturbeispiel der Halbleitervorrichtung> For example, as described in Fig. 6A, the insulator 250 may have a three-layer structure of the insulators 250a, 250b, and 250c. As another example, as shown in Fig. 6B, the insulator 250 may have a four-layer structure comprising the insulators 250a, 250b, 250c, and 250d. Without limitation to the Fig. 6B, one or more of the insulators 250a, 250b, 250c, and 250d may be selected to form the insulator 250. For example, the insulator 250 may have any of the Fig. 3A to Fig. 3D structures. <Materialien für die Halbleitervorrichtung>

[0183] Materials that can be used for the semiconductor device are described below. Note that the layers included in the semiconductor device may each have a single-layer structure or a multi-layer structure. < <substrat>>

[0184] As a substrate over which a transistor is formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttrium-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Another example is a semiconductor substrate in which an insulator region is provided in the above semiconductor substrate, such as a silicon-on-insulator (SOI) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.Examples of the substrate include a substrate containing a metal nitride and a substrate containing a metal oxide, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator. Alternatively, these substrates provided with one or more types of elements may be used. Examples of the element provided for the substrate include a capacitor, a resistor, a switching element, a light-emitting element, and a memory element. < <isolator>>

[0185] Any of the following insulators can be appropriately used for the insulators 212, 214, 216, 221, 222, 224, 250, 275, 280, 282, 283, 285, 241a, 241b, 271a, 271b, and 255 described in this embodiment. Examples of the insulators include an insulating oxide, an insulating nitride, an insulating oxynitride, an insulating nitride oxide, an insulating metal oxide, an insulating metal oxynitride, and an insulating metal nitride oxide.

[0186] For example, with miniaturization and high integration of transistors, a problem such as leakage current generation may arise due to a reduction in the thickness of a gate insulator. When a high-k material is used for the insulator serving as the gate insulator, the voltage at the time of transistor operation can be reduced while maintaining the physical thickness. In contrast, when a low-dielectric constant material is used for the insulator serving as the interlayer film, the parasitic capacitance generated between lines can be reduced. Therefore, a material is preferably selected depending on the function of an insulator.

[0187] Examples of the insulator having a high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0188] Examples of the insulator having a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, porous silicon oxide, and a resin.

[0189] A transistor containing a metal oxide can exhibit stable electrical properties when enclosed in an insulator having a function of preventing passage of oxygen and impurities such as hydrogen. The insulator having a function of preventing passage of oxygen and impurities such as hydrogen can, for example, have a single-layer structure or a multi-layer structure of an insulator(s) containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum. Specific examples of the insulator having a function of preventing passage of oxygen and impurities such as hydrogen include a metal oxide such asAluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide, and a nitride such as aluminum nitride, silicon nitride oxide and silicon nitride.

[0190] The insulator serving as the gate insulator preferably includes a region containing oxygen that is released by heating. For example, silicon oxide or silicon oxynitride, which includes a region containing oxygen that is released by heating, may be provided in contact with the oxide semiconductor 230 to compensate for oxygen vacancies in the oxide semiconductor 230. < <leiter>>

[0191] Any of the following conductors can be used as needed for the conductors 205, 242a, 242b, 260, 240a, and 240b described in this embodiment. For the conductor, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, and the like; an alloy containing any of the above metal elements; an alloy containing a combination of the above metal elements; or the like is preferably used. Examples of the conductors include tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel.Tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferred because they are oxidation-resistant conductive materials or materials that maintain their conductivity even after oxygen absorption. Alternatively, a semiconductor with high electrical conductivity, typically polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide, may be used.

[0192] For example, in the case where a multilayer structure of conductors is used, a multilayer structure in which a material containing any of the metal elements and an oxygen-containing conductive material are combined, a multilayer structure in which a material containing any of the metal elements and a nitrogen-containing conductive material are combined, or a multilayer structure in which a material containing any of the above metal elements, an oxygen-containing conductive material and a nitrogen-containing conductive material are combined may be used.

[0193] When an oxide is used for the channel formation region of the transistor, the conductor serving as the gate electrode preferably has a multilayer structure in which a material containing any of the above metal elements and an oxygen-containing conductive material are combined. In this case, the oxygen-containing conductive material is preferably provided on the channel formation region side. When the oxygen-containing conductive material is provided on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0194] In particular, a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed is preferably used for the conductor serving as the gate electrode. A conductive material containing any of the above metal elements and nitrogen may be used. For example, a nitrogen-containing conductive material such as titanium nitride or tantalum nitride may be used. One or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may be used. Nitrogen-containing indium gallium zinc oxide may also be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed can be trapped in some cases.Hydrogen entering from an external insulator or the like can also be trapped in some cases. <Beispiel für das Verfahren zum Herstellen der Halbleitervorrichtung>

[0195] An example of a method for manufacturing the semiconductor device of an embodiment of the present invention will be explained with reference to Fig. 9A to Fig. 9D to Fig. 16A to Fig. 16D. Here, the case of the production of the Fig. 1A to Fig. 1D as an example.

[0196] Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 14A, Fig. 15A and Fig. 16A are plan views. Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 14B, Fig. 15B and Fig. 16B are cross-sectional views along the dashed lines A1-A2 in Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 14A, Fig. 15A and Fig. 16A, which illustrate the transistor 200 in the channel longitudinal direction. Fig. 9C, Fig. 10C, Fig. 11C, Fig. 12C, Fig. 14C, Fig. 15C and Fig. 16C are cross-sectional views along the dash-dotted lines A3-A4 in Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 14A, Fig. 15A and Fig. 16A, which illustrate the transistor 200 in the channel width direction. Fig. 9D, Fig. 10D, Fig. 11D, Fig. 12D, Fig. 14D, Fig. 15D and Fig. 16D are cross-sectional views along the dash-dotted lines A5-A6 in Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 14A, Fig. 15A and Fig. 16A, which illustrate the transistor 200 in the channel width direction. It should be noted that for simplicity, some components in the plan views are shown in Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 14A, Fig. 15A and Fig. 16A cannot be shown. Fig. 13A1, Fig. 13B1, Fig. 13C1 and Fig. 13D1 are cross-sectional views showing a part of Fig. 1B and represent the transistor 200 in the channel longitudinal direction. Fig. 13A2, Fig. 13B2, Fig. 13C2 and Fig. 13D2 are cross-sectional views showing a part of Fig. 1C and represent the transistor 200 in the channel width direction.

[0197] In the following steps, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be appropriately formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0198] First, a substrate (not shown) is prepared, the insulator 212 is formed over the substrate, and the insulator 214 is formed over the insulator 212 (see Fig. 9A to Fig. 9D). Any of the above insulating materials can be used for the insulators 212 and 214. The insulators 212 and 214 can be formed, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. A sputtering method that does not require the use of a molecule containing hydrogen as a film-forming gas is preferably used, in which case the hydrogen concentration in the insulators 212 and 214 can be reduced.

[0199] In this embodiment, a silicon nitride film is formed as the insulator 212 by a sputtering method, and an aluminum oxide film is formed as the insulator 214 by a sputtering method. When silicon nitride having a function of preventing hydrogen diffusion is used for the insulator 212, the diffusion of hydrogen from a layer below the transistor 200 can be prevented. Furthermore, when aluminum oxide having a function of trapping or fixing hydrogen is used for the insulator 214, hydrogen contained in the insulator 216 or the like can be trapped or fixed by the insulator 214. Therefore, the hydrogen concentration in the oxide semiconductor 230 and the surrounding area can be reduced.

[0200] Before forming the insulator 212, a heat treatment is preferably performed to reduce water and hydrogen adsorbed on the substrate (including a circuit element and an interlayer film formed over the substrate). In this embodiment, the heat treatment temperature is 400°C.

[0201] Next, the insulator 216 is formed over the insulator 214. The insulator 216 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of a molecule containing hydrogen as a film-forming gas, the hydrogen concentration in the insulator 216 can be reduced. Note that the insulator 216 may alternatively be appropriately formed by, for example, a CVD method, an MBE method, a PLD method, or an ALD method instead of a sputtering method. In this embodiment, a silicon oxide film is formed as the insulator 216 by a sputtering method.

[0202] Insulators 212, 214, and 216 are preferably formed successively without exposure to air. For example, a multi-chamber film forming apparatus may be used. As a result, the amount of hydrogen in the formed films of insulators 212, 214, and 216 can be reduced, and hydrogen can be prevented from penetrating the films between film forming steps.

[0203] Then, an opening reaching the insulator 214 is formed in the insulator 216. The opening is formed in a region where the conductor 205 is to be formed. Wet etching can be used to form the opening, but dry etching is preferred for micropatterning. The insulator 214 is preferably an insulator that serves as an etching stopper film during the etching of the insulator 216. For example, in the case where silicon oxide or silicon oxynitride is used as the insulator 216, the insulator 214 is preferably silicon nitride, aluminum oxide, hafnium oxide, or the like.

[0204] After the opening is formed, a conductive film to become the conductor 205 is formed and subjected to CMP treatment until the insulator 216 is exposed, so that a part of the conductive film to become the conductor 205 is removed. In this way, the conductor 205 embedded in the insulator 216 can be formed (see Fig. 9A to Fig. 9D).

[0205] The conductive film to become the conductor 205 can be formed using any of the above conductive materials by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a tantalum nitride film, a titanium nitride film, and a tungsten film are stacked by a CVD method. Therefore, as shown in Fig. 2A, the conductor 205 may have a multilayer structure of the conductor 205a in which titanium nitride is arranged over tantalum nitride and the conductor 205b made of tungsten.

[0206] Next, the insulator 221 is formed over the insulator 216 and the conductor 205 (see Fig. 9A to Fig. 9D).

[0207] The above-described insulator, which has a barrier property against oxygen, hydrogen, and water, is used as the insulator 221. The insulator 221 can be formed, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, a silicon nitride film is formed as the insulator 221 by a PEALD method.

[0208] Then, the insulator 222 is formed over the insulator 221 (see Fig. 9A to Fig. 9D).

[0209] The insulator 222 is preferably formed using an insulator containing an oxide of aluminum and / or hafnium. Note that, as an insulator containing an oxide of aluminum and / or hafnium, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. Alternatively, hafnium-zirconium oxide is preferably used. The insulator containing an oxide of aluminum and / or hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in a component provided around the transistor can be prevented from diffusing into the transistor through the insulator 222, and consequently, oxygen vacancies can be prevented from being generated in the oxide semiconductor 230.

[0210] The insulator 222 can be formed, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, a hafnium oxide film is formed as the insulator 222 by a thermal ALD method.

[0211] In this embodiment, a silicon nitride film is formed as the insulator 221 by a PEALD method, and a hafnium oxide film is formed as the insulator 222 by a thermal ALD method. When silicon nitride having a hydrogen diffusion prevention function is used for the insulator 221, hydrogen can be prevented from diffusing from a layer below the transistor 200. Furthermore, by using hafnium oxide having a hydrogen trapping or fixing function for the insulator 222, hydrogen contained in the insulator 224 or the like can be trapped or fixed by the insulator 222. Therefore, the hydrogen concentration in the oxide semiconductor 230 and the surrounding area can be reduced.

[0212] Next, an insulating film 224f is formed over the insulator 222 (see Fig. 9A to Fig. 9D). For the insulating film 224f, an insulator corresponding to the insulator 224 is used. By forming the insulating film 224f in this manner, the insulating film 224f is formed parallel or substantially parallel to the surface of the substrate.

[0213] The insulating film 224f can be formed, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, a silicon oxide film is formed as the insulating film 224f by a sputtering method. Since no molecule containing hydrogen is used as the film-forming gas in a sputtering method, the hydrogen concentration in the insulating film 224f can be reduced. The hydrogen concentration in the insulating film 224f is preferably reduced in this way because the insulating film 224f is in contact with the oxide semiconductor 230 in a later step.

[0214] Next, an oxide semiconductor film 230f is formed over the insulating film 224f (see Fig. 9A to Fig. 9D). The oxide semiconductor film 230f is formed by the same method as an oxide semiconductor described in Embodiment 2. For the oxide semiconductor film 230f, an indium-containing oxide (e.g., indium oxide, indium gallium oxide, indium zinc oxide, indium gallium zinc oxide, or indium gallium tin zinc oxide) is preferably used. When the oxide semiconductor film 230f contains an indium-containing oxide, it is possible to provide a semiconductor device with high field-effect mobility. It is also possible to provide a semiconductor device having at least one of favorable electrical characteristics, high frequency characteristics, and high reliability. Note that the oxide semiconductor film 230f formed in the above manner is formed parallel or substantially parallel to the surface of the substrate.

[0215] In the case where, for example, as in Fig. 2A, the oxide semiconductor 230 has a three-layer structure of the oxide semiconductors 230a to 230c, films to become the oxide semiconductors 230a and 230b may be formed by an ALD method, and a film to become the oxide semiconductor 230c may be formed by a sputtering method. Specifically, the film to become the oxide semiconductor 230a may be formed to have a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or close thereto. Alternatively, gallium oxide may be used for the film to become the oxide semiconductor 230a. The film to become the oxide semiconductor 230b may be formed using indium oxide. The film to become the oxide semiconductor 230c can be formed using an oxide target having a composition of In:Ga:Zn = 1:1:1.2 [atomic ratio] or close thereto.

[0216] As another example, in the above structure, the oxide semiconductor 230a may be deposited by a sputtering method. Specifically, the film to become the oxide semiconductor 230a may be formed using an oxide target having a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or close thereto.

[0217] Next, a heat treatment is preferably performed. The heat treatment of the oxide semiconductor film 230f can be performed by the same method as the heat treatment described in Embodiment 2.

[0218] For example, a heat treatment can be carried out for one hour at 450 °C in a flow rate ratio of a nitrogen gas to an oxygen gas of 4:1.

[0219] By performing the heat treatment, the crystallinity of the oxide semiconductor 230 can be increased. Consequently, the forward current, subthreshold swing value (S value), field-effect mobility, frequency characteristics, and the like of the transistor 200 can be improved, so that a semiconductor device with favorable electrical characteristics can be provided. Furthermore, a highly reliable semiconductor device can be provided.

[0220] Note that the heat treatment is preferably performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more, respectively. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in the following manner: A heat treatment is performed in a nitrogen gas atmosphere or an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more, respectively, to compensate for released oxygen.

[0221] The gas used in the above heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the above heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. Heat treatment using a high-purity gas can prevent the penetration of moisture or the like into the oxide semiconductor film 230f and the like as much as possible. Note that a highly purified gas can also be used in a heat treatment before this step and a heat treatment after this step.

[0222] By the heat treatment using the above-described oxygen gas, impurities such as carbon, water, and hydrogen in the oxide semiconductor film 230f can be reduced. Impurities in the film are reduced in the above manner, whereby the crystallinity of the oxide semiconductor film 230f can be improved and a denser structure can be obtained. As a result, the crystal area in the oxide semiconductor film 230f can be expanded, and in-plane fluctuations of the crystal areas in the oxide semiconductor film 230f can be reduced. Therefore, in-plane fluctuations in the electrical characteristics of the transistors can be reduced.

[0223] The heat treatment can supply oxygen to the oxide semiconductor film 230f to reduce oxygen vacancies in the oxide semiconductor film 230f. Therefore, the reliability of the transistor 200 can be improved.

[0224] Through the heat treatment, hydrogen contained in the insulator 216, the insulating film 224f, and the oxide semiconductor film 230f is transferred to the insulator 222 and absorbed by the insulator 222. In other words, hydrogen contained in the insulator 216, the insulating film 224f, and the oxide semiconductor film 230f diffuses into the insulator 222. Accordingly, the hydrogen concentration in the insulator 222 increases, while the hydrogen concentrations in the insulator 216, the insulating film 224f, and the oxide semiconductor film 230f decrease. Note that the insulator 221 is provided in contact with the bottom surface of the insulator 222, thereby preventing the intrusion of moisture or contaminants such as condensate. B. hydrogen, from below the insulator 221, which could be caused by the heat treatment, can be prevented.

[0225] Specifically, the insulating film 224f (to become the insulator 224 later) serves as a second gate insulator of the transistor 200, and the oxide semiconductor film 230f (to become the oxide semiconductor 230 later) serves as a channel formation region of the transistor 200. The transistor 200 including the insulating film 224f and the oxide semiconductor film 230f with reduced hydrogen concentrations is preferable because of its advantageous reliability.

[0226] Subsequently, a conductive film 242f is formed over the oxide semiconductor film 230f (see Fig. 9A to Fig. 9D). For the conductive film 242f, a conductor corresponding to the conductors 242a and 242b is used. The conductive film 242f is formed over and in contact with the oxide semiconductor film 230f without performing an etching step or the like after the formation of the oxide semiconductor film 230f, whereby the upper surface of the oxide semiconductor film 230f can be protected by the conductive film 242f. Therefore, the diffusion of impurities into the oxide semiconductor 230 included in the transistor can be reduced, so that the electrical characteristics and reliability of the semiconductor device can be improved.

[0227] The conductive film 242f may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0228] In this embodiment, a tantalum nitride film is formed as the conductive film 242f by a sputtering method. Note that heat treatment may be performed before forming the conductive film 242f. The heat treatment may be performed under reduced pressure, and the conductive film 242f may be successively formed without exposure to air. By such treatment, moisture and hydrogen adsorbed on the surface of the oxide semiconductor 230 can be removed, and the moisture concentration and hydrogen concentration in the oxide semiconductor 230 can be reduced. The heat treatment temperature is preferably higher than or equal to 100°C and lower than or equal to 400°C.

[0229] Next, an insulating film 271f is formed over the conductive film 242f (see Fig. 9A to Fig. 9D). The insulating film 271f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 271f is preferably an insulating film having a function of preventing oxygen transmission. For example, as the insulating film 271f, a multilayer film of a silicon nitride film and a silicon oxide film is formed over the silicon nitride film by a sputtering method. With such a structure, the insulator 271a (or the insulator 271b) can have a multilayer structure of the insulator 271a1 (or the insulator 271b1) made of silicon nitride and the insulator 271a2 (or the insulator 271b2) made of silicon oxide.

[0230] Here, in the case where the insulating film 271f is formed by stacking films, the films are preferably formed successively without exposure to air. By forming the films without exposure to air, the interface between the stacked films of the insulating film 271f and the surrounding area can be kept clean. The conductive film 242f and the insulating film 271f are more preferably formed successively without exposure to air.

[0231] Note that the heat treatment may be performed before forming the insulating film 271f. The heat treatment may be performed under reduced pressure, and the insulating film 271f may be formed successively without exposure to air. Such treatment can remove moisture and hydrogen adsorbed on the surface of the conductive film 242f, and the moisture concentration and hydrogen concentration in the conductive film 242f can be reduced. The heat treatment temperature is preferably higher than or equal to 100°C and lower than or equal to 400°C.

[0232] Next, the insulating film 224f, the oxide semiconductor film 230f, the conductive film 242f, and the insulating film 271f are processed into an island shape by a lithography method, thereby forming the insulator 224, the oxide semiconductor 230, a conductor 242A, and an insulator 271A (see Fig. 10A to Fig. 10D).

[0233] Processing can be performed using a dry etching method or a wet etching method. A dry etching method is suitable for microstructuring. The insulating film 224f, the oxide semiconductor film 230f, the conductive film 242f, and the insulating film 271f can be processed under different conditions.

[0234] Here, the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A are preferably simultaneously processed into an island shape. In this case, the side end portion of the conductor 242A is preferably aligned or substantially aligned with the side end portion of the oxide semiconductor 230. The side end portion of the insulator 224 is preferably aligned or substantially aligned with the side end portion of the oxide semiconductor 230. The side end portion of the insulator 271A is preferably aligned or substantially aligned with the side end portion of the conductor 242A. With such a structure, the number of steps for the semiconductor device of one embodiment of the present invention can be reduced. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0235] The insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A are formed to at least partially overlap with the conductor 205. The insulator 222 is exposed in a region that does not overlap with the insulator 224, the oxide semiconductor 230, the conductor 242A, or the insulator 271A. However, without being limited to this structure, the insulator 224 may remain over the insulator 222 in a region that does not overlap with the oxide semiconductor 230. In this case, instead of an island shape, the insulator 224 has a shape in which, as in the transistor 200 in Fig. 4A to Fig. 4D an opening is partially formed.

[0236] As in Fig. 10B to Fig. As shown in Figure 10D, the side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A may be tapered. For example, the taper angle of the side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A may be greater than or equal to 60° and less than 90°. With such tapered side surfaces, the coverage with the insulator 275 and the like can be improved in a later step, so that the number of defects such as voids can be reduced.

[0237] Without limitation to the foregoing, the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A may have side surfaces that are perpendicular or substantially perpendicular to the top surface of the insulator 222. This structure allows a plurality of transistors to be provided in a small area with high density.

[0238] In a lithography process, a photoresist is first exposed through a mask. Next, an exposed portion is removed or left over using a developing solution, forming a photoresist mask. Then, etching is performed through the photoresist mask, whereby a conductor, semiconductor, insulator, or the like can be processed into a desired shape. For example, the photoresist mask can be formed by exposing the photoresist to, for example, KrF excimer laser light, ArF excimer laser light, or extreme ultraviolet (EUV) light. A liquid immersion technique may be used in which a portion between a substrate and a projection lens is filled with a liquid (e.g., water) to perform exposure. An electron beam or an ion beam may be used instead of the aforementioned light.It should be noted that in case of using an electron beam or an ion beam, no photomask is required.

[0239] To remove the photoresist mask that is no longer needed after processing, a dry etching treatment such as ashing using oxygen plasma (hereinafter referred to as oxygen plasma treatment in some cases) or a wet etching treatment may be performed. Alternatively, a wet etching treatment may be performed after a dry etching treatment, or a dry etching treatment may be performed after a wet etching treatment.

[0240] A hard mask formed from an insulator or a conductor may be used under the photoresist mask. When using a hard mask, a hard mask having a desired shape can be formed in the following manner: An insulating film or a conductive film, which is the material of the hard mask, is formed over the insulating film 271f, a photoresist mask is formed thereover, and then the hard mask material is etched. For example, tungsten may be used as the material of the hard mask. Etching of the insulating film 271f and the like may be performed after removing the photoresist mask or without removing it. In the latter case, the photoresist mask disappears during etching in some cases. The hard mask may be removed by etching after the oxide semiconductor 230f and the like have been etched.The hard mask does not need to be removed if the material of the hard mask does not affect the following process or can be used in the following process.

[0241] A spin-on-carbon (SOC) film and a spin-on-glass (SOG) film can be formed between a processing object and the photoresist mask. Using the SOC film and the SOG film as masks can improve the adhesion between the processing object and the photoresist mask, as well as the durability of a mask pattern. For example, the SOC film, the SOG film, and the photoresist mask are formed in this order over the processing object, and lithography can be performed.

[0242] A halogen-containing etching gas can be used as the dry etching gas; specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, as the etching gas, a C4F6 gas, a C5F6 gas, a C4F8 gas, a CF4 gas, an SF6 gas, a CHF3 gas, a CH2F2 gas, a Cl2 gas, a BCl3 gas, a SiCl4 gas, a BBr3 gas, or the like can be used alone or in combination. An oxygen gas, a carbon dioxide gas, a nitrogen gas, a helium gas, an argon gas, a hydrogen gas, a hydrocarbon gas, or the like can be added to the above etching gas as needed. Depending on an object to be dry etched, a gas containing a hydrocarbon gas or a hydrogen gas and not containing a halogen gas can be used as the etching gas. The hydrocarbon used for the etching gas can be one or more of methane (CH4), ethane (C2H6), propane (C3H8), butane (C4H 10 ), ethylene (C2H4), propylene (C3H6), acetylene (C2H2), and propylene (C3H4). The etching conditions can be adjusted appropriately depending on the object to be etched.

[0243] A capacitively coupled plasma (CCP) etching apparatus comprising parallel plate electrodes can be used as the dry etching apparatus. The capacitively coupled plasma etching apparatus comprising the parallel plate electrodes can have a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, high-frequency voltages of the same frequency can be applied to the parallel plate electrodes. As a further alternative, high-frequency voltages of different frequencies can be applied to the parallel plate electrodes. Such a CCP etching apparatus is referred to as a dual-frequency capacitively coupled plasma (DF-CCP) etching apparatus. In the DF-CCP etching apparatus, high-frequency voltages of different frequencies are applied to the parallel plate electrodes.Alternatively, different high-frequency voltages can be applied to one of the parallel plate electrodes. A dry etching device comprising a high-density plasma source can be used. As a dry etching device comprising a high-density plasma source, for example, an inductively coupled plasma (ICP) etching device can be used. The etching device can be appropriately adjusted depending on an object to be etched. Note that in the above dry etching device, a high-frequency voltage is applied to the electrode on the substrate side to generate a self-bias potential, whereby reactive ion etching can be performed. In reactive ion etching, ion species in plasma are accelerated to collide with an object to be processed, whereby etching with high anisotropy can be performed.

[0244] In the above etching step, the insulator 271A may serve as an etch stopper that protects the conductor 242A. For example, when a metal hard mask is formed over the insulator 271A in the above etching step, it is sometimes difficult to maintain the etching selectivity of the hard mask with respect to the conductor 242A when removing the hard mask. However, when the insulator 271A is formed over the conductor 242A, the insulator 271A may serve as an etch stopper that protects the conductor 242A during etching to remove the hard mask. This can prevent a curved surface from being formed between the side surface and the top surface of the conductor 242A; therefore, as shown in Fig. 1D, the end portion at the intersection between the side surface and the top surface of each of the conductors 242a and 242b to be formed later is square. The cross-sectional area of the conductor 242A is larger in the case where the end portion at the intersection of the side surface and the top surface of the conductor 242A is square than that in the case where the end portion is rounded. Furthermore, if a nitride insulator that is less likely to oxidize a metal is used for the insulator 271A, excessive oxidation of the conductor 242A can be prevented. Therefore, the resistance of the conductors 242a and 242b is reduced, so that the forward current of the transistor can be increased.

[0245] By processing the insulator 224 into an island shape, in a step to be described later, the insulator 275 can be provided in contact with the side surface of the insulator 224 and the top surface of the insulator 222. That is, the insulator 224 can be insulated from the insulator 280 by the insulator 275. Such a structure can prevent an excessive amount of oxygen and impurities such as hydrogen from penetrating the oxide semiconductor 230 from the insulator 280 through the insulator 224.

[0246] Next, the insulator 275 is formed to cover the insulator 224, the oxide semiconductor 230, the conductor 242A and the insulator 271A, and the insulator 280 is formed over the insulator 275 (see Fig. 11A to Fig. 11D). The insulating materials described above can be used for insulators 275 and 280.

[0247] Here, the insulator 275 is preferably in contact with the top of the insulator 222.

[0248] As the insulator 280, an insulator with a flat top surface is preferably formed in the following manner: An insulating film to become the insulator 280 is formed, and then the insulating film is subjected to CMP treatment. Note that a silicon nitride film may be formed over the insulator 280 by, for example, a sputtering method and then subjected to CMP treatment until the insulator 280 is exposed.

[0249] Each of the insulators 275 and 280 may be formed, for example, by a sputtering process, a CVD process, an MBE process, a PLD process, or an ALD process.

[0250] The insulator 275 is preferably formed using an insulator having a function of preventing oxygen permeation. For example, a silicon nitride film is preferably formed as the insulator 275 by a PEALD method. Alternatively, alumina may be deposited as the insulator 275 by a sputtering method, and silicon nitride may be deposited thereover by a PEALD method. When the insulator 275 has such a multilayer structure, the functions of preventing the diffusion of oxygen and impurities such as water and hydrogen can be enhanced.

[0251] In this way, the oxide semiconductor 230 and the conductor 242A can be covered with the insulator 275 having an oxygen diffusion prevention function. This can prevent direct diffusion of oxygen from the insulator 280 and the like into the oxide semiconductor 230 and the conductor 242A in a later step.

[0252] As the insulator 280, a silicon oxide film is preferably formed by a sputtering method. When an insulating film to become the insulator 280 is formed by a sputtering method in an oxygen-containing atmosphere, the insulator 280 containing excess oxygen can be formed. By using a sputtering method that does not require the use of a molecule containing hydrogen as a film-forming gas, the hydrogen concentration in the insulator 280 can be reduced. Note that the heat treatment may be performed before the formation of the insulating film. The heat treatment may be performed under reduced pressure, and the insulating film may be successively formed without exposure to air. Such treatment can remove moisture and hydrogen adsorbed on the surface of the insulator 280 and the like.The heat treatment can be carried out under the heat treatment conditions described above.

[0253] Next, the conductor 242A, the insulator 271A, the insulator 275, and the insulator 280 are processed by a lithography process, thereby forming an opening that reaches the oxide semiconductor 230 and the insulator 222 (see Fig. 12A to Fig. 12D). Here, conductor 242A is divided into conductors 242a and 242b, and insulator 271A is divided into insulators 271a and 271b. The opening formed in insulator 280 and insulator 275 overlaps with oxide semiconductor 230 and conductor 205.

[0254] The method described above can be appropriately used as a lithography method. To finely process the opening in the insulator 280, an electron beam or short-wavelength light, such as EUV light, is preferably used in the lithography method. For example, the opening is formed in the insulator 280, and the conductors 242a and 242b are formed by a method described in Fig. 13A1 to Fig. 13D2 is formed.

[0255] First, a coating film 277 is formed over the insulator 280, and a coating film 278 is formed thereover (see Fig. 13A1 and Fig. 13A2). The coating films 277 and 278 may have a function of improving the adhesion between a photoresist mask to be described later and the insulator 280. The coating films 277 and 278 are formed, for example, by a spin coating method.

[0256] A non-light-sensitive organic resin is used for the coating films 277 and 278.

[0257] Here, the coating film 278 serves as a mask in an etching treatment for processing the coating film 277. Therefore, under the etching conditions of the coating film 277, the etching rate of the coating film 278 is preferably lower than that of the coating film 277. For example, the coating film 277 is a film containing carbon, and the coating film 278 is a film containing silicon and carbon. In this embodiment, an SOC film is formed as the coating film 277, and an SOG film is formed as the coating film 278.

[0258] Note that the coating films 277 and 278 each contain an organic solvent such as alcohol at the time of application, but such contained organic substance may be reduced or removed in later steps or upon completion of the semiconductor device. Note that the coating films are provided as needed; only one of the coating films may be formed, or the coating films may not necessarily be provided in the case where a photoresist mask to be described later can function sufficiently.

[0259] Next, a photoresist mask 279 having an opening is formed over the coating film 278 by a lithography process (see Fig. 13A1 and Fig. 13A2). The photoresist mask 279 can be formed by, for example, exposing the photoresist to KrF excimer laser light, ArF excimer laser light, extreme ultraviolet (EUV) light, or the like. A liquid immersion technique may be used in which a portion between a substrate and a projection lens is filled with a liquid (e.g., water) to perform exposure. Instead of the aforementioned light, an electron beam or an ion beam may be used. Note that when an electron beam or an ion beam is used, no mask is necessary.

[0260] In the steps in Fig. 13B1 to Fig. 13D2, the object to be processed is preferably processed by a dry etching process. A dry etching process enables anisotropic etching and is therefore suitable for forming an opening with a high aspect ratio. In the case where anisotropic etching is performed, reactive ion etching, for example, is preferably performed. It should be noted that for the conditions and a device for the dry etching process, reference can be made to the above description. It should be noted that the steps in Fig. 13B1 to Fig. 13D2 should preferably be carried out successively without exposure to air. For example, processing is carried out using a multi-chamber etching device without exposure to air.

[0261] First, the coating film 278 is processed using the photoresist mask 279, thereby forming the coating film 278 with an opening. For example, in the case where an SOG film is used as the coating film 278, an etching treatment using CF4 as the etching gas may be performed with a DF-CCP etcher.

[0262] Next, the coating film 277 is processed using the coating film 278 as a mask, thereby forming the coating film 277 with an opening (see Fig. 13B1 and Fig. 13B2). For example, in the case where an SOC film is used as the coating film 277, an etching treatment using H2 and N2 as etching gases can be performed with a DF-CCP etcher. Here, the SOG film is used as the coating film 278, so that the coating film 278 can be prevented from disappearing in the etching step of the coating film 277.

[0263] The photoresist mask 279 is preferably removed during the processing of the coating film 277. Since the SOC film is used as the coating film 277, the photoresist mask 279 can be easily removed. In the case where the photoresist mask 279 remains after the formation of the coating film 277, the photoresist mask 279 is preferably removed.

[0264] Then, the insulator 280 is processed using the coating film 277 as a mask, thereby forming the insulator 280 with an opening. For example, in the case where a silicon oxide film is used as the insulator 280, an etching treatment using C4F8, C4F e , O2 and Ar as etching gases using a DF-CCP etching device.

[0265] Further, the insulators 275 and 271A are processed using the coating film 277 as a mask, thereby forming the insulators 275, 271a and 271b with an opening (see Fig. 13C1 and Fig. 13C2). For example, in the case where a silicon oxide film and a silicon nitride film are used as insulators 275 and 271A, an etching treatment using CH2F2, O2, and Ar as etching gases may be performed with a DF-CCP etcher. Conductor 242A and insulator 222 may serve as etch stoppers. Coating film 278 is preferably removed during processing of insulators 275 and 271A.

[0266] After the insulators 271a and 271b are formed, a dry etching treatment, such as ashing using oxygen plasma, is preferably performed to remove the coating film 277. However, without being limited to this step, the coating film 277 may be removed after the conductors 242a and 242b are formed.

[0267] Next, a surface oxide film of the conductor 242A is preferably removed using the insulator 280 as a mask. For example, in the case where a tantalum nitride film is used as the conductor 242A, an etching treatment using BCl3 and Cl2 as etching gases may be performed with an ICP etcher.

[0268] Further, the conductor 242A is processed using the insulator 280 as a mask, thereby forming the conductors 242a and 242b (see Fig. 13D1 and Fig. 13D2). In the case where, for example, a tantalum nitride film is used as the conductor 242A, an etching treatment using Cl2 and Ar as etching gases may be performed with an ICP etcher. The oxide semiconductor 230 and the insulator 222 may serve as etch stoppers. Here, as shown in Fig. 13D2, a curved surface may be provided between the side surface and the top surface of the oxide semiconductor 230 in the cross-sectional view of the transistor 200 in the channel width direction. That is, an end portion of the side surface and an end portion of the top surface are rounded in some cases.

[0269] In some cases, a recessed portion is formed in a portion of the oxide semiconductor 230 exposed from the conductors 242a and 242b. In other words, in the upper surface of the oxide semiconductor 230, in some cases, the height of a region located between the conductors 242a and 242b is lower than the height of a region overlapping with the conductor 242a and the height of a region overlapping with the conductor 242b.

[0270] In the above manner, the opening can be formed in the insulators 275 and 280, and the insulators 271a and 271b and the conductors 242a and 242b can be formed.

[0271] Note that an ashing treatment using oxygen plasma may be performed after processing the conductor 242A. Such an oxygen plasma treatment can remove impurities generated by the above etching treatment and diffused into the oxide semiconductor 230 or the like. The impurities are generated from a component of the object to be processed by the above etching treatment and a component contained in a gas or the like used for etching. Examples of the impurities include chlorine, fluorine, tantalum, silicon, and hafnium. When impurities adhering to the oxide semiconductor 230 are removed in this way, the electrical characteristics and reliability of the transistor can be improved.

[0272] The processing of the conductor 242A and the oxygen plasma treatment can be performed successively without exposure to air. For example, the processing is performed using a multi-chamber etching device without exposure to air.

[0273] To remove the impurities adhering to the surface of the oxide semiconductor 230 in the etching step, a cleaning treatment is preferably performed. Examples of the cleaning methods include wet cleaning using a cleaning solution or the like (wet cleaning may also be referred to as wet etching treatment), plasma treatment using plasma, and cleaning by heat treatment, and any of these cleaning methods can be appropriately combined. By the cleaning treatment, the recessed portion becomes deeper in some cases.

[0274] Wet cleaning may be performed using an aqueous solution in which one or more of oxalic acid, phosphoric acid, and hydrofluoric acid are diluted with carbonated water or pure water. Wet cleaning may be performed using an aqueous solution in which ammonia water is diluted with carbonated water or pure water. Wet cleaning may be performed with pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using such an aqueous solution, pure water, or carbonated water. As a further alternative, any of these cleaning methods may be combined as needed.

[0275] Note that in this specification and the like, in some cases, an aqueous solution in which hydrofluoric acid is diluted with pure water is referred to as dilute hydrofluoric acid, and an aqueous solution in which ammonia water is diluted with pure water is referred to as dilute ammonia water. The concentration, temperature, and the like of the aqueous solution are appropriately controlled according to an impurity to be removed, the structure of a semiconductor device to be cleaned, or the like. The concentration of ammonia in the dilute ammonia water is preferably higher than or equal to 0.01% and lower than or equal to 5%, more preferably higher than or equal to 0.1% and lower than or equal to 0.5%. The concentration of hydrogen fluoride in the dilute hydrofluoric acid is preferably higher than or equal to 0.01 ppm and lower than or equal to 100 ppm, more preferably higher than or equal to 0.1 ppm and lower than or equal to 10 ppm.

[0276] A frequency greater than or equal to 200 kHz is preferable for ultrasonic cleaning, and a frequency greater than or equal to 900 kHz is more preferable. With such a frequency, damage to the oxide semiconductor 230 and the like can be reduced.

[0277] The cleaning treatment can be performed multiple times, and the cleaning solution can be changed for each cleaning treatment. For example, diluted hydrofluoric acid or diluted ammonia water can be used for the first cleaning treatment, and pure water or carbonated water can be used for the second cleaning treatment.

[0278] As the cleaning treatment in this embodiment, wet cleaning using carbonated water is performed. This cleaning treatment enables removal of impurities adhering to the surfaces of the oxide semiconductor 230 and the like or diffused into the oxide semiconductor 230. Furthermore, the surface layer of the oxide semiconductor 230 damaged by the above etching treatment can be removed.

[0279] After etching or cleaning, heat treatment is preferably performed. The heat treatment temperature is higher than or equal to 100°C and lower than or equal to 650°C, preferably higher than or equal to 250°C and lower than or equal to 600°C, more preferably higher than or equal to 300°C and lower than or equal to 550°C, and even more preferably higher than or equal to 350°C and lower than or equal to 400°C. Note that the heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more, respectively. The heat treatment is preferably performed in an oxygen-containing atmosphere. For example, the flow rate ratio of a nitrogen gas to an oxygen gas is preferably 4:1, and the heat treatment is preferably performed at 350°C for one hour.Therefore, oxygen can be supplied to the oxide semiconductor 230 to reduce oxygen vacancies. Furthermore, the crystallinity of the oxide semiconductor 230 can be improved by the heat treatment. Furthermore, hydrogen remaining in the oxide semiconductor 230 reacts with supplied oxygen, so that the hydrogen can be removed as H2O (dehydration). This can prevent hydrogen remaining in the oxide semiconductor 230 from recombining with oxygen vacancies and forming V. O H is formed. Therefore, a transistor including the oxide semiconductor 230 can have favorable electrical characteristics and high reliability. In addition, variations in the electrical characteristics of transistors formed over the same substrate can be reduced. The heat treatment can be performed under reduced pressure. Alternatively, the heat treatment can be performed as follows: The heat treatment is performed in an oxygen atmosphere, and then another heat treatment is successively performed without exposure to air in a nitrogen atmosphere. The heat treatment can also serve as a heat treatment performed after the formation of the oxide semiconductor film 230f. Therefore, in some cases, the crystal region of the oxide semiconductor 230 grows by the heat treatment.

[0280] In the case where heat treatment is performed in a state where the oxide semiconductor 230 is in contact with the conductors 242a and 242b, in some cases, the sheet resistance in the oxide semiconductor 230 decreases in a region overlapping with the conductor 242a and in a region overlapping with the conductor 242b. Furthermore, the carrier concentration in these regions may increase. Therefore, in the oxide semiconductor 230, the resistance in the regions overlapping with the conductors 242a and 242b may be reduced in a self-aligning manner.

[0281] Even if, for example, the oxide semiconductor 230, as in Fig. 2A, has a multilayer structure, and the oxide semiconductor 230c is a metal oxide with relatively low conductivity or a metal oxide with a wide band gap, the resistance of the oxide semiconductor 230 in the regions overlapping with the conductors 242a and 242b can be reduced as described above. Therefore, the source region and the drain region can be formed in the oxide semiconductor 230c.

[0282] Next, an insulating film 250f to become the insulator 250 is formed to cover the opening formed in the insulator 280 and the like (see Fig. 14A to Fig. 14D). Here, the insulating film 250f is formed along the opening in the insulators 280 and 275. The insulating film 250f is in contact with the insulator 280, the conductors 242a and 242b, the insulators 222 and 224, and the oxide semiconductor 230.

[0283] The insulating film 250f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, the insulating film 250f is preferably formed by an ALD method. The insulating film 250f is preferably formed to have a small thickness, and variations in the thickness must be reduced. In an ALD method, a precursor and a reactant (such as an oxidizer) are alternately introduced to form a film, and the film thickness can be regulated depending on the number of repetitions of the introduction sequence, therefore, precise control of the film thickness is possible. The insulating film 250f must be formed to advantageously cover the bottom and side surfaces of the opening.An ALD process enables an atomic layer to be deposited step by step on the bottom and side surfaces of the opening, whereby the insulating film 250f can be formed in the opening with good coverage.

[0284] When the insulating film 250f is formed by an ALD method, ozone (O3), oxygen (O2), water (H2O), or the like is used as an oxidant. When an oxidant without hydrogen, such as ozone (O3) or oxygen (O2), is used, the amount of hydrogen diffused into the oxide semiconductor 230 can be reduced.

[0285] The Isolator 250 can, as in Fig. 2B and the like, have a multi-layer structure. A method for forming the insulating film 250f will be described below in the case where the insulator 250 is as shown in Fig. 2B has a four-layer structure of the insulators 250a, 250b, 250d and 250c.

[0286] First, a film to become the insulator 250a is formed to cover the opening formed in the insulator 280 and the like, and then a film to become the insulator 250b is formed over the film to become the insulator 250a. In this embodiment, an aluminum oxide film is formed by a thermal ALD method as the film to become the insulator 250a, and a silicon oxide film is formed by a PEALD method as the film to become the insulator 250b.

[0287] Next, microwave treatment is preferably performed in an oxygen-containing atmosphere. Here, microwave treatment refers, for example, to treatment using a device with a power source for generating high-density plasma using microwaves. In this specification and the like, a microwave refers to an electromagnetic wave with a frequency greater than or equal to 300 MHz and less than or equal to 300 GHz.

[0288] The microwave treatment is preferably performed, for example, with a microwave treatment device comprising a power source for generating high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably higher than or equal to 300 MHz and lower than or equal to 300 GHz, more preferably higher than or equal to 2.4 GHz and lower than or equal to 2.5 GHz, and may be, for example, 2.45 GHz. High-density oxygen radicals can be generated with high-density plasma. The electric power of the power source that applies microwaves to the microwave treatment device is preferably higher than or equal to 1000 W and lower than or equal to 10,000 W, more preferably higher than or equal to 2000 W and lower than or equal to 5000 W. The microwave treatment device may be provided with a power source that applies RF to the substrate side.Applying the RF to the side of the substrate allows oxygen ions generated by high-density plasma to be efficiently introduced into the oxide semiconductor 230.

[0289] The microwave treatment is preferably performed under reduced pressure, and the pressure is preferably higher than or equal to 10 Pa and lower than or equal to 1000 Pa, more preferably higher than or equal to 300 Pa and lower than or equal to 700 Pa. The treatment temperature is preferably lower than or equal to 750°C, more preferably lower than or equal to 500°C, and may be, for example, about 250°C. After the oxygen plasma treatment, heat treatment may be successively performed without exposure to air. The heat treatment temperature is, for example, preferably higher than or equal to 100°C and lower than or equal to 750°C, more preferably higher than or equal to 300°C and lower than or equal to 500°C.

[0290] The microwave treatment can be performed using, for example, an oxygen gas and an argon gas. Here, the flow rate ratio of oxygen (O2 / (O2+Ar)) is higher than 0% and lower than or equal to 100%. The flow rate ratio of oxygen (O2 / (O2+Ar)) is preferably higher than 0% and lower than or equal to 50%. The flow rate ratio of oxygen (O2 / (O2+Ar)) is more preferably higher than or equal to 10% and lower than or equal to 40%. The flow rate ratio of oxygen (O2 / (O2+Ar)) is even more preferably higher than or equal to 10% and lower than or equal to 30%. By performing the microwave treatment in an oxygen-containing atmosphere in this way, the carrier concentration of the region of the oxide semiconductor 230 exposed in the opening can be reduced.By preventing an excessive amount of oxygen from being introduced into the chamber during microwave treatment, an excessive reduction in the carrier concentration of the oxide semiconductor 230 can be prevented.

[0291] Through microwave treatment in an oxygen-containing atmosphere, an oxygen gas is converted into plasma using a high-frequency wave, such as a microwave or RF, and the oxygen plasma acts on a region of the oxide semiconductor 230, which region is located between the conductors 242a and 242b. Through the effects of the plasma, a microwave, and the like, V O H in the area can be divided into oxygen vacancies and hydrogen, and the hydrogen can be removed from the area. Here, in the case where the Fig. 2B and the like is used, the film to become the insulator 250a is preferably an insulating film having a function of capturing or fixing hydrogen (e.g., aluminum oxide). With such a structure, hydrogen generated by the microwave treatment can be captured or fixed in the film to become the insulator 250a. In this way, the amount of V O H contained in the channel formation region can be reduced. As a result, oxygen vacancies and V O H in the channel formation region to reduce the carrier concentration. Furthermore, oxygen radicals generated by the oxygen plasma can be supplied to oxygen vacancies formed in the channel formation region, thereby further reducing oxygen vacancies and reducing the carrier concentration in the channel formation region.

[0292] Oxygen implanted into the channel formation region takes various forms, such as an oxygen atom, an oxygen molecule, an oxygen ion, and an oxygen radical (also referred to as an O radical, which is an atom, molecule, or ion with an unpaired electron). The oxygen implanted into the channel formation region preferably takes one or more of the above forms. An oxygen radical is particularly preferred. In addition, the insulator 250 can have a higher film quality, which increases the reliability of the transistor.

[0293] On the other hand, the oxide semiconductor 230 includes a region overlapping with the conductor 242a or 242b. This region can serve as a source region or a drain region. Here, the conductors 242a and 242b preferably serve as blocking films for preventing the effect of high-frequency waves such as microwaves or RF, oxygen plasma, or the like during microwave processing in an oxygen-containing atmosphere. Therefore, the conductors 242a and 242b preferably have a function of blocking electromagnetic waves of greater than or equal to 300 MHz and less than or equal to 300 GHz, for example, greater than or equal to 2.4 GHz and less than or equal to 2.5 GHz.

[0294] Since the conductors 242a and 242b prevent the effect of high-frequency waves such as microwaves or RF, oxygen plasma, or the like, the effect does not reach the region of the oxide semiconductor 230 that overlaps with the conductor 242a or 242b. Therefore, a reduction of V O H and an excess amount of oxygen are not introduced into the source and drain regions due to the microwave treatment, preventing a reduction in the carrier concentration.

[0295] In the above manner, oxygen vacancies and V O H can be selectively removed from the channel formation region in the oxide semiconductor, whereby the channel formation region can be an i-type region or a substantially i-type region. Furthermore, an excessive amount of oxygen can be prevented from being supplied to the regions serving as the source region and drain region, and the conductivity before microwave treatment (the state of the low-resistance regions) can be maintained. As a result, a change in the electrical characteristics of the transistor can be prevented, and therefore, fluctuations in the electrical characteristics of the transistors in the substrate plane can be prevented.

[0296] The microwave treatment improves the quality of the films to become insulators 250a and 250b, thereby preventing hydrogen, water, impurities, and the like from diffusing. Accordingly, in the subsequent step, such as the formation of a conductive film to become conductor 260, or in the subsequent treatment such as heat treatment, hydrogen, water, impurities, and the like can be prevented from diffusing into the oxide semiconductor 230 and the like. Thus, by improving the film quality of insulator 250, the reliability of the transistor can be improved.

[0297] Next, a film to become the insulator 250d is formed over the film to become the insulator 250b. In this embodiment, a hafnium oxide film is formed as the film to become the insulator 250d by a thermal ALD method. Alternatively, a hafnium-zirconium oxide film may be formed as the film to become the insulator 250d by a thermal ALD method. After the film to become the insulator 250d is formed, microwave treatment may be performed again.

[0298] Subsequently, a film that will become the insulator 250c is formed over the film that will become the insulator 250d. In this embodiment, a silicon nitride film is formed by a PEALD method as the film that will become the insulator 250c. In this way, the insulating film 250f comprising the films that will become the insulators 250a to 250d can be formed.

[0299] Although an example is described above in which microwave treatment is performed after the formation of the film to become the insulator 250b and the formation of the film to become the insulator 250d, the present invention is not limited to the example. The microwave treatment may be performed after the formation of the film to become the insulator 250c. Alternatively, the microwave treatment may be performed before the formation of the film to become the insulator 250a. Alternatively, microwave treatment may be performed three or more times. In some cases, the microwave treatment may also serve as the heat treatment described in Embodiment 2. Therefore, in some cases, the crystal region of the oxide semiconductor 230 grows by the microwave treatment.

[0300] After the microwave treatment, heat treatment may be performed while maintaining the reduced pressure. Such treatment enables hydrogen in the insulating film and the oxide semiconductor 230 to be efficiently removed. Alternatively, the step of performing the microwave treatment and then performing the heat treatment may be repeated a plurality of times while maintaining the reduced pressure. Repeating the heat treatment enables hydrogen in the insulating film and the oxide semiconductor 230 to be more efficiently removed. Note that the heat treatment temperature is preferably higher than or equal to 300°C and lower than or equal to 500°C. The heat treatment may also serve as the heat treatment described in Embodiment 2. Therefore, in some cases, the crystal region of the oxide semiconductor 230 grows by the heat treatment.

[0301] Next, a conductive film 260f is formed to become the conductor 260 (see Fig. 14A to Fig. 14D). The conductive film 260f can be formed using any of the above conductive materials by a sputtering method, a CVD method, an MBE method, a PLD method, a plating method, or an ALD method. For example, a titanium nitride film and a tungsten film are stacked by a CVD method. As shown in Fig. As shown in Figure 2A, the conductor 260 may have a multilayer structure composed of the titanium nitride conductor 260a and the tungsten conductor 260b. Note that the conductive film 260f may be formed while heating the substrate. The substrate heating may also serve as the heat treatment described in Embodiment 2. Therefore, in some cases, the crystal region of the oxide semiconductor 230 grows due to the substrate heating.

[0302] Then, the insulating film 250f and the conductive film 260f are polished by CMP treatment until the insulator 280 is exposed. That is, portions of the insulating film 250f and the conductive film 260f exposed from the opening are removed. Therefore, the insulator 250 and the conductor 260 (the conductors 260a and 260b) are formed in the opening overlapping with the conductor 205 (see Fig. 15A to Fig. 15D).

[0303] As a result, insulator 250 is in contact with conductors 242a and 242b, oxide semiconductor 230, and insulators 224 and 222 in the opening. Conductor 260 is provided to fill the opening, with insulator 250 interposed therebetween. In this way, transistor 200 is formed.

[0304] Next, the insulator 282 is formed over the insulator 250, the conductor 260 and the insulator 280 (see Fig. 16A to Fig. 16D). The insulator 282 can be formed, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 282 is preferably formed by a sputtering method. Since no molecule containing hydrogen is used as a film-forming gas in a sputtering method, the concentration of hydrogen in the insulator 282 can be reduced.

[0305] As in Fig. 2A, the insulator 282 preferably has a multilayer structure composed of the insulators 282a and 282b. Here, the insulator 282a is preferably formed by an ALD process, and the insulator 282b is preferably formed by a sputtering process.

[0306] In this embodiment, an aluminum oxide film is formed as the insulator 282a by a thermal ALD process. The thickness of the insulator 282a is greater than or equal to 1 nm and less than or equal to 20 nm, preferably greater than or equal to 3 nm and less than or equal to 10 nm.

[0307] When the insulator 282a is formed by an ALD method, the insulator 282a can be formed without excessive damage to the formation surface. This can prevent excessive damage to the upper end portion of the insulator 250 and the top surface of the conductor 260, improving the electrical characteristics and reliability of the transistor 200.

[0308] When the insulator 282a is formed by an ALD method, the insulator 282a can be formed without adding oxygen to the insulator 280. In this way, an excessive amount of oxygen can be prevented from being added to the insulator 280. Thus, the electrical characteristics and reliability of the transistor 200 can be improved.

[0309] In this embodiment, an aluminum oxide film is formed as the insulator 282b by a sputtering process. Since no molecule containing hydrogen is used as the film-forming gas in a sputtering process, the concentration of hydrogen in the insulator 282 can be reduced.

[0310] By forming the insulator 282b by a sputtering method in an oxygen-containing atmosphere, oxygen can be added to the insulator 280 during formation. Therefore, excess oxygen can be contained in the insulator 280. The formation of the insulator 282b is preferably performed while heating the substrate. Here, when the insulator 282b is formed over the insulator 282a, oxygen is added through the insulator 282a; thus, the amount of oxygen supplied to the insulator 280 can be controlled. With a greater thickness of the insulator 282a, the addition of oxygen is more likely to be prevented, and the amount of oxygen supplied to the insulator 280 decreases. With a smaller thickness of the insulator 282a, the addition of oxygen is less likely to be prevented, and the amount of oxygen supplied to the insulator 280 increases.For example, when the thickness of the insulator 282a is within the above range, a sufficient amount of oxygen can be supplied to the oxide semiconductor 230, and an excessive amount of oxygen can be prevented from being supplied to the oxide semiconductor 230. Thus, the reliability and electrical characteristics of the transistor 200 can be improved. Note that when forming the insulator 282b, oxygen may be added not only to the insulator 280 but also to the upper end portion of the insulator 250.

[0311] When the insulator 282b is formed over the insulator 282a, the upper end portion of the insulator 250 and the top surface of the conductor 260 can be protected from an impact of the ion collision caused by forming the insulator 282b by sputtering.

[0312] The aluminum oxide film is formed using an aluminum target in an atmosphere containing an oxygen gas. The amount of oxygen implanted into the insulator 280 can be controlled depending on the amount of bias power applied to the substrate in a sputtering process. For example, with the lower bias power, the amount of oxygen supplied to the insulator 280 becomes smaller, and the amount of oxygen is easily saturated even when the insulator 282b has a small thickness. Furthermore, with the higher bias power, the amount of oxygen implanted into the insulator 280 increases. With the lower bias power, the amount of oxygen implanted into the insulator 280 can be decreased.It should be noted that when the substrate bias is applied by an RF power source, the RF frequency is preferably greater than or equal to 10 MHz. A typical frequency is 13.56 MHz. With higher RF frequencies, damage to the substrate can be reduced.

[0313] Note that heat treatment may be performed before forming the insulator 282b. The heat treatment may be performed under reduced pressure, and the insulator 282b may be successively formed without exposure to air. Such treatment allows moisture and hydrogen adsorbed on the surface of the insulator 280 to be captured or fixed by the insulator 282a, so that the moisture concentration and hydrogen concentration in the insulator 280 can be reduced. The heat treatment temperature is preferably higher than or equal to 100°C and lower than or equal to 400°C. In this embodiment, the heat treatment temperature is 250°C.

[0314] Next, the insulator 283 is formed over the insulator 282 (see Fig. 16A to Fig. 16D). The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 283 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of a molecule containing hydrogen as a film-forming gas, the hydrogen concentration in the insulator 283 can be reduced. In this embodiment, a silicon nitride film is formed as the insulator 283 by a sputtering method.

[0315] In this embodiment, a silicon nitride film is formed as the insulator 283 by a sputtering method, and an aluminum oxide film is formed as the insulator 282 by a thermal ALD method and a sputtering method. When silicon nitride having a hydrogen diffusion prevention function is used for the insulator 283, hydrogen can be prevented from diffusing from a layer above the transistor 200. Furthermore, by using aluminum oxide having a hydrogen trapping or fixing function for the insulator 282, hydrogen contained in the insulator 280 or the like can be trapped or fixed by the insulator 282. Therefore, the hydrogen concentration in the oxide semiconductor 230 and the surrounding area can be reduced.

[0316] Next, the insulator 285 is formed over the insulator 283 (see Fig. 16A to Fig. 16D). The insulator 285 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 285 is preferably formed by a sputtering method. Since no molecule containing hydrogen is used for a film-forming gas in a sputtering method, the concentration of hydrogen in the insulator 285 can be reduced. In this embodiment, a silicon oxide film is formed as the insulator 285 by a sputtering method.

[0317] Here, the insulators 282, 283, and 285 are preferably successively formed by a sputtering method without exposure to air. The film formation without exposure to air can prevent impurities or moisture in the air from adhering to the insulators 282, 283, and 285, so that the interface between the insulators 282 and 283, the interface between the insulators 283 and 285, and the surroundings of the interfaces can be kept clean.

[0318] Then, an opening reaching the conductor 242a is formed in the insulators 271a, 275, 280, 282, 283, and 285, and an opening reaching the conductor 242b is formed in the insulators 271b, 275, 280, 282, 283, and 285. The openings are formed by a lithography method. To form the openings, the above insulators are preferably processed by a dry etching method. A dry etching method enables anisotropic etching and is therefore suitable for forming an opening with a high aspect ratio. In the case where anisotropic etching is performed, reactive ion etching, for example, is preferably performed. Note that for the conditions and a device for the dry etching method, reference can be made to the above description. It should be noted that, for example, the shape of the openings in the plan view may be a circular shape, an almost circular shape, such ascan be an elliptical shape, a polygonal shape such as a square shape, or a polygonal shape such as a square shape with rounded corners.

[0319] Subsequently, heat treatment is performed after the openings are formed. The heat treatment temperature is higher than or equal to 100°C and lower than or equal to 600°C, preferably higher than or equal to 250°C and lower than or equal to 550°C, more preferably higher than or equal to 350°C and lower than or equal to 450°C. Note that the heat treatment is preferably performed in a nitrogen gas atmosphere or an inert gas atmosphere. The heat treatment is performed in a state where the conductors 242a and 242b are exposed; therefore, the heat treatment is preferably performed in an atmosphere containing no oxidizing gas or no oxygen gas. For example, heat treatment is preferably performed at 400°C for one hour in a nitrogen gas atmosphere. The heat treatment can be performed under reduced pressure.Through the heat treatment, oxygen contained in the insulator 280 can be supplied to the oxide semiconductor 230 through the insulator 250. Therefore, oxygen vacancies in the channel formation region of the oxide semiconductor 230 can be reduced. The heat treatment can also serve as the heat treatment described in Embodiment 2. Accordingly, in some cases, the crystal region of the oxide semiconductor 230 grows through the heat treatment.

[0320] Here, the side surface of the insulator 280 is exposed in the opening; thus, oxygen contained in the insulator 280 diffuses outward through the heat treatment, so that the amount of oxygen contained in the insulator 280 can be controlled. On the other hand, oxygen does not diffuse outward from the top surface of the insulator 280 because the insulators 282 and 283, each having an oxygen barrier property, are provided above the insulator 280. Consequently, oxygen can be prevented from excessively diffusing outward from the insulator 280, and thus oxygen vacancies can be prevented from forming in the insulator 280. The oxide semiconductor 230 and the conductors 242a and 242b are covered with the insulator 275. This can prevent an excessive amount of oxygen from directly diffusing from the insulator 280 into the oxide semiconductor 230 and the conductors 242a and 242b during the above heat treatment.

[0321] As described above, when forming the insulator 282b, oxygen is added to the insulator 280 through the insulator 282a, whereby the amount of oxygen added to the insulator 280 can be controlled. Furthermore, oxygen diffuses outward from the side surface of the insulator 280 through the heat treatment, whereby the amount of oxygen in the insulator 280 can be appropriate. In this way, oxygen is supplied to the oxide semiconductor 230 from the insulator 280 having a regulated amount of oxygen, whereby an appropriate amount of oxygen can be supplied to the oxide semiconductor 230. Accordingly, oxygen vacancies in the oxide semiconductor 230 can be reduced, and an excessive amount of oxygen can be prevented from being supplied to the oxide semiconductor 230. Thus, the electrical characteristics and reliability of the transistor 200 can be improved.Furthermore, a step of exposing the side surface of the insulator 280 can also serve as a step of forming openings in which the conductor 240a and the conductor 240b are embedded; therefore, the manufacturing process of the semiconductor device can be simplified.

[0322] Through the heat treatment, hydrogen contained in the insulators 280 and 250 and the oxide semiconductor 230 moves toward the insulator 282 and is trapped in the insulator 282. In other words, hydrogen contained in the insulators 280 and 250 and the oxide semiconductor 230 diffuses into the insulator 282. Accordingly, the hydrogen concentration in the insulator 282 increases, while the hydrogen concentrations in the insulators 280 and 250 and the oxide semiconductor 230 decrease. Note that the insulator 283 is provided in contact with the top surface of the insulator 282, which can prevent the intrusion of impurities such as moisture or hydrogen from a component above the insulator 283 during the heat treatment.Through the heat treatment, hydrogen contained in the insulators 216 and 224 and the oxide semiconductor 230 moves toward the insulator 222 and is trapped in the insulator 222. In other words, hydrogen contained in the insulators 216 and 224 and the oxide semiconductor 230 diffuses into the insulator 222. Accordingly, the hydrogen concentration in the insulator 222 increases, while the hydrogen concentrations in the insulators 216 and 224 and the oxide semiconductor 230 decrease. Note that the insulator 221 is provided in contact with the bottom surface of the insulator 222, which can prevent the intrusion of moisture or impurities such as hydrogen from below the insulator 221, which might be caused by the heat treatment.

[0323] Next, an insulating film to become the insulators 241a and 241b is formed along the shape of the openings. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film to become the insulators 241a and 241b is formed in the openings with a high aspect ratio and is therefore preferably formed by an ALD method. The insulating film to become the insulators 241a and 241b preferably has a function of preventing oxygen transmission. For example, a silicon nitride film is preferably formed by a PEALD method. Silicon nitride is particularly preferred because of its high hydrogen barrier property.

[0324] Next, the insulating film is anisotropically etched to form the insulators 241a and 241b. Here, the insulator 241a is formed to cover a sidewall of the opening above the conductor 242a, and the insulator 241b is formed to cover a sidewall of the opening above the conductor 242b. As anisotropic etching for the insulating film to become the insulators 241a and 241b, for example, a dry etching method is performed. For example, reactive ion etching is preferably performed. By providing the insulators 241a and 241b at the sidewall portions of the openings, oxygen can be prevented from entering from the outside and the conductors 240a and 240b formed in the next step can be prevented from being oxidized. Furthermore, impurities such as nitrous oxide can be prevented from entering the insulating film.Water and hydrogen contained in the insulator 280 or the like diffuse into the conductors 240a and 240b. Note that a part of each of the top surfaces of the conductors 242a and 242b may have a depressed portion due to the anisotropic etching.

[0325] Subsequently, a conductive film to become the conductors 240a and 240b is formed. It is desirable that the conductive film have a multilayer structure including a conductor with a function of preventing the transmission of impurities such as water or hydrogen. For example, a multilayer structure composed of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like may be used. The conductive film to become the conductors 240a and 240b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0326] Subsequently, the conductive film to become the conductors 240a and 240b is partially removed by CMP treatment, thereby exposing the top surface of the insulator 285. As a result, the conductive film remains only in the openings, whereby the conductors 240a and 240b, each having a flat top surface, can be formed (see Fig. 1A to Fig. 1D). CMP treatment allows a portion of the top surface of insulator 285 to be removed.

[0327] After the formation of the conductors 240a and 240b, a heat treatment may further be performed. The heat treatment may be performed under conditions similar to those for the above heat treatment. Through the heat treatment, the amount of oxygen supplied to the oxide semiconductor 230 can be regulated. Thus, the reliability and electrical characteristics of the transistor 200 can be improved.

[0328] Through the above steps, the semiconductor device formed in Fig. 1A to Fig. 1D.

[0329] The semiconductor device of this embodiment includes an OS transistor. In this embodiment, an indium-containing oxide (e.g., indium oxide, indium gallium oxide, indium zinc oxide, indium gallium zinc oxide, or indium gallium tin zinc oxide) is used for an oxide semiconductor layer of the OS transistor, whereby a semiconductor device with high field-effect mobility can be provided. For example, the electrical characteristics, forward current, S value, and frequency characteristics of the transistor can be improved. Furthermore, a highly reliable semiconductor device can be provided.

[0330] This embodiment may be combined with any of the other embodiments as needed. Where a plurality of structural examples are shown in one embodiment in this specification, the structural examples may be combined as needed. (Embodiment 2)

[0331] In this embodiment, an oxide semiconductor that can be used for a semiconductor layer of a transistor is described. As the oxide semiconductor of one embodiment of the present invention, a single layer or a stacked layer of a metal oxide can be used. Note that in an oxide semiconductor with a multilayer structure, it is difficult to detect a boundary between stacked films in some cases, as described later. [metal oxide]

[0332] The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), more preferably indium, as its main component. The metal oxide preferably contains two or three elements selected from indium, an element M, and zinc, and more preferably contains indium and zinc as its main components. Here, the metal oxide contains indium and zinc as its main components and may further contain the element M. The element M is a metal element or a semimetal element having a high binding energy to oxygen, such as a metal element or a semimetal element whose binding energy to oxygen is higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide of one embodiment of the present invention preferably comprises one or more selected from indium, gallium, and zinc. In this specification and the like, a metal element and a semi-metal element may be collectively referred to as a "metal element," and a "metal element" in this specification and the like may include a semi-metal element.

[0333] Examples of the metal oxide of one embodiment of the present invention include indium zinc oxide (also referred to as In-Zn oxide or IZO (registered trademark)), indium tin oxide (also referred to as In-Sn oxide or ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (also referred to as In-Ga-Sn oxide or IGTO), indium aluminum zinc oxide (also referred to as In-Al-Zn oxide or IAZO), indium tin zinc oxide (also referred to as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (also called In-Ga-Zn oxide or IGZO), indium tin oxide containing silicon oxide (ITSO), indium gallium tin zinc oxide (also called In-Ga-Sn-Zn oxide or IGZTO) and indium gallium aluminum zinc oxide (also called In-Ga-Al-Zn oxide, IGAZO or IAGZO).Alternatively, for example, gallium zinc oxide (also referred to as Ga-Zn oxide or GZO), aluminum zinc oxide (also referred to as Al-Zn oxide or AZO), gallium tin oxide (Ga-Sn oxide), or aluminum tin oxide (Al-Sn oxide) may be used. Indium oxide may be used as the metal oxide of one embodiment of the present invention. Alternatively, gallium oxide, zinc oxide, or the like may be used as the metal oxide of one embodiment of the present invention.

[0334] When the indium content in the metal oxide is increased, the transistor can have a high forward current and excellent frequency characteristics.

[0335] Instead of indium, the metal oxide may contain one or more types of metal elements whose periodic number is large in the periodic table. Alternatively, in addition to indium, the metal oxide may contain one or more types of metal elements whose periodic number is large in the periodic table. The greater the overlap between orbitals of metal elements, the more likely the metal oxide is to have high carrier conductivity. Therefore, if a metal element with a large periodic number in the periodic table is included in the metal oxide, the field effect mobility of the transistor can be increased in some cases. Examples of the metal element with a large periodic number in the periodic table include metal elements belonging to period 5 and metal elements belonging to period 6.Specific examples of the metallic element include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. It should be noted that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are referred to as light rare earth elements.

[0336] The metal oxide may contain one or more types selected from non-metal elements. A transistor containing the metal oxide containing a non-metal element can, in some cases, exhibit high field-effect mobility. Examples of the non-metal element include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0337] A metal oxide with a high zinc content exhibits high crystallinity, which can prevent the diffusion of impurities in the metal oxide. Consequently, changes in the electrical properties of the transistor are suppressed, and the transistor can exhibit high reliability.

[0338] A high content of the element M in the metal oxide can prevent the formation of oxygen vacancies in the metal oxide. Accordingly, the generation of charge carriers due to oxygen vacancies is prevented, which reduces the transistor's off-state current. Furthermore, changes in the transistor's electrical properties can be reduced, thus improving transistor reliability.

[0339] A structural example of an oxide semiconductor that enables the field-effect mobility of a transistor is described below. For example, a multilayer structure of indium oxide and IGZO is preferably used. Specifically, the oxide semiconductor preferably contains indium oxide and IGZO over the indium oxide. Furthermore, IGZO containing nitrogen is preferably used as the oxide semiconductor. For example, IGZO containing nitrogen can be formed by performing N2O plasma treatment during or after the deposition of IGZO. For the oxide semiconductor, at least one of indium oxide, In-Ga oxide, In-Zn oxide, and IGZTO is preferably used.

[0340] In this embodiment, In-M-Zn oxide is described as an example of the metal oxide in some cases.

[0341] The oxide semiconductor of one embodiment of the present invention preferably comprises a metal oxide having crystallinity. Examples of the structure of a metal oxide having crystallinity include a c-axis aligned crystalline (CAAC) structure, a polycrystalline structure, and a nanocrystalline (nanocrystalline, nc) structure. By using a metal oxide having crystallinity for the oxide semiconductor, the density of defect states in the oxide semiconductor can be reduced. This can improve the reliability of a transistor comprising the oxide semiconductor of one embodiment of the present invention, thereby improving the reliability of a semiconductor device comprising the transistor.

[0342] Note that there is no particular limitation on the crystallinity of the metal oxide contained in the oxide semiconductor. For example, in some cases, the oxide semiconductor contains at least one of an amorphous semiconductor (a semiconductor with an amorphous structure), a single-crystal semiconductor (a semiconductor with a single-crystal structure), and a semiconductor with crystallinity other than single-crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor partially comprising crystal regions). The oxide semiconductor with crystallinity can prevent deterioration of transistor characteristics in some cases.

[0343] The crystallinity of the oxide semiconductor can be analyzed using, for example, an X-ray diffraction (XRD) pattern, a transmission electron microscope (TEM) image, or an electron diffraction (ED) pattern. Alternatively, these methods can be combined as needed to be used for analysis.

[0344] The oxide semiconductor of one embodiment of the present invention preferably comprises a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals each having a hexagonal crystal structure) are aligned with respect to the c-axis and are connected to each other without alignment in the ab plane. According to a high-resolution TEM image (also called a multi-wavelength interference image) of a cross section of an oxide semiconductor having the CAAC structure, metal atoms are arranged layered in crystal parts. Therefore, the oxide semiconductor having the CAAC structure can also be regarded as having a structure comprising the layered crystal parts.

[0345] The CAAC structure is formed, for example, such that the c-axis is perpendicular or substantially perpendicular to a formation surface or the surface of an oxide semiconductor. In the CAAC structure, metal atoms are layered in a direction parallel or substantially parallel to the formation surface. In a region having the CAAC structure, an angle formed by the c-axis and the formation surface is preferably within 90° ± 20° (greater than or equal to 70° and less than or equal to 110°), more preferably within 90° ± 15° (greater than or equal to 75° and less than or equal to 105°), even more preferably within 90° ± 10° (greater than or equal to 80° and less than or equal to 100°), and even more preferably within 90° ± 5° (greater than or equal to 85° and less than or equal to 95°).

[0346] In the case where the oxide semiconductor has the CAAC structure, a group of bright spots (specifically, bright spots arranged in layers) reflecting a layered arrangement of metal atoms is observed in a cross-sectional TEM image of the oxide semiconductor. Specifically, a state is observed in which bright spots are arranged in layers in the direction parallel or substantially parallel to the formation surface.

[0347] When the oxide semiconductor with the CAAC structure is subjected to electron diffraction, spots showing alignment with respect to the c-axis (bright spots) are observed in the electron diffraction pattern.

[0348] A fast Fourier transform (FFT) pattern obtained by FFT processing on a TEM image reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0349] When a cross-sectional TEM image of an oxide semiconductor having a CAAC structure is obtained and each region of the cross-sectional TEM image is subjected to FFT processing to form an FFT pattern, the crystal axis direction in each region can be calculated from the obtained FFT pattern. Specifically, the direction of a line segment connecting two points having high luminance and substantially the same distance from the center among points observed in the obtained FFT pattern is referred to as the crystal axis direction.A region in which an angle formed by the crystal axis direction calculated from the FFT pattern and the formation surface is preferably greater than or equal to 70° and less than or equal to 110° (within 90° ± 20°), more preferably greater than or equal to 75° and less than or equal to 105° (within 90° ± 15°), still more preferably greater than or equal to 80° and less than or equal to 100° (within 90° ± 10°), and even more preferably greater than or equal to 85° and less than or equal to 95° (within 90° ± 5°) can be regarded as having a CAAC structure.

[0350] When the oxide semiconductor having the CAAC structure is observed from the direction perpendicular to the formation surface by using the TEM image, a triangular or hexagonal atom arrangement and crystallinity in the ab plane are observed. [Composition of a metal oxide]

[0351] The metal oxide of one embodiment of the present invention preferably contains indium (In), more preferably it has a high In content. Using a metal oxide with a high In content as the oxide semiconductor can increase the forward current of the transistor and improve the frequency characteristics of the transistor. For example, indium oxide is preferably used as the oxide semiconductor.

[0352] The metal oxide of one embodiment of the present invention may contain the element M. When the metal oxide contains the element M, formation of oxygen vacancies in the metal oxide can be prevented. Therefore, the reliability of the transistor comprising the oxide semiconductor can be increased.

[0353] For example, In-Zn oxide containing a small amount of the element M can be used as an oxide semiconductor. Specifically, it is possible to use a metal oxide with an atomic ratio of In:Ga:Zn = 4:0.1:1 or close to it, In:Ga:Zn = 2:0.1:1 or close to it, or In:Ga:Zn = 1:0.1:1 or close to it. It is also possible to use a metal oxide with an atomic ratio of In:Sn:Zn = 4:0.1:1 or close to it, In:Sn:Zn = 2:0.1:1 or close to it, or In:Sn:Zn = 1:0.1:1 or close to it.

[0354] In addition, In-Zn oxide containing the element M can be used as an oxide semiconductor. Specifically, it is possible to use a metal oxide with an atomic ratio of In:M:Zn = 1:1:1 or close to it, In:M:Zn = 1:1:1.2 or close to it, In:M:Zn = 1:1:0.5 or close to it, In:M:Zn = 1:1:2 or close to it, In:M:Zn = 4:2:3 or close to it, In:M:Zn = 1:3:2 or close to it, or In:M:Zn = 1:3:4 or close to it.

[0355] It should be noted that when the metal oxide is deposited by a sputtering process, the composition of the deposited metal oxide may differ from that of a sputtering target. In particular, the zinc content in the deposited metal oxide may be reduced to approximately 50% of that of the sputtering target.

[0356] In the case where a film of a metal oxide containing a variety of metal elements, such as In-Ga-Zn oxide, is formed by an ALD method, the cycle ratio of precursors containing respective metal elements can be adjusted according to the composition of the target. To form an In-Ga-Zn oxide film with an atomic ratio of In:Ga:Zn = 1:3:2, for example, one cycle of deposition using an In-containing precursor and an oxidant treatment, three cycles of deposition using a Ga-containing precursor and an oxidant treatment, and two cycles of deposition using a Zn-containing precursor and an oxidant treatment may be performed.It should be noted that in some cases, the atomic ratio of the metal elements in the formed metal oxide film does not match the cycle ratio of the precursors containing the respective metal elements.

[0357] The compositional analysis of the metal oxide used for the oxide semiconductor can be performed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, these methods can be combined to be used for analysis. Regarding an element whose content is low, the actual content may differ from the content obtained by analysis due to the influence of the analysis accuracy. For example, in the case where the content of the element M is low, the content of the element M obtained by analysis may be lower than the actual content.

[0358] The oxide semiconductor of one embodiment of the present invention may have a multilayer structure composed of two or more layers. In the case where the oxide semiconductor has a two-layer structure composed of a first layer and a second layer above the first layer, the composition of the second layer is preferably different from that of the first layer. In the case where the oxide semiconductor has a three-layer structure composed of a first layer, a second layer above the first layer, and a third layer above the second layer, the composition of the second layer is preferably different from those of the first layer and the third layer. Note that the composition of the first layer may be the same as that of the third layer. Alternatively, the first layer and the third layer may have different compositions.

[0359] The metal oxide described above can be used for each of the first to third layers.

[0360] For the second layer, for example, indium oxide, In-Zn oxide, or In-Zn oxide containing a small amount of the element M can be used. By increasing the In content in the second layer, the forward current and frequency characteristics can be improved.

[0361] The conduction band minimum of each of the first layer and the third layer is preferably positioned closer to the vacuum level than the conduction band minimum of the second layer. In other words, the energy of the conduction band minimum of each of the first layer and the third layer is preferably lower than the energy of the conduction band minimum of the second layer. In this case, the second layer is arranged between the first layer and the third layer, each of which has a conduction band minimum positioned closer to the vacuum level, and the second layer can primarily serve as a current path (channel).

[0362] When the second layer is disposed between the first layer and the third layer, carriers trapped at the interfaces between the second layer and the other layers and their surroundings can be reduced. Furthermore, the channel can be distanced from the surface of a gate insulating layer, so that the influence of surface scattering can be reduced. Consequently, a buried-channel transistor can be achieved in which a channel is distanced from the interface with an insulating layer, thereby increasing the field-effect mobility. Furthermore, the influence of interface states that may form on the channel backside is reduced, so that light deterioration (e.g., light negative bias deterioration) of the transistor can be prevented and the reliability of the transistor can be increased.

[0363] For example, a band diagram of the Fig. 2A, which comprises the oxide semiconductors 230a to 230c, and its surroundings as shown in Fig. 17 shown. In Fig. 17, the vertical axis represents energy, and the horizontal direction represents the thickness direction of a central portion of a channel formation region. Fig. 17 shows a valence band maximum (VBM) and a conduction band minimum (CBM) of each of the oxide semiconductors 230a to 230c and the insulator 250 in a state where no voltage is applied between the gate and the source. Fig. 17, a vacuum level Vac is represented by a dashed line.

[0364] It should be noted that the energy of the valence band maximum and the energy of the conduction band minimum change depending on constituent elements and compositions of the oxide semiconductors 230a to 230c and the insulator 250; therefore, the relationship between energy levels of the valence band maximum and the relationship between energy levels of the conduction band minimum are mainly described from the band diagram in Fig. 17 described.

[0365] As in Fig. 17, the oxide semiconductor 230b is arranged between the oxide semiconductors 230a and 230c, each having a conduction band minimum positioned closer to the vacuum level than that of the oxide semiconductor 230b, according to certain constituent elements and compositions of the oxide semiconductors 230a to 230c. This structure enables a buried channel. That is, in this structure, a path through which a larger amount of current (electrons are Fig. 17 as a charge carrier) flows through the oxide semiconductor 230b. Consequently, for example, the forward current or reliability can be increased.

[0366] For example, in the case where a buried channel is formed using the first to third layers, a metal oxide having a higher Ga content may be used for the first layer and the third layer than for the second layer. Specifically, for each of the first layer and the third layer, a metal oxide having an atomic ratio of In:Ga:Zn = 1:1:1 or close thereto, a metal oxide having an atomic ratio of In:Ga:Zn = 1:3:2 or close thereto, or a metal oxide having an atomic ratio of In:Ga:Zn = 1:3:4 or close thereto may be used, respectively. Alternatively, Ga-Zn oxide or gallium oxide may be used. When the Ga content in the first layer and the third layer is increased, the conduction band minimum of each of the first layer and the third layer is positioned closer to the vacuum level than the conduction band minimum of the second layer in some cases.

[0367] By increasing the Ga content in the first layer and the third layer, the hydrogen barrier properties of the first layer and the third layer can be improved. Therefore, hydrogen can be prevented from diffusing from below the first layer or above the third layer into the second layer. Furthermore, by increasing the Ga content in the first layer and the third layer, impurities such as hydrogen or water contained in the oxide semiconductor can be reduced by the heat applied after the oxide semiconductor is formed.

[0368] By increasing the Ga content in the first layer and the third layer, the oxygen barrier property in the first layer and the third layer can be enhanced. Therefore, oxygen release from the second layer where the channel is formed is prevented, thereby preventing oxygen vacancies from forming in the second layer or increasing the amount of oxygen vacancies in the second layer. Consequently, the transistor can exhibit favorable electrical properties.

[0369] When the Ga content in the first layer is increased, the resistivity of the first layer may be higher than that of the second layer in some cases. In the case where the first layer is provided on the channel backside, providing a high resistivity layer as the first layer can prevent the threshold voltage from shifting in the negative direction or the forward current from decreasing. Accordingly, the threshold voltage of the transistor shifts in the positive direction, so that the transistor can exhibit normally-off characteristics. In the above manner, the electrical characteristics and reliability of the transistor can be improved.

[0370] The band gap of the metal oxide can be evaluated using optical analysis with a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS). Alternatively, these methods can be combined as needed for analysis. The electron affinity, or conduction band minimum, can be obtained from a band gap and an ionization potential, which is the difference in energy between the vacuum level and the valence band maximum. The ionization potential can be evaluated, for example, by ultraviolet photoelectron spectroscopy (UPS).

[0371] Note that a metal oxide with a higher In content may be used for the first layer and the third layer than for the second layer. Furthermore, a metal oxide with a higher In content may be used for one of the first layer and the third layer than for the second layer, and a metal oxide with a higher Ga content may be used for the other of the first layer and the third layer than for the second layer.

[0372] Each of the first to third layers may comprise a stack of a plurality of layers, each having the composition described above. For example, the first layer may have a structure in which a metal oxide with a high In content is disposed over a metal oxide with a high Ga content. As another example, the third layer may have a structure in which a metal oxide with a high Ga content is disposed over a metal oxide with a high In content. [Formation process of the oxide semiconductor]

[0373] The oxide semiconductor of one embodiment of the present invention can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, an MBE method, a PLD method, an ALD method, or the like.

[0374] The oxide semiconductor of one embodiment of the present invention can be formed by forming metal oxides using two types of film formation methods. For example, the oxide semiconductor of one embodiment of the present invention can be formed by forming metal oxides using a first formation method and a second formation method.

[0375] The oxide semiconductor of one embodiment of the present invention may have a two-layer structure of a first layer and a second layer over the first layer. In the case where the oxide semiconductor has a two-layer structure, the oxide semiconductor may be formed in the following manner: The first layer is formed over a formation surface by a first formation method, and then the second layer is formed over the first layer by a second formation method.

[0376] As the first formation method, it is preferable to use a film formation method that causes less damage to the formation surface than the second formation method. Consequently, a mixed layer can be prevented from forming at the interface between the oxide semiconductor and a layer serving as the formation surface of the oxide semiconductor. Furthermore, impurities such as silicon can be prevented from penetrating into the second layer formed over the first layer, so that the crystallinity of the oxide semiconductor can be further enhanced in some cases.

[0377] Examples of the first formation method include an ALD method, a CVD method, and an MBE method. Examples of a CVD method include a plasma-enhanced CVD (PECVD) method, a thermal CVD method, a photo-CVD method, and an MOCVD method. An MBE method is a film formation method by which a thin film having a crystal structure reflecting a crystal system of a substrate is grown, and is one of film formation methods that causes less damage to a formation surface. A wet method can be used as the first formation method. A wet method is one of film formation methods that causes less damage to a formation surface. An example of a wet method is a spray coating method.

[0378] As the second formation method, it is preferable to use a method capable of forming a metal oxide having crystallinity. The resulting metal oxide particularly preferably has a CAAC structure. Examples of the second film formation method include a sputtering method and a PLD method. A metal oxide deposited by a sputtering method is likely to exhibit crystallinity, so a sputtering method is suitable as the second formation method.

[0379] When a metal oxide is formed over the formation surface by the second formation process, damage to the formation surface may cause alloying of a component contained in the metal oxide with a component contained in the layer serving as the formation surface. When alloying occurs, in some cases, a mixed layer is formed at the interface between the metal oxide and the layer serving as the formation surface. The mixed layer may also be referred to as an alloyed region. The formation of the mixed layer may also be referred to as alloying.

[0380] For example, in the case where a sputtering method is used as the second formation method, a mixture layer is formed in some cases due to, for example, particles emitted from a target or the like (also referred to as sputtered particles) or energy applied to the substrate side by sputtered particles or the like. In particular, in the case where a metal oxide is formed over an insulating layer containing silicon, such as a silicon oxide film, as the formation surface by the second formation method, silicon may infiltrate into the metal oxide. There is a risk that infiltration of impurities such as silicon into the metal oxide may hinder the crystallization of the metal oxide.When an oxide semiconductor into which impurities penetrate is used for a transistor, the initial characteristics or reliability of the transistor may be adversely affected. It is difficult to increase the crystallinity of an alloyed region even if a heat treatment, which will be described later, is performed.

[0381] Therefore, forming the metal oxide by the first formation method before forming the metal oxide by the second formation method as described above can prevent impurities from entering the oxide semiconductor. Furthermore, alloying with the layer serving as the formation surface can be prevented. Thus, the initial characteristics and reliability of the transistor can be improved. Furthermore, the crystallinity of the oxide semiconductor can be further increased.

[0382] It should be noted that in some cases, a mixture layer is formed at the interface between the first layer and the second layer. The mixture layer includes a component contained in the first layer and a component contained in the second layer. For example, in the case where gallium oxide is used for the first layer and an indium-containing metal oxide is used for the second layer, the mixture layer contains gallium and indium. For example, in the case where the indium content in the second layer is higher than that in the first layer, the indium content in the mixture layer is higher than or equal to that in the first layer and lower than or equal to that in the second layer.

[0383] An ALD method is suitable as a first formation method because damage to the formation surface can be prevented compared to a sputtering method. An ALD method is a film formation method that enables higher coverage than a sputtering method. By using an ALD method as a first-layer formation method, the oxide semiconductor can adequately cover the underlying component. Therefore, the oxide semiconductor can adequately cover a step, an opening portion, or the like with a high aspect ratio.

[0384] For the first layer, for example, in some cases, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than the CAAC structure is formed. Forming the second layer with high crystallinity on the first layer with low crystallinity or performing a heat treatment after the formation of the second layer can, in some cases, increase the crystallinity of the first layer with the second layer serving as the core. Consequently, in some cases, the crystallinity can be increased in the entire oxide semiconductor including the vicinity of the interface with the formation surface.

[0385] The layer serving as the formation surface is, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film. Note that in some transistor structures, the layer serving as the formation surface may be a conductive film such as a titanium nitride film, a tungsten film, or an ITSO film. The layer serving as the formation surface does not necessarily have crystallinity. In the case where the layer has crystallinity, the layer serving as the formation surface may have a crystal structure with a low lattice matching with the metal oxide contained in the oxide semiconductor.

[0386] The first layer is preferably formed by an ALD method. A method for forming an In-M-Zn oxide for the first layer by an ALD method is described herein.

[0387] First, a source gas containing an indium-containing precursor is introduced into a reaction chamber (also called a chamber), so that the precursor is adsorbed onto the formation surface. Subsequently, an oxidant as a reactant is introduced into the reaction chamber to react with the adsorbed precursor, and components other than indium are released while indium is adsorbed onto the substrate, thereby forming a layer in which indium and oxygen are bonded together.

[0388] Subsequently, a source gas containing a precursor containing the element M is introduced into the reaction chamber, and the precursor is adsorbed onto the layer where indium and oxygen are bonded together. Subsequently, an oxidant as a reactant is introduced into the reaction chamber to react with the adsorbed precursor, and components other than the element M are released while the element M is adsorbed onto the substrate, thereby forming a layer where the element M and oxygen are bonded together.

[0389] Next, a source gas containing a precursor containing zinc is introduced into the reaction chamber, and the precursor is adsorbed onto the layer where the element M and oxygen are bonded together. Subsequently, an oxidizing agent is introduced into the reaction chamber as a reactant to react with the adsorbed precursor, and components other than zinc are released while zinc is adsorbed onto the substrate, thereby forming a layer where zinc and oxygen are bonded together.

[0390] By repeating the above steps, an In-M-Zn oxide as an oxide semiconductor can be formed by an ALD method over the layer serving as a formation surface.

[0391] When the oxide semiconductor is formed by an ALD method, ozone (O3), oxygen (O2), water (H2O), or the like is used as an oxidant. Using an oxidant without hydrogen, such as ozone (O3) or oxygen (O2), can reduce the amount of hydrogen that penetrates into the oxide semiconductor.

[0392] It is preferable that, after the precursor has been adsorbed in the above steps, the introduction of the source gas containing the precursor is stopped and the reaction chamber is purged so that an excess precursor, a reaction product, and the like are removed from the reaction chamber. Furthermore, after the adsorbed precursor has reacted with the oxidant in the above steps, the introduction of the oxidant is preferably stopped and the reaction chamber is purged so that an excess reactant, a reaction product, and the like are removed from the reaction chamber.

[0393] In the explanation of this specification and the like, in the case of using ozone, oxygen and water as a reactant or oxidizing agent, they include not only those in states of a gas or a molecule, but also those in states of plasma, a radical and an ion, unless otherwise specified.

[0394] The second layer is preferably formed by a sputtering process.

[0395] In-M-Zn oxide can be used as a target used in a sputtering process. When a metal oxide is formed by a sputtering process, oxygen or a mixed gas of oxygen and a rare gas can be used as the sputtering gas. By increasing the oxygen content of the sputtering gas, the amount of excess oxygen contained in the oxide film to be formed can be increased.

[0396] A higher proportion of the flow rate of an oxygen gas to the flow rate of the total film-forming gas (also called the flow rate ratio of oxygen) used in forming the metal oxide allows, in some cases, the formed metal oxide to have higher crystallinity.

[0397] When the metal oxide is formed by a sputtering method, and the oxygen content in the sputtering gas is higher than or equal to 30% and lower than or equal to 100%, preferably higher than or equal to 70% and lower than or equal to 100%, a metal oxide with excess oxygen is formed in some cases. A transistor containing a metal oxide with excess oxygen in a channel formation region can have relatively high reliability. However, an embodiment of the present invention is not limited thereto. When the oxygen content in the sputtering gas is higher than or equal to 1% and lower than or equal to 30%, preferably higher than or equal to 5% and lower than or equal to 20%, an oxygen-deficient metal oxide is formed. A transistor containing an oxygen-deficient metal oxide in a channel formation region can have relatively high field-effect mobility.

[0398] When forming the metal oxide by a sputtering method, substrate heating is preferably performed. By raising the substrate temperature (phase temperature) during the formation of the metal oxide, a metal oxide with high crystallinity can be formed in some cases. When forming the metal oxide by a sputtering method, for example, the substrate heating temperature is preferably higher than or equal to 100°C and lower than or equal to 400°C, more preferably higher than or equal to 200°C and lower than or equal to 300°C.

[0399] By the above-described formation method, the thickness of the mixed layer formed at the interface between the layer serving as a formation surface and the metal oxide can be reduced, or the thickness of the alloyed region formed at the interface between the layer serving as a formation surface and the metal oxide can be thin enough to be unobserved. For example, the thickness of the alloyed region can be greater than or equal to 0 nm and less than or equal to 3 nm, preferably greater than or equal to 0 nm and less than or equal to 2 nm, more preferably greater than or equal to 0 nm and less than or equal to 1 nm, even more preferably greater than or equal to 0 nm and less than or equal to 0.3 nm.

[0400] It should be noted that in some cases, the thickness of the alloyed region can be calculated by performing SIMS analysis or composition line analysis by energy dispersive X-ray spectroscopy (EDX) on the region and its surroundings.

[0401] For example, EDX line analysis is performed on the alloyed region and its surroundings, where the direction perpendicular to the formation surface of the first layer is regarded as the depth direction. Next, in the profile of quantitative values of elements in the depth direction obtained from the analysis, the depth at which the quantitative value of a metal that is the main component of the first layer and is not the main component of the layer serving as the formation surface (In in the case where the first layer contains In) becomes half is defined as the depth (position) of the interface between the region and the first layer. The depth at which the quantitative value of an element (e.g.Si), which is a major component of the layer serving as the formation surface and is not a major component of the first layer, is defined as the depth (position) of the interface between the region and the layer serving as the formation surface. In the above manner, the thickness of the alloyed region can be calculated.

[0402] When the thickness of the alloyed region in the oxide semiconductor of one embodiment of the present invention is observed by EDX analysis, the thickness is, for example, greater than or equal to 0 nm and less than or equal to 3 nm, preferably greater than or equal to 0 nm and less than or equal to 2 nm, more preferably greater than or equal to 0 nm and less than or equal to 1 nm, even more preferably greater than or equal to 0 nm and less than 0.3 nm.

[0403] For example, when SIMS analysis is performed on the oxide semiconductor formed over a silicon oxide film serving as a formation surface, the depth at which the silicon concentration is 50% of the maximum value of the silicon concentration of the silicon oxide film is defined as the interface, and the distance between the interface and the depth at which the silicon concentration is reduced to 1.0 × 10 21 atoms / cm 3 , preferably 5.0 × 10 20 atoms / cm 3 , preferably 1.0 × 10 20 atoms / cm 3 is reduced is defined as thickness t. The thickness t is preferably less than or equal to 3 nm, more preferably less than or equal to 2 nm.

[0404] When the thickness of the alloyed region is reduced, the thickness t may be a value within the above range.

[0405] Note that when the thickness of the alloyed region is reduced, the CAAC structure can be formed in the vicinity of the formation surface. Here, the vicinity of the formation surface refers, for example, to a region located at a depth of greater than 0 nm and less than or equal to 3 nm, preferably greater than 0 nm and less than or equal to 2 nm, more preferably greater than or equal to 1 nm and less than or equal to 2 nm from the formation surface of the oxide semiconductor in the direction substantially perpendicular to the formation surface.

[0406] It should be noted that in some cases, the CAAC structure in the vicinity of the formation surface can be confirmed by TEM observation. For example, in high-resolution cross-sectional TEM observation of the oxide semiconductor, bright spots arranged layer by layer in the direction parallel to the formation surface are observed in the vicinity of the formation surface.

[0407] The oxide semiconductor of one embodiment of the present invention may have a three-layer structure of a first layer, a second layer over the first layer, and a third layer over the second layer.

[0408] In the case where the oxide semiconductor has a three-layer structure, the oxide semiconductor can be formed in the following manner: the first layer is formed over a formation surface by a first formation method, and then the second layer is formed by a second formation method, and the third layer is formed by the first formation method.

[0409] Even if the first layer and the third layer in the oxide semiconductor have a composition in which the CAAC structure is less likely to be achieved in the formation of a single layer, the entire oxide semiconductor including the first layer and the third layer may have the CAAC structure through crystal growth that occurs with the second layer serving as the core. Alternatively, the oxide semiconductor may have the CAAC structure in a region including the second layer and at least a part of each of the first layer and the third layer.

[0410] In particular, even in a composition where the first layer and the third layer have a high In content, crystallinity suitable for a semiconductor layer of a transistor can be obtained. The oxide semiconductor of one embodiment of the present invention achieves both high on-state characteristics and high reliability of the transistor by increasing the In content and achieving the CAAC structure with high crystallinity, respectively.

[0411] A metal oxide with the same composition as the second layer can be used for the first and third layers. By using the same composition, the oxide semiconductors can easily exhibit the CAAC structure after heat treatment.

[0412] Since the second layer has high crystallinity, crystal growth of the third layer can be achieved using the crystal of the second layer as a nucleus or seed. Therefore, even if a film formation method that easily imparts crystallinity is not used as the third layer formation method, the third layer can be crystallized. Here, for example, if a film formation method that enables higher coverage than that of the second layer is used to form the third layer, the entire oxide semiconductor can have both high crystallinity and high coverage.

[0413] When the influence of the formation surface on the second layer is reduced by providing the first layer, the crystallinity of the second layer is increased to a very high level. Therefore, the third layer, whose crystal grows with the second layer as a nucleus or seed, is also expected to exhibit very excellent crystallinity.

[0414] It should be noted that when an oxide semiconductor is used for a semiconductor layer of a transistor, the third layer, which is the uppermost layer of the oxide semiconductor, is sometimes in contact with a gate insulating layer. By increasing the crystallinity of the layer in contact with the gate insulating layer, the charge carrier mobility in the on-state of the transistor can be increased.

[0415] The crystallinity of the first layer and the third layer is increased, using the second layer with high crystallinity as a core or seed. Specifically, the crystallinity of the first layer can be increased during the formation of the second layer or by a heat treatment after the formation of the third layer. The crystallinity of the third layer can be increased during the formation of the third layer or by a heat treatment after the formation of the third layer. Note that the above heat treatments have an auxiliary function for increasing crystallinity.

[0416] As described above, in the method for forming the oxide semiconductor of one embodiment of the present invention, in which the second layer containing a metal oxide with high crystallinity (i.e., a c-axis aligned crystal or CAAC) is used as a core or seed, the crystallinity of the metal oxides above and below the second layer (here, the first layer and the third layer) can be increased. Consequently, the crystallinity of the entire oxide semiconductor can be increased. In other words, the second layer serves as a core or seed to induce solid-phase growth of the metal oxides above and below the second layer, so that the oxide semiconductor with high crystallinity can be formed. An oxide semiconductor formed by such a formation method, here, a CAAC film, can be referred to as axial growth CAAC (AG CAAC).

[0417] A region having the CAAC structure is preferentially distributed throughout the entire layer of the oxide semiconductor. Crystals in the region having the CAAC structure in the first layer are connected to crystals in the region having the CAAC structure in the second layer. Crystals in the region having the CAAC structure in the third layer are connected to crystals in the region having the CAAC structure in the second layer. Therefore, in some cases, no boundary is observed between the first layer and the second layer. Furthermore, in some cases, no boundary is observed between the second layer and the third layer. The oxide semiconductor can be expressed as a single layer in which the interfaces are not clearly observed. The oxide semiconductor can be expressed as a single layer in some cases.

[0418] For example, in the region containing the CAAC structure in each of the first to third layers, bright spots arranged parallel or substantially parallel to the formation surface are observed in a high-resolution cross-sectional TEM image. The c-axis of the CAAC structure included in each of the first to third layers is preferably parallel or substantially parallel to the normal direction of the formation surface or the surface of the oxide semiconductor.

[0419] In some cases, part of the first layer or the third layer is not crystallized.

[0420] In the case where the oxide semiconductor has a three-layer structure, the oxide semiconductor can also be formed in the following manner: a first layer is formed over a formation surface by a first formation method, and then a second layer is formed by the first formation method, and a third layer is formed by a second formation method.

[0421] As described above, when a metal oxide with a high In content is used for a transistor, the field-effect mobility of the transistor can be increased. On the other hand, a metal oxide with a high In content tends to have a cubic crystal structure. Therefore, when a metal oxide with a high In content is used for the second layer in contact with the third layer, crystals reflecting the orientation of crystals contained in the third layer can be formed.

[0422] It is preferable that the crystals contained in the third layer and the crystals contained in the second layer have a small lattice mismatch. Therefore, crystals reflecting the orientation of the crystals contained in the third layer can be formed in the second layer. At this time, for example, in high-resolution cross-sectional TEM observation of the oxide semiconductor, bright spots arranged layer by layer in the direction parallel to the formation surface are observed in the second layer.

[0423] There is no particular restriction on the crystal structure of the second layer, as long as the crystals contained in the third layer and the crystals contained in the second layer have a small lattice mismatch. The crystal structure of the second layer can be any of a cubic crystal structure, a tetragonal crystal structure, an orthorhombic crystal structure, a hexagonal crystal structure, a monoclinic crystal structure, and a trigonal crystal structure.

[0424] In the above structure, typically, the first layer may be a layer containing a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:2 or close thereto, or a layer containing gallium oxide, the second layer may be a layer containing a metal oxide containing a small amount of the element M or a layer containing indium oxide, and the third layer may be a layer containing a metal oxide with an atomic ratio of In:Ga:Zn = 1:1:1 or close thereto. In this case, the first layer contains gallium. In the case where the first layer contains a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:2 or close thereto, the indium content is lower than the gallium content in the first layer. The indium content in the second layer is higher than the indium content in the third layer.

[0425] In the case where the first layer and the second layer are formed by the first formation method, the first layer and the second layer are preferably formed successively without exposure to air. By forming the first layer and the second layer successively without exposure to air, productivity can be increased. Furthermore, impurities (typically moisture or the like) that might be absorbed into the interface between the first layer and the second layer and the surroundings thereof can be reduced.

[0426] One or more of the first to third layers may comprise a stack of a plurality of layers having different compositions. For example, the first layer may be formed in the following manner: A layer containing a metal oxide with a high Ga content is formed by the first formation method, and then a layer containing a metal oxide with a higher In content than the layer is formed by the first formation method.

[0427] After the formation of the layer by the first formation process, a microwave plasma treatment is preferably carried out.

[0428] In this specification and the like, a microwave refers to an electromagnetic wave with a frequency greater than or equal to 300 MHz and less than or equal to 300 GHz. For example, a microwave plasma treatment refers to a treatment that uses a device with a power source to generate high-density plasma using microwaves. Microwave plasma treatment may also be referred to as a microwave-excited high-density plasma treatment.

[0429] By performing microwave plasma treatment in an oxygen-containing atmosphere, the impurity concentration in the oxide semiconductor 230 can be reduced. Specific examples of impurities include hydrogen and carbon. Although the microwave plasma treatment is performed in an oxygen-containing atmosphere on the metal oxide in the above, an embodiment of the present invention is not limited thereto. For example, the microwave plasma treatment may be performed in an oxygen-containing atmosphere on an insulating film, particularly a silicon oxide film, positioned in the vicinity of the metal oxide. Furthermore, in some cases, the crystallinity of the oxide semiconductor increases due to heat in the microwave plasma treatment.

[0430] The microwave plasma treatment is preferably carried out under reduced pressure, and the pressure is preferably higher than or equal to 10 Pa and lower than or equal to 1000 Pa, more preferably higher than or equal to 50 Pa and lower than or equal to 700 Pa, even more preferably higher than or equal to 100 Pa and lower than or equal to 400 Pa. The treatment temperature is preferably higher than or equal to room temperature (25 °C) and lower than or equal to 750 °C, more preferably higher than or equal to 300 °C and lower than or equal to 500 °C, and may be higher than or equal to 400 °C and lower than or equal to 450 °C.

[0431] During microwave plasma treatment, substrate heating may be performed. The substrate heating temperature is preferably higher than or equal to room temperature (e.g., 25°C), higher than or equal to 100°C, higher than or equal to 200°C, higher than or equal to 300°C, higher than or equal to 400°C, and lower than or equal to 500°C or lower than or equal to 450°C.

[0432] The microwave plasma treatment can be performed, for example, using an oxygen gas and an argon gas. For example, the oxygen flow rate ratio (O2 / (O2+Ar)) in the microwave plasma treatment is preferably higher than 0% and lower than or equal to 10%, more preferably higher than or equal to 0.5% and lower than or equal to 5%, even more preferably higher than or equal to 0.5% and lower than or equal to 3%, and preferably typically 1%.

[0433] Microwave plasma treatment in an oxygen-containing atmosphere can convert an oxygen gas into plasma using a high-frequency wave such as a microwave or RF, and apply oxygen radicals generated by converting the oxygen gas into plasma to the oxide semiconductor. Through the effects of plasma, a microwave, oxygen radicals, and the like, a defect, which is an oxygen vacancy in the oxide semiconductor into which hydrogen has penetrated (hereinafter referred to as V in some cases), can be removed. O H), can be split into an oxygen vacancy and hydrogen, and hydrogen, which is an impurity, can be removed from the oxide semiconductor. In this way, V O H in the oxide semiconductor can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. When the microwave plasma treatment is performed in this manner, impurities such as carbon and hydrogen can be reduced. By supplying the oxygen radicals to oxygen vacancies formed in the oxide semiconductor, oxygen vacancies in the oxide semiconductor can be further reduced.

[0434] Microwave plasma treatment can increase the crystallinity of the layer formed by the first formation process. Here, the principles of improving the crystallinity of the oxide semiconductor by microwave plasma treatment are described. First, active species excited by a microwave, such as oxygen radicals, reach the surface of the oxide semiconductor, and a substitution reaction occurs between the active species and oxygen in the oxide semiconductor, thereby forming a core or seed. Furthermore, lateral growth of the core or seed is induced. Note that the active species excited by the microwave preferably contain oxygen (typically oxygen ions), which is likely to be adsorbed onto a side surface of the core or seed, in which case lateral growth is promoted.Microwave plasma treatment induces the formation of a core or seed and lateral growth of the core or seed, thus improving the crystallinity of the oxide semiconductor.

[0435] In contrast, when a portion of oxygen present in the oxide semiconductor before microwave plasma treatment reacts with hydrogen in the oxide semiconductor, i.e., a reaction "2H+O → H2O↑" occurs, the hydrogen can be removed as H2O (i.e., dehydration or dehydrogenation is achieved). H2O is a limiting factor for improving crystallinity and is therefore preferentially removed from the oxide semiconductor. Hydrogen in the oxide semiconductor is removed as H2O to reduce the hydrogen concentration in the oxide semiconductor, which can promote improvement in crystallinity. When the temperature of the microwave plasma treatment is increased, the hydrogen concentration in the oxide semiconductor can be further reduced.

[0436] It should be noted that after the microwave plasma treatment, heat treatment can be successively performed without exposure to air. For example, the heat treatment temperature is preferably higher than or equal to 100°C and lower than or equal to 750°C, more preferably higher than or equal to 300°C and lower than or equal to 500°C, and even more preferably higher than or equal to 400°C and lower than or equal to 450°C.

[0437] It should be noted that the crystallinity can also be improved by performing a plasma treatment using an oxygen gas instead of the microwave plasma treatment.

[0438] Increasing the crystallinity of the layer formed by the first formation process can further increase the crystallinity of a layer formed above the layer. Therefore, the crystallinity of the entire oxide semiconductor can be increased.

[0439] Oxygen supplied to the oxide semiconductor has any of various forms, such as an oxygen atom, an oxygen molecule, an oxygen ion (a charged oxygen atom or a charged oxygen molecule), and an oxygen radical (an oxygen atom, an oxygen molecule, or an oxygen ion with an unpaired electron). Oxygen injected into the oxide semiconductor preferably has one or more of the above forms. An oxygen radical is particularly preferred.

[0440] Heat treatment is preferably performed after the formation of the oxide semiconductor. By performing heat treatment, the crystallinity of the oxide semiconductor can be increased. Heat treatment here is not limited to treatment involving the application of heat. For example, heat applied during the formation process can be considered heat treatment.

[0441] The heat treatment temperature may, for example, be higher than or equal to 100°C and lower than or equal to 800°C, preferably higher than or equal to 250°C and lower than or equal to 650°C, more preferably higher than or equal to 350°C and lower than or equal to 550°C. Typically, the temperature may be set to 400°C ± 25°C (higher than or equal to 375°C and lower than or equal to 425°C). The treatment time may be less than or equal to 10 hours and may, for example, be longer than or equal to 1 minute and shorter than or equal to 5 hours, or longer than or equal to 1 minute and shorter than or equal to 2 hours. In the case of using an RTA device, the treatment time may, for example, be longer than or equal to 1 second and shorter than or equal to 5 minutes. The heat treatment is intended to heat the third layer formed by the first formation method (ieMolecules with crystallinity deposited by an ALD process) fill an atomic space between crystal parts of the CAAC structure of the second layer formed by the second formation process.

[0442] The heating device used for heat treatment is not limited to a particular device and may be a device for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or a rapid thermal annealing (RTA) device such as a lamp rapid thermal annealing apparatus (LRTA) or a gas rapid thermal annealing apparatus (GRTA) may be used. An LRTA device is a device for heating an object to be processed by irradiating it with light (an electromagnetic wave) emitted from a lamp such as a lamp.a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. A GRTA facility is a facility for heat treatment using a high-temperature gas.

[0443] Through the heat treatment step, the crystallinity of the region having the CAAC structure in the third layer formed by the first formation method can be increased. In the case where the region is formed only in the lower portion of the third layer after deposition by an ALD method, the heat treatment step can extend the region upward. This means that the heat treatment can form the region having the CAAC structure throughout the entire third layer.

[0444] Through the heat treatment step, at least a part of the first layer or the second layer formed by the first formation method preferably has the CAAC structure. The CAAC structure is intended to be easily formed, wherein a mixed layer is formed in the first layer or the second layer and serves as a core or seed in the formation of the layer by the second formation method. The CAAC region in the first layer or the second layer is preferably large, and the CAAC region preferably extends to the vicinity of the formation surface.

[0445] Since the CAAC region extends from the upper portion to the lower portion of the first layer or the second layer, the CAAC region can extend to the vicinity of the layer serving as the formation surface regardless of the material and crystallinity of the layer serving as the formation surface. For example, even if the layer serving as the formation surface has an amorphous structure, the crystallinity of the first layer or the second layer can be increased. Therefore, the method for forming the oxide semiconductor of one embodiment of the present invention is particularly suitable for the case where the layer serving as the formation surface has an amorphous structure.

[0446] When microwave plasma treatment and / or heat treatment are performed as described above, the crystallinity of the entire oxide semiconductor can be increased. Furthermore, impurities in the oxide semiconductor can be reduced. Crystal growth of the oxide semiconductor with a low impurity concentration can further increase crystallinity.

[0447] Increasing the crystallinity of the oxide semiconductor can prevent the electrical resistance of the semiconductor layer of a transistor comprising the oxide semiconductor from increasing, or can improve the initial characteristics (especially the forward current) of the transistor, and thus a transistor suitable for high-speed operation can be expected. In addition, the reliability and forward current of the transistor can be improved.

[0448] It should be noted that the microwave plasma treatment and / or the heat treatment may be performed directly on the oxide semiconductor or may be performed on an insulating film or the like formed over the oxide semiconductor.

[0449] Before forming the first layer or after forming the first layer or the second layer by the first formation method, a treatment for supplying oxygen to the first layer or the second layer may be performed. Accordingly, oxygen may be supplied to the oxide semiconductor, for example, by applying heat after this treatment.

[0450] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma treatment) in an oxygen-containing atmosphere. Furthermore, an oxide film (preferably a metal oxide film) may be formed by a sputtering method in an oxygen-containing atmosphere, thereby supplying oxygen to the first layer or the second layer formed by the first formation method. The formed oxide film may be removed immediately or left as it is. In the case where the oxide film is left as it is, the oxide film may be used as a layer provided over the first layer or the second layer (i.e., used as a second layer or third layer).It should be noted that an oxygen-containing atmosphere includes not only oxygen gas (O2), but also oxygen-containing compound gases such as ozone (O3) or nitrous oxide (N2O). The substrate temperature during plasma treatment is higher than or equal to room temperature (25 °C) and lower than or equal to 450 °C.

[0451] The oxide semiconductor of one embodiment of the present invention exhibits high crystallinity throughout the entire layer. Therefore, in some cases, boundaries between the stacked first to third layers are not observed in the oxide semiconductor. It may be difficult to observe the boundaries between the stacked layers, especially after heat treatment. Whether the boundaries between the stacked layers exist can be confirmed, for example, by cross-sectional observation with a TEM or a scanning transmission electron microscope (STEM).

[0452] The oxide semiconductor formed by the above-described two types of formation methods and having the CAAC structure has, in some cases, one or more of a higher dielectric constant, a higher film density, and a higher film hardness than an oxide semiconductor formed by one type of formation method and having the CAAC structure.

[0453] When the oxide semiconductor film formed by the above two types of formation methods and having the CAAC structure is used for a channel formation region of a transistor, the transistor can have excellent characteristics (e.g., high on-state current, high field-effect mobility, low S value, high frequency characteristics (also called f characteristics), or high reliability).

[0454] The oxide semiconductor of one embodiment of the present invention may be formed in some cases using the first formation method and a microwave plasma treatment and / or a heat treatment. In other words, the oxide semiconductor of one embodiment of the present invention may be formed in some cases without using the second formation method. For example, after the first layer is formed by the first formation method, a microwave plasma treatment and / or a heat treatment are performed, whereby the crystallinity of the first layer can be increased. Therefore, the crystallinity of the second layer formed over the first layer by the first formation method can be increased, using the first layer as a core or seed.If microwave plasma treatment and / or heat treatment are performed after the formation of the second layer, the crystallinity of the oxide semiconductor can be increased. Consequently, the CAAC structure can be formed in the oxide semiconductor.

[0455] As described above, even in the formation method in which the second formation method is not used, solid-phase growth of the layer above the first layer is enabled by using the first layer formed by the first formation method as a core or seed, thereby enabling the formation of an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a formation method may also be referred to as AG CAAC.

[0456] Note that in the case where the oxide semiconductor has a multilayer structure composed of two or more layers, the oxide semiconductor can also be formed by forming metal oxides by some kind of formation method. For example, in the case where the oxide semiconductor has a two-layer structure composed of a first layer and a second layer over the first layer, the oxide semiconductor can be formed by forming the first layer and the second layer in that order by a sputtering method. A sputtering method that achieves a higher deposition rate than an ALD method can increase productivity.As another example, in the case where the oxide semiconductor has a three-layer structure consisting of a first layer, a second layer over the first layer, and a third layer over the second layer, the first to third layers may be formed by a sputtering method. Furthermore, some of the first to third layers may be formed by an ALD method. For example, the second layer and / or the third layer may be formed by an ALD method. [Oxide semiconductor of the transistor]

[0457] The oxide semiconductor of this embodiment can be used for a semiconductor layer of a transistor.

[0458] The oxide semiconductor of this embodiment can be used as the oxide semiconductor 230 or the like included in the transistors described in Embodiment 1. For example, the first layer can be used as the oxide semiconductor 230a, the second layer can be used as the oxide semiconductor 230b, and the third layer can be used as the oxide semiconductor 230c. The layer serving as the formation surface corresponds to the insulator 224 described in Embodiment 1.

[0459] The oxide semiconductor of this embodiment preferably has the CAAC structure. In the oxide semiconductor having the CAAC structure, metal atoms in a crystal part are layered in the direction parallel or substantially parallel to the formation surface.

[0460] Oxide semiconductors with the CAAC structure are believed to exhibit current anisotropy. For example, in an IGZO crystal, current flows more easily along the a-axis than along the c-axis. This means that in oxide semiconductors with the CAAC structure, current is believed to flow more easily in the lateral direction than in the vertical direction.

[0461] In the oxide semiconductor 230 of the semiconductor device described in the previous embodiment, metal atoms are layered in the direction parallel or substantially parallel to the formation surface. This may also be referred to as "the ab plane of the CAAC structure is provided parallel or substantially parallel to the formation surface." With such a structure, the ab plane of the CAAC structure can be provided along a current flow direction in a channel of the transistor. Consequently, the transistor can have a high on-state current.

[0462] For example, in the case where the oxide semiconductor of this embodiment is used for a semiconductor layer of a transistor, the thickness of the oxide semiconductor is preferably greater than or equal to 3 nm and less than or equal to 200 nm, more preferably greater than or equal to 3 nm and less than or equal to 100 nm, more preferably greater than or equal to 5 nm and less than or equal to 100 nm, even more preferably greater than or equal to 10 nm and less than or equal to 100 nm, even more preferably greater than or equal to 10 nm and less than or equal to 70 nm, even more preferably greater than or equal to 15 nm and less than or equal to 70 nm, even more preferably greater than or equal to 15 nm and less than or equal to 50 nm, and even more preferably greater than or equal to 20 nm and less than or equal to 50 nm.In a transistor used for a further downsized semiconductor device, the thickness of the oxide semiconductor is preferably greater than or equal to 1 nm and less than or equal to 20 nm, more preferably greater than or equal to 3 nm and less than or equal to 15 nm, still more preferably greater than or equal to 5 nm and less than or equal to 12 nm, even more preferably greater than or equal to 5 nm and less than or equal to 10 nm. The average thickness of the oxide semiconductor in a channel formation region of the transistor is particularly preferably, for example, greater than or equal to 2 nm and less than or equal to 15 nm.

[0463] For example, the thickness of the first layer is preferably greater than or equal to 0.5 nm and less than or equal to 50 nm, more preferably greater than or equal to 0.5 nm and less than or equal to 30 nm, more preferably greater than or equal to 0.5 nm and less than or equal to 20 nm, even more preferably greater than or equal to 1 nm and less than or equal to 50 nm, even more preferably greater than or equal to 1 nm and less than or equal to 30 nm, even more preferably greater than or equal to 1 nm and less than or equal to 20 nm, even more preferably greater than or equal to 2 nm and less than or equal to 20 nm. The thickness of the first layer is more preferably greater than or equal to 0.5 nm and less than or equal to 3 nm.

[0464] The first layer preferably comprises a region having a thickness of greater than or equal to 0.1 nm and less than or equal to 3 nm, and more preferably a region having a thickness of greater than or equal to 0.1 nm and less than or equal to 2 nm. Alternatively, the first layer preferably comprises a region having a thickness of greater than or equal to 0.5 nm and less than or equal to 3 nm, and more preferably a region having a thickness of greater than or equal to 0.5 nm and less than or equal to 2 nm.

[0465] The thickness of the second layer is preferably, for example, less than or equal to 200 nm. In the case where the second layer has the form of a layer, the thickness of the second layer is preferably, for example, greater than or equal to 1 nm and less than or equal to 200 nm, more preferably greater than or equal to 1 nm and less than or equal to 100 nm, even more preferably greater than or equal to 2 nm and less than or equal to 100 nm.

[0466] Alternatively, in some cases, the second layer is not in the form of a single layer, but rather an aggregate of island-like regions, as long as the second layer can serve as a crystal nucleus. In such a case, the island-like regions of the second layer are present discretely, for example.

[0467] For the preferred range of thickness of the third layer, reference can be made to the description of the thickness of the first layer. [Impurities in the oxide semiconductor]

[0468] The influence of impurities in the oxide semiconductors is described here.

[0469] As described in the previous embodiment, in a transistor using the oxide semiconductor for a semiconductor layer, the electrical characteristics may vary slightly and the reliability may be reduced if oxygen vacancies (V O ) and impurities are present in a channel formation region in the oxide semiconductor. Therefore, in order to obtain stable electrical characteristics of the OS transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. To reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a film adjacent to the oxide semiconductor. Examples of impurities include hydrogen, carbon, and nitrogen. Note that impurities in an oxide semiconductor refer to, for example, elements other than the main components of an oxide semiconductor. For example, an element whose concentration is lower than 0.1 atomic % is an impurity.

[0470] When an oxide semiconductor contains silicon or carbon, which are Group 14 elements, defect states are formed in the oxide semiconductor. Consequently, the carbon concentration in the channel formation region of the oxide semiconductor, measured by SIMS, is less than or equal to 1 × 10 20 atoms / cm 3 , preferably less than or equal to 5 × 10 19 atoms / cm 3 , preferably less than or equal to 3 × 10 19 atoms / cm 3 , preferably less than or equal to 1 × 10 19 atoms / cm 3 , more preferably lower than or equal to 3 × 10 18 atoms / cm 3 , even more preferably lower than or equal to 1 × 10 18 atoms / cm 3 . The silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is less than or equal to 1 × 10 20 atoms / cm 3 , preferably less than or equal to 5 × 10 19 atoms / cm 3 , preferably less than or equal to 3 × 10 19 atoms / cm 3 , preferably less than or equal to 1 × 10 19 atoms / cm 3 , more preferably lower than or equal to 3 × 10 18 atoms / cm 3 , even more preferably lower than or equal to 1 × 10 18 atoms / cm 3 .

[0471] When the oxide semiconductor contains nitrogen, the oxide semiconductor easily becomes n-type due to the generation of electrons serving as charge carriers and an increase in the charge carrier concentration. As a result, a transistor comprising a nitrogen-containing oxide semiconductor as a semiconductor tends to exhibit self-conducting properties. Alternatively, when the oxide semiconductor contains nitrogen, a trap state is formed in some cases. This can lead to unstable electrical properties of the transistor. Consequently, the nitrogen concentration in the channel formation region of the oxide semiconductor, measured by SIMS, is less than or equal to 1 × 10 20 atoms / cm 3 , preferably less than or equal to 5 × 10 19 atoms / cm 3 , preferably less than or equal to 1 × 10 19 atoms / cm 3 , preferably less than or equal to 5 × 10 18 atoms / cm 3 , more preferably less than or equal to 1 × 10 18 atoms / cm 3 , even more preferably lower than or equal to 5 × 10 17 atoms / cm 3 .

[0472] Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water and thus, in some cases, forms an oxygen vacancy. As a result of hydrogen invading the oxygen vacancy, an electron serving as a charge carrier is generated in some cases. Furthermore, bonding of a portion of hydrogen with oxygen bonded to a metal atom generates an electron serving as a charge carrier. Therefore, a transistor comprising a hydrogen-containing oxide semiconductor tends to exhibit self-conducting properties. For this reason, hydrogen in the channel formation region of the oxide semiconductor is preferably reduced as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor, measured by SIMS, is lower than 1 × 10 20 atoms / cm 3 , preferably lower than 5 × 10 19 atoms / cm 3 , preferably lower than 1 × 10 19 atoms / cm 3 , more preferably lower than 5 × 10 18 atoms / cm 3 , more preferably lower than 1 × 10 18 atoms / cm 3 , even more preferably lower than 1 × 10 17 atoms / cm 3 .

[0473] When the oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states are sometimes formed and charge carriers are generated. Accordingly, a transistor containing an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to exhibit self-conducting properties. Therefore, the concentration of an alkali metal or an alkaline earth metal in the channel formation region of the oxide semiconductor, measured by SIMS, is less than or equal to 1 × 10 18 atoms / cm 3 , preferably less than or equal to 2 × 10 18 atoms / cm 3 .

[0474] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region in a transistor, the transistor can exhibit stable electrical characteristics.

[0475] This embodiment may be combined with any of the other embodiments as needed. Where a plurality of structural examples are shown in one embodiment in this specification, the structural examples may be combined as needed. (Embodiment 3)

[0476] In this embodiment, an example of a method for operating a memory device of one embodiment of the present invention will be described. In a memory cell described below as an example, the transistor comprising the ferroelectric described in Embodiment 1 can be used. [Hysteresis properties of the ferroelectric]

[0477] A ferroelectric exhibits hysteresis properties. Fig. Figure 18 is a graph showing an example of hysteresis characteristics of a ferroelectric. The hysteresis characteristics can be measured using a capacitor comprising a ferroelectric (a ferroelectric capacitor). Fig. In Figure 18, the horizontal axis represents a voltage (an electric field) applied to the ferroelectric. The voltage is a potential difference between one electrode and the other electrode of the ferroelectric capacitor. The electric field strength can be obtained by dividing the potential difference by the thickness of the ferroelectric.

[0478] In Fig. In Figure 18, the vertical axis represents the polarization of the ferroelectric. Positive polarization indicates that a positive charge in the ferroelectric is concentrated on one electrode side of the capacitor, and a negative charge is concentrated on the other electrode side of the capacitor. In contrast, negative polarization indicates that a negative charge in the ferroelectric is concentrated on one electrode side of the capacitor, and a positive charge is concentrated on the other electrode side of the capacitor.

[0479] Alternatively, the polarization shown in the diagram in Fig. 18 represented by the vertical axis, be considered positive when a negative charge is concentrated on the side of one electrode of the capacitor and a positive charge is concentrated on the side of the other electrode of the capacitor, and be considered negative when a positive charge is concentrated on the side of one electrode of the capacitor and a negative charge is concentrated on the side of the other electrode of the capacitor.

[0480] As in Fig. As shown in Figure 18, the hysteresis characteristics of the ferroelectric can be represented by a curve 651 and a curve 652. Voltages at the intersections of curve 651 and curve 652 are called saturation polarization voltage +VSP (also referred to as "+VSP") and saturation polarization voltage -VSP (also referred to as "-VSP"). It can be said that +VSP and -VSP have different polarities.

[0481] When a voltage lower than or equal to -VSP is applied to the ferroelectric and then the voltage applied to the ferroelectric is increased, the polarization of the ferroelectric is increased along curve 651. On the other hand, when a voltage higher than or equal to +VSP is applied to the ferroelectric and then the voltage applied to the ferroelectric is increased, the polarization of the ferroelectric is increased along curve 652. Note that +VSP is sometimes referred to as the positive saturation polarization voltage or the first saturation polarization voltage. Furthermore, -VSP is sometimes referred to as the negative saturation polarization voltage or the second saturation polarization voltage. The absolute value of the first saturation polarization voltage may be equal to or different from the absolute value of the second saturation polarization voltage.

[0482] The voltage at the time the polarization of the ferroelectric changes along curve 651 to reach 0 is called the coercive voltage +Vc. The voltage at the time the polarization of the ferroelectric changes along curve 652 to reach 0 is called the coercive voltage -Vc. The value of +Vc and the value of -Vc are each a value between +VSP and -VSP. In some cases, +Vc is called the positive coercive voltage or first coercive voltage, and -Vc is called the negative coercive voltage or second coercive voltage. The absolute value of the first coercive voltage may be equal to or different from the absolute value of the second coercive voltage.

[0483] The maximum value of polarization when no voltage is applied to the ferroelectric (when the voltage is 0 V) is called the remanent polarization +Pr or remanent polarization Pr1, and the minimum value is called the remanent polarization -Pr or remanent polarization Pr2. The absolute value of the difference between the remanent polarization +Pr and the remanent polarization -Pr is called the remanent polarization 2Pr. A larger remanent polarization 2Pr increases the range of change in the capacitance of the ferroelectric capacitor due to polarization reversal. The remanent polarization 2Pr is preferably as large as possible. [Relationship between the polarization of the ferroelectric and Id-Vg properties]

[0484] Next, a structure in which a transistor is provided with a capacitor including a ferroelectric will be described. The relationship between the polarization of a ferroelectric included in a capacitor 620 and the Id-Vg characteristics of a transistor 610 will be described below.

[0485] Fig. 19A and Fig. 19B are equivalent circuit diagrams of a semiconductor device 600 including transistor 610 and capacitor 620, which is a ferroelectric capacitor. Capacitor 620 includes an electrode 663 that also serves as the gate of transistor 610, an electrode 668 connected to a wiring WL, and an insulating layer 667 between electrodes 663 and 668. Transistor 610 includes electrode 663, an electrode 660 connected to a wiring BL, and an electrode 655 connected to a wiring SL. Electrode 660 serves as one of a source electrode and a drain electrode, and electrode 655 serves as the other of a source electrode and a drain electrode. Insulating layer 667 serves as a ferroelectric layer. Fig. 19A and Fig. 19B schematically illustrate the polarization of the insulating layer 667. The electrode 663 may also be referred to as node FN.

[0486] The semiconductor device 600 corresponds to a semiconductor device including the insulator 250 and the conductor 252, which are Fig. 3E in the embodiment 1, and the insulating layer 667 of the capacitor 620 corresponds to that shown in Fig. 3E. Although the structure in which the capacitor 620, which is a ferroelectric capacitor, is connected to the gate of the transistor 610 will be described below, the present invention is not limited to this structure. A structure may be employed in which the insulating layer 667, which is a ferroelectric, is provided as the gate insulating layer of the transistor 610 without providing the capacitor 620 in the semiconductor device 600, as shown in Fig. 19C (such a structure can be called an FeFET). Here, the electrode 663 of the transistor 610 is connected to the line WL. The Fig. 19C corresponds to the transistor 200 which has the Fig. 3A to Fig. 3D in the embodiment 1. The functional principles and the operating method described below can also be applied to the in Fig. 19C, semiconductor device 600 may apply.

[0487] Fig. Figure 19D is a graph showing the Id-Vg characteristics of transistor 610 at the time when the voltage between the source and drain (also referred to as drain voltage or Vd) is constant. In Fig. 19D, the horizontal axis represents a voltage between the source and the gate (also called gate voltage or Vg) and the vertical axis represents a current flowing between the source and the drain (also called drain current or Id).

[0488] In Fig. 19D, characteristics 690 illustrate Id-Vg characteristics of the transistor 610 at the time when no polarization is induced in the insulating layer 667 included in the capacitor 620.

[0489] In Fig. 19D, characteristics 691 represent Id-Vg characteristics of the transistor 610 at the time when the polarization of the insulating layer 667 is the remanent polarization Pr1. Fig. Figure 19A schematically illustrates the polarization of the insulating layer 667 included in the capacitor 620 when the transistor 610 has the characteristics 691.

[0490] Since the remanent polarization Pr1 is a positive polarization, a positive voltage is generated at node FN. Therefore, the Id-Vg characteristics 690 shift in the negative direction of Vg and become characteristics 691. In other words, the threshold voltage of transistor 610 shifts in the negative direction of Vg.

[0491] In Fig. 19D illustrates characteristics 692 Id-Vg characteristics of the transistor 610 at the time when the polarization of the insulating layer 667 is the remanent polarization Pr2. Fig. Figure 19B schematically illustrates the polarization of the insulating layer 667 included in the capacitor 620 when the transistor 610 has the characteristics 692.

[0492] Since the remanent polarization Pr2 is a negative polarization, a negative voltage is generated at node FN. Therefore, the Id-Vg characteristics 690 shift in the positive direction of Vg and become characteristics 692. In other words, the threshold voltage of transistor 610 shifts in the positive direction of Vg.

[0493] As in Fig. 19A to Fig. As shown in Figure 19C, the Id-Vg characteristics of the transistor 610 can be changed according to the polarization of the insulating layer 667, which is a ferroelectric layer. In other words, the threshold voltage of the transistor 610 can be controlled by controlling the polarization of the insulating layer 667. Therefore, the semiconductor device 600 including the transistor 610 and the capacitor 620 can serve as a memory cell for holding binary data.

[0494] For example, when binary data of data "0" or "1" is written into the semiconductor device 600 serving as a memory cell, the polarization of the insulating layer 667 is changed to the remanent polarization Pr1 to write the data "1", and the polarization of the insulating layer 667 is changed to the remanent polarization Pr2 to write the data "0". The Id-Vg characteristics of the semiconductor device 600 in which the data "1" has been written become characteristics 691. The Id-Vg characteristics of the semiconductor device 600 in which the data "0" has been written become characteristics 692.

[0495] Next, an erase operation, a write operation, a hold operation, and a read operation of the semiconductor device 600 will be described. <Löschvorgang>

[0496] Before writing data to the semiconductor device 600 serving as a memory cell, data in the semiconductor device 600 must be erased. In this embodiment, an operation for writing data "0" to the semiconductor device 600 is performed as an erase operation. That is, the polarization of the insulating layer 667 is changed to the remanent polarization Pr2.

[0497] Fig. 20A is a timing chart for describing the erasing process. Fig. 20B is a circuit diagram illustrating a state of the semiconductor device 600 in a period T11. Note that in a circuit diagram and the like, in order to easily understand a potential of a wiring or the like, a symbol indicating the potential of the wiring is sometimes displayed next to the wiring or the like. Furthermore, a boxed letter is sometimes written near a wiring or the like whose potential has changed.

[0498] In period T11, a potential L is applied to the line WL, and a potential H is applied to the line BL and the line SL.

[0499] Note that the gate capacitances of transistor 610 and capacitor 620 are connected in series between wirings WL and BL, and between wirings WL and SL. A voltage applied to capacitor 620 is determined by the ratio of the gate capacitance of transistor 610 to the capacitance of capacitor 620. In this embodiment, the ratio of the gate capacitance of transistor 610 to the capacitance of capacitor 620 is 1:1. Accordingly, the difference between potential H and potential L is set to twice or more the absolute value of VSP. To change the polarization of insulating layer 667 to the remanent polarization Pr2, potential H is applied to wiring BL and wiring SL, and potential L is applied to wiring WL. Potential H is higher than potential L.

[0500] For example, in the case where a potential COM is a reference potential (0 V), the potential H is higher than the potential COM and differs from the potential COM by +VSP. Similarly, the potential L is lower than the potential COM and differs from the potential COM by -VSP.

[0501] Under the above conditions, the potential L is applied to the WL line, and the potential H is applied to the BL line and the SL line, thereby applying -VSP to the capacitor 620. Next, 0 V is applied to the WL line, the BL line, and the SL line in a period T12. That is, the WL line, the BL line, and the SL line are made to have the same potential.

[0502] In the period T12, the polarization of the insulating layer 667 becomes the remanent polarization Pr2 (see Fig. 18). Since, as described above, the remanent polarization Pr2 is a negative polarization, a negative voltage is generated at the node FN. Therefore, the Id-Vg characteristics 690 shift in the positive direction of Vg and become the characteristics 692. This means that the threshold voltage of the transistor 610 shifts in the positive direction of Vg (see Fig. 19D).

[0503] During a period T13, a potential RL is applied to the line WL. The potential RL is described in detail in the description of the hold operation. Note that period T12 can be omitted, and period T11 can be followed by period T13. Period T11 generates a negative voltage at node FN even if period T12 is omitted. <schreibvorgang>

[0504] Next, an operation for writing data "1" into the semiconductor device 600 serving as a memory cell will be described. Fig. Figure 21A is a timing chart for describing the write operation. Fig. 21B is a circuit diagram illustrating a state of the semiconductor device 600 in a period T21.

[0505] After the erasing operation has been performed in period T11, the potential H is applied to the line WL in period T21, and the potential L is applied to the line BL and the line SL. Therefore, +VSP is applied to the capacitor 620, and the polarization of the insulating layer 667 changes along the curve 651 (see Fig. 18). Next, 0 V is applied to the WL line, the BL line, and the SL line during a period T22. This means that the WL line, the BL line, and the SL line are set to the same potential.

[0506] In the period T22, the polarization of the insulating layer 667 becomes the remanent polarization Pr1 (see Fig. 18). Since, as described above, the remanent polarization Pr1 is a positive polarization, a positive voltage is generated at the node FN. Therefore, the Id-Vg characteristics 690 shift in the negative direction of Vg and become the characteristics 691. This means that the threshold voltage of the transistor 610 shifts in the negative direction of Vg (see Fig. 19D).

[0507] In this way, the data "1" can be written into the semiconductor device 600. Since the capacitor 620 is a ferroelectric capacitor, the polarization of the insulating layer 667, which is a ferroelectric, is maintained even if the power supply to the semiconductor device 600 is interrupted. Therefore, data written into the semiconductor device 600 is maintained even if the power supply to the semiconductor device 600 is interrupted. Accordingly, the semiconductor device 600 serves as a non-volatile memory cell.

[0508] The operation for writing data "0" into the semiconductor device 600 is the same as the erasing operation described above. Therefore, it is unnecessary to perform the operation for writing data "0" after the erasing operation. <haltevorgang>

[0509] After data has been written to the semiconductor device 600, the potential RL is supplied to the line WL in a period T23. The potential RL is a potential at which the transistor 610 is turned off, even if the Id-Vg characteristics of the transistor 610 are the characteristics 691 (see Fig. 19D). Therefore, the potential RL is set to a potential lower than the threshold voltage of the properties 691. In addition, in order to hardly cause a change in the polarization of the insulating layer 667, the potential RL is set to a voltage at which a voltage applied to the capacitor 620 is higher than or equal to the coercive voltage -Vc.

[0510] After the write operation, the potential of the wiring WL is preferably the potential RL until the read operation is performed. When the potential of the wiring WL remains as the potential RL, the transistor 610 is surely turned off; therefore, the power consumption of the semiconductor device 600 is reduced. Furthermore, in the case where the semiconductor devices 600 are arranged in a matrix to form a memory cell array, interference in the read operation of another memory cell (semiconductor device 600) can be prevented. Therefore, the memory cell array can have higher reliability.

[0511] It should be noted that period T22 can be omitted and period T21 can be followed by period T23. <lesevorgang>

[0512] Next, the operation for reading data held in the semiconductor device 600 serving as a memory cell will be described. Fig. Figure 22A is a timing diagram for describing the reading operation. Fig. 22B is a circuit diagram illustrating a state of the semiconductor device 600 in the period T31.

[0513] In this embodiment, the reading operation of the semiconductor device 600 holding the data "1" will be described.

[0514] In a period T31, the line BL is precharged to the potential H. This means that after the potential of the line BL is set to the potential H, the line BL is placed in a floating state (a state in which electrical energy is not supplied from anywhere). Furthermore, the potential COM is applied to the line SL.

[0515] Next, in a period T32, a potential RH, which is a read potential, is applied to the wiring WL. The potential RH is a potential higher than or equal to the threshold voltage of the characteristics 691 and lower than the threshold voltage of the characteristics 692. In addition, in order to hardly cause a change in the polarization of the insulating layer 667, the potential RH is set to a voltage at which the voltage applied to the capacitor 620 is lower than or equal to the coercive voltage +Vc.

[0516] In the case where the data "1" is held in the semiconductor device 600, when the potential RH is supplied to the wiring WL, the transistor 610 is turned on, and a current Id1 flows between the source and the drain (see Fig. 19D). Therefore, electrical continuity is established between the line BL and the line SL, and the potential of the line BL, which is in a potential-free state, changes towards the potential COM.

[0517] The case where the potential of the wiring BL changes after the potential RH is supplied to the wiring WL, it can be determined that the data "1" has been written into the semiconductor device 600. The case where it is judged that the potential of the wiring BL does not change even if the potential RH is supplied to the wiring WL, it can be determined that the data "0" has been written into the semiconductor device 600.

[0518] After the reading operation, the potential RL is applied to the wiring WL for a period T33. Since the potential RH is set to a voltage at which the voltage applied to the capacitor 620 is lower than or equal to the coercive voltage +Vc, the polarization of the insulating layer 667 included in the capacitor 620 is less likely to change. Therefore, non-destructive reading of the semiconductor device 600 can be achieved.

[0519] It should be noted that the hysteresis characteristics of the ferroelectric vary depending on the material, structure, and formation method. Accordingly, the potential RH is preferably a voltage at which the voltage applied to the capacitor 620 is 0.8 times or less, preferably 0.6 times or less, the coercive voltage +Vc. Furthermore, the potential RL is preferably a voltage at which the voltage applied to the capacitor 620 is 0.8 times or more, preferably 0.6 times or more, the coercive voltage -Vc.

[0520] The above is the description of the method of operating the storage device.

[0521] At least a portion of this embodiment may be implemented in combination with any of the other embodiments in this description, as desired. (Embodiment 4)

[0522] In this embodiment, a semiconductor device 900 according to one embodiment of the present invention is described. The semiconductor device 900 can serve as a memory device.

[0523] Fig. 23 is a block diagram illustrating a structural example of the semiconductor device 900. The Fig. 23 includes a driver circuit 910 and a memory array 920. The memory array 920 includes at least one memory cell 950. Fig. 23 illustrates an example in which the memory array 920 includes a plurality of the memory cells 950 arranged in a matrix.

[0524] The transistor exemplified in Embodiment 1 can be used for memory cell 950. Using the transistor, the operating speed of the memory device can be increased. This further enables miniaturization and higher integration of the memory device. Furthermore, the capacity per area of the memory device can be increased.

[0525] The driver circuit 910 includes a power switch (PSW) 931, a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912, and a voltage generation circuit 928.

[0526] In the semiconductor device 900, it is possible to appropriately select whether each circuit, signal, and voltage is provided or used. Another circuit or signal may also be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are externally input signals, and a signal RDA is an externally output signal. The signal CLK is a clock signal.

[0527] The BW, CE, and GW signals are control signals. The CE signal is a chip enable signal. The GW signal is a global write enable signal. The BW signal is a byte write enable signal. The ADDR signal is an address signal. The WDA signal is a write data signal, and the RDA signal is a read data signal. The PON1 and PON2 signals are power gating control signals. Note that the PON1 and PON2 signals may be generated in control circuit 912.

[0528] The control circuit 912 is a logic circuit that has a function of controlling the entire operation of the semiconductor device 900. For example, the control circuit 912 performs logical processing of the signals CE, GW, and BW to determine the operation mode (e.g., write operation or read operation) of the semiconductor device 900. The control circuit 912 generates a control signal for the peripheral circuit 911 to execute the operation mode.

[0529] The voltage generation circuit 928 has a function of generating a negative voltage. The WAKE signal has a function of controlling the input of the CLK signal to the voltage generation circuit 928. For example, when an H-level signal is applied as the WAKE signal, the CLK signal is input to the voltage generation circuit 928, and the voltage generation circuit 928 generates a negative voltage.

[0530] The peripheral circuit 911 is a circuit for writing and reading data to / from the memory cell 950. The peripheral circuit 911 includes a row decoder 941, a column decoder 942, a row driver 923, a column driver 924, an input circuit 925 (Input Cir.), an output circuit 926 (Output Cir.), and a sense amplifier 927.

[0531] Row decoder 941 and column decoder 942 have a function of decoding the ADDR signal. Row decoder 941 is a circuit for determining a row to be accessed. Column decoder 942 is a circuit for determining a column to be accessed. Row driver 923 has a function of selecting the row designated by row decoder 941. Column driver 924 has functions such as writing data to memory cell 950, reading data from memory cell 950, and holding the read data.

[0532] Input circuit 925 has a function of holding the WDA signal. Data held in input circuit 925 is output to column driver 924. Data output from input circuit 925 is data (Din) written to memory cell 950. Data (Dout) read from memory cell 950 by column driver 924 is output to output circuit 926. Output circuit 926 has a function of holding Dout. In addition, output circuit 926 has a function of outputting Dout to the outside of semiconductor device 900. The data output from output circuit 926 is the RDA signal.

[0533] The PSW 931 has a function for controlling the supply of V DD to the peripheral circuit 915. The PSW 932 has a function for controlling the supply of V HM to the row driver 923. Here, in the semiconductor device 900, a high power supply voltage V DD , and a low power supply voltage is GND (ground potential). In addition, V HM a high power supply potential used to set the word line to the H level and is higher than V DD . The on / off state of the PSW 931 is controlled by the signal PON1, and the on / off state of the PSW 932 is controlled by the signal PON2. The number of current domains to which V DD is supplied, one is at the peripheral circuit 915 in Fig. 23, but it can be more than one. In this case, a power switch is provided for each power domain.

[0534] Structural examples of further memory cells, each of which can be used as memory cell 950, are shown in Fig. 24A to Fig. 24H described. [DOSRAM]

[0535] Fig. 24A illustrates an example of a circuit structure of a memory cell for a DRAM. In this specification and the like, a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM). A memory cell 951 includes a transistor M1 and a capacitor CA.

[0536] Note that transistor M1 may include a front gate (sometimes simply referred to as a gate) and a back gate. The back gate may be connected to a line supplied with a constant potential or a signal. The front gate and back gate may be connected to each other.

[0537] A first terminal of transistor M1 is connected to a first terminal of capacitor CA. A second terminal of transistor M1 is connected to a line BIL. The gate of transistor M1 is connec...

Claims

[1] Semiconductor device comprising: an oxide semiconductor; a first conductor and a second conductor above the oxide semiconductor, which are separated from each other; a first insulator over the first conductor and the second conductor, the first insulator including an opening that overlaps with a region between the first conductor and the second conductor; a second insulator in the opening, the second insulator being in contact with a top surface of the oxide semiconductor; and a third conductor over the second insulator in the opening, the third conductor comprising a region overlapping with the oxide semiconductor with the second insulator therebetween, wherein the oxide semiconductor comprises a first layer, a second layer over the first layer, and a third layer over the second layer in a region overlapping with the third conductor, wherein the first layer comprises gallium and oxygen, wherein the second layer comprises indium oxide, wherein the third layer comprises indium, gallium and oxygen, and wherein an indium content of the second layer is higher than an indium content of the third layer. [2] A semiconductor device according to claim 1, wherein a conduction band minimum of the first layer is closer to a vacuum level than a conduction band minimum of the second layer; and wherein a conduction band minimum of the third layer is closer to the vacuum level than the conduction band minimum of the second layer. [3] A semiconductor device according to claim 1, wherein the first layer comprises indium, and where an indium content is lower than a gallium content in the first layer. [4] The semiconductor device according to claim 1, wherein in a plan view, a side surface of a part of the first insulator is aligned or substantially aligned with a side surface of the first conductor and a side surface of the second conductor. [5] A semiconductor device according to claim 1, further comprising: a third insulator in contact with a top surface of the third conductor, an upper end portion of the second insulator, and a top surface of the first insulator; and a fourth insulator in contact with a top surface of the third insulator. [6] The semiconductor device according to claim 5, wherein the third insulator comprises alumina. [7] The semiconductor device according to claim 6, wherein the fourth insulator comprises silicon nitride. [8] A semiconductor device according to claim 1, wherein the first conductor and the second conductor each comprise a first conductive layer and a second conductive layer over the first conductive layer, and wherein a shortest distance between the first conductive layer of the first conductor and the first conductive layer of the second conductor is smaller than a shortest distance between the second conductive layer of the first conductor and the second conductive layer of the second conductor. [9] The semiconductor device according to claim 8, wherein, in a plan view, a side surface of a part of the first insulator is aligned or substantially aligned with a side surface of the second conductive layer of the first conductor and a side surface of the second conductive layer of the second conductor. [10] The semiconductor device according to claim 8, wherein the first conductive layer of the first conductor and the first conductive layer of the second conductor each comprise tantalum nitride. [11] A semiconductor device according to claim 8, further comprising: a fifth insulator, wherein the fifth insulator lies in the opening and is in contact with a top surface of the first conductive layer of the first conductor, a side surface of the second conductive layer of the first conductor, a top surface of the first conductive layer of the second conductor, and a side surface of the second conductive layer of the second conductor, and wherein the fifth insulator includes an opening that overlaps with a region between the first conductive layer of the first conductor and the first conductive layer of the second conductor. [12] The semiconductor device of claim 11, wherein the fifth insulator comprises silicon nitride. [13] A semiconductor device according to claim 1, wherein the second insulator comprises a first insulating layer, and wherein the first insulating layer comprises a hafnium-containing oxide. [14] The semiconductor device according to claim 13, wherein the first insulating layer comprises hafnium zirconium oxide. [15] A semiconductor device according to claim 14, wherein the second insulator comprises a second insulating layer over the first insulating layer, and wherein the second insulating layer comprises silicon nitride. [16] The semiconductor device according to claim 14, wherein an upper surface of the first insulating layer is in contact with the third conductor. [17] The semiconductor device according to claim 1, wherein the first layer and the second layer comprise crystallinity. [18] A memory device comprising the semiconductor device according to claim 1. [19] A display device comprising the semiconductor device according to claim 1. [20] An electronic device comprising the semiconductor device according to claim 1.

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