SEMI-CONDUCTOR ARRANGEMENTS AND MANUFACTURING PROCEDURES

Abstract

A method for fabricating semiconductor devices, the fabricated semiconductor devices, and devices for forming the semiconductor devices are described, in which byproducts from etching processes are heated independently and separately from a semiconductor wafer. In certain embodiments, a dielectric is deposited in a trench over a semiconductor substrate, and the dielectric is cut out by an etching process. The etching process includes heating the semiconductor substrate and separately heating a byproduct of the etching process.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over the following preliminary US patent applications: Application No. 63 / 674,724, filed on July 23, 2024, entitled “Enhance Etch Control of Vertical Patterning by Extra Heating Source”, and Application No. 63 / 694,255, filed on September 13, 2024, entitled “Enhance Etch Control of Vertical Patterning by Extra Heating Source”, which are incorporated herein by reference. BACKGROUND

[0002] Semiconductor devices are used in various electronic applications such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers onto a semiconductor substrate. The various material layers are then structured using lithography to create circuit components and elements.

[0003] The semiconductor industry is continuously improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum device size, thus enabling more components to be integrated into a given area. As the semiconductor industry progresses toward higher device density, higher performance, and lower costs, challenges in both manufacturing and design have led to stacked device devices, such as stacked transistors, which include complementary field-effect transistors (CFETs). However, with the reduction of the minimum device size, additional devices are being introduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this revelation are best understood from the following detailed description, when read in conjunction with the accompanying figures. It should be noted that various elements are not drawn to scale, as is common practice in the industry. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 illustrates a perspective view of exemplary complementary field-effect transistors (CFETs) according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13 to Fig. Figure 14 shows intermediate stages in the manufacture of CFETs according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various elements of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, only examples and are not to be understood as limiting. For example, the formation of a first element or a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and it may also include embodiments in which further elements may be formed between the first and second elements, so that the first and second elements need not be in direct contact. Furthermore, this disclosure may repeat reference numerals and / or letters from the various examples.This repetition serves for simplicity and clarity and does not in itself dictate a relationship between the various designs and / or facilities discussed.

[0006] Furthermore, spatially relative terms such as "underlying," "below," "lower," "above," "upper," and the like may be used herein for the sake of simplicity to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the device during use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in another orientation), and the spatially relative terms used herein may be interpreted accordingly.

[0007] The following describes embodiments relating to a specific embodiment in which byproducts of an etching process during the fabrication of a CFET (Complementary Field-Effect Transistor) structure are heated independently of the semiconductor wafer. However, the embodiments described here are intended to illustrate the presented ideas and are not meant to limit the embodiments to this precise description. Instead, the ideas can be implemented in a wide range of processes and devices, and all such processes and devices are intended to be fully encompassed by the scope of these embodiments.

[0008] Fig. Figure 1 illustrates an example of a stacked transistor 10 (comprising the FETs (transistors) 10U and 10L) according to some embodiments. Fig. Figure 1 is a three-dimensional view, and some elements of the stacked transistor have been omitted for a clearer illustration.

[0009] The stacked transistor comprises multiple vertically stacked FETs. For example, a stacked transistor can include a lower nanostructured FET 10L of a first device type (e.g., n / p) and an upper nanostructured FET 10U of a second device type (e.g., p / n). If the stacked transistor is a CFET, the second device type of the upper nanostructured FET 10U is opposite the first device type of the lower nanostructured FET 10L. The nanostructured FETs 10U and 10L comprise semiconductor nanostructures 26 (including lower semiconductor nanostructures 26L and upper semiconductor nanostructures 26U), with the semiconductor nanostructures 26 serving as channel regions for the nanostructured FETs. The lower semiconductor nanostructures 26L are for the lower nanostructure FET 10L, and the upper semiconductor nanostructures 26U are for the upper nanostructure FET 10U. In other embodiments, the stacked transistors can also be used with other transistor types (e.g.,finFETs or the like) are used.

[0010] The gate dielectrics 78 surround the respective semiconductor nanostructures 26. The gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectrics 78. The source / drain regions 62 (including the lower source / drain regions 62L and the upper source / drain regions 62U) are arranged on opposite sides of the gate dielectrics 78 and the respective gate electrodes 80. Each of the source / drain regions 62 can refer to a source or a drain, individually or collectively, depending on the context. Insulating elements (not shown) can be formed to separate desired source / drain regions 62 and / or desired gate electrodes 80.

[0011] In Fig. 2 A wafer is provided comprising the semiconductor substrate 20. The semiconductor substrate 20 can be a semiconductor substrate, such as a bulk semiconductor, which may be doped (e.g., with a p- or n-type dopant) or undoped. Other substrates, such as a multilayer or gradient substrate, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 20 may comprise silicon, germanium, carbon-doped silicon, a III-V compound semiconductor, or the like, or combinations thereof.

[0012] Semiconductor strips 28 are formed from the semiconductor substrate 20 and extend upwards. Each semiconductor strip 28 comprises a semiconductor strip 20' (structured sections of the semiconductor substrate 20, also referred to as semiconductor fins 20') and a multilayer stack 22. The stacked components of the multilayer stack 22 are subsequently referred to as nanostructures. The multilayer stack 22 specifically comprises dummy nanostructures 24A, dummy nanostructures 24B, lower semiconductor nanostructures 26L, and upper semiconductor nanostructures 26U. Dummy nanostructures 24A and dummy nanostructures 24B can also be collectively referred to as dummy nanostructures 24, and the lower semiconductor nanostructures 26L and the upper semiconductor nanostructures 26U can also be collectively referred to as semiconductor nanostructures 26.

[0013] The dummy nanostructures 24A are formed from a first semiconductor material, and the dummy nanostructures 24B are formed from a second semiconductor material that differs from the first. The first and second semiconductor materials can be selected from the available semiconductor materials of the semiconductor substrate 20. The first and second semiconductor materials exhibit high etch selectivity with each other. Therefore, the dummy nanostructures 24B can be removed more quickly in subsequent processes than the dummy semiconductor layers 24A.

[0014] The semiconductor nanostructures 26 (including the lower semiconductor nanostructures 26L and the upper semiconductor nanostructures 26U) are formed from one or more third semiconductor materials. The third semiconductor material(s) can be selected from the semiconductor materials of the semiconductor substrate 20. The lower semiconductor nanostructures 26L and the upper semiconductor nanostructures 26U can be formed from the same semiconductor material or from different semiconductor materials. Furthermore, the first and second semiconductor materials of the dummy nanostructures 24 exhibit high etch selectivity with respect to the third semiconductor material(s) of the semiconductor nanostructures 26. Thus, the dummy nanostructure 24 can be selectively removed in subsequent process steps without substantially removing the semiconductor nanostructures 26.In some embodiments, the dummy semiconductor nanostructures 24A are formed from or comprise silicon germanium, the semiconductor layers 26 consist of silicon, and the dummy nanostructures 24B may be formed from germanium or silicon germanium with a higher germanium atom content than the semiconductor nanostructures 24A.

[0015] The lower semiconductor nanostructures 26L represent channel regions for the lower nanostructure FETs of the CFETs. The upper semiconductor nanostructures 26U represent channel regions for the upper nanostructure FETs of the CFETs. The semiconductor nanostructures 26, which are located directly above / below (e.g., in contact with) the dummy nanostructures 24B, can be used for insulation and may or may not serve as channel regions for the CFETs. The dummy nanostructures 24B are subsequently replaced by insulation structures that define the boundaries between the lower nanostructure FETs and the upper nanostructure FETs.

[0016] To form the semiconductor strips 28, layers of the first, second, and third semiconductor material (arranged as illustrated and described above) can be deposited onto the semiconductor substrate 20. The layers of the first, second, and third semiconductor material can be built up by a process such as vapor deposition (VDE) or molecular beam epitaxy (MBE), or deposited by a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. A structuring process can then be applied to the layers of the first, second, and third semiconductor material, as well as to the semiconductor substrate 20, to define the semiconductor strips 28, which comprise the semiconductor strips 20', the dummy nanostructures 24, and the semiconductor nanostructures 26.

[0017] The semiconductor fins and nanostructures can be structured using any suitable method. The structuring process can, for example, include one or more photolithography processes, including dual or multiple structuring methods. Generally, dual or multiple structuring processes combine photolithography and self-alignment processes, allowing the creation of structures with, for example, spacings smaller than would otherwise be possible using a single direct photolithography process. For instance, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-alignment process.The sacrificial layer is then removed, and the remaining spacers can be used as an etching mask for the patterning process to etch the layers of the first, second, and third semiconductor materials and the semiconductor substrate 20. The etching can be performed by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic.

[0018] As also in Fig. As illustrated in Figure 2, STI regions 32 are formed above the semiconductor substrate 20 and between adjacent semiconductor strips 28. STI regions 32 can comprise a dielectric liner and a dielectric material above the dielectric liner. Both the dielectric liner and the dielectric material can comprise an oxide, such as silicon oxide, a nitride, such as silicon nitride, or the like, or a combination thereof. The formation of the STI regions 32 can involve the deposition of the dielectric layer(s) and the execution of a planarization process, such as a chemical-mechanical polishing (CMP) process, a mechanical polishing process, or the like, to remove excess sections of the dielectric. The deposition processes can include ALD, high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof.In some embodiments, the STI regions 32 comprise silicon oxide produced by an FCVD process and a subsequent annealing process. The dielectric layers are then cut out to define the STI regions 32. The dielectric layer(s) may be cut out such that the upper portions of the semiconductor strips 28 (including the multilayer stacks 22) protrude higher than the remaining STI regions 32.

[0019] After the STI regions 32 have been formed, dummy gate stacks 42 can be formed over and along the sidewalls of the upper sections of the semiconductor strips 28 (the sections that project higher than the STI regions 32). Forming the dummy gate stacks 42 can include forming a dummy dielectric layer 36 on the semiconductor strips 28. The dummy dielectric layer 36 can, for example, be composed of or comprise silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally built up by acceptable methods. A dummy gate layer 38 is formed over the dummy dielectric layer 36. The dummy gate layer 38 can, for example, be deposited by physical vapor deposition (PVD), CVD, or other methods and subsequently planarized, such as by a CMP process.The material of the dummy gate layer 38 is conductive or non-conductive and can be selected from a group that includes amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), or the like. A mask layer 40, which may comprise, for example, silicon nitride, silicon oxynitride, or the like, is formed over the planarized dummy gate layer 38. Next, the mask layer 40 can be patterned by photolithography and etching processes to form a mask, which is then used for etching and patterning the dummy gate layer 38 and possibly the dummy dielectric layer 36. The remaining portions of the mask layer 40, the dummy gate layer 38, and the dummy dielectric layer 36 form dummy gate stacks 42.

[0020] In Fig. Gate spacers 44 and source / drain cutouts 46 or trenches are formed. First, the gate spacers 44 are formed over the multilayer stacks 22 and on the exposed sidewalls of the dummy gate stacks 42. The gate spacers 44 can be formed by conformal forming of one or more dielectric layers and subsequent anisotropic etching of the dielectric layers. The applicable dielectrics can include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which may be formed by a deposition process such as CVD, ALD, or the like.

[0021] Source / drain cutouts 46 are subsequently formed in the semiconductor strips 28. The source / drain cutouts 46 are formed by etching and can extend through the multilayer stacks 22 and into the semiconductor strips 20'. The undersides of the source / drain cutouts 46 can be located above, below, or at the same level as the upper surfaces of the STI regions 32. During the etching processes, the gate spacers 44 and the dummy gate stacks 42 mask some sections of the semiconductor strips 28. The etching can consist of a single etching process or multiple etching processes. Timed etching processes can be used to stop the etching of the source / drain cutouts 46 when the source / drain cutouts 46 have reached a desired depth.

[0022] In Fig. 4. Internal spacers 54 and dielectric insulating layers 56 are formed. The formation of the internal spacers 54 and the dielectric insulating layers 56 can include an etching process that laterally etches the dummy nanostructures 24A and removes the dummy nanostructure 24B. The etching process can be isotropic and selective for the material of the dummy nanostructures 24, so that the dummy nanostructures 24 are etched faster than the semiconductor nanostructures 26. The etching process can also be selective for the material of the dummy nanostructures 24B, so that the dummy nanostructures 24B are etched faster than the dummy nanostructures 24A. Thus, the dummy nanostructures 24B can be completely removed from the area between the lower semiconductor nanostructures 26L (common) and the upper semiconductor nanostructures 26U (common) without completely removing the dummy nanostructures 24A.In some embodiments, where the dummy nanostructures 24B are made of germanium or silicon germanium with a high germanium atom content, the dummy nanostructures 24A are made of silicon germanium with a low germanium atom content, and the semiconductor nanostructures 26 are made of germanium-free silicon, the etching process can include a dry etching process using chlorine gas, with or without plasma. Since the dummygate stacks 42 bulge around the sidewalls of the semiconductor nanostructures 26 (see . Fig. 2) The dummy gate stacks 42 can support the upper semiconductor nanostructures 26U, preventing the upper semiconductor nanostructures 26U from collapsing when the dummy nanostructures 24B are removed. Furthermore, the sidewalls, although illustrated as straight after etching, can be concave or convex.

[0023] Internal spacers 54 are formed on the side walls of the cut-out dummy nanostructures 24A, and dielectric insulating layers 56 are formed between the upper semiconductor nanostructures 26U (shared) and the lower semiconductor nanostructures 26L (shared). As described in more detail below, source / drain regions are subsequently formed in the source / drain cutouts 46, and the dummy nanostructures 24A are replaced by corresponding gate structures. The internal spacers 54 act as an insulating element between the subsequently formed source / drain regions and the subsequently formed gate structures. Furthermore, the internal spacers 54 can be used to prevent damage to the subsequently formed source / drain regions from subsequent etching processes, such as those used to form gate structures.The dielectric insulating layers 56 are used, on the other hand, to insulate the upper semiconductor nanostructures 26U (together) from the lower semiconductor nanostructures 26L (together). Furthermore, the middle semiconductor nanostructures (those of the semiconductor nanostructures 26 that are in contact with the dielectric insulating layers 56) and the dielectric insulating layers 56 can define the boundaries of the lower nanostructure FETs and the upper nanostructure FETs.

[0024] The internal spacers 54 and the dielectric insulating layers 56 can be formed by conformal deposition of an insulating material in the source / drain cutouts 46, on the sidewalls of the dummy nanostructures 24, and between the upper and lower semiconductor nanostructures 26U and 26L, followed by etching of the insulating material. The insulating material can be a hard dielectric, such as a carbon-containing dielectric like silicon oxycarbonitride, silicon oxycarbide, silicon oxynitride, or the like. Other materials with a low dielectric constant (low-k materials) and a k-value of less than 3.5 can be used. The insulating material can be formed by a deposition process such as ALD, CVD, or the like. The etching of the insulating material can be anisotropic or isotropic.After etching, the insulating material has sections that remain in the side walls of the dummy nanostructures 26A (thus forming the inner spacers 54) and sections that remain between the upper and lower semiconductor nanostructures 26U and 26L (thus forming the dielectric insulating layers 56).

[0025] As in Fig. As also illustrated in Figure 4, lower epitaxial source / drain regions 62L are formed. These lower epitaxial source / drain regions 62L are formed in the lower sections of the source / drain cutouts 46. The lower epitaxial source / drain regions 62L are in contact with the lower semiconductor nanostructures 26L and not with the upper semiconductor nanostructures 26U (in Figure 4). Fig. 4 not illustrated, but further below in relation to Fig. 7 illustrated and discussed). The inner spacers 54 electrically isolate the lower epitaxial source / drain regions 62L from the dummy nanostructures 24A, which are replaced by substitute gates in subsequent processes.

[0026] The lower epitaxial source / drain regions 62L are constructed epitaxially and feature a conductivity type suitable for the device type (p or n) of the lower nanostructure FETs. If the lower epitaxial source / drain regions 62L are n-type, the material may include silicon or carbon-doped silicon doped with an n-type dopant such as phosphorus, arsenic, or the like. If the lower epitaxial source / drain regions 62L are p-type, the material may include silicon or silicon germanium doped with a p-type dopant such as boron, indium, or the like. The lower epitaxial source / drain regions 62L may be in-situ doped and implanted with the appropriate p- or n-type dopants, but this is not required.During epitaxy of the lower epitaxial source / drain regions 62L, exposed areas of the upper semiconductor nanostructures 26U (e.g., sidewalls) can be masked to prevent unwanted epitaxial growth on the upper semiconductor nanostructures 26U. After the lower epitaxial source / drain regions 62L have grown, the masks on the upper semiconductor nanostructures 26U can be removed.

[0027] Due to the epitaxial processes used to form the lower epitaxial source / drain regions 62L, the upper surfaces of the lower epitaxial source / drain regions 62L exhibit facets that extend laterally outward beyond the sidewalls of the multilayer stacks 22. In some embodiments, adjacent lower epitaxial source / drain regions 62L remain separate after completion of the epitaxial process. In other embodiments, these facets cause adjacent lower epitaxial source / drain regions 62L of the same FET to fuse together.

[0028] A first contact etch stop layer (CESL) 66 and a first interlayer etch stop layer (ILD) 68 are formed over the lower epitaxial source / drain regions 62L. The first CESL 66 can be formed from a dielectric material exhibiting high etch selectivity with respect to the etching of the first ILD 68, such as silicon dioxide, silicon nitride, silicon oxynitride, or the like, which may be formed by any suitable deposition method, such as CVD, ALD, or the like. The first ILD 68 can be formed from a dielectric material that may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The applicable dielectric material of the first ILD 68 may include silicon dioxide, SiOC, SiON, phosphosilicate glass (PSG), boron silicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.The manufacturing processes can include the deposition of a conformal CESL layer, the deposition of material for the first ILD 68, and a subsequent planarization process.

[0029] Fig. 5A illustrates a first section of cutting out the first ILD 68. In one embodiment, the first ILD 68 can be cut out by one or more etching processes (in Fig. 5A (shown by the arrows labeled 501) can be cut out using an etchant or combination of etchants that are selective for the material of the first ILD 68. Thus, while the exact etchants used depend at least partially on the material of the first ILD 68, in certain embodiments where the first ILD 68 comprises silicon oxide, etchants such as hydrogen fluoride (HF) and ammonia (NH3) can be used to cut out the material of the first ILD 68. However, any suitable etchant may be used.

[0030] The etching process 501 can be initiated by placing the semiconductor substrate 20 in an etching system 500, as described in Fig. Figure 5B illustrates how to position the etching system 500. In some embodiments, the etching system 500 may include an etchant supply system 503 that can deliver one or more gaseous etchants to an etching chamber 504. The etchant supply system 503 feeds the various desired etchants to the etching chamber 504 via an etching regulator 513 and a distributor 505. The etchant supply system 503 may also help to control the flow rate of the etchant or etchants into the etching chamber 504 by controlling the flow and pressure of a carrier gas through the etchant supply system 503.

[0031] In one embodiment, the etchant supply system 503 can comprise several etchant suppliers 511 together with a carrier gas supply 507. Fig. Although only two etchant suppliers 511 are illustrated in Figure 5B, this is merely for clarity, as any number of etchant suppliers 511 can be used, such as one etchant supplier 511 for each etchant to be used within the etching system 500. In an embodiment in which five different etchants are used, there can, for example, be five etchant suppliers 511.

[0032] Each of the etchant suppliers 511 can be a vessel, such as a gas storage tank, located either near or away from the etching chamber 504. In other embodiments, the etchant supplier 511 can be a device that independently produces and supplies the desired etchants. Any suitable source of the desired etchants can be used as an etchant supplier 511, and all such sources are intended to be fully encompassed within the scope of the embodiments.

[0033] In some embodiments, each of the etchant suppliers 511 supplies an etchant to the etching regulator 513 through first lines 502 with first valves 508. The first valves 508 are controlled by a control unit 528, which controls and regulates the introduction of the various etchants and carrier gases into the etching chamber 504.

[0034] A carrier gas supply 507 can provide a desired carrier gas or diluent gas that can be used to force or "carry" the various desired etchants into the etching chamber 504. The carrier gas can be an inert gas or another gas that does not react with the etchant itself or with byproducts of the etchant's reactions. The carrier gas can be, for example, nitrogen (N2), helium (He), argon (Ar), combinations of these gases, or the like, although other suitable carrier gases can also be used.

[0035] The carrier gas supply 507 or the diluent supply can be a vessel, such as a gas storage tank, located either near or away from the etching chamber 504. In other embodiments, the carrier gas supply 507 can be a device that independently processes the carrier gas and supplies it to the etching regulator 513. Any suitable source of carrier gas can be used as the carrier gas supply 507, and all such sources are intended to be fully encompassed within the scope of the embodiments. The carrier gas supply 507 can deliver the desired carrier gas to the etching regulator 513 via a second line 510 with a second valve 506, which connects the carrier gas supply 507 to the first lines 502. The second valve 506 is also controlled by the control unit 528, which monitors and regulates the supply of the various etchants and carrier gases to the etching chamber 504.After combination, the lines can be directed to the etching regulator 513 to allow controlled entry into the etching chamber 504.

[0036] The etching chamber 504 can have any shape suitable for dispersing the etchant and for the etchant coming into contact with the semiconductor substrate 20. In the Fig. In the illustrated embodiment 5B, the etching chamber 504 has a cylindrical side wall and a bottom. However, the etching chamber 504 is not limited to a cylindrical shape, but can also have any other suitable shape, such as a hollow square tube, an octagonal shape, or the like. Furthermore, the etching chamber 504 can be enclosed by an etching chamber housing 515 made of a material that is inert to the various process materials. Thus, the housing of the etching chamber 515 can be made of any suitable material that can withstand the chemical properties and pressure of the etching process. In some embodiments, the housing of the etching chamber 515 can be made of steel, stainless steel, nickel, aluminum, alloys of these materials, combinations of these materials, etc.

[0037] In addition, the etching chamber 504 and the mounting platform 545 can be part of a cluster tooling system (not shown). The cluster tooling system can be used in conjunction with an automatic handling system to position and place the semiconductor substrate 20 in the etching chamber 504 before the etching process, to position and hold the semiconductor substrate 20 during the etching process, and to remove the semiconductor substrate 20 from the etching chamber 504 after the etching process.

[0038] Within the etching chamber 504, a mounting platform 545 is positioned to place and control the semiconductor substrate 20 during the etching process. The mounting platform 345 can hold the semiconductor wafer 100 using electrostatic forces, clamps, vacuum pressure, combinations thereof, or the like, and can also include heating and cooling mechanisms to control the temperature of the semiconductor substrate 20 during the processes.

[0039] In addition, the mounting platform 545 can include one or more first heating elements 530, which serve to increase and control the temperature of the semiconductor substrate 20 during the etching process. In one embodiment, the one or more first heating elements 530 can be a resistance heater or another type of heater to aid in controlling and maintaining the temperature. However, any suitable type of heating element can be used.

[0040] In some embodiments, the etching chamber 504 includes a shower head 532. In one embodiment, the shower head 532 receives the various etchants from the distributor 505 and helps to distribute the various etchants in the etching chamber 504. The shower head 532 can be designed to disperse the etchants uniformly in order to minimize undesirable process conditions that can arise from uneven dispersion. In one embodiment, the shower head 532 can have a circular design with openings evenly dispersed around the shower head 532 to allow the dispersion of the desired etchants into the etching chamber 504. However, any suitable method for introducing the desired etchants, such as inlet openings, can be used to introduce the desired etchants into the etching chamber 504.

[0041] The etching chamber 504 can also be connected to a vacuum pump 525. In one embodiment, the vacuum pump 525 is controlled by the control unit 528 and can be used to regulate the pressure in the etching chamber 504 to a desired value. Furthermore, after completion of the etching process, the vacuum pump 525 can be used to evacuate the etching chamber 504 in order to prepare for the removal of the semiconductor substrate 20.

[0042] Although a number of specific sections of the etching system 500 have been described above, other suitable sections may also be included. For example, end-point supports, linings, and other parts that support the operation or control of the etching process may also be included. All such parts are intended to be fully encompassed within the scope of the embodiments.

[0043] To begin the cutout of the first ILD 68, the process can be started by placing the semiconductor substrate 20 on the mounting platform 545. After the semiconductor substrate 20 has been placed on the mounting platform 545, it can be secured to the mounting platform 545 using a clamping process. In an embodiment where the mounting platform 545 is an electrostatic chuck, the semiconductor substrate 20 can be secured to the mounting platform 545 by applying an initial current (e.g., alternating current) so that electrostatic forces exert a force to hold the semiconductor substrate 20 to the mounting surface of the mounting platform 545.

[0044] Once the semiconductor substrate 20 is positioned and attached to the mounting platform 545, the controller 528 can initiate the cutting process by setting the temperature of the semiconductor substrate 20 using the first heating element 530. In one embodiment, the first heating element 530 can be used to set the temperature to a value between approximately -60 °C and approximately 80 °C. However, any other suitable temperature can also be used.

[0045] Once the temperature has been set using the first heating element 530, the controller 528 can connect one or more of the etchant feeds 511 and one of the carrier gas feeds 507 to the etching chamber 504 to apply a first etchant combination (e.g., hydrogen fluoride (HF) and ammonia (NH3)) to the semiconductor substrate 20. In the embodiment in which hydrogen fluoride and ammonia are used to etch the first ILD 68, where the first ILD 68 comprises silicon oxide, the etching process can react according to the following chemical equation: SiO 2(g) +4HF (g) +4NH 3(g) → SiF 4(g) + 2H2O (g) + 4NH3

[0046] As can be seen, the silicon oxide reacts with the etching agents to form silicon fluoride (SiF4) and water, thereby removing the material of the first ILD 68 from the structure.

[0047] However, the reaction described above is not the only reaction that occurs during the removal process, and other side reactions can occur, forming unwanted byproducts 531 and / or salts that may remain in the source / drain cutouts 46 and on the surface of the semiconductor substrate 20. As an example of such a side reaction, the silicon fluoride formed in the main reaction can react further according to the following chemical equation: SiF 4(g) +2HF (g) + 2NH 3(g) → (NH4)2SiF 6(s)

[0048] In such a side reaction, an undesired byproduct 531, such as ammonium hexafluorosilicate (AFS), is formed. Furthermore, this byproduct 531 is formed as a solid in the resulting source / drain sections 46. If this situation is not improved, the solid form of the ammonium hexafluorosilicate interferes with further etching and can lead to significant differences in the depths formed in the various source / drain sections 46.

[0049] Thus, as in the Fig. As illustrated in Figures 6A to 6B, a secondary heating element 527 is included in the etching chamber 504 to assist in the removal of unwanted byproducts 531 (e.g., ASF) so that the byproducts 531 do not interfere with the rest of the removal process 501. In a particular embodiment, the secondary heating element 527 includes a laser device that can direct a laser beam 529 onto the semiconductor substrate 20, and more specifically, that can direct a laser beam 529 onto the unwanted byproducts 531 placed in the source / drain cutouts 46. In some embodiments, the secondary heating element 527 can have a tunable direction to adjust the angle of incidence of the laser beam 529 striking the semiconductor substrate 20.

[0050] In one embodiment, the laser beam 529 is also tunable such that it comprises one or more wavelengths of light that promote the decomposition of the unwanted byproduct 531. In one embodiment where the unwanted byproduct 531 is AFS, the laser beam 529, for example, comprises light along a spectrum, wherein the light along the spectrum is absorbed by the bonds present in the AFS (e.g., an AFS adsorption spectrum). By using such a spectrum, the laser beam 529 facilitates the decomposition of the AFS upon impact by causing decomposition according to the following chemical formula: (NH4)2SiF 6(s) → SiF 4(g) +2HF (g) + 2NH 3(g)

[0051] By using the laser beam 529, the unwanted byproducts 531 can be more easily removed during the cutting of the first ILD 68. Thus, if the byproducts 531 are not present, they are unable to interfere with the other etching processes 501, and the deviations between the different source / drain cutouts 46 can be reduced.

[0052] Fig. Figure 7 illustrates that after excision of the first ILD 68, an anisotropic etching process is performed to remove the sections of the first CESL 66 that are higher than the excised first ILD 68. After excision, the sidewalls of the upper semiconductor nanostructures 26U are exposed.

[0053] Upper epitaxial source / drain regions 62U are then formed in the upper sections of the source / drain cutouts 46. The upper epitaxial source / drain regions 62U can be epitaxially constructed from the exposed areas of the upper semiconductor nanostructures 26U. The materials of the upper epitaxial source / drain regions 62U can be selected from the same group of candidate materials used to form the lower source / drain regions 62L, depending on the desired conductivity of the upper epitaxial source / drain regions 62U. The conductivity type of the upper epitaxial source / drain regions 62U can be opposite to that of the lower epitaxial source / drain regions 62L in embodiments where the stacked transistors are CFETs. For example, the upper epitaxial source / drain regions 62U can be doped oppositely to the lower epitaxial source / drain regions 62L.Alternatively, the conductivity types of the upper epitaxial source / drain regions 62U and the lower epitaxial source / drain regions 62L can be identical. The upper epitaxial source / drain regions 62U can be doped and / or implanted in situ with an n- or p-type dopant. Adjacent upper source / drain regions 62U can remain separate or be fused after the epitaxial process.

[0054] After the epitaxial source / drain regions 62U have been formed, a second CESL 70 and a second ILD 72 are formed. The materials and formation processes can be similar to those of the first CESL 66 and the first ILD 68, respectively, and are not discussed in detail here. The formation process can include the deposition of the layers for CESL 70 and ILD 72 and the execution of a planarization process to remove the excess portion of the respective layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacers 44, and the masks 86 (if present) or dummy gates 84 are substantially coplanar (within process variations). Thus, the top surfaces of the masks 40 (if present) or dummy gates 38 are exposed by the second ILD 72. In the illustrated embodiment, the masks 40 remain after the removal process.In other embodiments, the masks 40 are removed so that the upper surfaces of the dummy gates 38 are exposed by the second ILD 72.

[0055] Fig. Figure 8 illustrates a replacement gate process in which the dummy gate stacks 42 and the dummy nanostructures 24A are replaced by gate stacks 90. The replacement gate process first involves removing the dummy gate stacks 42 and the remaining portions of the dummy nanostructures 24A. The dummy gate stacks 42 are removed in one or more etching processes, such that cutouts are defined between the gate spacers 44 and the upper portions of the semiconductor strips 28 are exposed. The remaining portions of the dummy nanostructures 24A are then removed by etching, so that the cutouts extend between the semiconductor nanostructures 26. During the etching process, the dummy nanostructures 24A are etched faster than the semiconductor nanostructures 26, the dielectric insulating layers 56, and the inner spacers 54. The etching can be anisotropic.For example, if the dummy nanostructures 24A are made of silicon germanium and the semiconductor nanostructures 26 are made of silicon, the etching process may include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH) or the like.

[0056] The gate dielectrics 78 are then deposited in the cutouts between the gate spacers 44 and on the exposed semiconductor nanostructures 26. The gate dielectrics 78 conform to the exposed surfaces of the cutouts (the removed gate stacks 42 and the dummy nanostructures 24A), including the semiconductor nanostructures 26 and the gate spacer 44. In some embodiments, the gate dielectrics 78 surround all (e.g., four) sides of the semiconductor nanostructures 26. Specifically, the gate dielectrics 78 can be formed on the top surfaces of the fins 20', on the upper surfaces, side walls, and bottom surfaces of the semiconductor nanostructures 26, and on the side walls of the gate spacers 90. The gate dielectric 78 can comprise an oxide, such as silicon oxide or a metal oxide, a silicate, such as a metal silicate, combinations thereof, several layers thereof, or the like.The gate dielectric 78 can comprise a material with a high dielectric constant (high-k material) with a k-value greater than approximately 7.0, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation processes for the gate dielectrics 78 can include molecular beam deposition (MBD), ALD, PECVD, and the like, followed by a planarization process (e.g., CMP) to remove portions of the gate dielectrics 78 above the second ILD 72. Although the gate dielectrics 78 are illustrated as a single layer, they can also comprise multiple layers, such as an interface layer and an overlying high-k dielectric layer.

[0057] The lower gate electrodes 80L are formed on the gate dielectrics 78 around the lower semiconductor nanostructures 26L. The lower gate electrodes 80L surround, for example, the lower semiconductor nanostructures 26L. The lower gate electrodes 80L can be formed from a metal-containing material such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multiple layers thereof, or the like. Although single-layer gate electrodes are illustrated, the lower gate electrodes 80L can include any number of work function tuning layers, any number of barrier layers, any number of adhesive layers, and a filler material.

[0058] The lower gate electrodes 80L are formed from one or more materials suitable for the device type of lower nanostructure FETs. For example, the lower gate electrodes 80L may include one or more work function tuning layers formed from materials suitable for the device type of lower nanostructure FETs. In some embodiments, the lower gate electrodes 80L include an n-work function tuning layer, which may be formed from titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, or the like. In some embodiments, the lower gate electrodes 80L include a p-work function tuning layer, which may be formed from titanium nitride, tantalum nitride, combinations thereof, or the like.Additionally or alternatively, the lower gate electrodes 80L can include a dipole-inducing element suitable for the device type of lower nanostructure FETs. Acceptable dipole-inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0059] The lower gate electrodes 80L can be formed by conformal deposition of one or more gate electrode layers, with the gate electrode layer(s) being cut out. Any acceptable etching process, such as dry etching, wet etching, or a combination thereof, can be used to cut out the gate electrode layer(s). The etching can be anisotropic. By etching the lower gate electrodes 80L, the upper semiconductor nanostructures 26U can be exposed.

[0060] In some embodiments, insulating layers (not explicitly illustrated) can optionally be formed on the lower gate electrodes 80L. The insulating layers serve as insulating elements between the lower gate electrodes 80L and the subsequently formed upper gate electrodes 80U. The insulating layers can be formed by conformal deposition of a dielectric (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, combinations thereof, or the like) and subsequent excision of the dielectric to expose the upper semiconductor nanostructures 26U.

[0061] The upper gate electrodes 80U are then formed on the insulating layers described above (if present) or on the lower gate electrodes 80L. The upper gate electrodes 80U are arranged between the upper semiconductor nanostructures 26U. In some embodiments, the upper gate electrodes 80U surround the upper semiconductor nanostructures 26U. The upper gate electrodes 80U can be formed from the same candidate materials and candidate processes as the lower gate electrodes 80L. The upper gate electrodes 80U are formed from one or more materials suitable for the device type of upper nanostructure FETs. For example, the upper gate electrodes 80U can include one or more work function tuning layer(s) (e.g.,The upper gate electrodes comprise n-function tuning layer(s) and / or p-function tuning layer(s) formed from one or more materials suitable for the device type of upper nanostructure FETs. Although single-layer gate electrodes 80U are illustrated, the upper gate electrodes 80U can comprise any number of function tuning layers, any number of barrier layers, any number of adhesive layers, and a filler material.

[0062] Furthermore, a removal process is performed to smooth the upper surfaces of the upper gate electrodes 80U and the second ILD 72. The removal process for forming the gate dielectrics 78 can be the same as the removal process for producing the upper gate electrodes 80U. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a re-etching process, combinations thereof, or the like, can be used. After the planarization process, the upper surfaces of the upper gate electrodes 80U, the gate dielectrics 78, the second ILD 72, and the gate spacers 44 are substantially coplanar (within process variations). Each respective pair of a gate dielectric 78 and a gate electrode 80 (including an upper gate electrode 80U and / or a lower gate electrode 80L) can be collectively referred to as a "gate structure" 90 (including upper gate structures 90U and lower gate structures 90L).Each gate structure 90 extends along three sides (e.g., a top surface, a side wall, and a bottom surface) of a channel region of a semiconductor nanostructure 26 (see . Fig. 1) The lower gate structures 90L can also extend along the side walls and / or the upper surface of a semiconductor fin 20'.

[0063] As also in Fig. As shown in Figure 8, gate masks 92 are formed over the gate stacks 42. The formation process can include cutting out gate stacks 90, filling the resulting cutouts with a dielectric such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride or the like, and performing a planarization process to remove the excess sections of the dielectric over the second ILD 72.

[0064] In Fig. Metal-semiconductor alloy regions 94 and source / drain contacts 96 are formed by the second ILD 72 to electrically couple the upper epitaxial source / drain regions 62U and / or the lower electrical source / drain regions 62L. To form the source / drain contacts 96, openings are created, for example, through the second ILD 72 and the second CESL 70 using acceptable photolithography and etching techniques. Within the openings, a lining (not illustrated separately), such as a diffusion barrier, an adhesion layer, or the like, and a conductive material are formed. The lining may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be cobalt, tungsten, copper, a copper alloy, silver, gold, aluminum, nickel, or the like. A removal process can be carried out to remove excess material from the upper surfaces of the gate spacers 44 and the second ILD 72.The remaining lining and conductive material form the source / drain contacts 96 in the openings. In some embodiments, a planarization process such as CMP, a back-etching process, combinations thereof, or the like is used. After the planarization process, the upper surfaces of the gate spacers 44, the second ILD 72, and the source / drain contacts 96 are substantially coplanar (within process variations).

[0065] Optionally, metal-semiconductor alloy regions 94 are formed at the interfaces between the source / drain regions 62 and the source / drain contacts 96. The metal-semiconductor alloy regions 94 can be silicide regions formed from a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed from a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), silicon germanide regions formed from both a metal silicide and a metal germanide, or the like. The metal-semiconductor alloy regions 94 can be formed upstream of the source / drain contact material(s) 96 by depositing a metal in the openings for the source / drain contacts 96 and then performing a thermal annealing process. The metal can be any metal that is compatible with semiconductor materials (e.g. silicon, silicon germanium, germanium, etc.).The source / drain regions 62 can react to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other high-melting-point metals, rare-earth metals, or their alloys. A metal can be deposited by a deposition process such as ALD, CVD, PVD, or the like. After thermal annealing, a cleaning process, such as wet cleaning, can be performed to remove any metal residue from the source / drain contact openings 96, such as from the surfaces of the metal-semiconductor alloy regions 94. The source / drain contact material(s) 96 can then be formed on the metal-semiconductor alloy regions 94.

[0066] Then an ESL 104 and a third ILD 106 are formed. In some embodiments, the ESL 104 may comprise a dielectric material exhibiting high etch selectivity with respect to the etching of the third ILD 106, such as aluminum oxide, aluminum nitride, silicon oxycarbide, or the like. The third ILD 106 may be formed by flowable CVD, ALD, or the like, and the material may comprise PSG, BSG, BPSG, USG, or the like, which can be deposited by any suitable process, such as CVD, PECVD, or the like.

[0067] Gate contacts 108 and source / drain vias 110 are subsequently formed to contact the upper gate electrodes 80U and the source / drain contacts 96, respectively. To form the gate contacts 108 and the source / drain vias 110, openings for the gate contacts 108 and the source / drain vias 110 are created, for example, by the third ILD 106 and the ESL 104. The openings can be formed using acceptable photolithography and etching techniques. Within the openings, a lining (not illustrated separately), such as a diffusion barrier, an adhesion layer, or the like, and a conductive material are formed. The lining can comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be cobalt, tungsten, copper, a copper alloy, silver, gold, aluminum, nickel, or the like.A planarization process, such as CMP, can be performed to remove excess material from the top surface of the third ILD 106. The remaining liner and conductive material form the gate contacts 108 and the source / drain vias 110 in the openings. The gate contacts 108 and the source / drain vias 110 can be formed in different processes or in the same process. Although they are shown as being formed with the same cross-section, it should be noted that the gate contacts 108 and the source / drain vias 110 can be formed with different cross-sections, thus preventing short-circuiting of the contacts.

[0068] A front-facing interconnect structure 114 is formed on the device layer 112. The front-facing interconnect structure 114 comprises dielectric layers 116 and layers with conductive elements 118 within the dielectric layers 116. The dielectric layers 116 may include low-k dielectric layers formed from dielectrics with a low k-value. The dielectric layers 116 may further comprise passivation layers formed from dielectrics that do not have a low k-value and dense dielectrics such as undoped silicate glass (USG), silicon dioxide, silicon nitride, or the like, or combinations thereof, over the dielectrics that do not have a low k-value. The dielectric layers 116 may also include polymer layers.

[0069] The conductive elements 118 can comprise conductor tracks and vias, which may be formed using the Damascus process. Conductive elements 118 can include metal conductors and metallic vias, which include diffusion barriers and a copper-containing material over the diffusion barriers. Aluminum pads, electrically connected to the metal conductors and vias, may also be located over them. In some embodiments, the contacts to the lower gate structure 90L and to the lower source / drain regions 80L can be made through the back side of the device layer 112 (e.g., via the side opposite the front interconnect structure 114).

[0070] The use of the secondary heating element 527 allows for independent heating of the unwanted byproducts 531. Furthermore, this heating is separate and independent from the heating controlled by the primary heating element 530. Thus, with such independent heating, the byproducts 531 can be removed and decomposed without affecting the rest of the etching process.

[0071] Although the above description describes the use of the secondary heating element 527 after the initiation of the etching processes 501, this is not intended to restrict the embodiments. Instead, the secondary heating element 527 can be initiated at any point in the process, such as simultaneously with the initiation of the etching processes 501.

[0072] Fig. Figure 10 illustrates another embodiment of the secondary heating element 527. In this embodiment, the secondary heating element 527 can be a laser emitting a laser beam (as above in relation to Fig. (described in section 5B) an ultraviolet light source, an infrared light source, a light-emitting diode (LED), or a vacuum ultraviolet emitter that emits a light beam of 1001. However, any suitable wavelength of light can be used.

[0073] Furthermore, in some embodiments, the secondary heating element 527 can be tunable with respect to both the wavelength of the emitted light and the scanning method. For example, in some embodiments, the wavelength of the generated light can be partially tuned based on the by-product 531 to be decomposed. Additionally, if the output light beam 1001 is not sufficiently large to illuminate the entire desired area, a scanning method can be used in which the semiconductor substrate 20 or the secondary heating element 527 are rotated relative to each other. Any suitable tuning method can be used.

[0074] Fig. Figure 11 illustrates another embodiment of the secondary heating element 527. In this embodiment, the secondary heating element 527 can be a laser emitting a laser beam (as described above in relation to Fig. 5B), or a light-emitting diode LED (as described above in relation to Fig. (as described in Figure 10) is an electron beam generator. In this embodiment, the secondary heating element 527 emits an electron beam 1101 which heats the by-products 531 separately and independently of the rest of the semiconductor substrate 20.

[0075] In this embodiment, the secondary heating element 527 can also be tuned with respect to both the wavelength and angle of incidence of the emitted electron beam 1101 and the scanning method. For example, in some embodiments, the wavelength of the generated electron beam 1101 can be partially tuned based on the desired by-product 531. Furthermore, if the output electron beam 1101 is not large enough to illuminate the entire desired area, a scanning method can be used in which the semiconductor substrate 20 or the secondary heating element 527 are rotated relative to each other.

[0076] Fig. Figure 12 illustrates another embodiment of the secondary heating element 527. In this embodiment, the secondary heating element 527 can be a laser emitting a laser beam (as above in relation to Fig. 5B), a light-emitting diode (LED) (as described above in relation to Fig. 10) or an electron beam generator (as described above in relation to Fig. (described in Figure 11) is a hot neutral injection device. In this embodiment, the secondary heating element 527 introduces gases or radicals into the etching chamber 504, which originate, for example, from a neutral heating box 1201. In one embodiment, the neutral heating box 1201 receives gases and / or radicals and heats the gases and / or radicals using a heating method such as lasers, microwaves (MW), light-emitting diodes, plasma processes, combinations of these methods, or the like. However, any suitable heating method can be used.

[0077] After the gases and / or radicals have been heated in the neutral heating box 1201, they are introduced into the etching chamber 504 through one or more secondary shower heads 1203. In one embodiment, the one or more secondary shower heads 1203 can be operated similarly to the shower head 532 (shown above in relation to the Fig. 5B described). However, any suitable method or device can be used to inject the neutral heating elements into the etching chamber 504.

[0078] Furthermore, in this embodiment, the secondary heating element 527 can be adjusted with respect to the introduction of the hot neutral substances. For example, if the introduction of the hot neutral elements is not large enough to introduce the hot neutral elements into the entire desired area, a scanning method can be used in which the semiconductor substrate 20 or the secondary heating element 527 is rotated relative to each other.

[0079] Fig. Figure 13 illustrates another embodiment of the secondary heating element 527. In this embodiment, the secondary heating element 527 can be a laser emitting a laser beam (as above in relation to Fig. 5B), a light-emitting diode (LED) (as described above in relation to Fig. 10), an electron beam generator (as described above in relation to Fig. 11) or a hot neutral injector (as described above in relation to Fig. (as described in Figure 12) is an electron bombardment device. In this embodiment, the secondary heating element 527 introduces electrons 1301 into the etching chamber 504, e.g., from an electron injector. Once the electrons 1301 have been injected into the etching chamber 504, an electrode 1303 can be used to provide a DC bias voltage that accelerates the electrons 1301 toward the semiconductor substrate 20.

[0080] Although a certain number of embodiments have been presented above, the ideas are not intended to be limited to the embodiments described in detail. Instead, any other suitable method for independently heating the by-products 531 can be used, causing the by-products 531 to decompose. All such methods are intended to be fully encompassed within the scope of the embodiments.

[0081] Fig. Figure 14 illustrates that the ideas presented are not limited to the structures described, even though a specific structure was introduced above. Instead, the ideas can be applied to any suitable material (e.g., a first material 1401) arranged in a cutout within another suitable material (e.g., a second material 1403). In such embodiments, the first material 1401 can be a material such as silicon oxide, silicon oxycarbide, silicon oxynitride, combinations thereof, or the like, while the second material 1403 can be a material such as silicon, silicon nitride, silicon carbonitride, SiOCN, aluminum oxide, titanium nitride, tungsten, combinations thereof, or the like. However, any suitable materials can be used.

[0082] After the first material 1401 has been separated into the second material 1403, the first material 1401 is excised. The first material 1401 can be used with the above reference to the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13 to Fig. The procedures described in section 14 can be eliminated, including the use of an independent heating source to heat and degrade unwanted byproducts 531 during the etching processes 501. Thus, the byproducts 531 can be removed and do not interfere with the remaining sections of the etching processes 501.

[0083] In the embodiment described here, an independent heating source is used to remove the byproducts 531 and salts that form during the chemical etching process. This feature allows the temperature control of the semiconductor substrate 20 and the byproducts 531 to be separated. Such separation helps to improve the depth variation and avoid a drop in the etch rate caused by the use of a generally high temperature.

[0084] According to one embodiment, a method for manufacturing a semiconductor device comprises: depositing a dielectric in a trench over a semiconductor substrate; excising the dielectric by an etching process, wherein the etching process comprises: heating the semiconductor substrate; and separately heating a byproduct of the etching process. In one embodiment, the byproduct is ammonium hexafluorosilicate. In one embodiment, the separate heating is performed at least partially with a laser. In one embodiment, the separate heating is performed at least partially with a light-emitting diode (LED). In one embodiment, the separate heating is performed at least partially with electron injection. In one embodiment, the separate heating is performed at least partially with hot neutral elements. In one embodiment, the separate heating is performed at least partially with an electron beam.

[0085] According to another embodiment, a method for manufacturing a semiconductor device comprises: placing a semiconductor wafer in an etching chamber, the etching chamber comprising a first heating element, the semiconductor wafer comprising a dielectric placed in a first cutout; reacting the dielectric to form a gas and cutting out the dielectric, the reaction of the dielectric additionally generating a byproduct; and heating the byproduct with a second heating element different from the first heating element. In one embodiment, the second heating element is an electron injector. In another embodiment, the second heating element is an electron beam generator. In another embodiment, the second heating element is a neutral heating box. In another embodiment, the second heating element is a light-emitting diode. In another embodiment, the second heating element is a laser.In one embodiment, the byproduct is ammonium hexafluorosilicate.

[0086] According to a further embodiment, a device for manufacturing a semiconductor device, the device comprising: an etching chamber; a mounting platform; a first heating element; and a second heating element independent of the first heating element. In one embodiment, the first heating element is a resistance heating element. In one embodiment, the second heating element is a laser. In one embodiment, the second heating element is an electron beam. In one embodiment, the second heating element is a light-emitting diode. In one embodiment, the second heating element is an infrared generator.

[0087] The above outlines elements of various embodiments so that those skilled in the field can better understand the aspects of this disclosure. Those skilled in the field should note that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as the embodiments introduced herein. They should also understand that such respective designs do not deviate from the spirit and scope of this disclosure and that they can make various changes, substitutions, and modifications to it without deviating from the spirit and scope of this disclosure.

Images