Optical device with anti-reflective coating film and recessed silicon microlens

Abstract

A sacrificial component is placed over one side of a substrate. The sacrificial component has a curved profile. Initial etching processes are performed on the sacrificial component and the substrate from the first side, removing the sacrificial component and defining a first section of the substrate below the sacrificial component as a microlens. The microlens has a second curved profile. A mask layer is formed over the first side of the substrate to surround the microlens. The mask layer and the substrate have different material compositions. Second etching processes are performed on the mask layer and the substrate from the first side. The mask layer is etched at a slower rate than the substrate, so that after the second etching processes are complete, the microlens has a lower height than a second section of the substrate below the mask layer. The mask layer is then removed.

Description

PRIORITY DATA

[0001] The present application is a utility model application of the preliminary US patent application No. 63 / 684,611, filed on August 19, 2024, entitled “Microlens and Anti-reflective Coating Film For Optical Path”, which is incorporated by reference into the present disclosure. BACKGROUND

[0002] The integrated semiconductor (semiconductor) circuitry industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. As IC development progresses, functional density (i.e., the number of interconnected devices per unit area of ​​the chip) has generally increased, while geometric size (i.e., the smallest component (or trace) that can be produced using a manufacturing process) has decreased. This downward scaling process generally offers advantages by increasing production efficiency and reducing associated costs. However, such downward scaling has also increased the complexity of IC processing and manufacturing.For example, microlenses and antireflection coating films (ARC films) have been implemented on various structures, but their fabrication has not been optimized. Consequently, the resulting structures may exhibit suboptimal performance and / or yield.

[0003] Although the conventional methods for manufacturing optical devices were generally suitable, they were therefore not satisfactory in every respect. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present disclosure is best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale and are used for illustrative purposes only. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1A is a perspective view of an IC component according to various aspects of the present disclosure. Fig. Figure 1B is a planar top view of an IC component according to various aspects of the present disclosure. Fig. Figure 1C is a cross-sectional side view of an IC component according to various aspects of the present disclosure. Fig. Figures 2-13 are cross-sectional views of various embodiments of an optical device at different stages of manufacture according to different aspects of the present disclosure. Fig. Figure 14 is a block diagram of a manufacturing system according to various aspects of the present disclosure. Fig. Figure 15 is a flowchart illustrating a method for manufacturing a semiconductor device according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves for simplicity and clarity and does not in itself indicate any relationship between the various embodiments and / or configurations discussed.

[0006] Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition serves for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Furthermore, the formation of a feature on, in conjunction with, and / or coupled with another feature in the present disclosure that follows may include embodiments in which the features are formed in direct contact, and also embodiments in which additional features may be formed between the features, so that the features may not be in direct contact. Furthermore, spatially related terms, for example, "lower," "upper," "horizontal," "vertical," "above," "over," "below," "under," "top," "bottom," "super-," "sub-," etc., and derivatives thereof (e.g., "horizontal," "downward," "upward," etc.) are used.For the sake of simplicity in the present disclosure, the relationship between one feature and another is defined. The spatially related terms are intended to cover different orientations of the device incorporating the features. Furthermore, when a number or range of numbers is described by "about," "approximately," and the like, the term is intended to include numbers that lie within a reasonable range including the described number, such as within + / -10% of the described number or other values ​​as a person skilled in the art would understand. For example, the term "about 5 nm" encompasses the dimensional range from 4.5 nm to 5.5 nm.

[0007] The present disclosure relates generally to semiconductor devices, and more specifically to optical devices formed using semiconductor fabrication processes. More precisely, optical devices (also called photonic devices) can use light (as opposed to electrical signals) to transmit data. For example, computational results obtained by a graphics processing unit (GPU) or a central processing unit (CPU) can be transmitted via optical devices using light. Such an optical data transmission scheme is faster and / or more efficient than data transmission via purely electrical paths. In some applications, the optical devices themselves can also be used to implement the GPUs or CPUs (or parts thereof).

[0008] However, manufacturing optical devices using existing methods can still face certain challenges. For example, optical devices can utilize a polymer material to form their microlenses, which are used to focus light. Unfortunately, microlenses formed using polymer materials may impose stricter requirements on subsequent manufacturing processes (e.g., temperature restrictions) and / or these polymer-based microlenses may be more prone to deformation or other potential defects. Consequently, the polymer-based microlenses suffer from poor performance, such as an inability to focus light onto a intended target.Additionally, optical devices formed by existing methods often lack antireflection films at certain points, which in turn can increase the insertion loss of the optical devices, as optical energy can be excessively reflected and / or refracted away.

[0009] To address the various problems discussed previously, the present disclosure provides a process flow for manufacturing optical devices with silicon microlenses. In other words, the microlenses are formed as part of a silicon wafer. Consequently, the microlenses of the present disclosure exhibit better mechanical / structural integrity, are less prone to deformation, have less stringent requirements for subsequent manufacturing processes, and offer better light focusing capabilities. Furthermore, the optical devices of the present disclosure also utilize various antireflection films to reduce optical energy losses from unintended light reflection / refraction, and consequently, insertion loss is minimized.

[0010] Various aspects of the present revelation will now be discussed below with reference to Fig. 1-15 are discussed. In particular, they describe Fig. 1A-1C describe exemplary types of transistors that can be implemented in a device having an optical device. Fig. 2-13 describes an exemplary manufacturing process flow used to manufacture an optical device according to an embodiment of the present disclosure. Fig. 14 an exemplary manufacturing system and describes Fig. 15 a flowchart according to a method for manufacturing an optical device according to an embodiment of the present disclosure.

[0011] With reference to now Fig. Figures 1A-1B each illustrate a three-dimensional perspective view and a top view of a section of an integrated circuit component (IC component) 90. The IC component 90 may be an intermediate device manufactured during the processing of an IC, or a section thereof, which may include electronic memory circuits and / or other logic circuits, passive components such as resistors, capacitors, and inductors, and active components such as p-FETs (PFETs), n-FETs (NFETs), FinFETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS transistors), bipolar transistors, high-voltage transistors, high-frequency transistors, and / or other memory cells.The present disclosure is not limited to any particular number of devices or device regions or to any particular device configurations, unless otherwise claimed. Although the illustrated IC component 90 is a three-dimensional FinFET device, the concepts of the present disclosure may also apply, for example, to planar FET devices or GAA devices.

[0012] As in Fig. As shown in Figure 1A, the IC component 90 has a substrate 110. The substrate 110 can comprise an elemental semiconductor (single-element semiconductor), such as silicon, germanium, and / or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 110 can be a single-layer material with a uniform composition. Alternatively, the substrate 110 can have multiple layers of material with similar or different compositions suitable for IC component fabrication. In one example, substrate 110 can be a silicon-on-insulator substrate (SOI substrate) that has a semiconductor silicon layer formed on a silicon oxide layer.In another example, the substrate 110 can have a conductive layer, a semiconductor layer, a dielectric layer, other layers, or combinations thereof. Various doped regions, such as source / drain regions, can be formed in or on the substrate 110. The doped regions can be doped with n-type dopants, such as phosphorus or arsenic, and / or p-type dopants, such as boron, depending on the design requirements. The doped regions can be formed directly on the substrate 110, in a p-well structure, an n-well structure, a double-well structure, or using a raised structure. The doped regions can be formed by implantation of dopant atoms, in-situ doped epitaxial growth, and / or other suitable techniques.

[0013] Three-dimensional active regions 120 are formed on the substrate 110. The active regions 120 are elongated, fin-like structures that project upwards from the substrate 110. Therefore, the active regions 120 can henceforth be referred to interchangeably as fins 120 or fin structures 120. The fin structures 120 can be produced using suitable processes, including photolithography and etching. The photolithography process can include forming a photoresist layer over the substrate 110, exposing the photoresist to a structure, performing post-exposure firing processes, and developing the photoresist to form a masking element (not shown) including the resist. The masking element is then used to etch recesses into the substrate 110, leaving the fin structures 120 embedded on the substrate 110.The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, the fin structure 120 can be formed by dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-alignment processes, enabling the creation of structures with, for example, spacings smaller than those obtainable using a single, direct photolithography process. As an example, a layer can be formed over a substrate and structured using a photolithography process. Spacers are formed along the structured layer using a self-alignment process.The layer is then removed, and the remaining spacers or mandrels can then be used to structure the fin structures 120.

[0014] The IC component 90 also features source / drain features 122 formed over the fins 120. The source / drain features 122 may include epi-layers grown epitaxially on the fin structures 120. The IC component 90 further features isolation structures 130 formed over the substrate 110. The isolation structures 130 electrically isolate different components of the IC component 90. The isolation structures 130 may contain silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), a dielectric material with a low k-value, and / or other suitable materials. In some embodiments, the isolation structures 130 may exhibit shallow trench isolation features (STI features). In one embodiment, the isolation structures 130 are formed by etching trenches in the substrate 110 during the formation of the fin structures 120.The trenches can then be filled with a previously described insulating material, followed by a chemical-mechanical planarization process (CMP process). Other insulating structures, such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures, can also be implemented as the insulating structures 130. Alternatively, the insulating structures 130 can have a multilayer structure, for example, with one or more thermal oxide lining layers.

[0015] The IC component 90 also features gate structures 140 formed over the fins 120, which engage with each fin 120 on three sides in a channel region. The gate structures 140 can be dummy gate structures (containing, for example, an oxide gate dielectric and a polysilicon gate electrode), or they can be high-k-value metal-metal (HCM) structures containing a high-k-value gate dielectric and a metal gate electrode, where the HCM structures are formed by replacing the dummy gate structures. Although not shown here, the gate structure 140 can have additional material layers, such as an interface layer over the fins 120, a cover layer, other suitable layers, or combinations thereof.

[0016] With reference to Fig. 1B Several fins 120 are aligned lengthwise along the X-direction, and several gate structures 140 are aligned lengthwise along the Y-direction, i.e., generally perpendicular to the fins 120. In many embodiments, the IC component 90 has additional features, such as gate spacers arranged along the side walls of the gate structures 140, a hard mask layer (or layers) arranged over the gate structures 140, and numerous other features.

[0017] Fig. Figure 1C illustrates a cross-sectional side view of a section of an IC component 200, which is manufactured according to embodiments of the present disclosure, where the IC component 200 is a gate-all-around device (GAA device) and may hereinafter be referred to as a GAA device 200. It is understood that the GAA device 200 may be an NFET in some embodiments or a PFET in other embodiments.

[0018] With reference to Fig. 1C is the cross-sectional view of the GAA device 200 along an XZ plane, where the X direction (the same X direction as in Fig. 1A) the horizontal direction and the Z-direction (the same Z-direction as in Fig. 1A) the vertical direction. The GAA device 200 has a fin structure 210, which may be similar to the previously discussed fin structure 120. In some embodiments, the fin structure 210 contains silicon. The GAA device 200 has source / drain features 220, which may be similar to the previously discussed source / drain features 122. In embodiments where the GAA device 200 is an NFET, the source / drain features 220 contain silicon phosphorus (SiP). In embodiments where the GAA device 200 is a PFET, the source / drain features 220 contain silicon germanium (SiGe).

[0019] The GAA device 200 has a plurality of channels, for example channels 230-233, as in Fig. Figure 1C shows that channels 230-233 each contain a semiconducting material, for example, silicon or a silicon compound. Channels 230-233 are nanostructures (e.g., with sizes on the order of a few nanometers) and can each have an elongated shape extending in the X direction. In some embodiments, channels 230-233 can each have a nanowire shape, a nanolayer shape, a nanotube shape, etc. The cross-sectional profile of the nanowire, nanolayer, or nanotube can be round / circular, square, rectangular, hexagonal, elliptical, or a combination thereof.

[0020] In some embodiments, the lengths (e.g., measured in the X-direction) of channels 230-233 may differ from one another. For example, the length of channel 230 may be less than the length of channel 231, which may be less than the length of channel 232, which may be less than the length of channel 233. In some embodiments, each of the channels 230-233 may not have uniform thicknesses.

[0021] In some embodiments, the spacing (e.g., measured in the Z-direction) between channels 230-233 (each channel from adjacent channels) is in a range of approximately 2 nanometers (nm) to approximately 12 nm. In some embodiments, the thickness (e.g., measured in the Z-direction) of each of channels 230-233 is in a range of approximately 5 nm to approximately 2 nm. In some embodiments, the width (e.g., in the Y-direction) is Fig. (Measured in 1A) each of the channels 230-233 in a range between about 15 nm and about 150 nm. A plurality of interfacial layers (ILs) 240 can also be formed on the upper and lower surfaces of the channels 230-233.

[0022] The GAA device 200 also features gate structures arranged above and between channels 230-233. The gate structures may include gate dielectric layers 250. In some embodiments, the gate dielectric layers 250 have a gate dielectric with a high k-value. The gate structures further feature one or more working exit metal layers 260. In embodiments where the GAA device 200 is an NFET, the one or more working exit metal layers 260 have N working exit metal layers, such as TiAlC. In embodiments where the GAA device 200 is a PFET, the one or more working exit metal layers 260 have P working exit metal layers, such as TiN.

[0023] The gate structures also include filler metals 280. In the section of the gate structure formed over channels 230-233, the filler metals 280 are formed over one or more working exit metal layers 260. The one or more working exit metal layers 260 are U-shaped and are wound around the filler metal 280, and the gate dielectric layer 250 is also U-shaped and wound around the one or more working exit metal layers 260. In sections of the gate structures formed between channels 230-233, the filler metal 280 is completely surrounded (in cross-sectional view) by the one or more working exit metal layers 260, which is then completely surrounded by the gate dielectric layer 250.It is understood that the gate structures may also include an adhesive layer formed between the one or more working exit metal layers 260 and the filler metal 280 to enhance adhesion. However, for the sake of simplicity, such an adhesive layer is not specifically illustrated here.

[0024] The GAA device 200 also features gate spacers 290 and internal spacers 295 arranged on side walls of the gate dielectric layer 250. The internal spacers 295 are also arranged between the channels 230-233. The gate spacers and the internal spacers 295 can contain a dielectric material, for example, a material with a low k-value, such as SiOCN, SiON, SiN, or SiOC.

[0025] The GAA device 200 further comprises source / drain contacts 296 formed over the source / drain features 220. The source / drain contacts 296 may contain a conductive material, such as cobalt, copper, aluminum, tungsten, or combinations thereof. The source / drain contacts 296 are surrounded by barrier layers, for example, barrier layers 297A and 297B, which help to prevent or reduce the diffusion of materials from and into the source / drain contacts 296. In some embodiments, barrier layer 297A contains TiN, and barrier layer 297B contains SiN. A silicide layer 298 may also be formed between the source / drain features 220 and the source / drain contacts 296 to reduce the source / drain contact resistance. The silicide layer 298 may contain a metal silicide material, such as cobalt silicide in some embodiments.

[0026] The GAA device 200 further comprises an interlayer dielectric (ILD) 299. The ILD 299 provides electrical insulation between the various components of the GAA device 200, for example between the gate structures and the source / drain contacts 296.

[0027] The previously discussed FinFET and GAA devices can be implemented in photonic applications. The fabrication of photonic applications can involve microlenses and arc films. However, the microlens fabrication process is not well established, and its implementation on silicon wafers can be challenging. Additionally, structures without arc films can lead to high insertion loss due to energy losses from reflection and / or refraction. To address these issues, the present disclosure includes a microlens and arc film design capable of creating a low-insertion-loss optical input / output path in an advanced silicon photonics packaged product. For example, the present disclosure describes the optical input / output device (e.g., a silicon microlens) on a silicon wafer.The present disclosure also designs a multilayer ARC film scheme on the front and back sides of the silicon wafer, as will be discussed in more detail below.

[0028] Fig. Figures 2-13 illustrate fragmentary cross-sectional side views of a section of an optical device 300 in various stages of manufacture according to embodiments of the present disclosure. Each of the cross-sectional side views is shown along an X-direction (as the horizontal direction) and a Z-direction (as the vertical direction). With reference to Fig. 2 In this manufacturing stage, the optical device 300 has a silicon substrate 310, which is part of a silicon wafer. The optical device 300 has a side 320 and a side 321 opposite side 320 in the vertical Z-direction. Side 320 can also be referred to as a front side, while side 321 can be referred to as a back side.

[0029] One or more layers 350 are formed over the side 321 of the silicon substrate 310. For example, the one or more layers 350 can comprise one or more circuit layers (e.g., circuits comprising the FinFET devices and / or the GAA devices previously described with reference to Fig. (discussed in Sections 1A-1C). These circuit layers can be configured to control certain aspects of the operation of the optical device 300 and / or to perform certain computational tasks. The one or more layers 350 can also include one or more antireflection coating films (ARC films). The ARC films can reduce reflection or refraction of light, which in turn helps to focus light more accurately onto its intended target and reduce insertion loss. The one or more layers 350 can also include certain markers or markings (e.g., copper markers) which can be used to provide alignment between the optical device 300 and other devices that can be coupled to the optical device 300. The one or more layers 350 can also include a protective layer.The protective layer can help protect the components of the optical device 300 from contaminants, moisture, mechanical deformation, etc. In some embodiments, the protective layer can comprise a silicon oxide layer. In other embodiments, the protective layer can contain another type of suitable dielectric material. In some embodiments, the protective layer can have a thickness of approximately 2000 angstroms.

[0030] The silicon substrate 310 may also have a substantially flat or smooth surface (e.g., a surface with very low topographic variations) on side 320. For example, a planarization process, such as a chemical-mechanical polishing (CMP) process, may have been carried out on the surface of the silicon substrate 310 that is exposed opposite side 320.

[0031] Then, a process 360 is performed to form a plurality of sacrificial components, such as sacrificial components 370 and 371, over the area of ​​the silicon substrate 310 exposed opposite side 320. In some embodiments, the process 360 includes a lithography process. In other embodiments, the process 360 includes an output process. In some embodiments, the sacrificial components may contain a material similar to a material of the silicon substrate 310, so that they have the same or a substantially similar etch rate for an upcoming etching process. In other embodiments, the sacrificial components may contain a polymeric material, such as a photoresist material.

[0032] Regardless of the specific type of process used to form the sacrificial components 370 and 371, or the specific material compositions of the sacrificial components 370 and 371, it is understood that the process parameters of process 360 are set to adapt the profile of the sacrificial components 370 and 371 so that the sacrificial components 370 and 371 in the cross-sectional side view of Fig. 2 each can be substantially curved. It is also understood that the flatness of the topography of the surface of the silicon substrate 310, which is exposed opposite side 320, can help to improve the radius of curvature (NU %) of the sacrificial components 370 and 371. The curved cross-sectional profile of the sacrificial components 370 and 371 resembles the curved profile of a desired microlens, since the sacrificial components 370 and 371 are used to define the microlenses of the optical device 300, as discussed in more detail below.

[0033] The sacrificial components 370 and 371 can each have a width (e.g., a horizontal dimension measured in the X direction, also referred to as the critical dimension) 380 and a height 390 (e.g., a vertical dimension measured in the Z direction). In some embodiments, the width 380 is in a range of about 50 micrometers to about 150 micrometers, for example, about 100 micrometers. In some embodiments, the height 390 is in a range of about 2 micrometers to about 3.2 micrometers, for example, about 2.6 micrometers.

[0034] With reference to now Fig. 3-5 An etching process 400 is carried out on the optical device 300 to transfer the shape / profile of the sacrificial components 370 and 371 onto the sections of the silicon substrate 310 below. As shown in Fig. As shown in Figure 3, the etching process 400 can be carried out more precisely on the optical device 300 from page 320 while the sacrificial components 370 and 371 are still intact. In some embodiments, the etching process 400 comprises an anisotropic etching process. In some embodiments, the anisotropic etching process comprises an ICP-RIE process (inductively coupled plasma reactive-ion etching process), in which the etchant is a fluorine-based etchant (e.g., CHF3, CF4, C4F8, NF3, SF6, or a mixture thereof). In some embodiments, the etchant may further contain a reactive gas or a diluting gas (e.g., O2, Ar, He, or a mixture thereof).

[0035] In the manufacturing stage, which in Fig. As shown in Figure 4, the etching process 400 is underway, and the transfer of the cross-sectional profile of the sacrificial components 370 and 371 into sections 420 and 421 of the silicon substrate 310 is taking place step by step, but is not yet complete. For example, the upper sections of the sacrificial components 370 and 371 have been etched away by the etching process 400, but the lower sections of the sacrificial components 370 and 371 still remain. Meanwhile, section 420 of the silicon substrate 310, which is located directly below the sacrificial component 370, now has curved side faces, as does section 421 of the silicon substrate 310, which is located directly below the sacrificial component 371. In this manufacturing stage, an interface 440 can form between the sacrificial component 370 and the section 420 of the silicon substrate 310 (or a similar interface between the sacrificial component 371 and the section 421 of the silicon substrate 310) above (e.g.with a larger vertical uprighting in the Z direction) of an upper surface 450 of the remainder of the silicon substrate 310, which is exposed opposite side 320.

[0036] With reference to now Fig. In this manufacturing stage, the sacrificial components 370 and 371 have been completely etched away by the etching process 400, and the curved cross-sectional profiles of the sacrificial components 370 and 371 have each been transferred to sections of the silicon substrate 470 and 471 located directly beneath the sacrificial components 370 and 371. The sections 470 and 471 of the silicon substrate 310 can serve as microlenses and can therefore be referred to interchangeably as microlenses 470 and 471 in the following. The microlenses 470 and 471 can each have a width 480 (e.g., a horizontal dimension measured in the X direction). In some embodiments, the width 480 of the microlenses 470 / 471 is similar to the width 380 of the sacrificial components 370 / 371. For example, in some embodiments the width 480 of the microlenses 470 / 471 can be within 10% of the width 380 of the sacrificial components 370 / 371.

[0037] The microlenses 470 and 471 also project outwards in the Z-direction from the rest of the silicon substrate 310. Such a vertical projection can be defined as a height 490, measured from the uppermost surface (or a topmost point) of the microlens 470 (or microlens 471) to the surface 450 of the silicon substrate 310 that is exposed opposite side 320. In some embodiments, the height 490 of the microlenses 470 / 471 is similar to the height 390 of the sacrificial components 370 / 371. For example, in some embodiments, the height 490 of the microlenses 470 / 471 may be within 10% of the height 390 of the sacrificial components 370 / 371.

[0038] It is understood that, although the curved shape of the microlenses 470 and 471 is defined based on the curved shape of the sacrificial components 370 and 371, the microlenses 470 / 471 do not necessarily have to have the same curved profiles as the sacrificial components 370 / 371. For example, the sacrificial components 370 or 371 may have a first degree of curvature, while the microlenses 470 or 471 may have a second degree of curvature that differs from the first degree of curvature. In some embodiments, the second degree of curvature may be greater than the first degree of curvature. In other embodiments, the second degree of curvature may be less than the first degree of curvature. In any case, it is understood that the degree of curvature of the microlenses 470 and 471 still depends on the degree of curvature of the sacrificial components 370 and 371 as well as the process parameters of the etching process 400.Therefore, the curved profiles of the sacrificial components 370 and 371, as well as the parameters of the etching process 400, can be carefully set up to achieve a desired degree of curvature for the microlenses 470 and 471 (or other aspects of their shape), so that light can be precisely focused from the microlenses 470 and 471 onto their intended targets.

[0039] With reference to now Fig. 6. A process 500 is carried out to form a mask layer 510 over sections of the surface 450 (which is exposed opposite side 320) of the silicon substrate 310. The material of the mask layer 510 is configured to be different from the silicon substrate 310 (e.g., there is a distinct etch selectivity between the material of the mask layer 510 and the silicon substrate 310). In some embodiments, the material of the mask layer 510 may comprise a metal. In some other embodiments, the material of the mask layer 510 may comprise a polymer (e.g., a photoresist). The mask layer 510 may define recesses 520 and 521 within which the microlenses 470 and 471 are located.

[0040] In some embodiments, the mask layer 510 can be formed by a lithographic process. For example, a continuous mask material layer can be deposited over the area 450 of the silicon substrate 310, including over the areas of the microlenses 470 and 471, via a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or combinations thereof. A lithographic process can then be performed on the continuous mask material layer. The lithographic process can include one or more pre-exposure firing, exposure firing, post-exposure firing, development, rinsing, etc., processes (which are not necessarily performed in this order).

[0041] As a result of the lithography process, the continuous mask material layer is structured into mask layer 510, which is in Fig. Figure 6 shows that different segments of the mask layer 510 laterally surround the microlenses 470 and 471. In other words, each microlens 470 or 471 is surrounded on opposite sides by different segments of the mask layer 510. In this fabrication stage, the mask layer 510 has a height 530, measured from a bottom surface of the mask layer 510 (which may be substantially coplanar to the surface 450 of the silicon substrate 310) to a top surface of the mask layer 510. In some embodiments, the height 530 of the mask layer 510 is greater than the height 490 of the microlenses 470 and 471. This is shown in Fig. 6 obviously, where the top surface (exposed opposite side 320) of the mask layer 510 has a greater vertical orientation in the Z direction than the top surface (exposed opposite side 320) of the microlenses 470 or 471.

[0042] It should be noted that the fact that microlenses 470 and 471 have a silicon material composition is one of the inherent results of the unique fabrication process flow of the present disclosure. Instead of forming the microlenses with a layer of a different material composition (e.g., polymer), the present disclosure defines, for example, sections of the silicon substrate 310 to form the microlenses 470 and 471 using the sacrificial components 370 and 371. In other words, the microlenses 470 and 471 are machined from the silicon substrate 310 and therefore inherently have the same material composition as the silicon substrate 310, as opposed to a non-polymer material composition.

[0043] With reference to now Fig. Figures 7-9 describe how an etching process 600 is performed on the optical device 300 from side 320 to further extend the recesses 520 and 521 vertically downwards in the Z-direction. In some embodiments, the etching process 600 comprises an anisotropic etching process. As discussed previously, the different material compositions between the mask layer 510 and the silicon substrate 310 (e.g., metal versus silicon) allow for significant etch selectivity between the mask layer 510 and the silicon substrate 310 during the etching process 600. For example, the various process parameters (e.g., the type of etchant) of the etching process 600 can be configured such that the silicon substrate 310 can be etched away at a substantially faster rate (e.g., 10 times or more) than the mask layer 510.This allows the mask layer 510 to serve as a protective layer during the etching process 600, so that the sections of the silicon substrate 310 located directly below the mask layer 510 are protected from being etched away by the etching process 600, while the sections of the silicon substrate 310 that are exposed opposite side 320 (i.e., not protected by the mask layer 510) are gradually removed.

[0044] In the manufacturing stage of Fig. At stage 7, the etching process 600 has just started and almost no section of the silicon substrate 310 has yet been etched away, regardless of whether it is protected by the mask layer 510 or not. At the manufacturing stage of Fig. 8. The etching process 600 removed some sections of the silicon substrate 310 that are not protected by the mask layer 510, including the microlenses 470 and 471, as they are also exposed opposite side 320. It should be noted that the etch rate with respect to the microlenses 470 and 471 and the remainder of the exposed sections of the silicon substrate 310 may be similar, since the microlenses 470 and 471 and the remainder of the silicon substrate 310 may have the same material composition (e.g., both may have a silicon composition). Therefore, the curved cross-sectional view profile of the microlenses 470 and 471 can be at least partially preserved regardless of the microlenses 470 and 471 that are etched by the etching process 600.

[0045] During the manufacturing stage, which in Fig. As shown in Figure 9, a sufficient amount of the silicon substrate 310 and the microlenses 470 and 471 has been removed, and the etching process 600 can be stopped. At this point, the remaining sections of the mask layer 510 each have a thickness 610, which may be less than or as large as the height 530 of the mask layer 510 before the etching process 600 is carried out, since the etching process 600 may have etched away a small amount of the mask layer 510. The remaining sections 310A of the silicon substrate 310, which are located directly beneath the mask layers, may each have a height 620, which is measured from the area 450 of the silicon substrate 310 exposed opposite side 320 and an interface between the mask layer 510 and the silicon substrate 310 in the Z-direction.

[0046] Meanwhile, at the end of the etching process 600, the microlenses 470 and 471 may each have a height of 630, which is also measured from the flat surface 450 of the silicon substrate 310, exposed opposite side 320, and from the highest point of the microlens 470 or 471 in the Z-direction. The height 630 may be less than the height 490 of the microlenses 470 and 471 before the etching process 600 is performed, since the etching process 600 may have etched away a slightly larger amount of the microlenses 470 and 471 than the remaining silicon substrate 310 that is not protected by the mask layer 510. The height 630 of the microlenses 470 and 471 is also arranged to be less than the height 620 of the remaining sections 310A of the silicon substrate 310 directly below the mask layer 510.This is done in such a way that the remaining sections 310 of the silicon substrate 310 can help to protect the microlenses 470 and 471 from damage or contamination in subsequent manufacturing processes, as discussed in more detail below.

[0047] With reference to now Fig. 10. A removal process 700 is performed on the optical device 300 to remove the mask layer 510. In some embodiments, the removal process 700 comprises one or more etching processes that can be configured with high etch selectivity between the material of the mask layer 510 (e.g., metal) and the material of the silicon substrate 310. In other words, such an etching process can be configured to etch away the material of the mask layer 510 at a substantially faster rate than the material of the silicon substrate 310. In other embodiments, where the mask layer 510 contains a photoresist material, the removal process 700 can comprise a stripping process or an ashing process configured to remove the photoresist material.

[0048] Notwithstanding the details of the removal process 700, the end result is that recesses, such as recesses 710 and 711 (e.g., like the remnants of recesses 520 and 521 after removal of the mask layer 510), can be formed in the optical device 300. Recesses 710 and 711 are defined by sections 310A of the silicon substrate 310 (which project vertically in the Z-direction toward side 320) and a remnant of the silicon substrate 310. The microlens 470 is located within recess 710, while the microlens 471 is located within recess 711, which is an inherent result of performing the unique manufacturing processes of the present disclosure.For example, the etching processes 600 are carried out with the mask layer 510, which serves as a protective mask to ensure that the sections 310A of the silicon substrate 310 (which partially define the recesses 710 and 711) are larger than the microlenses 470 and 471.

[0049] With reference to now Fig. 11. One or more deposition processes 750 can be performed on the optical device 300 to form an antireflection coating layer (ARC layer) 770 over the side 320 of the silicon substrate 310, including over the surfaces of the microlenses 470 and 471. In some embodiments, the ARC layer 770 is deposited in a conformal manner (e.g., with relatively uniform thicknesses throughout). In some embodiments, the ARC layer 770 can contain a single type of material. In some embodiments, the ARC layer 770 can contain several types of materials (e.g., with multiple layers of different materials). Some candidates for the materials of the ARC layer 770 are listed in the table below. ARC-Materialtyp Brechungsindex X-Wert Y-Wert SiOxFy 1,0~3,0 0-5 0-5 SiOxBy 1,0~3,0 0-5 0-5 SiOxPy 1,0~3,0 0-5 0-5 SiOxNy 1,0~3,0 0-5 0-5 SiCxOy 1,0~3,0 0-5 0-5 SiCxNy 1,0~3,0 0-5 0-5

[0050] It is understood that the candidate materials listed in the previous table can also be used to implement the ARC films in layers 350 formed on side 321 of the silicon substrate 310.

[0051] With reference to now Fig. 12. After removing the mask layer 510, additional processes 800 can be performed on the optical device 300. For example, one of the additional processes 800 can involve a coupling process. More precisely, the optical device 300 can be turned upside down (i.e., side 321 now faces upwards and side 320 now faces downwards) and placed on a support 810 (e.g., a chuck). In other words, the optical device 300 is coupled to the support 810 via side 320. For simplicity, the ARC layer 770 is not specifically in Fig. Figure 12 illustrates, although it is understood that the ARC layer 770 is arranged between the carrier 810 and the rest of the optical device 300.

[0052] As in Fig. As shown in Figure 12, the recesses 710 and 711 are clamped by the presence of the support 810. In other words, the recesses 710 and 711 can appear as cavities clamped between the support 810 and the rest of the optical device 300. It should be noted that, since the height 620 of section 310A of the silicon substrate 310 is greater than the height 630 of the microlenses 470 or 471, a gap vertically separates the support 810 and the microlenses 470 or 471 in the Z-direction. Such a vertical separation ensures that the microlenses 470 and 471 are protected from mechanical damage (e.g., a scratch on the microlens surface), dirt particles, and / or environmental factors (e.g., excessive humidity) in the subsequent manufacturing processes.In other words, the present disclosure specifically dictates the dimensions of the microlenses 470 and 471, as well as the surrounding sections 310A of the silicon substrate 310, to ensure that the microlenses 470 and 471 are securely accommodated within the recesses 710 and 711. Since the microlenses 470 and 471 are not exposed to external elements, potential damage to the microlenses 470 and 471 can be minimized. For example, the additional processes 800 can include additional manufacturing processes performed on the optical device 300 from side 321 (referred to, for example, as back-side processing) while the optical device 300 is being placed on the substrate 810. During these additional manufacturing processes, the microlenses 470 and 471 are protected from potential damage and / or contamination.

[0053] Fig. Figure 13 illustrates the optical device 300 as part of an optical engine comprising a photonic integrated circuit (PIC), an electronic integrated circuit (EIC), and a lens structure incorporating the lens, such as the microlenses 470-471 discussed previously. With reference to Fig. 13. Additional manufacturing processes can form an EIC 830 and a PIC 831 on page 321. The EIC 830 can serve as a central processing unit, which may include the control circuitry (e.g., a microcontroller) for controlling the operation of the devices in the PIC 831. Additionally, the EIC 830 may include the circuitry for processing the electrical signals converted from the optical signals in the PIC 831. In some embodiments, the control circuitry of the EIC 830 and / or the circuitry for processing the electrical signals may be implemented using the previously discussed FinFET devices or GAA devices, which may be formed in a substrate 840 of the EIC 830 (e.g., a silicon substrate).

[0054] The EIC 830 can also incorporate an Interconnect Structure 850, which may include multiple dielectric layers, metal conductors, and vias. The dielectric layers may be composed of silicon oxide, silicon oxynitride, silicon nitride, or the like, or of low-k dielectric materials with k-values ​​less than approximately 3.0. Low-k dielectric materials may include Black Diamond (a registered trademark of Applied Materials), a low-k carbon dielectric, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like. The metal conductors and vias may be formed using Damascene processes and may, for example, include copper on diffusion barrier layers. The diffusion barrier layers may be composed of titanium, titanium nitride, tantalum, tantalum nitride, or the like.A plurality of bonding pads, such as bonding pad 851, are formed over and connected to the metal conductors / vias of the interconnect structure 850. The bonding pads 851 can be made of aluminum and / or copper or combinations thereof, although the disclosure is not limited to this.

[0055] The PIC 831 can have a substrate 841, such as a semiconductor substrate (e.g., a silicon substrate), a dielectric substrate (e.g., a silicon oxide substrate), or a silicon-on-insulator (SOI) substrate. The PIC 831 has an optical coupler 860 configured to be optically coupled to an optical signal source, such as optical fibers or the like. In some embodiments, the optical coupler 860 is a grating coupler, but the disclosure is not limited thereto. The upper sections of the optical coupler 860 can have gratings, so that the optical coupler 860 can have the function of receiving and / or transmitting light.In some embodiments, the optical coupler 860, used for receiving light, receives the light from an overlying light source or optical signal source and transmits the light to a waveguide, which may be structured by sections of the substrate 841. The optical coupler 860, used for transmitting light, receives light from the waveguide and transmits light to a fiber optic array unit 865.

[0056] Therefore, the PIC 831 is configured to receive optical signals, transmit the optical signals within the PIC 831, transmit the optical signals out of the PIC 831, and communicate electronically with an electronic die (e.g., the EIC 830, which is in Fig. (as shown in Figure 13). Accordingly, the PIC 831 can also be responsible for the input / output (I / O) of the optical signals. It is also understood that the PIC 831 may include active devices, such as transistors (e.g., the FinFET devices or the GAA devices discussed previously) and / or diodes (which may include photodiodes). The PIC 831 may also include passive devices, such as capacitors, resistors, or the like. In some embodiments, no active devices are formed, while passive devices may be included in the PIC 831.

[0057] The PIC 831 can also include an interconnect structure 870, which can also have multiple dielectric layers and metal traces and vias, similar to the interconnect structure 850. The interconnect structure 870 can have metal traces or bonding pads that are electrically and physically bonded to the bonding pads 851 of the EIC 830, enabling the establishment of electrical connectivity between the EIC 830 and the PIC 831. The interconnect structure 870 can also have metal traces or bonding pads that are electrically and physically bonded to the bonding pads 871 formed on page 321, which can be used to help establish electrical connectivity between the microelectronic components of the optical device 300 and devices that are external to the optical device 300.

[0058] In some embodiments, the PIC 831 is in wafer form, and the EIC 830 is a fragmented die that has been removed and inserted over the PIC 831. For example, the EIC 830 can be coupled to the PIC 831 by a die-to-wafer bonding process. For example, direct metal-to-metal thermal pressure bonding or any type of hybrid bonding technique can be used to facilitate the coupling of the EIC 830 and the PIC 831. An encapsulation material 880 can also be provided over the PIC 831. The encapsulation material 880 encapsulates the EIC 830 at least laterally. In some embodiments, the encapsulation material 880 can be formed from a translucent material, such as silicon dioxide, or any other suitable oxide material. In some embodiments, an upper surface of the encapsulation material 880 may be higher than an upper surface of the EIC 830.For example, the encapsulation material 880 can cover the top surface of the EIC 830.

[0059] In the embodiment of Fig. 13. A light source and / or a receiver can be positioned above one or more of the microlenses, such as above microlens 470 (e.g., vertically aligned with them). For example, the fiber array unit 865, as a light receiver, can be positioned above and aligned with one or more microlenses 470. The fiber array unit 865 can have an array of units, each configured to receive light, such as light 861. Light 861 can propagate through microlens 470, which can help to focus light 861 with respect to the optical coupler 860.As previously discussed, the unique manufacturing process flow of the present disclosure embeds the microlens 470 within the recess 710, which is defined by structuring the silicon substrate 310 to ensure that the microlens 470 has a lower height than the sections of the silicon substrate 310 surrounding the microlens 470. Consequently, the microlens 470 can be protected from accidental damage (e.g., scratches) and / or contamination. Furthermore, by implementing the microlens 470 with a silicon material that is more durable and less likely to deform, the microlens 470 can be able to focus the light with greater precision.

[0060] It should be noted that Fig. Figure 13 also provides an enlarged view of a section of the optical device 300 (corresponding to what is contained in the dashed box). More precisely, the layers 770, which are arranged on side 320 of the silicon substrate 310, can have a plurality of ARC films, and the layers 350, which are arranged on side 321 of the silicon substrate 310, can also have a plurality of ARC films. Such a multi-film aspect of layers 770 and 350 is clearly illustrated in the enlarged view. By implementing one or more ARC films on both sides of the silicon substrate 310, the optical device 300 can achieve lower insertion loss, since less light will be wasted due to unwanted reflection and / or refraction.

[0061] Fig. Figure 14 illustrates a system 900 for manufacturing integrated circuits, which can be used to manufacture the optical device 300 according to embodiments of the present disclosure. The manufacturing system 900 comprises a plurality of entities 902, 904, 906, 908, 910, 912, 914, 916 ..., N, which are connected by a communication network 918. The network 918 can be a single network or can be a variety of different networks, such as an intranet and the Internet, and can include both wired and wireless communication channels.

[0062] In one embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer, who monitors the products of interest; entity 906 represents an engineer, such as a process engineer for controlling the process and the relevant recipes, or an equipment engineer for monitoring or adjusting the conditions and settings of the processing tools; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor processing tool, such as an EUV tool, used to perform lithography processes for defining the various components of a transistor; entity 912 represents a virtual metrology module linked to processing tool 910;Entity 914 represents an advanced processing control module that is linked to processing tool 910 and additionally to other processing tools; and entity 916 represents a sampling module that is linked to processing tool 910.

[0063] Each entity can interact with other entities and can provide integrated circuit manufacturing capabilities, processing control capabilities, and / or computing capabilities to other entities and / or receive such capabilities from them. Each entity can also have one or more computer systems for performing calculations and executing automations. For example, the advanced processing control module of entity 914 can have multiple computer hardware components in which software instructions are encoded. The computer hardware can include hard disks, flash drives, CD-ROMs, RAM, display devices (such as monitors), and an input / output device (such as a mouse and keyboard). The software instructions can be written in any suitable programming language and designed to perform specific tasks.

[0064] The System 900 for integrated circuit fabrication enables interaction between entities for the purpose of manufacturing integrated circuits (ICs) and advanced processing control of the IC fabrication process. In one embodiment, advanced processing control includes adjusting the processing conditions, settings, and / or recipes of a processing tool that can be applied to the relevant wafers, according to the metrology results.

[0065] In another embodiment, the metrology results are measured using a subset of processed wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, the metrology results are measured using selected fields and points of the subset of processed wafers according to an optimal sampling field / point determined based on various process quality and / or product quality characteristics.

[0066] One of the functions provided by the IC Manufacturing System 900 can facilitate collaboration and information access in areas such as design, engineering and processing, metrology, and advanced processing control. Another function provided by the IC Manufacturing System 900 can integrate systems between facilities, such as between the metrology tool and the processing tool. Such integration allows facilities to coordinate their activities. For example, integrating the metrology tool and the processing tool can enable manufacturing information to be incorporated more efficiently into the manufacturing process or the APC module, and can facilitate wafer data from online or on-site measurement with the metrology tool integrated into the associated processing tool.

[0067] Fig.Figure 15 is a flowchart of a method 1000 for fabricating a semiconductor device according to various aspects of the present disclosure. The method 1000 comprises a step 1010 for forming a sacrificial component over a first side of a substrate. The sacrificial component has a first curved profile in a cross-sectional side view. In some embodiments, the sacrificial component is formed via a lithography process or an output process.

[0068] Method 1000 comprises a step 1020 for performing one or more first etching processes on the sacrificial component and the substrate from the first side. The one or more first etching processes remove the sacrificial component and define a first section of the substrate below the sacrificial component as a microlens. The microlens has a second curved profile in the cross-sectional side view. In some embodiments, the first curved profile and the second curved profile have different degrees of curvature. In some embodiments, the sacrificial component and the microlens have substantially similar dimensions in a horizontal direction in the cross-sectional side view. In some embodiments, the one or more first etching processes comprise an anisotropic etching process. In some embodiments, the anisotropic etching process comprises an inductively coupled plasma reactive ion etching process.In some embodiments, the anisotropic etching process is carried out using a fluorine-based etchant. In some embodiments, the fluorine-based etchant contains CHF3, CF4, C4F8, NF3, or SF6. In some embodiments, the anisotropic etching process is carried out using a reactive gas or a diluting gas. In some embodiments, the mask layer is formed at least partially by defining a metal layer or a polymer layer using a lithography process.

[0069] Method 1000 includes a step 1030 for forming a mask layer over the first side of the substrate. The mask layer surrounds the microlens in the cross-sectional side view. The mask layer and the substrate have different material compositions.

[0070] Method 1000 comprises a step 1040 for performing one or more second etching processes on the mask layer and the substrate from the first side. The mask layer is etched at a slower rate than the substrate, so that the microlens has a lower height than a second section of the substrate below the mask layer in the cross-sectional side view after the one or more second etching processes have been completed. In some embodiments, the one or more second etching processes include an anisotropic etching process. In some embodiments, the mask layer is formed such that it has a greater height than the microlens in the cross-sectional side view before the one or more second etching processes are performed.

[0071] Procedure 1000 includes a step 1050 for removing the mask layer.

[0072] It is understood that the process 1000 may include further steps performed before, during, or after steps 1010-1050. For example, before step 1010 is performed to form the sacrificial component, the process 1000 may include a step of forming one or more layers of material over a second side of the substrate opposite to the first side. The one or more layers of material may include a circuit layer or an antireflective coating layer. As another example, after the mask layer is removed in step 1050, the process 1000 may include a step of forming an antireflective coating layer over the first side of the substrate, including over a top surface of the microlens, as well as a step of bonding the first side of the substrate to a chuck. A gap is formed between the chuck and the first side of the substrate after bonding.The microlens is positioned within the slit. For the sake of simplicity, other additional steps are not discussed in detail here.

[0073] In summary, the present disclosure includes a unique process flow for forming silicon microlenses within a recess for an optical device. For example, curved sacrificial components can be formed over a front face of a silicon substrate, and anisotropic etching processes can be performed from the front face to progressively transfer the curved profile of the sacrificial components onto sections of the silicon substrate, thereby forming silicon-based microlenses. Subsequently, a structured mask layer can be formed to laterally surround the microlenses. The silicon substrate and the microlenses can then be etched from the front face, while the structured mask layer acts as a protective mask, allowing the sections of the silicon substrate protected by the mask layer to have greater heights than the microlenses at the end of the etching process.The mask layer is then removed, and the front of the optical device is attached to a support. Further processing of the optical device can then be carried out from the back.

[0074] The embodiments of the present disclosure offer advantages. However, it is understood that other embodiments may offer additional advantages, and not all advantages are necessarily disclosed herein, and that no particular advantage is required for all devices. One advantage is the improved yield of the optical device. More precisely, microlenses in optical devices are typically formed using a polymer material. However, polymer is susceptible to potential deformation, for example, due to the application of mechanical forces and / or environmental conditions such as high temperature. Deformation of the microlenses can cause the optical device to become defective, thus reducing its yield.By implementing sections of a silicon substrate as microlenses, the microlenses are more durable, have better structural integrity, and are less likely to deform. Consequently, the device yield can be improved. Additionally, existing methods of implementing microlenses can expose them to external elements (e.g., leaving them protruding from the substrate). Therefore, the microlenses can be scratched and / or otherwise accidentally damaged. Here, the microlenses are protected by the surrounding sections of the silicon substrate, which have greater height. In other words, the microlenses are less likely to be accidentally damaged, such as scratched, because they are each contained within a recess.Because they are located in recesses, the microlenses can also be protected from contamination and / or other environmental factors. For these reasons, the optical devices can deliver a better performance in this configuration.

[0075] Another advantage is the improved performance of the optical device. As previously discussed, polymer-based microlenses can be prone to deformation. If such deformation occurs, the polymer microlenses may be unable to focus the light precisely onto the intended targets. In contrast, silicon-based microlenses are less likely to deform. Furthermore, the fact that the silicon-based microlenses are embedded in recesses of the silicon substrate protects them from potential damage, meaning they are able to focus the light with improved precision onto their intended targets. Additionally, the implementation of antireflection layers on both sides of the silicon substrate can effectively reduce unwanted light reflection and / or refraction.This further reduces insertion loss and improves the performance of the optical devices involved. Additional advantages may include compatibility with existing manufacturing processes and easy, cost-effective implementation.

[0076] One aspect of the present disclosure relates to a method. According to the method, a sacrificial component is located above a first side of a substrate. The sacrificial component has a first curved profile in a cross-sectional side view. One or more first etching processes are performed on the sacrificial component and the substrate from the first side. The one or more first etching processes remove the sacrificial component and define a first section of the substrate below the sacrificial component as a microlens. The microlens has a second curved profile in a cross-sectional side view. A mask layer is formed above the first side of the substrate. The mask layer surrounds the microlens in a cross-sectional side view. The mask layer and the substrate have different material compositions. One or more second etching processes are performed on the mask layer and the substrate from the first side.The mask layer is etched at a slower rate than the substrate, so that the microlens has a lower height than a second section of the substrate below the mask layer in the cross-sectional side view after one or more second etching processes have been completed. The mask layer is then removed.

[0077] Another aspect of the present disclosure relates to a process. According to the process, a sacrificial component is formed on the front face of a silicon wafer. The sacrificial component has a first curved shape in a cross-sectional side view. A first etching process is performed on the sacrificial component and the silicon wafer from the front face until the sacrificial component is removed. A first section of the silicon wafer below the sacrificial component is etched into a microlens, which has a second curved shape in a cross-sectional side view. A mask layer is formed over the front face of the silicon wafer. The mask layer defines a recess within which the microlens is located in a cross-sectional side view. The mask layer contains a metallic material or a polymer material.A second etching process is performed on the microlens and the silicon wafer from the front side, extending the recess to the back side of the silicon wafer. The mask layer protects a second section of the silicon wafer from being etched. The mask layer is then removed.

[0078] Another aspect of the present disclosure relates to a structure. The structure comprises a silicon substrate. The structure includes a silicon microlens projecting from a first side of the silicon substrate. The silicon microlens has a curved surface and is laterally surrounded by a section of the silicon substrate that also projects from the first side. This section of the silicon substrate is taller than the silicon microlens. The structure includes one or more antireflection coating layers arranged over the first side of the silicon substrate, including over the silicon microlens and over the section of silicon substrate. The structure includes one or more material layers arranged over a second side of the silicon substrate, opposite to the first side.

[0079] The foregoing explains features of various embodiments so that a person skilled in the art can better understand the aspects of the present disclosure. A person skilled in the art should recognize that he can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same advantages as the embodiments presented herein. A person skilled in the art should also realize that such equivalent designs do not deviate from the essence and scope of the present disclosure and that he can make various changes, substitutions, and modifications therein without deviating from the essence and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 684,611

[0001]

Claims

[1] Procedure, encompassing: Forming a sacrificial component over a first side of a substrate, wherein the sacrificial component has a first curved profile in a cross-sectional side view; Performing one or more first etching processes on the sacrificial component and the substrate from the first side, wherein the one or more first etching processes remove the sacrificial component and define a first section of the substrate below the sacrificial component as a microlens, wherein the microlens has a second curved profile in the cross-sectional side view; Forming a mask layer over the first side of the substrate, wherein the mask layer surrounds the microlens in the cross-sectional side view, and wherein the mask layer and the substrate have different material compositions; Performing one or more second etching processes on the mask layer and the substrate from the first side, wherein the mask layer is etched at a slower rate than the substrate, such that the microlens has a lower height than a second section of the substrate below the mask layer in the cross-sectional side view after the one or more second etching processes have been completed; and Removing the mask layer. [2] Method according to claim 1, wherein the sacrificial component is formed via a lithography process or an output process. [3] Method according to claim 1 or 2, further comprising, prior to forming the sacrificial component, forming one or more material layers over a second side of the substrate opposite the first side, wherein the one or more material layers comprise a circuit layer or an antireflection coating layer. [4] Method according to any one of claims 1 to 3, further comprising, after removal of the mask layer: Forming an antireflection coating layer over the first side of the substrate, including over a top surface of the microlens; and Bonding the first side of the substrate to a chuck, wherein a gap is formed between the chuck and the first side of the substrate after bonding, and wherein the microlens is positioned inside the gap. [5] Method according to any one of claims 1 to 4, wherein the first curved profile and the second curved profile have different degrees of curvature. [6] Method according to any one of claims 1 to 5, wherein the sacrificial component and the microlens have substantially similar dimensions in a horizontal direction in the cross-sectional side view. [7] Method according to any one of claims 1 to 6, wherein at least some of the one or more first etching processes or of the one or more second etching processes comprise an anisotropic etching process. [8] Method according to claim 7, wherein the anisotropic etching process comprises a reactive ion etching process with inductively coupled plasma. [9] Method according to claim 7, wherein the anisotropic etching process is carried out using a fluorine-based etchant. [10] Method according to claim 9, wherein the fluorine-based etchant contains CHF3, CF4, C4F8, NF3, SF6. [11] Method according to claim 7, wherein the anisotropic etching process is carried out using a reactive gas or a diluting gas. [12] Method according to any one of claims 1 to 11, wherein the mask layer is formed at least partially by defining a metal layer or a polymer layer using a lithography process. [13] Method according to any one of claims 1 to 12, wherein the mask layer is formed such that it has a greater height than the microlens in the cross-sectional side view before one or more second etching processes are carried out. [14] Procedures, including: Forming a sacrificial component on a front face of a silicon wafer, wherein the sacrificial component has a first curved shape in a cross-sectional side view; Performing a first etching process on the sacrificial component and the silicon wafer from the front side until the sacrificial component is removed, wherein a first section of the silicon wafer below the sacrificial component is etched into a microlens which has a second curved shape in the cross-sectional side view; Forming a mask layer over the front face of the silicon wafer, wherein the mask layer defines a recess within which the microlens is located in the cross-sectional side view, and wherein the mask layer contains a metal material or a polymer material; Performing a second etching process on the microlens and the silicon wafer from the front side, thereby extending the recess to a rear side of the silicon wafer, with the mask layer protecting a second section of the silicon wafer from being etched; and Removing the mask layer. [15] Method according to claim 14, wherein the recess is extended by the second etching process so that the second section of the silicon wafer has a larger vertical dimension than the microlens in the cross-sectional side view. [16] Method according to claim 14 or 15, further comprising: Formation of one or more initial antireflection coating layers over the back side of the silicon wafer prior to the formation of the sacrificial component; and Formation of one or more second antireflection coating layers over the front of the silicon wafer after removal of the mask layer, including over the microlens and the second section of the silicon wafer. [17] The method of claim 16, further comprising: Attaching the front face of the silicon wafer to a chuck, wherein a gap separates the microlens from the chuck; and Performing additional manufacturing processes on the silicon wafer from the back side after attachment. [18] Structure, comprehensive: a silicon substrate; a silicon microlens projecting from a first side of the silicon substrate, wherein the silicon microlens has a curved surface and is laterally surrounded by a section of the silicon substrate that also projects from the first side, and wherein the section of the silicon substrate has a greater height than the silicon microlens; one or more antireflective coating layers arranged over the first side of the silicon substrate, including over the silicon microlens and over the section of the silicon substrate; and one or more layers of material arranged opposite to the first side of the silicon substrate on a second side. [19] Structure according to claim 18, wherein the one or more material layers comprise one or more circuit-containing layers or one or more additional anti-reflective coating layers. [20] Structure according to claim 18 or 19, wherein the silicon substrate and the silicon microlens have identical material compositions.

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