CONNECTING A PCB SUBSTRATE TO ANOTHER SUBSTRATE OR A

Abstract

A method for bonding a printed circuit board (PCB) substrate and an integrated circuit (IC) die, comprising: applying epoxy into a die cavity of a PCB substrate, the die cavity having a full-surface edge plating; positioning an IC die in the die cavity and substantially aligning a top surface of the IC die with a top surface of the PCB substrate; curing the applied epoxy; curing the applied epoxy; substantially filling a gap between the PCB substrate and the IC die with an underfill; filling a remaining gap between the PCB substrate and the IC die with a non-conductive, aerosol-printed material; curing the underfill and the non-conductive, aerosol-printed material;Using additive manufacturing to deposit conductive traces at desired locations that bridge the gap and connect the PCB substrate and the IC die; and sintering the deposited conductive traces. Related processes are also discussed.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS

[0001] This disclosure is a non-provisional version of US Provisional Application No. 63 / 553,080 entitled "EXTREMELY HIGH BANDWIDTH INTERCONNECTS", filed on February 13, 2024, the disclosure of which is incorporated herein by reference in its entirety. FIELD OF TECHNOLOGY

[0002] This disclosure relates to test and measurement instruments, and more particularly to high bandwidth interconnect structures and methods of fabricating such structures. BACKGROUND

[0003] Test and measurement instruments, such as oscilloscopes, require ever-increasing bandwidths to accurately measure signals at ever-increasing speeds into a device under test (DUT). Generally, test and measurement instruments receive an input signal to be measured from a DUT through an input port, either via a cable or a probe connected between the DUT and the instrument. The input signal is then typically passed to a circuit that performs signal conditioning or other processing on the signal. Often, such a signal conditioning or processing circuit is embodied, for example, in a custom ASIC.

[0004] The developments of the presented technology remedy deficiencies in the state of the art. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows a method for connecting a printed circuit board (PCB) substrate and an integrated circuit die (IC die) according to an exemplary embodiment. Fig. 2 is an isometric view of a substrate-die connection using aerosol printing according to an exemplary embodiment. Fig. 3 is a detailed view of a portion of the substrate-die connection of Fig. 2. Fig. Figure 4 is an exploded view of a portion of the substrate-die connection of Fig. 3. Fig. 5-7 are partial exploded views of a portion of the substrate-die connection of Fig. 3, which show how some of the components are arranged. Fig. Figure 8 shows a section of the substrate-die connection of Fig. 3, after the exploded components of the Fig. 4-7 have been positioned. Fig. 9 shows a method for connecting printed circuit board (PCB) substrates according to an exemplary embodiment. Fig. 10 is an isometric view of a substrate-to-substrate connection using aerosol printing, according to an exemplary embodiment. Fig. 11 is an exploded view of a portion of the substrate-to-substrate connection of Fig. 10. Fig. 12-13 are partial exploded views of a portion of the substrate-to-substrate connection of Fig. 10, which show how some of the components are arranged. Fig. Figure 14 shows part of the substrate-to-substrate connection of Fig. 10, after the exploded components of Fig. 10-13 have been positioned. Fig. 15 shows a method for connecting printed circuit board (PCB) substrates. Fig. 16 is an isometric view of a substrate-to-substrate connection using ribbon bonding according to an exemplary embodiment. Fig. 17 is an exploded view of a portion of the substrate-to-substrate connection of Fig. 16. Fig. 18-19 are partial exploded views of a portion of the substrate-to-substrate connection of Fig. 16, which show how some of the components are arranged. Fig. Figure 20 shows part of the substrate-to-substrate connection of Fig. 16, after the exploded components of Fig. 17-19 have been positioned. DETAILED DESCRIPTION

[0005] The disclosed technology includes interconnect structures that enable higher-bandwidth test and measurement instruments, e.g., with bandwidths from DC to over 110 GHz. Specifically, the designs provide robust, high-performance interconnects for routing the input signal from the external, customer-facing connector on the front panel of an instrument to the inputs of a custom ASIC. There are two major interconnect challenges along this path: 1) connector-to-substrate and 2) substrate-to-ASIC.

[0006] With the first type of connection, i.e., from the terminal to the low-loss substrate, the challenge is that the connection must support an electromechanically robust interface from the outgoing terminal to a low-loss substrate material that meets the characteristic requirements for precious metals, and finally, a connection to an ASIC. Finished connectors (interconnects) supporting 110 GHz cannot be directly connected to the low-loss substrate materials required for the manufacture of ultra-high-bandwidth anti-aliasing filters and attenuators, or to support wire bond pitches for connecting to an ASIC. For example, all 1 mm connectors are designed for a compression connection using PTFE-based or other organic low-loss materials (which exhibit water absorption that cannot be tolerated in an instrument) manufactured using the PCB process.The PCB process doesn't support the small line widths and tolerances required for filters or the pitch for wire or ribbon bonding into the ASIC. Therefore, an interconnect must be developed that allows a lead to be placed on a conformal material etched in the PCB process and then transitioned to a sensitive material (such as quartz) to support filters, attenuators, etc., and connected to the ASIC. Commercial high-speed applications typically don't require the demanding performance of an oscilloscope, so the losses associated with off-the-shelf components are acceptable in these applications, but not for an oscilloscope.

[0007] With the second type of connection, the low-loss substrate to the ASIC, the challenge is, among other things, that ribbon bonds are typically used in RF and millimeter-wave applications, but supporting bandwidths above 80 GHz is not feasible for a variety of reasons. The inductance of ribbon bonds is high-impedance over the required lengths. Parallel bonds, which would reduce inductance, require closer spacing than the tools can support to avoid risking damage and lifting of the die pad metallization (which results in unreliability and low yield). The die pad capacitance is low-impedance over the required sizes. The length over which the combination of high and low impedance occurs becomes large compared to wavelengths above 80 GHz.There are matching techniques that make this easy to achieve in commercial narrowband applications, but they cannot be used for the broadband bandwidth (DC - 110 GHz) required by a power oscilloscope. Substrate materials that can support mode-free (dispersion-free) operation are limited. Aluminum is commonly used at 70 GHz and below, but at 110 GHz, it must be so thin (on the order of 2 mm) that it becomes too difficult to handle without breaking.

[0008] Therefore, the interconnects according to the disclosure have three main objectives: (1) Reliability: Meeting the operating conditions and mechanical stresses for a power instrument; (2) Manufacturability: Manufacturable process and assembly methods without manual adjustments on the test bench and low yield; and (3) Stability: Consistent measurement accuracy of the instrument under various operating conditions. Insertion loss variations over temperature and humidity must be consistent and predictable. It must not exhibit small ground loop resonances (<0.5 dB) that appear, disappear, and shift in frequency during normal operating temperature and humidity variations. It must also not exhibit similar unacceptable changes induced by forces acting on the connector.For example, the customer should not notice any change in the measured values ​​when the cable attached to the connector moves.

[0009] Accordingly, as in Fig. 1-8, a method 150 for bonding a printed circuit board (PCB) substrate 101 and an integrated circuit (IC) die 102 to provide a bonded assembly 100 includes depositing 153 of epoxy 103 into a die cavity 104 of the PCB substrate 101. In certain embodiments, the die cavity 104 may include one or more cutouts or ears 105 that align with a corner of the IC die 102. These ears 105 allow a needle tip to deposit the epoxy 103 between the IC die 102 and the PCB substrate 101. The die cavity 104 is provided with a full-surface edge plating 106. "Full-surface" means that the edge plating 106 extends between the grounds below the signal trace. In embodiments, the full-surface edge plating 106 of the PCB substrate 101 enables an extremely high bandwidth, i.e., over 110 GHz.The method 150 of bonding the PCB substrate 101 and the IC die 102 also includes positioning 154 the IC die 102 in the die cavity 104 and substantially aligning a top surface 107 of the IC die 102 with a top surface 108 of the PCB substrate 101. In this context, “substantially aligning” means that the top surface 107 of the IC die 102 and the top surface 108 of the PCB substrate 101 lie largely or substantially in the same plane without requiring perfect coplanarity, as in . Fig. 8 shown.

[0010] Once the IC die 102 is positioned in the die cavity 104, the method 150 for bonding the PCB substrate 101 and the IC die 102 also includes curing 155 the applied epoxy 103. The curing 155 may, for example, be performed as a flash cure (or rapid cure).

[0011] As in Fig. 1-8, the method 150 for bonding the PCB substrate 101 and the IC die 102 also includes substantially filling 156 a gap 109 between the PCB substrate 101 and the IC die 102 with underfill 110. After the gap 109 is substantially filled, the underfill 110 is cured 158. In this context, “substantially filling” means substantially filling the gap 109 without actually filling the entire gap 109. As particularly illustrated in Fig. As shown in Figure 6, the underfill 110 substantially fills the gap 109, but it does not completely fill the gap. Instead, a remaining gap 111 remains between the PCB substrate 101 and the IC die 102, where the remaining gap 111 is the portion of the gap 109 not filled with the underfill 110. Accordingly, the method 150 for bonding the PCB substrate 101 and the IC die 102 also includes filling 157 the remaining gap 111 between the PCB substrate 101 and the IC die 102 with a non-conductive, aerosol-printed material 112. The non-conductive, aerosol-printed material 112 is printed in place into the remaining gap 111, rather than being printed elsewhere and then positioned in the remaining gap 111 after being printed.Once the non-conductive, aerosol-printed material 112 is placed, the method 150 for bonding the PCB substrate 101 and the IC die 102 also includes curing 158 the non-conductive, aerosol-printed material 112. The underfill 110 may be cured 158 before or after the application of the non-conductive, aerosol-printed material 112.

[0012] The term “PCB Substrate 101” in relation to the Fig. 1-8 is intended to include the electrical conductor of the lower layer of the substrate 113 and the electrical conductor of the upper layer of the substrate 114, unless the context indicates otherwise. Fig. 2-8 also show examples of plated vias 115 on the PCB substrate 101.

[0013] Next, the method 150 for bonding the PCB substrate 101 and the IC die 102 includes using additive manufacturing 159 to deposit conductive traces 116 at the desired locations that bridge the gap 109. The deposited conductive traces 116 are deposited at the desired locations that bridge the gap 109, rather than being deposited elsewhere and then positioned at the desired locations. The deposited conductive traces 116 connect the PCB substrate 101 and the IC die 102 to each other. Then, the method 150 includes sintering 160 the deposited conductive traces 116 to harden the deposited conductive traces 116 and improve the conductivity of the deposited conductive traces 116.

[0014] In embodiments, the method 150 for bonding the PCB substrate 101 and the IC die 102 may include positioning 151 the PCB substrate 101 on a conductive preform 118 before substantially aligning the top surface 107 of the IC die 102 with the top surface 108 of the PCB substrate 101. The conductive preform 118 may be, for example, a conductive epoxy preform. In such embodiments, the method 150 may also include positioning 152 the PCB substrate 101 and the conductive preform 118 on a metal package 117 before substantially aligning 154 the top surface 107 of the IC die 102 with the top surface 108 of the PCB substrate 101.

[0015] As in Fig. As shown in Figures 9-14, a method 250 for bonding printed circuit board (PCB) substrates to provide a bonded assembly 200 includes positioning 252 gold foil 201 on a conductive preform 202 at a desired location for the bond. The gold foil 201 may comprise, for example, 100 mil (=1 / 1000 inch) square and 0.5 mil thick gold sheets. The conductive preform 202 may be, for example, a conductive epoxy preform. In embodiments, the method 250 also includes positioning 251 the conductive preform 202 on a metal housing 203 prior to positioning the gold foil 201 on the conductive preform 202.

[0016] The method 250 for bonding printed circuit board (PCB) substrates also includes positioning 253 a first PCB substrate 204 on the conductive preform 202 to partially overlap the gold foil 201. The first PCB substrate 204 has an edge-plated cutout 205 on the portion of the first PCB substrate 204 that overlaps the gold foil 201. The term "first PCB substrate" is intended to include the top metallization 215 of the first PCB substrate 204 and the bottom metallization 215 of the first PCB substrate 204, unless the context indicates otherwise. In embodiments, the first PCB substrate 204 is positioned on the conductive preform 202 by using fiducials on the first PCB substrate 204 and on the metal housing 203 to align the first PCB substrate 204 on the conductive preform 202. After positioning, the first PCB substrate 204 is cured on the conductive preform 202. The cure 254 can, for example,rapid hardening, e.g. by applying heat via a collet.

[0017] The method 250 for bonding printed circuit board (PCB) substrates also includes positioning 255 a second PCB substrate 206 on the conductive preform 202 to partially overlap the gold foil 201 while maintaining a gap 207 between the first PCB substrate 204 and the second PCB substrate 206. The term "second PCB substrate" is intended to include the top metallization 217 of the second PCB substrate 206 and the bottom metallization 216 of the second PCB substrate 206, unless the context indicates otherwise. In embodiments, edge features of the first PCB substrate 204 are used to properly position the second PCB substrate 206 on the conductive preform 202. Preferably, the width 208 of the gap 207 between the first PCB substrate 204 and the second PCB substrate 206 is between about 1 mil and about 7 mils. More preferably, the width 208 of the gap 207 is between about 3 mils and about 5 mils.More preferably, the width 208 of the gap 207 is about 4 mils.

[0018] The second PCB substrate 206 has an edge-plated cutout 209 at the portion of the second PCB substrate 206 that overlaps the gold foil 201. When the second PCB substrate 206 is positioned on the conductive preform 202, the edge-plated cutout 205 of the first PCB substrate 204 is substantially aligned with the edge-plated cutout 209 of the second PCB substrate 206. In this context, “substantially aligned” means that the end edges 210 of the edge-plated cutout 205 of the first PCB substrate 204 and the end edges 211 of the edge-plated cutout 209 of the second PCB substrate 206 are largely or substantially in line, without requiring perfect collinearity; an example of this is shown in Fig. 14 shown.

[0019] Next, the method 250 for bonding printed circuit board (PCB) substrates also includes filling 256 the gap 207 between the first PCB substrate 204 and the second PCB substrate 206, the edge-plated cutout 205 of the first PCB substrate 204, and the edge-plated cutout 209 of the second PCB substrate 206 with a low-loss, non-conductive material 212. Once the gap 207 is filled, the applied low-loss, non-conductive material 212 is cured 257.

[0020] Next, the method 250 for connecting printed circuit board (PCB) substrates also includes the use of additive manufacturing 258 to deposit conductive traces 213 at desired locations that bridge the gap 207. The conductive traces 213 interconnect the first PCB substrate 204 and the second PCB substrate 206 across the gap 207. In some embodiments, additive manufacturing is performed using aerosol printing to deposit the conductive traces 213. Aerosol printing techniques enable finer precision of the line width and gap width. After deposition, the method 250 may include sintering 259 the deposited conductive traces 213 to harden the conductive traces 213 and improve the conductivity of the conductive traces 213.

[0021] As in Fig.15-20, a method 350 for bonding printed circuit board (PCB) substrates to provide a bonded assembly 300 includes positioning 352 gold foil 301 on a conductive preform 302 at a desired location for the bond. The gold foil 301 may comprise, for example, 100 mil square and 0.5 mil thick gold sheets. The conductive preform 302 may be, for example, a conductive epoxy preform. In embodiments, the method 350 also includes positioning 351 the conductive preform 302 on a metal housing 303 before positioning the gold foil 301 on the conductive preform 302.

[0022] The method 350 for bonding printed circuit board (PCB) substrates also includes positioning 353 a first PCB substrate 304 on the conductive preform 302 to partially overlap the gold foil 301. The term "first PCB substrate" is intended to include the top metallization 311 of the first PCB substrate 304 and the bottom metallization 310 of the first PCB substrate 304, unless the context indicates otherwise. The first PCB substrate 304 has an edge plating 305 at an edge-plated portion of the first PCB substrate 304, the edge-plated portion being where the first PCB substrate 304 overlaps the gold foil 301. In embodiments, the first PCB substrate 304 is positioned on the conductive preform 302 by using fiducials on the first PCB substrate 304 and on the metal housing 303 to align the first PCB substrate 304 on the conductive preform 302.After positioning, the first PCB substrate 304 is cured on the conductive preform 302. The curing 354 can be a rapid cure, e.g., by applying heat via a collet.

[0023] The method 350 for bonding printed circuit board (PCB) substrates also includes positioning 355 a second PCB substrate 306 on the conductive preform 302 to partially overlap the gold foil 301 while leaving a gap 307 between the first PCB substrate 304 and the second PCB substrate 306. Preferably, the width 308 of the gap 307 between the first PCB substrate 304 and the second PCB substrate 306 is between about 0.3 mil and about 2 mils. More preferably, the width 308 of the gap 307 is between about 0.7 mil and about 1.3 mil. Even more preferably, the width 308 of the gap 307 is about 1 mil. The term “second PCB substrate” is intended to include the upper metallization 313 of the second PCB substrate 306 and the lower metallization 312 of the second PCB substrate 306, unless the context indicates otherwise.

[0024] Next, the method 350 for connecting printed circuit board (PCB) substrates also includes attaching 356 ribbon bonds 309 to bridge the gap 307 at the edge-plated portion of the first PCB substrate 304. The ribbon bonds 309 connect the first PCB substrate 304 and the second PCB substrate 306 together.

[0025] Preferably, there is no edge plating 305 on the second PCB substrate 306 where the ribbon bonds 309 connect the first PCB substrate 304 and the second PCB substrate 306. More specifically, only one of the two PCB substrates—either the first PCB substrate 304 or the second PCB substrate 306—has an edge plating 305 where the ribbon bonds 309 connect the first PCB substrate 304 and the second PCB substrate 306. EXAMPLES

[0026] Examples of the disclosed technologies are listed below. A particular implementation of the technologies may include one or more, and any combination, of the examples described below.

[0027] Example 1 includes a method for bonding a printed circuit board (PCB) substrate and an integrated circuit (IC) die, the method comprising: applying epoxy into a die cavity of a PCB substrate, the die cavity having a full-surface edge plating; positioning an IC die in the die cavity and substantially aligning a top surface of the IC die with a top surface of the PCB substrate; curing the applied epoxy; substantially filling a gap between the PCB substrate and the IC die with underfill; filling a remaining gap between the PCB substrate and the IC die with a non-conductive, aerosol-printed material; curing the underfill and the non-conductive, aerosol-printed material;Using additive manufacturing to deposit conductive traces at desired locations that bridge the gap and connect the PCB substrate and the IC die; and sintering the deposited conductive traces.

[0028] Example 2 includes the method of any Example 1, wherein the PCB substrate is positioned on a conductive preform before substantially aligning the top side of the IC die with the top side of the PCB substrate.

[0029] Example 3 includes the method of Example 2, wherein the PCB substrate and conductive preform are positioned on a metal package before the top side of the IC die is substantially aligned with the top side of the PCB substrate.

[0030] Example 4 includes a method for connecting printed circuit board (PCB) substrates, the method comprising: positioning a gold foil on a conductive preform at a desired location for connection; positioning a first PCB substrate on the conductive preform to partially overlap the gold foil, the first PCB substrate having an edge-plated cutout at a portion of the first PCB substrate that overlaps the gold foil; curing the positioned first PCB substrate on the conductive preform;Positioning a second PCB substrate on the conductive preform to partially overlap the gold foil and leave a gap between the first PCB substrate and the second PCB substrate, the second PCB substrate having an edge-plated cutout on a portion of the second PCB substrate that overlaps the gold foil, the edge-plated cutout of the second PCB substrate being substantially aligned with the edge-plated cutout of the first PCB substrate; Filling the gap between the first PCB substrate and the second PCB substrate, the edge-plated cutout of the first PCB substrate, and the edge-plated cutout of the second PCB substrate with a low-loss, non-conductive material; Curing the applied low-loss, non-conductive material;Using additive manufacturing to deposit conductive traces at desired locations that bridge the gap and to interconnect the first PCB substrate and the second PCB substrate; and sintering the deposited conductive traces.

[0031] Example 5 includes the method of Example 4, wherein the conductive preform is positioned on a metal housing before the gold foil is positioned on the conductive preform.

[0032] Example 6 includes the method of any one of Examples 4 to 5, wherein the use of additive manufacturing to deposit conductive traces includes the use of aerosol printing to deposit the conductive traces.

[0033] Example 7 includes a method for connecting printed circuit board (PCB) substrates, the method comprising: positioning a gold foil on a conductive preform at a desired location for connection; positioning a first PCB substrate on the conductive preform to partially overlap the gold foil, the first PCB substrate having edge plating on an edge-plated portion of the first PCB substrate; curing the positioned first PCB substrate on the conductive preform; positioning a second PCB substrate on the conductive preform to partially overlap the gold foil and leave a gap between the first PCB substrate and the second PCB substrate; and placing ribbon bonds that bridge the gap at the edge-plated portion of the first PCB substrate and interconnect the first PCB substrate and the second PCB substrate.

[0034] Example 8 includes the method of Example 7, wherein the conductive preform is positioned on a metal housing before the gold foil is positioned on the conductive preform.

[0035] The aspects may operate on specially designed hardware, firmware, digital signal processors, or on a specially programmed general-purpose computer with a processor that operates according to programmed instructions. As used herein, the terms "controller" or "processor" are intended to include microprocessors, microcomputers, ASICs, and special-purpose hardware controllers. One or more aspects may be embodied in the form of computer-usable data and computer-executable instructions, for example, in one or more program modules executed by one or more computers (including supervisory modules) or other devices. In general, program modules include routines, programs, objects, components, data structures, etc., that perform specific tasks or implement specific abstract data types when executed by a processor in a computer or other device.The computer-executable instructions may be stored on a non-transitory computer-readable medium such as a hard disk, an optical disk, a removable storage device, solid-state memory, RAM, etc. As one skilled in the art will appreciate, the functionality of the program modules may be arbitrarily combined or distributed in various embodiments. Furthermore, the functionality may be embodied in whole or in part in firmware or hardware equivalents such as integrated circuits, field-programmable gate arrays (FPGAs), and the like. Certain data structures may be used to more effectively implement one or more aspects of the disclosed systems and methods, and such data structures are contemplated as part of the computer-executable instructions and computer-usable data described herein.

[0036] The contents of this document have been presented for purposes of illustration and description, but this content is not intended to be exhaustive or limited to the disclosure in the form disclosed. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the disclosure. The aspects of the disclosure in this document were selected and described to explain the principles of the disclosure and practical application, and to enable others skilled in the art to understand the disclosure with various modifications as are suitable for particular uses.

[0037] Accordingly, the disclosure in this specification is intended to encompass all possible combinations of the particular features mentioned in this specification. For example, if a particular feature is disclosed in connection with a particular exemplary embodiment, that feature may, to the extent possible, also be used in connection with other exemplary embodiments.

[0038] Furthermore, the described versions of the disclosed subject matter have many advantages that have either been described or would be obvious to a person of ordinary skill. However, not all of these advantages or features are required in all versions of the disclosed devices, systems, or methods.

[0039] Although this application refers to a method comprising two or more defined steps or operations, the defined steps or operations may be performed in any order or simultaneously, unless the context excludes such possibilities.

[0040] The terminology used in this description is for the purpose of describing particular aspects only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” “the,” and “the” include the plural forms, unless the context clearly indicates otherwise. It is further understood that the terms “comprises” or “comprising,” when used in this description, specify the presence of certain features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. For example,an article "comprising" or "comprising" components A, B and C may contain only components A, B and C, or it may contain components A, B and C together with one or more other components.

[0041] Directions such as "vertical," "horizontal," "right," and "left" are also used for convenience and to refer to the views depicted in the illustrations. In practice, however, the device may have a variety of orientations. For example, a feature shown as vertical, horizontal, right, or left in the illustrations may not have the same orientation or direction in actual use.

[0042] It should be understood that the present subject matter may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth in this specification. Rather, these exemplary embodiments are provided so that this subject matter will be thorough and complete, and will convey the disclosure to those skilled in the art. Indeed, the subject matter is intended to cover alternatives, modifications, and equivalents of these exemplary embodiments included within the scope and spirit of the subject matter set forth in this disclosure. Furthermore, in the detailed description of the present subject matter, specific details are set forth in order to provide a thorough understanding of the present subject matter. However, it will be apparent to one skilled in the art that the present subject matter may be practiced without such specific details. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 553,080

[0001]

Claims

[1] A method of joining a printed circuit board (PCB) substrate and an integrated circuit (IC) die, the method comprising: Applying epoxy into a die cavity of a PCB substrate, the die cavity having a full-area edge plating; Positioning an IC die in the die cavity and substantially aligning a top surface of the IC die with a top surface of the PCB substrate; Curing of the applied epoxy; essentially filling a gap between the PCB substrate and the IC die with an underfill; Filling any remaining gap between the PCB substrate and the IC die with non-conductive, aerosol-printed material; Curing the underfill and the non-conductive, aerosol-printed material; Using additive manufacturing to deposit conductive traces at desired locations that bridge the gap and connect the PCB substrate and the IC die; and Sintering of the applied conductor tracks. [2] The method of claim 1, further comprising positioning the PCB substrate on a conductive preform before substantially aligning the top side of the IC die with the top side of the PCB substrate. [3] The method of claim 2, further comprising positioning the PCB substrate and the conductive preform on a metal package before substantially aligning the top side of the IC die with the top side of the PCB substrate. [4] A method of joining printed circuit board (PCB) substrates, the method comprising: Positioning a gold foil on a conductive preform at a desired location for the connection; Positioning a first PCB substrate on the conductive preform to partially overlap the gold foil, the first PCB substrate having an edge-plated cutout at a portion of the first PCB substrate that overlaps the gold foil; Curing the positioned first PCB substrate on the conductive preform; Positioning a second PCB substrate on the conductive preform to partially overlap the gold foil and leave a gap between the first PCB substrate and the second PCB substrate, the second PCB substrate having an edge-plated cutout at a portion of the second PCB substrate that overlaps the gold foil, the edge-plated cutout of the second PCB substrate being substantially aligned with the edge-plated cutout of the first PCB substrate; Filling the gap between the first PCB substrate and the second PCB substrate, the edge-plated cutout of the first PCB substrate and the edge-plated cutout of the second PCB substrate with a low-loss, non-conductive material Curing of the applied low-loss, non-conductive material; Using additive manufacturing to deposit conductive traces at desired locations that bridge the gap and connect the first PCB substrate and the second PCB substrate; and Sintering of the applied conductor tracks. [5] The method of claim 4, further comprising positioning the conductive preform on a metal housing before positioning the gold foil on the conductive preform. [6] The method of claim 4 or 5, wherein using additive manufacturing to apply conductive traces comprises using aerosol printing to apply the conductive traces. [7] A method of joining printed circuit board (PCB) substrates, the method comprising: Positioning gold foil on a conductive preform at a desired location for the connection; Positioning a first PCB substrate on the conductive preform to partially overlap the gold foil, the first PCB substrate having an edge plating on an edge-plated portion of the first PCB substrate; Curing the positioned first PCB substrate on the conductive preform; Positioning a second PCB substrate on the conductive preform to partially overlap the gold foil and leave a gap between the first PCB substrate and the second PCB substrate; and Placing ribbon bonds that bridge the gap at the edge-plated portion of the first PCB substrate and interconnect the first PCB substrate and the second PCB substrate. [8] The method of claim 7, further comprising positioning the conductive preform on a metal housing before placing the gold foil on the conductive preform.

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