SELECTIVE CANAL WIDTH SCALING USING IMPLANTS

Abstract

An integrated circuit comprises a source region and a drain region, and a body of semiconductor material extending between the source and drain regions. The body has first and second end portions, and a middle portion between the first and second end portions. The body comprises an implantation species, wherein a concentration of the implantation species in the middle portion of the body is 10% or more higher than a concentration of the implantation species in the first and second end portions. The integrated circuit comprises a gate structure on the middle portion of the body, a first gate spacer on the first end portion of the body, and a second gate spacer on the second end portion of the body. The implantation species comprises, for example, a non-dopant element with an atomic mass unit of 80 or less or a halide, e.g.one of fluorine, chlorine, argon or boron.

Description

AREA OF REVELATION

[0001] The present disclosure relates to integrated circuits and, more particularly, to fin-based transistor devices. BACKGROUND

[0002] A FinFET is a transistor constructed around a thin strip of semiconductor material (commonly referred to as the fin). The transistor includes standard field-effect transistor (FET) nodes, including a gate structure, a source region, and a drain region. The conductive channel of the FinFET device is present on the outer portions of the fin adjacent to the gate structure. Specifically, current flows along / inside both sidewalls of the fin (sides perpendicular to the substrate surface) as well as along the top of the fin (side parallel to the substrate surface). Because the conductive channel of such configurations is essentially present along the three distinct outer, planar regions of the fin, such a FinFET design is sometimes referred to as a tri-gate transistor.Other types of FinFET configurations are also available, such as so-called double-gate FinFETs, in which the conductive channel is present primarily only along the two sidewalls of the fin (and not along the top of the fin). Another transistor type is a so-called gate-all-around transistor, which comprises nanoribbons or nanowires extending between the source and drain regions. In such gate-all-around devices, the gate structure wraps around the nanoribbons or nanowires. The nanoribbons or nanowires are "released" during gate processing by removing sacrificial layers of a multilayer fin. In such fin-based transistors, a portion of the fin structure may remain below the gate structure and the source and drain regions. This portion of the fin is generally referred to as a partial fin. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A, Fig. 1B, Fig. 1C and Fig. 1D show various views of an integrated circuit (IC) comprising a plurality of devices, each device comprising a respective fin, each fin comprising a central portion between two end portions, the central portion of at least one fin having a different thickness profile and / or a different taper profile compared to the two corresponding end portions of the at least one fin and / or the central portion of the at least one fin comprising an implantation species, according to an embodiment of the present disclosure. Fig. 2 shows a diagram illustrating a variation of a concentration of an implantation species along the depth of a central portion of a fin, according to an embodiment of the present disclosure. Fig. 3 illustrates a flowchart illustrating a method 300 for forming any IC (e.g., the IC of Fig. 1A-1D) according to an embodiment of the present disclosure. Fig. 4A1, Fig. 4A2, Fig. 4A3, Fig. 4B1, Fig. 4B2, Fig. 4B3, Fig. 4C1, Fig. 4C2, Fig. 4C3, Fig. 4D1, Fig. 4D2, Fig. 4D3, Fig. 4E1, Fig. 4E2 and Fig. 4E3 show different views of an IC (e.g. the IC of the Fig. 1A-1D) at different stages of processing according to the methodology of Fig. 3 according to an embodiment of the present disclosure. Fig. 5 illustrates a computing system implemented with integrated circuit structures formed using the techniques disclosed herein, according to some embodiments of the present disclosure.

[0003] These and other features of the present embodiments can be better understood by reading the following detailed description, together with the figures described herein. In the drawings, each identical or nearly identical component shown in different figures may be represented by a like number. For clarity, not every component may be identified in every drawing. Further, as can be appreciated, the figures are not necessarily drawn to scale or are not intended to necessarily limit the described embodiments to the specific configurations shown. For example, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of the disclosed techniques may, given the real-world limitations of manufacturing processes, involve less than perfect straight lines and right angles (e.g.,curved or tapered sidewalls and rounded corners), and some features may have surface topography or may otherwise be non-smooth. Furthermore, some of the features in the drawings may have a textured and / or shaded fill, which is provided solely to assist in visually identifying the different features. In short, the figures are provided solely to show example structures. DETAILED DESCRIPTION

[0004] Techniques are provided here for selectively thinning the gate-channel region of non-planar transistors such as FinFETs and gate-all-around (GAA) transistors. In one example, a central portion of a fin structure in the gate-channel region is thinner than the corresponding end portions of the fin. A gate structure is located on the thinner central portion of the fin, and first and second gate spacers are located on the wider respective end portions of the fin. Source and drain regions can be grown or otherwise formed on the end portions. In one example, the selective thinning of the fin is achieved by implanting an implant species into the central portion of the fin.The implantation species modifies the surface properties of the fin such that the etchability of the implanted fin sections is effectively increased compared to the non-implanted fin sections, enabling selective fin formation in the middle section during subsequent processing. The end sections receive less or no implantation species because they are protected by the spacers. In one example, the implantation species comprises an element with an atomic mass unit of 80 or less (also referred to herein as a “light element”), such as fluorine, chlorine, argon, boron, arsenic, bromine, nitrogen, silicon (such as amorphous silicon), or halides. The techniques described here can be advantageously applied to FinFET devices that have fins as channel regions, as well as to other transistor structures derived from a fin-like structure, such asGate-all-around devices with nanoribbons or nanowires, or other transistor structures having a channel region at least partially wrapping the gate structure. Numerous variations, embodiments, and applications will be apparent in light of the present disclosure. General overview

[0005] With increasing device dimensions, the increasingly smaller fins lead to short-channel effects, where a relatively narrow channel width contributes to a higher resistance between the source or drain region and the channel region, which in turn leads to poor device performance. For example, in a finFET with epitaxial source and drain regions, a fin extends from the source region to the drain region. During typical fin scaling, the width of the entire fin is reduced uniformly at the time of fin formation. Accordingly, end portions of the fin adjacent to the source or drain regions also have a narrower width, which increases the resistance between the fin and the source or drain regions and impairs device performance.

[0006] Accordingly, techniques are provided herein for selectively thinning a fin such that gate portions of the fin are scaled or thinned, but end portions of the fin adjacent to the source and drain regions are not scaled or thinned. Selectively thinning the center portion of the fin without correspondingly thinning the end portions has several advantages. For example, selectively thinning the center portion improves the gate control of the transistor and thereby reduces leakage current. Such selective thinning of the center portion of the fin structure particularly improves transistor performance in low-voltage and / or low-power applications.Because the end portions of the fin that contact the source and drain regions remain relatively thicker, the relatively low resistance between the gated portion of the fin and the source or drain regions is also maintained. Furthermore, selective thinning of the central portion I can be achieved. ONof the device and / or the switching frequency performance with matched off-state leakage, with little or no corresponding penalty in capacitance, gate leakage, reliability metrics, and / or parasitic source-drain resistance. In one example, selective thinning of a fin is achieved by implanting an implant species into the central portion of the fin. As described further below, the end portions receive less or no implant species. The implant species facilitates a controlled etch of the central portion of the fin into which the implant species is implanted by making the central portion of the fin more responsive (etchable) to a subsequent process in which at least a portion of the central portion of the fin is trimmed.

[0007] In one embodiment, as described above, the fin has a first end portion abutting a source region, a second end portion abutting a drain region, and a middle portion located laterally between the first and second end portions. A gate structure is located on the middle portion of the fin, a first gate spacer is located on the first end portion of the fin, and a second gate spacer is located on the second end portion of the fin. An implant species is implanted into the middle portion of the fin and not into the first and second end portions. The implantation may, for example, be performed before the formation of the final gate structure of the FinFET device. In some of these examples, after the formation of the fin, the gate spacers, and the source and drain regions, the implant species is covered by a sacrificial mask (e.g.,Polysilicon and / or a dummy gate oxide) is implanted into the fin. If the thinning of a first channel region of a first device is desired and the thinning of a second channel region of a laterally adjacent second device is not desired, the second channel region may be masked when the implant species is implanted into the first channel region of the first device. In either case, the spacers on the first and second end portions of the fin prevent or at least reduce the implantation of the implant species within the first and second end portions of the fin.

[0008] Subsequently, during one or more downstream processes, at least portions of the fin's central portion are trimmed, with trimming facilitated by the implantation. An example of one or more downstream processes is a dummy gate removal process. Because the end portions comprise no or otherwise fewer implant species, the fin's end portions remain substantially untouched (or otherwise etch at a much slower rate) during the trimming process. After trimming portions of the fin's central portion, the device's final gate structure can be formed. As described further below, due to selective trimming of the fin's central portion with less or no trimming of the fin's end portions, differences in the width, height, and / or taper of the fin's central portion compared to the fin's end portions may result.It should be noted that the implantation species is different from a dopant, which can alter charge carrier transport in the channel region. In this sense, the implantation is a non-dopant. In some examples, the central portion may comprise a dopant in addition to the implantation species, while in other cases, the central portion is free of any dopant.

[0009] Materials that are “compositionally different” or “compositionally distinct” as used herein refer to two materials that have different chemical compositions. This difference in composition may exist, for example, due to an element being included in one material but not in the other (e.g., SiGe differs in composition from silicon), or because one material has all the same elements as a second material, but at least one of those elements is intentionally provided in a different concentration in one material relative to the other material (e.g., SiGe with 70 atomic percent germanium differs in composition from SiGe with 25 atomic percent germanium). In addition to this diversity in chemical composition, the materials may also contain different dopants (e.g.,Gallium and magnesium) or the same dopants but in different concentrations. In yet other embodiments, compositionally different materials may further refer to two materials that have different crystallographic orientations. For example, (110) silicon is compositionally different or distinct from (100) silicon. Creating a stack with different orientations could be achieved, for example, by cap-to-wafer transfer. If two materials are elementally different, then one of the materials has an element that is not present in the other material.

[0010] It should be understood that the meaning of "above" and "over" in the present disclosure should be interpreted as broadly as possible, such that "above" and "over" not only mean "directly upon" something, but also encompass the meaning of over something with an intermediate feature or layer in between. As used herein, the term "backside" generally refers to the area beneath one or more semiconductor devices (beneath the device layer), either within the device substrate or in the region of the device substrate (in the case where the bulk of the device substrate has been removed). It should be noted that the backside can become a frontside, and vice versa, when a given structure is flipped.For this purpose, and as will be appreciated, the use of terms such as "above," "below," "beneath," "upper," "lower," "top," and "bottom" is used to facilitate discussion and is not intended to imply a rigid structure or a fixed orientation; rather, such terms merely indicate spatial relationships when the structure is in a given orientation.

[0011] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A monolayer is a layer consisting of a single layer of atoms of a given material. A layer may extend over the entirety of an underlying or overlying structure or may have a lesser extent than the extent of an underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or inhomogeneous continuous structure, with the layer having a lesser thickness than the thickness of the continuous structure. For example, a layer may be positioned between any pair of horizontal planes between or at a top surface and a bottom surface of the continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface.A layer can conform to a given surface (whether flat or curved) with a relatively uniform thickness across the entire layer.

[0012] Use of the techniques and structures provided herein may be detectable using tools such as electron microscopy, including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nano-beam electron diffraction (NBD or NBED), and reflection electron microscopy (SEM); composition mapping; x-ray crystallography or diffraction (XRD); energy-dispersive x-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; Local electrode atom probe (LEAP) techniques;3D tomography; or high-resolution physical or chemical analysis, to name a few suitable examples of analytical tools. In some embodiments, such tools may be used in particular to detect the presence of an implantation species in a central portion of a fin, wherein a concentration of the implantation species in the central portion of the fin is at least 10% or at least 50% higher than within the end portions of the fin. In one embodiment, such tools may also be used to detect differences in the width, height, and / or taper of the central portion of the fin compared to the end portions of the fin. Numerous configurations and variations will be apparent in light of this disclosure. architecture

[0013] Fig. 1A, Fig. 1B, Fig. 1C and Fig. 1D show various views of an integrated circuit (IC) 100 comprising a plurality of devices 102a, 102b, 102c, wherein each device comprises a corresponding fin 106, wherein each fin 106 comprises two end portions 115 and 117 and a central portion 116 between the two end portions 115, 117, wherein the central portion 116a of at least one fin 106a has a different thickness profile and / or taper profile compared to the two corresponding end portions 115a, 117a of the at least one fin 106a and / or wherein the central portion 116a of the at least one fin 106a is implanted with an implantation species 125, according to an embodiment of the present disclosure.

[0014] Fig. 1A shows a perspective view of the IC 100, and Fig. 1B shows a top view or plan view of the fins 106a, 106, 106c, wherein a gate structure 103 and gate spacers 150a, 150b over the fins 106a, 106b, 106c are illustrated as transparent such that the fins 106a, 106b, 106c are visible. Fig. Figure 1C shows a cross-sectional view of the IC 100 along line AA' of Fig. 1A and illustrates the fins 106a, 106b, 106c below the gate structure 103. In the view of Fig. 1C, the IC 100 is cut through the gate structure 103. Fig. Figure 1D shows a cross-sectional view of the IC 100 along the line BB' of Fig. 1A and illustrates the fins 106a, 106b, 106c below the gate spacer 150a. The view of Fig. 1D shows a section through the spacer 150a.

[0015] The IC 100 comprises three components 102a, 102b, 102c each with fins 106a, 106b, 106c. Although in Fig. 1A-1D depict three components with three corresponding fins, the IC 100 may include any other number of such components and any other corresponding number of fins. It should be noted that the labels in Fig. 1A refer to the general positions of the fins 106a, 106b, 106c, since the fins 106a, 106b, 106c in Fig. 1A are covered by the gate structure 103 and the gate spacers 150a, 150b.

[0016] As shown in the top view of Fig. 1B, each fin 106 includes end portions 115 and 117 and a central portion 116 located laterally between end portions 115 and 117. For example, fin 106a includes end portions 115a, 117a and central portion 116a between end portions 115a, 117a; fin 106b includes end portions 115b, 117b and central portion 116b between end portions 115b, 117b, etc.

[0017] A gate structure 103 is located above and on a central portion 116 of each fin 106. For example, the gate structure 103 is located above the central portions 116a, 116b, 116c of the fins 106a, 106b, 106c, respectively. It is noted that in Fig. 1B, the gate structure 103 is shown transparently, so that the central sections 116a, 116b, 116c of the fins are visible under the gate structure 103.

[0018] A first spacer 150a is located above and on an end portion 117 of the individual fins 106. For example, the spacer 150a is located above the end portions 117a, 117b and 117c of the fins 106a, 106b, 106c, respectively. Fig. 1B, the gate spacer 150a is shown as transparent such that the end portions 117a, 117b, 117c of the fins are visible under the gate spacer 150a.

[0019] A second spacer 150b is located above and on an end portion 115 of each fin 106. For example, the spacer 150b is located above the end portions 115a, 115b, and 115c of the fins 106a, 106b, 106c, respectively. Fig. 1B, the gate spacer 150b is shown as transparent such that the end portions 115a, 115b, 115c of the fins are visible under the gate spacer 150a.

[0020] As in Fig. 1B, the source and drain regions 120, 122 are located on either side of and adjacent to each fin 106. For example, in device 102a, a source region 120a is located adjacent to the end portion 117a of the fin 106a and a drain region 122a is located adjacent to the end portion 115a of the fin 106a, such that the fin 106a extends between the source region 120a and the drain region 122a. In one example, the position of the source region 120a and the drain region 122a may be interchangeable, and accordingly, the regions 120a, 122a are generally referred to as source or drain (S / D) regions.

[0021] Similarly, in device 102b, an S / D region 120b is adjacent to the end portion 117b of fin 106b, and another S / D region 122b is adjacent to the end portion 115b of fin 106b, such that fin 106b extends between S / D regions 120b and 122b. Similarly, in device 102c, an S / D region 120c is adjacent to the end portion 117c of fin 106c, and another S / D region 122c is adjacent to the end portion 115c of fin 106c, such that fin 106c extends between S / D regions 120c and 122c.

[0022] In Fig. 1A-1D, a length of a fin is measured along the X-axis direction. For example, a length Lc of the fin 106c (see Fig. 1B) in the direction of the X-axis of the Fig. 1A-1D and between the S / D regions 120c and 122c.

[0023] Widths of different parts of a fin are measured in the direction of the Y-axis from Fig. 1A-1D and measured in a direction perpendicular to the direction in which the length is measured. For example, the width is measured in a direction in which the gate structure 103 extends, which is orthogonal to the direction of the length of a fin 106.

[0024] In the top view of Fig. 1B, widths of various sections of fin 106a are shown, and this description of the widths of fin 106a also applies to fin 106c. Note the differences in the width profiles of fins 106a, 106c compared to the width profile of fin 106b, as described below.

[0025] As from Fig. As can be seen from Figure 1B, each of the end portions 115a, 117a, 115b, 117b, 115c, 117c of the fins 106a, 106b, 106c has a width of ws. Thus, the end portions of each of the fins have substantially the same width (e.g., within a tolerance of at most 0.5 nm or 1 nm). Note that the "s" in the width ws indicates that it is the width of a fin below a "spacer" (e.g., spacers 150a, 150b).

[0026] The central portion 116a of the fin 106a has a width of "wag." Note that the "a" in the width wag indicates that this width is associated with the fin 106a. Furthermore, the "g" in the width wag indicates that this width applies to a portion of a fin below a "gate" structure (such as the gate structure 103). As shown in Fig. 1B, the width wag of the central portion 116a of the fin 106a is less than the width ws of the end portions 115a, 117a of the fin 106a. Therefore, the central portion 116a of the fin 106a is narrower or thinner than each of the end portions 115a, 117a of the fin 106a. In one example, the width wag is less than the width ws by at least 3 angstroms, at least 5 angstroms, or at least 8 angstroms, or at least 1 nm, or at least 1.5 nm, or at least 2 nm. Similarly, the central portion 116c of the fin 106c has a width “wcg” that is less than the width ws of the end portions 115c, 117c of the fin 106c, e.g., B. by at least 3 angstroms, at least 5 angstroms or at least 8 angstroms or at least 1 nm or at least 1.5 nm or at least 2 nm, for example.

[0027] In contrast to the fins 106a and 106c described above, in one example, the central portion 116b of the fin 106b has a width wbg that substantially corresponds to the width ws of the end portions 115b, 117b, as shown in Fig. 1B.

[0028] As described below, the central portions 116a and 116c of the fins 106a and 106c, respectively, are selectively narrowed or thinned without narrowing or thinning the central portion 116b of the fin 106b. Accordingly, as shown in Fig. 1B, the width profiles of the middle sections 116a, 116b of the fins 106a and 106b differ from each other. Different fins are not always trimmed selectively, so all fins can be globally trimmed at once.

[0029] As described above, Fig. 1C is a cross-sectional view of the IC 100 along line AA' of Fig. 1A and illustrates the fins 106a, 106b, 106c below the gate structure 103. Thus, in Fig. 1C shows cross-sectional views of the middle sections 116a, 116b and 116c of the fins 106a, 106b, 106c, respectively. Fig. 1C, the fins 106 extend in the Z-axis or vertical direction. A central portion 116 of a fin 106 includes a gated portion located laterally between portions of the gate structure 103 and a partial fin portion located below the gated portion, see, for example, Fig. 1B and 1C.

[0030] The gate structure 103 includes a gate electrode 144 and a gate dielectric 130 between each fin 106 and the gate electrode 144. The gate dielectric 130 may also be located on the bottom surface of the gate trench, as shown in Fig. 1C. The gate structure 103 is described in more detail below.

[0031] In one embodiment, the middle section 116 of a fin 106 has an upper region 108 and a lower region 107 below the upper region 108. For example, the middle section 116a of the fin 106a has an upper region 108a and a lower region 107a, the middle section 116b of the fin 106b has an upper region 108b and a lower region 107b, and the middle section 116c of the fin 106c has an upper region 108c and a lower region 107c, as in Fig. 1C. An upper region 108 of a central portion 116 of a fin 106 has a corresponding gate structure 103 at least on the top and side surfaces thereon. Therefore, an upper portion of a central portion 116 of a fin 106 having a corresponding gate structure 103 at least on the top and side surfaces is referred to as an upper region 108 of the central portion 116 of the fin and is a gated portion of the fin. The upper region 108 of the central portion 116 of a fin 106 lies laterally between portions of the gate structure 103. The upper region 108 of the central portion 116 of a fin 106 is also referred to herein as an "active region" or "channel region" of the fin, since this region 108 contributes to current conduction between a corresponding source region and a corresponding drain region.That is, current is selectively transferred between a source and a drain region through the upper region 108 of the fin's central portion 116. In contrast, the lower region 107 of the fin's central portion 116 is a subfin region located below the active region of the fin 106.

[0032] The upper regions 108a, 108b, and 108c of fins 106a, 106b, and 106c each have a height of Hagu, Hbgu, and Hcgu, respectively. The "g" in the heights Hagu, Hbgu, and Hcgu indicates that the upper regions 108a, 108b, and 108c of fins 106a, 106b, and 106c belong to the middle sections 116 of fins 106 and are located below the "gate" structure 103. The "u" in the heights Hagu, Hbgu, and Hcgu indicates that these heights apply to the "upper" regions 108a, 108b, and 108c.

[0033] In one embodiment and as in Fig. 1C, the height Hbgu is greater than the heights Hagu and / or Hcgu. For example, as described below, the middle portions 116a and 116c of the fins 106a, 106c, respectively, are selectively trimmed and thinned, resulting in a reduction in the heights Hagu and / or Hcgu. In contrast, the middle portion 116b of the fin 106b is not trimmed and thinned, such that the height Hbgu is greater than the heights Hagu and / or Hcgu, e.g., by at least 3 angstroms, by at least 5 angstroms, by at least 8 angstroms, by at least 1 nm, by at least 1.5 nm, or by at least 2 nm.

[0034] For example in Fig. 4D2, which is described further below, a top surface of the central portion 116b of the fin 106b is higher than the top surfaces of the central portions 116a, 116c of the fins 106a, 116c, e.g., by a vertical distance H, where H is, for example, at least 3 angstroms, at least 5 angstroms, or at least 8 angstroms, or at least 1 nm, or at least 1.5 nm, or at least 2 nm.

[0035] In one embodiment, the middle portions 116a and 116c of the fins 106a, 106c, respectively, are selectively trimmed and thinned so that each of the upper regions 108a and 108c has a tapered shape. For example, an upper portion of the upper region 108a has a width of w1, while a lower portion of the upper region 108a has a width of w1, as shown in Fig. 1C. In one example, the portion of the central section 116a of the fin 106a having the width wag is also referred to as the intermediate portion of the fin 106a, which forms a boundary between the upper or gated region 108a and the lower or partial fin region 107a. In one example, the width wag is at least 3 angstroms, or at least 5 angstroms, or at least 8 angstroms, or at least 1 nm, or at least 1.5 nm, or at least 2 nm greater than w1, resulting in the tapered shape of the upper region 108a. The upper region 108c is also similarly tapered. In contrast, in one example, the upper region 108b of the central section 116b of the fin 106b may not be tapered.

[0036] In one example, the upper region 108a (e.g., the gated portion of the fin 106a) is tapered, and the lower region 107a (e.g., the partial fin portion of the fin 106a) is also tapered (although Fig. 1C does not show such a taper), and the lower region 107a tapers outwardly at a greater rate than the taper of the upper region 108a described above.

[0037] Fig. Figure 1D shows the cross-sectional view of the IC 100 along the line BB' of Fig. 1A and illustrates the fins 106a, 106b, 106c below the gate spacer 150a. Thus, in Fig. 1D cross-sectional views of the end portions 117a, 117b and 117c of the fins 106a, 106b, 106c, respectively. In Fig. 1D, the fins 106 extend in the Z-axis or vertical direction. The spacer 150b is located above and on the sides of the end portions 117a, 117b, 117c of the fins 106a, 106b, 106c. While in Fig. 1D the end portions 117a, 117b, 117c of the fins 106a, 106b, 106c are shown below the gate spacer 150a, the other end portions 115a, 115b, 115c of the fins 106a, 106b, 106c below the gate spacer 150b may also have a similar structure.

[0038] In one embodiment, the end portion 117 of a fin 106 has an upper region 128 and a lower region 127 below the upper region 128. For example, the end portion 117a of the fin 106a has an upper region 128a and a lower region 127a, the end portion 117b of the fin 106b has an upper region 128b and a lower region 127b, and the end portion 117c of the fin 106c has an upper region 128c and a lower region 127c, as in Fig. 1D. An upper region 128 of an end portion 117 of a fin 106 has a corresponding gate spacer 150a on at least the top and side surfaces. The upper region 128 of the end portion 116 of a fin 106 is also the active region or channel region of the fin, since this region 128 contributes to current conduction between a corresponding source region and a corresponding drain region. That is, current is selectively transferred between a source and a drain region through the upper region 128 of the end portion 117 of the fin. In contrast, the lower region 127 of the end portion 117 of a fin is a sub-fin region located below the active region of the fin 106.

[0039] In one embodiment, the end portions 117a, 117b, 117c of the fins 106a, 106b, 106c are not trimmed or thinned (e.g., protected by the gate spacer 150a during the thinning process). Accordingly, the end portions 117a, 117b, 117c of the fins 106a, 106b, 106c have a substantially similar height and / or width profile. For example, the upper regions 128a, 128b, 128c of the fins 106a, 106b, 106c each have heights Hasu, Hbsu, Hcsu, respectively. The "s" in the heights Hasu, Hbsu, and Hcsu indicates that the upper regions 128a, 128b, and 128c are located below a "spacer" 150a. The "u" in the heights Hasu, Hbsu, and Hcsu indicates that these heights apply to the "upper" regions 128a, 128b, and 128c. In one example, the heights Hasu, Hbsu, and Hcsu are essentially the same, although there may be some differences due to manufacturing variations.In one example, the lower regions 127a, 127b, 127c may also have substantially the same height, although there may be differences due to manufacturing variations.

[0040] In one example, during trimming of the fin 106a, 106c, only the middle sections 115a, 115c of the fins 106a, 106c are trimmed, and the end sections 115a, 115c, 117a, 117c of the fins 106a, 106c are not trimmed. Accordingly, in one example, the height Hagu of the upper region of the middle section 116a of the fin 106a is greater than the height Hasu of the upper region of the end section 117a of the fin 106a. For example, the middle portion 116a of the fin 106 has a first top surface, the end portion 115a of the fin 106a has a second top surface, and the end portion 117a of the fin 106a has a third top surface, wherein the first top surface is at least 3 angstroms, at least 5 angstroms, or at least 8 angstroms, or at least 1 nm, or at least 1.5 nm, or at least 2 nm above the second and / or third top surfaces.For example, the first topmost surface lies at least partially on a first horizontal plane and the first and third topmost surfaces lie at least partially on a second horizontal plane, wherein the first horizontal plane is vertically at least 3 angstroms, at least 5 angstroms, or at least 8 angstroms, or at least 1 nm, or at least 1.5 nm, or at least 2 nm above the second horizontal plane.

[0041] In one embodiment, an implantation species 125 is implanted into one or more portions of one or more fins 106. In one example, the implantation species 125 (also referred to herein as implantation 125) is implanted into a fin 106 (e.g., fins 106a, 106c) such that it is relatively easier to selectively trim and thin the fin. For example, in Fig. 1A-1D, the fins 106a and 106c are implanted within the implantation 125, while the fin 106b is without such an implantation.

[0042] The implants 125 are in the Fig. 1B-1D are symbolically represented by dots. The number of dots within a particular portion of a fin provides some indication of the relative concentration of the implantation 125 within the portion (e.g., if a first section has more dots than a second portion, this means that the first portion has a higher concentration of the implantation 125 than the second portion). However, the dots are not an indicator of the actual concentration or actual position of the implantation 125 within a fin.

[0043] As in Fig. 1B-1D, the fin 106b is free of the implant 125. The implant 125 is implanted into the fins 106a and 106c such that the fins 106a and 106c are selectively thinned and trimmed without the fin 106b being thinned and trimmed.

[0044] In one embodiment, for each of the fins 106a and 106c, a concentration of the implantation 125 is higher in a central portion 116 of the fin than in the end portions 115 or 117. For example, the central portion 116a of the fin 106a has a higher concentration of the implantation 125 than the end portions 115a, 117a of the fin 106a; and the central portion 116c of the fin 106c has a higher concentration of the implantation 125 than the end portions 115c, 117c of the fin 106c. In one example, the concentration of the implantation 125 in the middle portion of the fins 106a, 106c is at least 10%, or at least 20%, or at least 50%, or at least 80%, or at least 100%, or at least 200% higher than the concentration of the implantation 125 in the end portions of the fins 106a, 106c.In one example, the end portions 115a, 117a, 115c, 117c of the fins 106a, 106c lack the implantation 125 or have a relatively low concentration of the implantation 125, as described above.

[0045] In the following, an implantation concentration for the fin 106a is described, and this description also applies to the fin 106c. In one example, the implantation concentration within the central section 116a of the fin 106a varies in the range of 1.0E+19 atoms / cm 3 up to 5.0E+21 atoms / cm 3 or in the subrange of 5.0 E+19 atoms / cm 3 up to 4.0E+20 atoms / cm 3 .

[0046] In one embodiment, a concentration of the implantation 125 within the central portion 116a of the fin 106a varies along the depth of the fin 106a. As in Fig. 1C, the upper region 108a of the central portion 116a of the fin 106a generally has a higher concentration of implantation than the lower region 107a of the central portion 116a of the fin 106a. As previously mentioned, the implantation is distinct from any dopant that may (or may not) be included in the central portion of the fin.

[0047] Fig. 2 shows a diagram 200 illustrating a variation in a concentration of implantation species 125 along a depth of a central portion 116a of the fin 106a, according to an embodiment of the present disclosure. The X-axis of the diagram 200 indicates the depth within the fin. For example, the top surface of the central portion 116a of the fin 106a has a depth of zero, and a bottom surface of the central portion 116a of the fin 106a has a greatest depth, and the depth of the central portion 116a of the fin 106a increases along the X-axis. For example, region A of the X-axis represents the upper region or gated portion 108a (see Fig. 1C) of the central portion 116a of the fin 106a, which is part of the active channel region of the fin 106a. Region B of the X-axis represents the lower region 107a of the central portion 116a of the fin 106a, which is the partial fin region of the fin 106a. The Y-axis of the diagram 200 represents the concentration of the implantation 125.

[0048] As in Fig. 2, both the average and maximum concentration of implantation 125 in region A (e.g., in the upper region 108a) of the middle section 116a of the fin 106a is higher than in region B (e.g., in the lower region 107a) of the middle section 116a of the fin 106a. In one example, there is a small peak at the beginning of region B because the uppermost part of the partial fin region of the fin (e.g., region B) contains some implantation from a Fig. 1A with 139 (e.g., an area not covered by the gate spacers 150a, 150b). In one example, the Fig. The concentration profile shown in Figure 2 may vary from one implementation to the next and may be based on the implantation energy used for the implantation process as well as the composition of the channel material.

[0049] In one example, the implant 125 comprises a halide, such as fluorine, chlorine, or argon. In one example, the implant 125 comprises an element with an atomic mass unit of 80 or less, such as a light element, e.g., fluorine, chlorine, argon, boron, arsenic, bromine, nitrogen, silicon (such as amorphous silicon). In one advantageous embodiment, the implant 125 comprises fluorine.

[0050] In one embodiment, by implanting the implantation 125 within the central portion 116 of a fin 106 (such as fins 106a and / or 106c), the surface property of the semiconductor material of the fin 106 is changed such that the etch rate of this implanted fin portion is increased compared to a non-implanted fin portion. As a result, the central portion 116 of a fin 106 may be at least partially thinned during an etching process (e.g., compared to a central portion of another fin in which the implantations 125 were not implanted). Once the central portions 116a, 116c of the fins 106a, 106c are implanted with the implantation 125, the fins 106a, 106b, 106c are subjected to an etching process. Since the fin 106b has not been implanted, the fin 106b is not significantly etched or thinned by the etching process.However, due to the presence of the implantation 125 in the middle sections 116a, 116c of the fins 106a, 106c, the middle sections 116a, 116c of the fins 106a, 106c are trimmed as described below.

[0051] It should be noted that the implantation 125 is implanted primarily or only within the central portions 116a, 116c of the fins 106a, 106c and not within the end portions 115a, 115c, 117a, 117c. Accordingly, the selective etching process for trimming the central portions 116a, 116c does not significantly affect the end portions 115a, 115c, 117a, 117c. As a result, the central portions 116a, 116c are now thinner than the end portions 115a, 115c, 117a, 117c, as shown in Fig. 1B. Since the fin 106b is not implanted, the central portion 116b and the end portions 115b, 117b of the fin 106b have substantially the same width, as in Fig. 1B. In this way, the selective trimming process can be carried out globally (e.g., via the three Fig. 1B or another subset of fins, or across a portion or block of the wafer, or across the entire wafer), wherein the implanted fins are trimmed and the non-implanted fins are not trimmed.

[0052] In addition, the upper regions 108a, 108c of the middle sections 116a, 116c of the fins 106a, 106c may be tapered or have rounded corners due to the trimming of the middle sections 116a, 116c, as in Fig. 1C, where no or lesser such taper or rounding occurs for the upper region 108b of the central portion 116b of the fin 106b. For similar reasons, the height Hagu may be greater than the height Hbgu, as shown in Fig. 1C. Since the end portions 115a, 115c, 117a, 117c are not etched, there is no such tapering or rounding in the upper regions 128a, 128c of the end portions 117a, 117c as in Fig. 1D (or in the upper regions of the end sections 115a, 115c).

[0053] Thus, with reference to fin 106a (and the same description also applies to fin 106c), since the central portion 116a is now thinner (e.g., compared to the end portions 115a, 117a), the channel region corresponding to fin 106a is reduced in size. Such selective thinning of the central portion 116a may contribute to improving the performance of the corresponding transistor, e.g., through improved gate control, lower leakage current, and / or improved low-voltage and / or low-power performance. Furthermore, the end portions of fin 106a that contact the S / D regions 120a, 122a are not correspondingly thinned, so that the parasitic resistance between fin 106a and the S / D regions 120a, 122a does not increase correspondingly due to the fin thinning. For example, in one example, selective thinning of the central portion 116a may reduce the inrush current (I ON) of the device 102a and / or the switching frequency performance with adjusted off-state leakage, with little or no corresponding penalty in capacitance, gate leakage, reliability metrics, and / or parasitic source-drain resistance. It is noted that the fin 106b in the example of Fig. 1A-1D is not thinned, since such thinning may not be desired for this fin 106b.

[0054] In one example, implantation 125 contributes to the selective thinning of the fins, but it does not contribute to or significantly affect the charge present in the channel region of the fins. For example, the doping of the fins is not affected by implantation 125, although in another example, the fins may also be doped.

[0055] In one example, the fins 106 are formed on a substrate and from the substrate, and the fins and the substrate have a similar composition. In other embodiments, the fins 106 may be formed, grown, or fabricated by other suitable methods. In some cases, for example, the fins 106 may be grown from trenches formed in the substrate (e.g., epitaxially). In some cases, the fins are made of a single semiconductor material. In some other cases, the fins are formed from alternating layers of semiconductor material that may be etched selectively to each other to facilitate the release of nanoribbons. More generally, the fins may be formed using any suitable technique. In some examples, any remaining portion of the substrate beneath the fins may be removed (e.g.,by chemical mechanical planarization or CMP) to facilitate backside processing of the IC 100.

[0056] It should further be noted that individual fins 106 may be used for an NMOS, a PMOS, or a CMOS device (e.g., the fins of one device may be used for an n-type MOSFET and the fins of a neighboring device may be used for a p-type MOSFET). The fins 106 may be made of any suitable semiconductor materials used for fins (or nanoribbons, nanowires, or other such semiconductor bodies), such as silicon, silicon germanium, III-V material, and / or other suitable materials used for fins. In one example, portions of the fins may be doped. Any suitable p-type dopant or n-type dopant may be used for doping a particular fin, e.g., based on a target application of the fin.

[0057] Referring to Fig. 1A-1D, gate spacers 150a, 150b are also provided on both sides of gate stack 103. Such gate spacers 150a, 150b may be used to assist in determining the channel length and / or assist in gate replacement processes, for example. Gate spacers 150a, 150b may comprise any suitable dielectric, e.g., an oxide or a nitride (e.g., silicon oxide, silicon nitride, or silicon oxynitride).

[0058] The gate structure 103 includes a gate stack with a gate dielectric 130 and a gate electrode 144. As in Fig. 1C, the gate dielectric 130 separates the gate electrode 144 from the upper regions (or gated regions) 108a, 108b, 108c of the fins 106a, 106b, 106c, respectively. The gate dielectric 130 may comprise any suitable dielectric (such as silicon dioxide and / or a high-k dielectric). Examples of high-k gate dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. In some embodiments, the gate dielectric 130 may comprise one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals).In some embodiments, an annealing process may be performed on the gate dielectric 130 to improve its quality when using high-k dielectric material. The gate electrode 130 may comprise a wide range of materials, such as polysilicon or various suitable metals or metal alloys, such as, for example, aluminum, tungsten, titanium, tantalum, copper, cobalt, molybdenum, titanium nitride, or tantalum nitride. In some embodiments, the gate dielectric 130 and / or the gate electrode 144 may, for example, comprise a multilayer structure of two or more material layers. In one embodiment, the gate dielectric 130 comprises, for example, a first layer of silicon dioxide on the channel region and a second layer of hafnium oxide on the first layer. The gate electrode 130 may, for example,a metal plug along with one or more work function layers, resistance-reducing layers, and / or barrier layers. In some embodiments, the gate dielectric 130 and / or the gate electrode 144 may include graduating (e.g., increasing and / or decreasing) the content / concentration of one or more materials in at least a portion of the one or more features. It is noted that in the embodiment of FIG. 1, the gate dielectric 130 may be a metal plug. Fig. C between the gate electrode 144 and the fins 106; in other embodiments, the gate dielectric may also be located between the gate electrode 144 and one or both of the gate spacers 150a, 150b, for example. Numerous different gate structure configurations are apparent in light of this disclosure.

[0059] In Fig. 1A-1B, S / D regions 120, 122 are illustrated on two sides of each fin 106, such that the top regions 108 and 128 of a fin 106 lie laterally between the corresponding S / D regions 120, 122. According to some embodiments, the source or drain regions are epitaxial regions provided using an etch-and-replace process. In other embodiments, one or more of the source or drain regions could be, for example, implant-doped native portions of the fins 106 or the substrate. Any semiconductor materials suitable for source and drain regions (e.g., Group IV and Group III-V semiconductor materials) may be used. The source and drain regions may include multiple layers, such as liners and cap layers, to improve contact resistance.In any such cases, the composition and doping of the source and drain regions can be the same or different, depending on the polarity of the transistors. Any semiconductor materials suitable for the source and drain regions (e.g., group IV and group III-V semiconductor materials) can be used. Fig. 1A, regions 121 below the source and drain regions are also illustrated, where regions 121 may be part of the lower regions of the original fins over which the source and drain regions are formed. Source and drain contacts may each be coupled to the corresponding source and drain regions to couple the source and drain regions to external circuitry. The conductive source and drain contacts may be made of any suitable conductive material, e.g., a metal or an alloy thereof. The conductive source and drain contacts comprise, for example, one or more of tungsten (W), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, the conductive source and drain contacts comprise one or more of the same metal materials as the gate electrode or another conductive material.

[0060] Although the canal regions in the example of Fig. 1A-1D are fins, the channel regions may also have other suitable structures, such as gate-all-around (GAA) structures, e.g., nanoribbons, nanosheets, or nanowires. It should be noted that in some embodiments, nanoribbons are used to describe a GAA structure, but nanowires or other similar semiconductor bodies with any number of height-to-width aspect ratios may be used in a gate-all-around configuration. Thus, in some examples, a plurality of nanoribbons (or nanosheets or nanowires) may extend between a respective source region and a respective drain region, with each nanoribbon having a central portion wrapped by a gate structure and end portions wrapped by gate spacers.In one example, the implantation 125 may be located within the central portion of each nanoribbon and not within the end portions of each nanoribbon, facilitating thinning of the central portion of one or more nanoribbons without correspondingly thinning the end portions. This achieves the above-described benefits of thinning the central portion (and not the end portions adjacent to the S / D regions) of the channel region. methodology

[0061] Fig. 3 illustrates a flowchart illustrating a method 300 for forming an IC (e.g., the IC 100 of Fig. 1A-1D), according to an embodiment of the present disclosure. Fig. 4A1, Fig. 4A2, Fig. 4A3, Fig. 4B1, Fig. 4B2, Fig. 4B3, Fig. 4C1, Fig. 4C2, Fig. 4C3, Fig. 4D1, Fig. 4D2, Fig. 4D3, Fig. 4E1, Fig. 4E2 and Fig. 4E3 show different views of an IC (e.g. the IC 100 of the Fig. 1A-1D) at different stages of processing according to the methodology300 of Fig. 3 according to an embodiment of the present disclosure. Fig. 2 and 4A1-4E3 are discussed together.

[0062] The views of Fig. 4A1, Fig. 4B1, Fig. 4C1, Fig. 4D1 and Fig. 4E1 are similar to those of Fig. 1B, for example, a top view of the fins 106a-106c, wherein the gate spacers 150a, 150b, a dummy gate stack 310 comprising a dummy gate material (such as polysilicon or a dummy gate oxide, or both), and / or the gate structure 103 are illustrated as transparent. The cross-sectional views of Fig. 4A2, Fig. 4B2, Fig. 4C2, Fig. 4D2 and Fig. 4E2 are similar to those of Fig. 1C, e.g. along the line AA' from Fig. 1A, and show the fins 106a, 106b, 106c below the dummy gate oxide 310 or below the gate structure 103. The cross-sectional views of Fig. 4A3, Fig. 4B3, Fig. 4C3, Fig. 4D3 and Fig. 4E3 are similar to those of Fig. 1D, e.g. along the line BB' of Fig. 1A, and show the fins 106a, 106b, 106c below the gate spacer 150a.

[0063] As in Fig. 3, the method 300 includes, at 304, forming the fins 106a, 106b, 106c, the gate spacers 150a, 150b, the source and drain regions 122a, 122b, 122c, 120a, 120b, 120c, and the dummy gate oxide 310 over the middle portions 116a, 116b, 116c of the fins 106a, 106b, 106c, respectively. The formation process 304 may, according to one embodiment, be performed using any suitable process for forming FinFETs. The resulting structure is shown in FIGS. Fig. 4A1, Fig. 4A2, Fig. 4A3. In Fig. 4A1, Fig. 4A2, Fig. 4A3 and process 304, the final gate structure 103 is not yet formed, and the dummy gate oxide 310 is located over the central portions 116a, 116b, 116c of the fins 106a, 106b, 106c. The dummy gate oxide 310 comprises a suitable sacrificial material, such as polysilicon, which will later be replaced by the final gate structure 103.

[0064] As in Fig. 3, the method 300 goes from 304 to 308, wherein a mask 304 is structured above the fin 106b, without the mask 304 being located above the fins 106a, 106c, as also shown in Fig. 4A1, Fig. 4A2, Fig. 4A3. In Fig. 4A1 (and also in the version described below Fig. 4B1), the mask 304 is shown transparent, allowing the underlying fin 106b to be seen. Any suitable hard mask may be used, such as a carbon-based hard mask (CHM) or another type of mask that can prevent the implants 125 from reaching the fin 106b in a subsequent process.

[0065] Again on Fig. 3, the method 300 proceeds from 308 to 312, wherein the implantation species 125 is implanted through the dummy gate oxide 310 and within the fins 106a, 106c, as in Fig. 4B1, Fig. 4B2, Fig. 4B3. In one example, the implantation is performed using a plasma implantation process or another implantation process. Example implantation types have been described previously.

[0066] Since the fin 106b is covered by the mask 304, the implantation 125 does not reach the fin 106b through the mask 304. Therefore, the material of the mask 304 is chosen such that the implantation 125 does not propagate through the mask 304.

[0067] However, the dummy gate oxide 310 may comprise relatively porous material through which the implantation 125 may propagate and reach the fins 106a, 106c. For example, the implantation 125 comprises a relatively light element with an atomic mass unit of 80 or less, as described above. Accordingly, in one example, the implantation 125 propagates through the relatively porous material of the dummy gate oxide 310 and reaches the central portions 116a, 116c of the fins 106a, 106c, respectively, see Fig. 4B1, Fig. 4B2.

[0068] However, the gate spacers 150a, 150b are located above the end portions 115a, 115b, 117a, 117b, and in one example, the implant 125 cannot propagate through the gate spacers 150a, 150b. Accordingly, in such an example, the implant 125 cannot reach the end portions 115a, 115b, 117a, 117b. Accordingly, as shown in Fig. 4B3, the end sections 115a, 115b, 117a, 117b are free of the implantation 125 or have a relatively lower concentration of the implantation 125 (e.g., compared to a concentration in the middle sections 116a, 116c).

[0069] The implantation 125 differs from a dopant, which could also be included in one or more of the corresponding channel regions of the fins 106a-c. In some examples, the fins 106a-c are free of dopants that can alter charge carrier transport in the channel region. In other examples, the one or more of the fins 106a-c may comprise, in addition to the implantation species, one or more dopants that can alter charge carrier transport. In this way, the implantation species is a non-dopant that does not alter charge carrier transport.

[0070] As in Fig. 3, the method 300 then continues from 312 to 316, where the mask 304 is removed, as shown in Fig. 4C1, Fig. 4C2 and Fig. 4C3. In one example, the mask 304 is removed using a mask removal process, such as an etching process or an ashing process.

[0071] Again referring to Fig. 3, the method 300 then proceeds from 316 to 320, where the dummy gate oxide 310 is removed and at least parts of the middle sections 116a, 116c of the fins 106a, 106c, respectively, are also trimmed, as in Fig. 4D1, Fig. 4D2 and Fig. 4D3. In one example, at least portions of the central portions 116a, 116c are trimmed using the same removal process as the removal process for the dummy gate oxide 310. For example, in the removal process for the dummy gate oxide, at least portions of the central portions 116a, 116c are also trimmed, e.g., using a suitable etching process. In another example, the removal process for the dummy gate oxide and the process for trimming at least portions of the central portions of the fins are two different and separate processes.

[0072] In one example, as described above, the implantation 125 within the central portions 116a, 116c of the fins 106a, 106c prepares the central fin surface portions for controlled etching, e.g., compared to the central portion 116b of the fin 106b that was not implanted by the implantation 125. Accordingly, the subsequent etching process trims at least portions of the central portions 116a, 116c of the fins 106a, 106c, respectively, without such trimming of the central portion 116b of the fin 106b, or otherwise at a much higher rate (e.g., more than 10x higher) than trimming of the central portion 116b. Accordingly, as shown in Fig. 4D1, the middle sections 116a, 116c of the fins 106a, 106c are thinner than the end sections 115a, 115b, 117a, 117b. In contrast, the non-implanted middle section 116b is not thinned, as also shown in Fig. 4D1 shown.

[0073] Similarly, the upper regions 108a, 108c of the middle sections 116a, 116c each have a tapered shape and a lower height, e.g., compared to the upper region 116b of the middle section 116b, as also shown in Fig. 4D2 and as described above. As shown in Fig. 4D2, for example, a top surface of the central portion 116b of the fin 106b is higher than the top surfaces of the central portions 116a, 116c of the fins 106a, 116c, e.g., by a vertical distance H, where H is, for example, at least 3 angstroms, at least 5 angstroms, or at least 8 angstroms, or at least 1 nm, or at least 1.5 nm, or at least 2 nm.

[0074] Similarly, in an example, the height Hasu (see Fig. 4D3) greater than the height Hagu (see Fig. 4D2) by at least 3 angstroms, at least 5 angstroms, or at least 8 angstroms, or at least 1 nm, or at least 1.5 nm, or at least 2 nm, for example. For example, the upper surface of the end portions 115a, 117a is at least 3 angstroms, at least 5 angstroms, or at least 8 angstroms, or at least 1 nm, or at least 1.5 nm, or at least 2 nm higher than the upper surface of the central portion 116a of the fin 106a or higher.

[0075] With further reference to Fig. 3, the method 300 proceeds from 320 to 324, wherein the final gate structure 103 is formed with a gate dielectric 130 and a gate electrode 144, as in Fig. 4E1, Fig. 4E2 and Fig. 4E3. For example, the gate dielectric 130 is conformally deposited within the gate trench (e.g., emptied by removing the dummy gate oxide 310) such that the gate dielectric 130 may be located on the central portions 116a-116c of the fins, on the sidewalls of the gate spacers 150a, 150b facing the gate structure 103, and also on the bottom surface of the gate trench. The gate electrode 144 is then deposited such that the gate electrode 144 is separated from the fins 106a-106c by the gate dielectric 130. The formation of the final gate structure 103 may be performed using techniques for forming final gate structures in FinFET devices.

[0076] It should be noted that the processes in method 300 are shown in a particular order for ease of description. However, according to some embodiments, one or more of the processes may be performed in a different order or not at all (and thus may be optional).

[0077] Although Fig. For example, while FIG. 3 shows that the implantation process 312 is performed before the removal of the dummy gate oxide 310, the implantation process 312 may be performed after the removal of the dummy gate oxide 310 and before the formation of the final gate structure 103. Thus, in such an example, after the removal of the dummy gate oxide 310, the implantation 125 is selectively implanted within the central portions 116a, 116c of the fins 106a, 106c (e.g., while the fin 106b is obscured by a mask). After implantation, the mask is removed, and the fins are subjected to an etching process in which at least portions of the central sections 116a, 116c of the fins 106a, 106c (e.g., those now ready for controlled etching after implantation 125) are selectively trimmed. In such an example, processes 308 and 312 may be performed after removal of the dummy gate oxide 310.In one example, the implant 125 may be implanted within the central portions 116a, 116c of the fins 106a, 106c at any suitable time prior to the formation of the final gate structure 324. Numerous variations to method 300 and the techniques described herein will be apparent in light of this disclosure. Example system

[0078] Fig.5 illustrates a computing system 2000 implemented with integrated circuit structures formed using the techniques disclosed herein, according to some embodiments of the present disclosure. As can be seen, the computing system 2000 houses a motherboard 2002. The motherboard 2002 may include a number of components, including, but not limited to, a processor 2004 and at least one communication chip 2006, each of which may be physically and electrically coupled to or otherwise integrated with the motherboard 2002. It should be noted that the motherboard 2002 may be, for example, any printed circuit board, whether a main board, a daughter board attached to a main board, the sole board of the system 2000, etc.

[0079] Depending on its applications, the computing system 2000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 2002. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a GPS (global positioning system) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard disk drive, CD (compact disk), DVD (digital versatile disk), and so on).Any of the components included in computing system 2000 may include one or more integrated circuit structures or devices formed using the disclosed techniques according to an example embodiment. In some embodiments, multiple functions may be integrated into one or more chips (for example, it is noted that communications chip 2006 may be part of, or otherwise integrated with, processor 2004).

[0080] The communication chip 2006 enables wireless communication for the transfer of data to and from the computing system 2000. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not include any wires, although they may not in some embodiments. The communication chip 2006 can implement any number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols referred to as 3G, 4G, 5G, and beyond. The computing system 2000 may include a plurality of communication chips 2006. For example, a first communication chip 2006 may be dedicated for shorter-range wireless communication, such as Wi-Fi and Bluetooth, and a second communication chip 2006 may be dedicated for longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0081] The processor 2004 of the computing system 2000 includes an integrated circuit die packaged within the processor 2004. In some embodiments, the integrated circuit die of the processor includes embedded circuitry implemented with one or more integrated circuit structures or devices formed using the disclosed techniques, as variously described herein. The term "processor" may refer to any device or portion of a device that, for example, processes electronic data from registers and / or memory to transform that electronic data into other electronic data that may be stored in registers and / or memory.

[0082] The communication chip 2006 may also include an integrated circuit die packaged within the communication chip 2006. According to some such example embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the disclosed techniques as variously described herein. In light of this disclosure, it is appreciated that multi-standard wireless capability may be integrated directly into the processor 2004 (e.g., where the functionality of any chips 2006 is integrated into the processor 2004 rather than comprising separate communication chips). Further, it is appreciated that the processor 2004 may be a chipset having such wireless capability. In short, any number of processors 2004 and / or communication chips 2006 may be used.Similarly, any chip or chipset may have multiple functions integrated into it.

[0083] In various implementations, computing system 2000 may be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a cellular phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment controller, a digital camera, a portable music player, a digital video recorder, or any other electronic device or system that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques as variously described herein. It should be understood that reference to a computing system is also intended to include computing devices, apparatus, and other structures configured to compute or process information. Further examples

[0084] The following examples refer to further embodiments from which numerous permutations and configurations are obvious.

[0085] Example 1. An integrated circuit comprising: a source region and a drain region; a body of semiconductor material extending from the source region to the drain region, the body having a first end portion adjacent to the source region, a second end portion adjacent to the drain region, and a middle portion between the first and second end portions, the body further comprising an implant species, wherein a concentration of the implant species in the middle portion of the body is at least 10% higher than a concentration of the implant species in the first and second end portions; a gate structure on the middle portion of the body; and a first gate spacer on the first end portion of the body and a second gate spacer on the second end portion of the body.

[0086] Example 2. The integrated circuit of example 1, wherein the concentration of the implant species in the middle portion of the body is at least 50% higher than the concentration of the implant species in the first and / or second end portions.

[0087] Example 3. The integrated circuit of example 1 or 2, wherein at least a portion of the first end portion adjacent to the source region and / or at least a portion of the second end portion adjacent to the drain region is free of the implantation species.

[0088] Example 4. The integrated circuit of any one of examples 1-3, wherein the implantation species comprises an element having an atomic mass unit of 80 or less.

[0089] Example 5. The integrated circuit of any one of examples 1-4, wherein the implantation species comprises fluorine, chlorine, argon, or boron.

[0090] Example 6. The integrated circuit of any one of examples 1-5, wherein the implantation species comprises a halide.

[0091] Example 7. The integrated circuit of any one of examples 1-6, wherein the body extends in a first direction from the source region to the drain region and the gate structure extends in a second direction orthogonal to the first direction, and wherein a top surface of the middle portion of the body has a first width in the second direction; a top surface of the first end portion of the body has a second width in the second direction; and the first width is at least 5 angstroms less than the second width.

[0092] Example 8. The integrated circuit of example 7, wherein a top surface of the second end portion of the body has a third width; and the first width is at least 5 angstroms less than the third width.

[0093] Example 9. The integrated circuit of any one of examples 1-8, wherein the middle portion of the body has a first topmost surface; and the first end portion of the body has a second topmost surface located at least 1 nm above the first topmost surface.

[0094] Example 10. The integrated circuit of any one of examples 1-9, wherein the body extends in a first direction from the source region to the drain region and the gate structure extends in a second direction orthogonal to the first direction, and wherein: the central portion of the body is tapered such that a top surface of the central portion of the body has a first width that is at least 5 angstroms less than a second width of an intermediate region of the central portion of the body, the first and second widths being measured in the second direction; and the central portion of the body is more tapered than any taper of the first and / or second end portions.

[0095] Example 11. The integrated circuit of any one of examples 1-10, wherein the body is a fin.

[0096] Example 12. The integrated circuit of any one of examples 1-11, wherein the body comprises one of a nanoribbon, a nanowire, or a nanosheet.

[0097] Example 13. The integrated circuit of any one of examples 1-12, wherein the central portion of the body comprises a gated portion located laterally between portions of the gate structure and a partial fin portion located below the gated portion, and the partial fin portion tapers outwardly at a greater rate than the gated portion, and the gated portion of the central portion tapers outwardly at a greater rate than each of the first end portion and the second end portion.

[0098] Example 14. An integrated circuit comprising: a source region and a drain region; and a body of semiconductor material extending between the source region and the drain region, the body having a first end portion, a second end portion, and a middle portion between the first and second end portions, the body further comprising an implantation species comprising an element having an atomic mass unit of 80 or less or a halide, wherein a top surface of the middle portion has a first width, a top surface of the first end portion of the body has a second width that is at least 5 angstroms greater than the first width.

[0099] Example 15. The integrated circuit of Example 14, further comprising: a gate structure on the central portion of the body, wherein the body extends in a first direction between the source region and the drain region and the gate structure extends in a second direction orthogonal to the first direction, and wherein the first and second widths are measured in the second direction; and a first gate spacer on the first end portion of the body and a second gate spacer on the second end portion of the body.

[0100] Example 16. The integrated circuit of example 14 or 15, wherein a concentration of the implant species in the middle portion of the body is at least 50% higher than a concentration of the implant species in the first and second end portions.

[0101] Example 17. The integrated circuit of any one of examples 14-16, wherein the implantation species comprises fluorine, chlorine, argon, or boron.

[0102] Example 18. A method comprising: forming (i) a first body comprising a semiconductor material, the first body having a first end portion, a second end portion, and a middle portion between the first and second end portions, (ii) a second body laterally adjacent to the first body, (iii) a first gate spacer on the first end portion of the first body, and a second gate spacer on the second end portion of the first body and a dummy gate on the middle portion of the first body, and (iv) a first source or drain region adjacent to the first end portion of the first body and a second source or drain region adjacent to the second end portion of the first body;Implanting an implant species within the central portion of the first body without implanting the implant species within the second body, such that a concentration of the implant species in the central portion of the body is at least 10% higher than a concentration of the implant species in the first and / or second end portions, wherein the implant species comprises one of the elements having an atomic mass unit of 80 or less or a halide; and forming a gate structure on the central portion of the first body.

[0103] Example 19. The method of Example 18, wherein the first body extends in a first direction between the source region and the drain region and the gate structure extends in a second direction orthogonal to the first direction, and wherein the method further comprises: prior to forming the gate structure, trimming at least the portion of the central portion of the first body such that (i) a top surface of the central portion of the first body has a first width in the second direction, (ii) a top surface of the first end portion of the body has a second width in the second direction, and (iii) the first width is at least 5 angstroms less than the second width.

[0104] Example 20. The method of example 18 or 19, further comprising: patterning a mask located over the second body and not over the first body, wherein implanting comprises implanting the implant species within the central portion of the first body without implanting the implant species within the second body; and removing the mask and at least a portion of the first body.

[0105] Example 21. The integrated circuit of any one of Examples 1 to 17 or the method of any one of Examples 18 to 20, wherein the body is free of any dopants that can alter charge carrier transport.

[0106] Example 22. The integrated circuit of any one of Examples 1 to 17 or the method of any one of Examples 18 to 20, wherein the body comprises one or more dopants capable of altering charge carrier transport.

[0107] Example 23. The integrated circuit of any one of Examples 1 to 17, 21 or 22 or the method of any one of Examples 18 to 20, wherein the implantation species is a non-dopant that does not alter charge carrier transport.

[0108] Example 24. The integrated circuit of any one of Examples 1 to 17, 21-23 or the method of any one of Examples 18 to 20, wherein the concentration of the implant species in the middle portion of the body is at least 15% higher than the concentration of the implant species in the first and / or the second end portion, or at least 20% higher, or at least 25% higher, or at least 30% higher, or at least 35% higher, or at least 40% higher, or at least 45% higher, or at least 55% higher, or at least 60% higher, or at least 65% higher, or at least 70% higher, or at least 75% higher, or at least 80% higher, or at least 85% higher, or at least 90% higher, or at least 95% higher, or at least 100% higher.

[0109] The foregoing description of exemplary embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure be limited not by this detailed description, but rather by the claims appended hereto. Future applications claiming priority from this application may claim the disclosed subject matter in a different manner and may generally include any set of one or more limitations variously disclosed or otherwise shown herein.

Claims

[1] An integrated circuit comprising: a source region and a drain region; a body of semiconductor material extending from the source region to the drain region, the body having a first end portion adjacent to the source region, a second end portion adjacent to the drain region, and a middle portion between the first and second end portions, the body further comprising an implantation species, wherein a concentration of the implantation species in the middle portion of the body is at least 10% higher than a concentration of the implantation species in the first and second end portions; a gate structure on the middle section of the body; and a first gate spacer on the first end portion of the body and a second gate spacer on the second end portion of the body. [2] The integrated circuit of claim 1, wherein the concentration of the implantation species in the central portion of the body is at least 50% higher than the concentration of the implantation species in the first and / or second end portions. [3] The integrated circuit according to claim 1 or 2, wherein at least a part of the first end portion adjacent to the source region and / or at least a part of the second end portion adjacent to the drain region is free of the implantation species. [4] The integrated circuit of any one of claims 1 to 3, wherein the implantation species comprises an element having an atomic mass unit of 80 or less. [5] The integrated circuit of any one of claims 1 to 4, wherein the implantation species comprises fluorine, chlorine, argon or boron. [6] The integrated circuit of any one of claims 1 to 5, wherein the implantation species comprises a halide. [7] The integrated circuit according to any one of claims 1 to 6, wherein the body extends in a first direction from the source region to the drain region and the gate structure extends in a second direction orthogonal to the first direction, and wherein: an upper surface of the central portion of the body has a first width in the second direction; an upper surface of the first end portion of the body has a second width in the second direction; and the first width is at least 5 angstroms less than the second width. [8] The integrated circuit according to claim 7, wherein: an upper surface of the second end portion of the body has a third width, and the first width is at least 5 angstroms less than the third width. [9] The integrated circuit according to any one of claims 1 to 8, wherein: the middle portion of the body has a first uppermost surface; and the first end portion of the body has a second uppermost surface which is at least 1 nm above the first uppermost surface. [10] The integrated circuit according to any one of claims 1 to 9, wherein the body extends in a first direction from the source region to the drain region and the gate structure extends in a second direction orthogonal to the first direction, and wherein: the central portion of the body is tapered such that a top surface of the central portion of the body has a first width that is at least 5 angstroms less than a second width of an intermediate region of the central portion of the body, the first and second widths being measured in the second direction; and the middle section of the body is more tapered than the taper of the first and / or second end section. [11] The integrated circuit of any one of claims 1 to 10, wherein the body is a fin. [12] The integrated circuit of any one of claims 1 to 10, wherein the body comprises one of a nanoribbon, a nanowire, or a nanosheet. [13] The integrated circuit of any one of claims 1 to 12, wherein the central portion of the body comprises a gated portion located laterally between portions of the gate structure and a partial fin portion located below the gated portion, and the partial fin portion tapers outwardly at a greater rate than the gated portion, and the gated portion of the central portion tapers outwardly at a greater rate than each of the first end portions and the second end portion. [14] The integrated circuit according to any one of claims 1 to 13, wherein the implantation species is a non-dopant that does not alter charge carrier transport. [15] The integrated circuit according to any one of claims 1 to 14, wherein the concentration of the implantation species in the central portion of the body is at least 100% higher than the concentration of the implantation species in the first and / or second end portion. [16] An integrated circuit comprising: a source region and a drain region; and a body of semiconductor material extending between the source region and the drain region, the body having a first end portion, a second end portion, and a middle portion between the first and second end portions, the body further comprising an implantation species comprising an element having an atomic mass unit of 80 or less or a halide, wherein a top surface of the middle portion has a first width, a top surface of the first end portion of the body has a second width that is at least 5 angstroms greater than the first width. [17] The integrated circuit of claim 16, further comprising: a gate structure on the central portion of the body, wherein the body extends in a first direction between the source region and the drain region and the gate structure extends in a second direction orthogonal to the first direction, and wherein the first and second widths are measured in the second direction; and a first gate spacer on the first end portion of the body and a second gate spacer on the second end portion of the body. [18] The integrated circuit of claim 16 or 17, wherein a concentration of the implantation species in the central portion of the body is at least 50% higher than a concentration of the implantation species in the first and second end portions. [19] The integrated circuit of any one of claims 16 to 18, wherein the implantation species comprises fluorine, chlorine, argon or boron. [20] The integrated circuit according to any one of claims 16 to 19, wherein the implantation species is a non-dopant that does not alter charge carrier transport. [21] The integrated circuit according to any one of claims 16 to 20, wherein a concentration of the implantation species in the central portion of the body is at least 100% higher than a concentration of the implantation species in the first and / or second end portion. [22] A method comprising: Forming (i) a first body comprising a semiconductor material, the first body having a first end portion, a second end portion, and a middle portion between the first and second end portions, (ii) a second body laterally adjacent to the first body, (iii) a first gate spacer on the first end portion of the first body, and a second gate spacer on the second end portion of the first body and a dummy gate on the middle portion of the first body, and (iv) a first source or drain region adjacent to the first end portion of the first body and a second source or drain region adjacent to the second end portion of the first body; Implanting an implantation species within the central portion of the first body without implanting the implantation species within the second body, such that a concentration of the implantation species in the central portion of the body is at least 10% higher than a concentration of the implantation species in the first and / or second end portions, wherein the implantation species comprises one of the elements having an atomic mass unit of 80 or less or a halide; and Forming a gate structure on the middle portion of the first body. [23] The method of claim 22, wherein the first body extends in a first direction between the source region and the drain region and the gate structure extends in a second direction orthogonal to the first direction, and wherein the method further comprises: prior to forming the gate structure, trimming at least the part of the central portion of the first body such that (i) a top surface of the central portion of the first body has a first width in the second direction, (ii) a top surface of the first end portion of the body has a second width in the second direction, and (iii) the first width is at least 5 angstroms less than the second width. [24] The method of example 22 or 23, further comprising: patterning a mask located over the second body and not over the first body, wherein implanting comprises implanting the implant species within the central portion of the first body without implanting the implant species within the second body; and removing the mask and at least a portion of the first body. [25] The method according to any one of claims 22 to 24, wherein the implantation species is a non-dopant that does not alter charge carrier transport.

Images