Integrated circuit structure with backside source or drain contact selectivity using colored hard masks

Abstract

Source and drain contact backside selectivity using colored hard masks is described. A structure includes a first epitaxial source or drain structure at one end of first nanowires or a fin, a first conductive source or drain contact vertically below a bottom of the first epitaxial source or drain structure, and a first hard mask material below and in contact with the first conductive source or drain contact. A second epitaxial source or drain structure is at one end of the second nanowires or a fin, with a second conductive source or drain contact vertically below and in contact with a bottom of the second epitaxial source or drain structure, and with a second hard mask material below the second conductive source or drain contact.The first hard mask material extends laterally across the first conductive source or drain contact and is laterally continuous around the second hard mask material.

Description

BACKGROUND

[0001] In recent decades, feature scaling in integrated circuits has been a driving force behind the ever-growing semiconductor industry. Scaling to ever smaller features enables increased densities of functional units within the limited footprint of semiconductor chips. For example, shrinking transistor sizes allows for the integration of an increased number of memory or logic components on a chip, enabling the production of products with increased capacity. However, the pursuit of ever-increasing capacity is not without its challenges. The need to optimize the performance of each component is becoming increasingly important.

[0002] The variability of conventional and currently known manufacturing processes may limit the possibility of extending them further into the 10-nanometer or sub-10-nanometer node range. Consequently, the fabrication of the functional components required for future technology nodes may require the introduction of new methods or the integration of new techniques into or in place of current manufacturing processes.

[0003] In integrated circuit device manufacturing, multi-gate transistors, such as trigate transistors, have become increasingly common as device dimensions continue to shrink. Trigate transistors are generally fabricated on either bulk silicon or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred due to their lower cost and compatibility with existing high-yield bulk silicon substrate infrastructure.

[0004] However, the scaling of multi-gate transistors has not been without consequences. As the dimensions of these fundamental building blocks of a microelectronic circuit are reduced and as the sheer number of fundamental building blocks fabricated in a given region increases, the constraints on the semiconductor processes used to manufacture these devices have become overwhelming. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows cross-sectional views of a front-side power delivery interconnect stack and a rear-side power delivery interconnect stack according to an embodiment of the present disclosure. Fig. 2-3, 4A-4E and 5-8 show angled cross-sectional views illustrating various operations in methods of fabricating an integrated circuit structure with backside source or drain contact selectivity, according to an embodiment of the present disclosure. Fig. 9A and Fig. 9B show angled cross-sectional views illustrating various operations in a method of fabricating an integrated circuit structure having a backside source or drain contact color scheme with minimal stack height loss, according to an embodiment of the present disclosure. Fig. 9C-9E show angled cross-sectional views and a planar cross-sectional view illustrating various operations in a method of fabricating an integrated circuit structure with a two-layer etch stop to enable backside coloring in the presence of exposed via layer features, according to an embodiment of the present disclosure. Fig. 10A illustrates a top view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode. Fig. 10B illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode. Fig. 11A illustrates a top view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode, according to an embodiment of the present disclosure. Fig. 11B illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode, according to an embodiment of the present disclosure. Fig. 12A-12J illustrate cross-sectional views of various operations in a method of manufacturing a gate-all-around integrated circuit structure according to an embodiment of the present disclosure. Fig. 13 illustrates a computing device according to an implementation of the disclosure. Fig. 14 shows an interposer incorporating one or more embodiments of the disclosure. Fig. 15 is an isometric view of a mobile computing platform employing an IC manufactured according to one or more of the processes described herein or including one or more of the features described herein, according to an embodiment of the present disclosure. Fig. 16 illustrates a cross-sectional view of a die attached to a flip chip, according to an embodiment of the present disclosure. DESCRIPTION OF THE EMBODIMENTS

[0005] Integrated circuit structures with backside source or drain contact selectivity using colored hard masks are described. In the following description, numerous specific details are set forth, such as specific integration and material specifications, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one of ordinary skill in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order not to unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the figures are exemplary representations and are not necessarily drawn to scale.

[0006] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or application and the uses of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any implementation described herein as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background, brief summary, or subsequent detailed description.

[0007] This description includes references to "a single embodiment" or "an embodiment." The appearance of the phrases "in a single embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. Certain features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0008] Terminology. The following paragraphs provide definitions or context for terms found in this disclosure (including the appended claims): "Comprising." This term is open-ended. As used in the appended claims, this term does not preclude additional structure or operations.

[0009] "Capable." Various units or components may be described or claimed as being "capable of" performing a task or tasks. In such contexts, "capable of" is used to refer to a structure by indicating that the units or components comprise a structure that performs that task or tasks during operation. As such, the unit or component may be described as being capable of performing the task even if the specified unit or component is not currently in operation (e.g., not turned on or active). Stating that a unit, circuit, or component is "capable" of performing one or more tasks is expressly not intended to invoke 35 U.S.C. §112 paragraph six for that unit or component.

[0010] “First,” “second,” etc. As used herein, these expressions are used as labels for nouns they precede and do not imply any kind of ordering (e.g., spatial, temporal, logical, etc.).

[0011] "Coupled" - The following description refers to elements, nodes, or features that are "coupled" to one another. As used herein, unless expressly stated otherwise, "coupled" means that one element, node, or feature is directly or indirectly linked to (or communicates directly or indirectly with) another element, node, or feature, and not necessarily mechanically.

[0012] Additionally, certain terminology may also be used in the following description for reference purposes only and is not intended to be limiting. For example, terms such as "upper," "lower," "over," and "under" refer to directions in the drawings to which reference is made. Terms such as "front," "rear," "back," "side," "outer," and "iner" describe the orientation or position, or both, of portions of the component within a consistent but arbitrary frame of reference made clear by reference to the text and associated drawings describing the component being discussed. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

[0013] "Prevent" - As used herein, prevent is used to describe a reducing or minimizing effect. When a component or feature is described as preventing an action, movement, or condition, it may completely prevent the outcome, result, or future state. Additionally, "prevent" can also refer to a reduction or decrease in the outcome, performance, or effect that might otherwise occur. Accordingly, when a component, element, or feature is described as preventing an outcome or condition, it need not completely prevent or eliminate the outcome or condition.

[0014] Embodiments described herein may relate to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first stage of integrated circuit (IC) fabrication, where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. After the final FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

[0015] Embodiments described herein may relate to back-end-of-line (BEOL) semiconductor processing and structures. BEOL is the second stage of IC fabrication, where the individual devices (e.g., transistors, capacitors, resistors, etc.) are connected to wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bond positions for chip-to-package connections. During the BEOL portion of the fabrication stage, contacts (pads), bond wires, vias, and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added during BEOL.

[0016] Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. Specifically, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.

[0017] One or more embodiments address the coloration (selectivity) of backside source or drain contact structures, e.g., using dual-backside epitaxial (epi) contacts. One or more embodiments described herein relate to gate-all-around integrated circuit structures fabricated using backside hardmask selectivity or coloration. Unless otherwise stated, it is understood that reference herein to nanowires may indicate nanowires or nanoribbons, nanosheets, or forksheets. One or more embodiments described herein relate to fin-based integrated circuit structures fabricated using backside hardmask selectivity or coloration. In one embodiment, a backside contact coloration scheme with single-pass frontside processing is described, enabling cell height scaling.In one embodiment, a backside contact coloration scheme with minimal stack height loss is described. In one embodiment, two-layer etch stops are described that enable backside coloration in the presence of exposed via layer features.

[0018] To provide context, with increasing cell height scaling, the edge placement error (EPE) for the connection between BM0 and the backside contact of the correct color (e.g., NEPI vs. PEPI) will decrease. Furthermore, the concurrent scaling of poly pitch increases the importance of contact resistance reduction through factors such as the choice of epitaxial etch, implantation species, and contact metallization, which may vary for contacts of different colors. While patterning schemes that allow independent selection of PMOS and NMOS epitaxial etch, implant, and contact metal for frontside contacts are known, patterning schemes that allow the same for backside contacts are limited by bond distortions, which impose a high lower bound on pattern registration error.The coloring scheme presented here mitigates both of these problems without requiring any changes to the front-side processing.

[0019] According to one or more embodiments of the present disclosure, a dyeing scheme is described in which NMOS and PMOS can be independently opened, etched, implanted, and metallized on the backside without changing the processing on the frontside, and then dyed after contact metallization to increase the EPE margin between BM0 and backside contact, which decreases as the cell height continues to scale to smaller dimensions. To be compatible with the minimum registration absolute maximum error that can be achieved on the backside with bond distortions, this method includes allowing the backside contact placeholder material to be removed isotropically from the backside, so that lithographic patterning only needs to expose a narrow region of the backside contact placeholder material to enable removal.Post-contact coloring to increase the BM0-to-back contact EPE requires two fillable materials that can be etched selectively to each other and to other materials exposed after the BM0 etch.

[0020] To provide more context, as semiconductor scaling results in ever-tighter interconnects, low-resistance power delivery solutions are needed. Backside power delivery, a scheme in which a power delivery interconnect network connects directly to the transistors from the backside of the wafer rather than sharing space with frontside routing, is a potential solution for future generations of semiconductor technology.

[0021] Traditionally, power is delivered via a front-panel interconnect. At the standard cell level, power can be delivered directly to the transistors or via an upper and lower cell boundary. The power delivered by an upper and lower cell boundary enables a relatively shorter standard cell height with a slightly higher power network resistance. However, a front-panel interconnect network shares the interconnect stack with the signal routing, reducing signal routing traces. Furthermore, for a high-performance design, the metal wires at the upper and lower cell boundaries must be wide enough to reduce the power network resistance and improve performance. This typically results in an increase in cell height.According to one or more embodiments of the present disclosure, power delivery may be provided from a wafer or substrate backside to address area and performance concerns. At the cell level, a wider metal 0 power at the top and bottom cell boundaries may no longer be required, allowing cell height reduction. Furthermore, power network resistance can be significantly reduced, leading to performance improvements. At the block and chip level, signal routing lanes on the frontside are enlarged by eliminating power outages, and power network resistance is significantly reduced through very wide wires, large vias, and reduced interconnect layers.

[0022] In previous technologies, a bump-to-transistor power delivery network required significant block resources. This resource utilization on the metal stack manifested itself in some process nodes as standard cell architectures with layout versioning or block-level cell placement constraints. In one embodiment, eliminating the power delivery network on the front side of the metal stack enables free-sliding placement of cells in the block without power delivery complications and without placement-related delay time variations.

[0023] As an example comparison, Fig. 1 Cross-sectional views of a front-side power delivery interconnect stack and a rear-side power delivery interconnect stack according to an embodiment of the present disclosure.

[0024] As in Fig. 1, a front-side power interconnect stack 100 includes a transistor 102 and a signal and power delivery metallization 104. The transistor 102 includes a bulk substrate 106, semiconductor fins 108, a terminal 110, and a device contact 112. The signal and power delivery metallization 104 includes conductive vias 114, conductive lines 116, and a metal bump 118.

[0025] As in Fig. 1, a backside power interconnect stack 150 includes a transistor 152, a frontside signal metallization 154A, and a power delivery metallization 154B. The transistor 152 includes semiconductor nanowires or nanoribbons 158, a terminal 160, a device contact 162, and a deep confinement via 163. The frontside signal metallization 154A includes conductive vias 164A, conductive lines 166A, and a metal bump 168A. The power delivery metallization 154B includes conductive vias 164B, conductive lines 166B, and a metal bump 168B. It should be noted that a backside power approach may also be used for structures with semiconductor fins.

[0026] To provide more context, a fundamental component of a backside power delivery network is an electrically functional feature that connects the source or drain contacts of a transistor to the backside interconnect network. Therefore, there is a need for a design and method for fabricating an interface function that is compatible with existing library cell design and transistor contact flow conventions.

[0027] Currently, there are no solutions for high-volume production because backside power delivery has not yet been adopted in high-volume manufacturing. Possible approaches include deep trench contact (TCN), direct backside source-drain contacts, or replacing a gate contact trace with a backside power contact. Depending on the proposed scheme, these solutions may suffer from high-resistance contacts, negating the inherent value of co-optimizing backside power delivery with front-end transistor processing, leading to defect and performance risks and trade-offs.

[0028] In a first aspect, a backside contact staining scheme with single-pass frontside processing is described that enables cell height scaling.

[0029] According to one embodiment of the present disclosure, backside connections to the gates and / or source / drains may be formed. In certain embodiments, the "coloring" of the hard mask is used to provide selectivity in forming such a connection.

[0030] As an example processing scheme show Fig. 2-3, 4A-4E, and 5-8 are angled cross-sectional views illustrating various operations in methods for fabricating an integrated circuit structure with backside source or drain contact selectivity, according to an embodiment of the present disclosure. It should be noted that the described and illustrated embodiments may also be applicable to a fin structure instead of a stack of nanowires or nanoribbons or nanosheets or forksheets.

[0031] Fig. Figure 2 shows a starting structure 200 with a plurality of horizontally stacked nanowires (or nanoribbons, nanosheets, or forksheets, or alternatively, a fin) 202, each overlying a corresponding partial fin 204 on a substrate 201, such as silicon nanowires overlying a silicon partial fin on a silicon substrate. A corresponding gate stack 206, e.g., a stack comprising a metal gate electrode and a high-k gate dielectric layer, is located over and around each of the plurality of horizontally stacked nanowires 202. Alternatively, the gate stacks 206 may also be dummy gate stacks at this stage. A dielectric gate cap layer 207, e.g., a silicon nitride cap, may be present on each gate stack 206.

[0032] Dielectric sidewall spacers 208, such as silicon nitride or carbon-doped silicon nitride spacers, are located along the sides of each gate stack 206 and can be retained over each gate stack 206 (along with an optional helmet layer) by various processing operations. A shallow trench isolation structure 210, such as a silicon oxide isolation structure, is located near the partial fin 204. A cavity 212 is located between gate stacks at locations where source or drain structures are ultimately to be formed. The gate stacks 206 can be used as a mask to etch trenches into exposed portions of the fins (e.g., nanowire-forming fins), such as in the source and drain regions of the fins, creating the illustrated structure with cavities 212. In one embodiment, the etching extends at least partially into, or even completely through, the partial fins 204.

[0033] In Fig. 3, an etch is performed beneath the source or drain locations for possible contact formation on the backside. For example, an etch is extended into the source or drain locations, and then first conductive source or drain contacts 214 (e.g., deep titanium nitride via structures) are formed at these locations, e.g., by a deposition and etch-back process.

[0034] After manufacturing the structure from Fig. 3 epitaxial source or drain structures are formed, front side processing is completed, the structure is inverted and back side exposure is performed.

[0035] As an example of a resulting structure, structure 400 is shown in Fig. 4A is shown after exposure from back to top. The structure 400 includes a front-side support 402, a front-side BEOL structure 404, and gate stacks 410. Epitaxial source or drain structures 406 and 408, such as silicon germanium or silicon epitaxial source or drain structures (or vice versa), are then arranged in trenches between gate stacks 410 at the ends of nanowires (or fins). First conductive source or drain contacts 412 (which may be placeholder structures) are located above the epitaxial source or drain structures 406 and 408 and were exposed by backside exposure. A patterning stack 414 is formed and patterned on the exposed backside.

[0036] As in Fig. 4B, selected ones of the first conductive source or drain contacts 412 are removed, e.g., through a masking and etching process, to form cavities 416. The other ones of the first conductive source or drain contacts 412 remain. In one embodiment, first conductive source or drain contacts 412 in N-type locations are removed, while first conductive source or drain contacts 412 in P-type locations are retained. In another embodiment, first conductive source or drain contacts 412 in P-type locations are removed, while first conductive source or drain contacts 412 in N-type locations are retained. The patterning stack 414 may be reduced to the patterning stack 414A, as shown in the figure.

[0037] As in Fig. 4C, the cavities 416 may be etched to form cavities 418 that may be wider than the cavities 416.

[0038] In Fig. 4D, second conductive source or drain contacts 420 (e.g., deep tungsten via structures) are formed in the cavities 418, e.g., by a deposition and planarization process.

[0039] As in Fig. As shown in Figure 4E, the second conductive source or drain contacts 420 are selectively recessed, e.g., based on metal selectivity, to form recessed second conductive source or drain contacts 420A. A "coloring" dielectric or hard mask material 422, such as silicon nitride, is then formed in the recesses, e.g., through a deposition and planarization process.

[0040] In Fig. 5, the structure 500 is a mirror image of Fig. 4E, wherein the remainder of the first conductive source or drain contacts 412 are removed, e.g., by a selective etching process, to form cavities 424.

[0041] As in Fig. 6, the cavities 424 may be etched to form cavities 426 that may be wider than the cavities 424.

[0042] As in Fig. 7, third conductive source or drain contacts 428 (e.g., deep tungsten via structures) are formed in cavities 426, e.g., by a deposition and planarization process.

[0043] As in Fig. 8, the structure 800 is formed by selectively deepening the third conductive source or drain contacts 428 to form deepened third conductive source or drain contacts 428A, e.g., based on metal selectivity. A "coloring" dielectric or hard mask material 430, e.g., silicon carbide, is then formed in the recesses, e.g., through a deposition and planarization process. In one embodiment, the hard mask material 430 has a different composition than the hard mask material 422 to achieve etch selectivity between the locations of the epitaxial source or drain structure 406 and the locations of the epitaxial source or drain structure 408.

[0044] It should be noted that for further processing, a hard mask location 422 or 430 is selectively removed to expose a contact to the epitaxial source or drain structure 406 or 408, respectively. For example, the bottom ILD may be deposited, patterned, and etched, and vias connecting BM0 to selected ones of the epitaxial source or drain structures 406 or 408 may be metallized. It should be noted that such a via may not extend the entire length of the epitaxial source or drain structure 406 or 408, and therefore, portions of the corresponding "colored" hard mask material 422 or 430 may remain on the corresponding recessed second conductive source or drain contacts 420A or recessed third conductive source or drain contacts 428A at locations inside and / or outside the page.

[0045] In a second aspect, a backside contact dyeing scheme with minimal stack height loss is described.

[0046] To provide context, with increasing cell height scaling, it becomes increasingly difficult to prevent the connection of the backside power rail of one polarity to the backside contact of the transistor with the opposite polarity. Colored etch stops on the backside contacts are one method to prevent the backside power rail of one polarity from meeting the backside contact of a transistor with the opposite polarity, but this comes at the cost of additional planarization steps that consume stack height, increasing the occurrence of backside power rail-to-gate shorts. According to one embodiment of the present disclosure, the following coloring scheme can be implemented to achieve colored backside contacts without additional reduction in the stack height between the backside power rail and the transistor gates beyond that of the uncolored backside contacts.

[0047] Other solutions, as described above, achieve colored backside contacts with processes that result in stack height loss in multiple operations, including: (1) an additional polishing of the contact metal, (2) an additional etching of the contact metal recess for each contact color, and (3) an additional polishing operation for each contact coloring material.

[0048] According to one embodiment of the present disclosure, the coloring scheme described below implements one or more helmets that are deposited after removing the second set of contact placeholders to color the first set of contacts that have already been metallized. After metallizing the second set of contacts, the contact metal is recessed, a second coloring material is deposited, and this coloring material is polished to expose the helmet material forming the opposite color. The height of the helmet stack forming the first coloring material can be adjusted to achieve the desired height of the etch stop forming the second coloring material, taking into account the losses due to the contact metal recess and the polishing of the second coloring material.

[0049] Embodiments can be implemented to improve yield by reducing the occurrence of short circuits between the backside power rail and the gate, and performance can be improved by reducing the capacitance between the backside power rail and the gate. As cell height scaling increases, maintaining the stack height between the gate and backside power rail becomes more difficult because (1) the aspect ratio of the etches defining the ribbon stack / subfin increases and (2) the oxide area for the shallow trench isolation, where the backside exposure polish stops, decreases.

[0050] Detection of the implementation of the embodiments described here can be achieved using standard FA techniques (XSEM, XTEM): A cross-section may show a trace completely covered by an etch stop of one color, except for the regions above the contacts of the opposite color, where the backside metal interconnect connects to the recessed contact metal of the backside contact. The alignment of the backside power rail to the contacts may be incorrect. Etch stops may occur in a misaligned region, preventing the backside power rail from having the transistor contact with the wrong polarity, as described below.

[0051] As an example processing scheme show Fig. 9A and Fig. 9B are angled cross-sectional views illustrating various operations in a method of fabricating an integrated circuit structure having a backside source or drain contact color scheme with minimal stack height loss, according to an embodiment of the present disclosure. It should be noted that the described and illustrated embodiments may also be applicable to a fin structure instead of a stack of nanowires or nanoribbons or nanosheets or forksheets.

[0052] In Fig. 9A illustrates a starting structure 900 in preparation for patterning placeholder stripes. In particular, the starting structure 900 includes first epitaxial source or drain structure types 902 (e.g., NMOS or PMOS) and second epitaxial source or drain structure types 904 (e.g., PMOS or NMOS). Generic backside contact holders 906 are located on the backside (shown here face up) of the first epitaxial source or drain structure types 902 and the second epitaxial source or drain structure types 904. Frontside contacts 908 are located on the frontside (shown here face down) of the first epitaxial source or drain structure types 902. Frontside contacts 910 are located on the frontside (shown here face down) of the second epitaxial source or drain structure types 904. Dielectric walls 912 may separate the structures from each other, as shown.A mask stack 914 with an opening 916 is located on the back of the structure.

[0053] The processing of the initial structure 900 of Fig. 9A may include patterning the backside contact placeholders 906 using the mask stack 914 as an etch mask to enable a first placeholder stripe, filling and polishing the contact metal, forming a second placeholder stripe, building up a helmet color layer, filling and polishing the contact metal, recessing the contact metal, filling and overburdening the color material, and polishing the color to form the structure 920 of Fig. 9B to receive.

[0054] As in Fig. 9B, the structure 920 includes backside contacts 922 on the backside (shown here with the top side up) of the first epitaxial source or drain structure types 902 and backside contacts 924 on the backside (shown here with the top side up) of the second epitaxial source or drain structure types 904. A first colored hard mask 926 is located on the backside contacts 922 on the backside of the first epitaxial source or drain structure types 902. A second colored hard mask 928, different from the first colored hard mask 926, is located on the backside contacts 924 on the backside of the second epitaxial source or drain structure types 904.In one embodiment, the first colored hard mask 926 is a non-discrete first colored hard mask that extends laterally beyond the backside contacts 922 and is laterally continuous around discrete portions of the second colored hard mask 928 that are confined to the backside contacts 924, as shown.

[0055] The structure 920 from Fig. 9B can then be provided with non-patterned contact opening etches. For example, after the open etch of the non-patterned contact 1, a contact metal in the polarity 1 trace is exposed, while the contact metal in the polarity 2 trace is covered with an etch stop. Misaligned regions of a polarity 1 trace may appear like a polarity 2 trace. After the open etch of the non-patterned contact 2, the contact metal in the polarity 2 trace is exposed, while the contact metal in the polarity 1 trace is covered with a cap layer etch stop of helmet material. Misaligned regions of a polarity 2 trace may appear like a polarity 1 trace.

[0056] In a third aspect, two-layer etch stops are described that enable backside coloring in the presence of exposed via layer features.

[0057] For context, features that cut through the device layer, such as metal gate cut and fin trim isolation, are often used to enable further scaling of the cell height. These features, filled with dielectric materials, are subsequently exposed during backside processing, which limits the choice of dielectric materials that can be used to color the source, drain, and / or gate contacts on the backside. In one embodiment, a dual-color, two-layer etch stop scheme is described in which a dielectric liner is used to mask these via-layer features, allowing one of the two colored etch stops to be composed of the same material as the exposed via-layer features.

[0058] Other solutions include the use of selective dielectric etches to deepen via-layer features, such as metal gate cuts and fin trim isolation, after exposing the backside and replacing them with a fillable silicon oxide similar to the oxide used for shallow trench isolation. An advantage of the approach described below is that the alternative solution can result in stack height loss (e.g., reduced power rail-to-gate distance on the backside) due to dielectric etching and polishing of the replacement dielectric, whereas this is not the case when using two-layer dielectric etch stops.

[0059] According to one embodiment of the present disclosure, a two-color contact patterning scheme relies on (1) selectively etching one color etch stop to the other color etch stop and (2) selectively etching each etch stop to the materials exposed in the array. In the case of backside contacts, the materials exposed in the array include not only the shallow trench isolation oxide and the partial fin replacement oxide, but also the exposed via layer features, such as the metal gate cut and fin trim isolation, which are often filled with another dielectric material. In the approach described here, a liner is implemented covering the exposed via layer features, so that one of the two color etch stops does not need to be etched selectively to the exposed via layer features.

[0060] The embodiments can be implemented to restore flexibility in the choice of color etch stops for backside contacts without the disadvantages of the previous solution. Two-color patterned backside contacts provide a path for further scaling of cell height with comparatively low lithographic alignment / registration requirements.

[0061] Detection of the implementation of embodiments described herein may include identifying a dielectric liner that may remain in at least two locations: (1) under the back power rail / back interconnect trench plugs and (2) under the etch stops of the second color in misaligned regions of the back power rail / back interconnect traces associated with the first color.

[0062] As an example processing scheme show Fig. 9C-9E are angled cross-sectional views and a planar cross-sectional view illustrating various operations in a method of fabricating an integrated circuit structure with a two-layer etch stop to enable backside coloring in the presence of exposed via layer features, according to an embodiment of the present disclosure. It should be noted that the described and illustrated embodiments may also be applicable to a fin structure instead of a stack of nanowires or nanoribbons or nanosheets or forksheets.

[0063] In Fig. 9C illustrates an initial structure 950 after metal recessing. In particular, the initial structure 950 includes first epitaxial source or drain structure types 952 (e.g., NMOS or PMOS) and second epitaxial source or drain structure types 954 (e.g., PMOS or NMOS). Backside contacts 956 are located on the backside (shown here upside up) of the first epitaxial source or drain structure types 952. Backside contacts 958 are located on the backside (shown here upside up) of the second epitaxial source or drain structure types 954. Frontside contacts 962 are located on the frontside (shown here downside) of the first epitaxial source or drain structure types 952. Frontside contacts 964 are located on the frontside (shown here downside) of the second epitaxial source or drain structure types 954.Dielectric walls 960 may separate the structures from each other, as shown. A global hard mask 964 with openings 966 therein is located on the backside of the structure. In one embodiment, the openings 966 expose the backside contacts 956, as shown.

[0064] The processing of the output structure 950 from Fig. 9C may include opening 966, filling and overstressing, and planarization to form a first colored hard mask, a global backside contact recess, liner deposition, deposition of a second colored hard mask, and planarization to form structure 970 of Fig. 9D to provide.

[0065] As in Fig. 9D, the structure 970 includes a first colored hard mask 972 on the backside contacts 956 on the backside of the first epitaxial source or drain structure types 952. A second colored hard mask 974, different from the first colored hard mask 972, is located over the backside contacts 958 on the backside of the second epitaxial source or drain structure types 954. A global hard mask layer 976 lies on top of the first colored hard mask 972 and is located between the second colored hard mask 974 and the backside contacts 958. In one embodiment, the global hard mask layer 976 has a different composition than the first colored hard mask 972. In one embodiment, the global hard mask layer 976 lies continuously over the first colored hard mask 972 and along the sidewalls, as well as under the second colored hard mask 974.

[0066] The structure 970 from Fig. 9D can then be provided with non-patterned contact opening etches. After patternless opening of the first color etch stops (etching the dielectric liner followed by etching the first color etch stop), the contact metal of the contacts associated with the first color is exposed, while the dielectric liner remains under the second color etch stop. The dielectric liner under the second etch stop material in misaligned regions of traces associated with the first color is detectable in a final product. During a non-patterned opening of the second color etch stops (etching the second color etch stop followed by etching the dielectric liner), the dielectric liner protects the via layer features from the second color contact etch, so that the second contact coloring material is the same as the fill material of the via layer features before it is completely removed.The presence of contact material of the first color, but not of the dielectric liner, in misaligned regions of the trace associated with the second color is detectable in a final product, as is the absence of a depression of via layer features having a composition similar to that of the second color material in the trace associated with the second color (i.e., not substantially distinguishable by contact etching of the second color).

[0067] In Fig. For example, FIG. 9E shows a structure 980 including a mask pattern 986 with a first trace 982 and a second trace 984, which may expose portions of recesses 988 created for contact openings. The structure 980 highlights the two-layer masks 974 / 976 and 976 / 972, as well as the remainder of the dielectric liner 976 beneath the backside interconnect trench plugs 986, which may be detectable in a final product.

[0068] It should be noted that the dual-material approach described above is detectable in final products. Cross-sections may show different contact "colors" that have different dimensions and / or compositions. The final appearance may differ from previous approaches in that the dimensions between different contact colors may match the front-side registration error, which is significantly lower than the back-side registration error of the pattern. Cross-sections may also show residual coloring dielectric materials outside the vias, meaning the coloring dielectric materials may also remain in non-contacted regions.Cross-sections may show different epitaxial etch profiles, implantation species, and contact metals in adjacent NMOS and PMOS backside contacts, which, due to bond distortions, are closer together than can be reliably patterned on the backside. It should be noted that, although the above figures show gate-all-around based transistors, the embodiments can be applied to channels of any shape or material (fins, nanowires, nanoribbons, nanocomb / forksheet, etc.). It should be noted that, although the figures show a single layer of transistors, the embodiments can also be applied to multilayer transistor architectures.It is noted that, although the figures show that all backside contact regions are metallized and covered with a dielectric, backside contact regions that do not require active connections can be depopulated (i.e., non-active regions are filled with a dielectric) by a patterning operation before metallization of the backside contacts.

[0069] It should be noted that, as used throughout the disclosure, a partial fin, nanowire, nanoribbon, or fin described herein may be a silicon partial fin, silicon nanowire, silicon nanoribbon, or silicon fin. As used throughout, a silicon layer or structure may be used to describe a silicon material comprising a very substantial amount, if not exclusively, of silicon. However, it is understood that virtually 100% pure Si may be difficult to form and thus could include a tiny percentage of carbon, germanium, or tin. Such impurities may be included as an unavoidable impurity or component during the deposition of Si, or may "contaminate" the Si upon diffusion during post-deposition processing.As such, embodiments described herein directed to a silicon layer or structure may include a silicon layer or structure comprising a relatively small amount, e.g., an "impurity" level, of non-Si atoms or species, such as Ge, C, or Sn. It should be understood that a silicon layer or structure as described herein may be undoped or doped with dopant atoms such as boron, phosphorus, or arsenic.

[0070] It should be noted that, as used throughout the disclosure, a partial fin, nanowire, nanoribbon, or fin described herein may be a silicon-germanium partial fin, a silicon-germanium nanowire, a silicon-germanium nanoribbon, or a silicon-germanium fin. As used throughout, a silicon-germanium layer or structure may be used to describe a silicon-germanium material composed of substantial portions of both silicon and germanium, such as at least 5% of each. In some embodiments, the amount of germanium is greater than the amount of silicon. In certain embodiments, a silicon-germanium layer or structure comprises about 60% germanium and about 40% silicon (Si 40 Ge 60). In other embodiments, the amount of silicon is greater than the amount of germanium. In certain embodiments, a silicon-germanium layer or structure comprises about 30% germanium and about 70% silicon (Si 70 Ge 30). It is understood that virtually 100% pure silicon germanium (commonly referred to as SiGe) may be difficult to form and thus might include a tiny percentage of carbon or tin. Such impurities may be included as an unavoidable impurity or component during the deposition of SiGe or may "contaminate" the SiGe upon diffusion during post-deposition processing. Thus, embodiments described herein directed to a silicon germanium layer or structure may include a silicon germanium layer or structure comprising a relatively small amount, e.g., an "impurity" level, of non-Ge and non-Si atoms or species, such as carbon or tin. It is understood that a silicon germanium layer or structure as described herein may be undoped or doped with dopant atoms, such as boron, phosphorus, or arsenic.

[0071] Another aspect is to note that backside source or drain contact selectivity using colored hard masks can also be implemented with frontside architectures. In one example, backside source or drain contact selectivity using colored hard masks can be implemented with contact over active gate (COAG) structures and processes. It is further noted that the following features of the "color" hard mask COAG are also applicable to the backside contact concepts described above. One or more embodiments of the present disclosure are directed to semiconductor structures or devices having one or more gate contact structures (e.g., gate contact vias) disposed over active portions of gate electrodes of the semiconductor structures or devices.One or more embodiments of the present disclosure are directed to methods of manufacturing semiconductor structures or devices having one or more gate contact structures formed over active portions of gate electrodes of the semiconductor structures or devices. Approaches described herein may be used to reduce standard cell area by enabling gate contact formation over active gate regions. In accordance with one or more embodiments, tapered gate and trench contacts are implemented to enable COAG manufacturing. The embodiments may be implemented to enable closely spaced patterning.

[0072] To provide further background on the importance of a COAG process scheme, in technologies where space and layout constraints are somewhat relaxed compared to current generation space and layout constraints, contact to a gate structure can be made by making contact to a portion of the gate electrode disposed over an isolation region. As an example, Fig. 10A is a plan view of a semiconductor device having a gate contact disposed over an inactive portion of a gate electrode.

[0073] Referring to Fig. 10A, a semiconductor structure or device 1000A includes a diffusion or active region 1004 disposed in a substrate 1002 and within an isolation region 1006. One or more gate lines (also known as poly lines), such as gate lines 1008A, 1008B, and 1008C, are disposed over the diffusion or active region 1004 as well as over a portion of the isolation region 1006. Source or drain contacts (also known as trench contacts), such as contacts 1010A and 1010B, are disposed over source and drain regions of the semiconductor structure or device 1000A. Trench contact vias 1012A and 1012B each make contact with trench contacts 1010A and / or 1010B. A separate gate contact 1014 and an overlying gate contact via 1016 provide contact to the gate line 1008B.In contrast to the source or drain trench contacts 1010A or 1010B, the gate contact 1014 is disposed above the isolation region 1006 from a top view perspective, but not above the diffusion or active region 1004. Furthermore, neither the gate contact 1014 nor the gate contact via 1016 is disposed between the source or drain trench contacts 1010A and 1010B.

[0074] Fig. 10B illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact disposed over an inactive portion of a gate electrode. Referring to Fig. 10B includes a semiconductor structure or device 1000B, e.g., a non-planar version of the device 1000A of Fig. 10A, a non-planar diffusion or active region 1004B (e.g., a fin structure) formed from the substrate 1002 and within the isolation region 1006. The gate line 1008B is disposed over the non-planar diffusion or active region 1004B as well as over a portion of the isolation region 1006. As shown, a gate line 1008B includes a gate electrode 1050 and a gate dielectric layer 1052 along with a dielectric cap layer 1054. The gate contact 1014 and an overlying gate contact via 1016 are also visible from this perspective, along with an overlying metal interconnect 1060, all arranged in interlayer dielectric stacks or layers 1070. As also seen from the perspective of Fig. 10B, the gate contact 1014 is disposed over the isolation region 1006, but not over the non-planar diffusion or active region 1004B.

[0075] Referring again to Fig. 10A and Fig. In FIG. 10B, the arrangement of semiconductor structure or device 1000A and 1000B each places the gate contact over isolation regions. Such an arrangement wastes layout space. Placing the gate contact over active regions would either require an extremely tight alignment budget or gate dimensions would have to increase to provide enough space to land the gate contact. Furthermore, historically, contacting the gate via diffusion regions has been avoided due to the risk of drilling through another gate material (e.g., polysilicon) and contacting the underlying active region. One or more embodiments described herein address the problems described above by providing feasible approaches and resulting structures for fabricating contact structures that contact portions of a gate electrode formed over a diffusion or active region.

[0076] As an example, Fig. 11A illustrates a top view of a semiconductor device having a gate contact via disposed over an active portion of a gate electrode, according to an embodiment of the present disclosure. Referring to Fig. 11A, a semiconductor structure or device 1100A includes a diffusion or active region 1104 disposed in a substrate 1102 and within an isolation region 1106. One or more gate lines, such as gate lines 1108A, 1108B, and 1108C, are disposed over the diffusion or active region 1104 as well as over a portion of the isolation region 1106. Source or drain trench contacts, such as trench contacts 1110A and 1110B, are disposed over source and drain regions of the semiconductor structure or device 1100A. Trench contact vias 1112A and 1112B each make contact with trench contacts 1110A and / or 1110B. A gate contact via 1116 without an intervening separate gate contact layer provides contact to the gate line 1108B. In contrast to Fig. 10A, from a top view perspective, the gate contact 1116 is disposed above the diffusion or active region 1104 and between the source or drain contacts 1110A and 1110B.

[0077] Fig. 11B illustrates a cross-sectional view of a non-planar semiconductor device having a gate contact via disposed over an active portion of a gate electrode, according to an embodiment of the present disclosure. Referring to Fig. 11B includes a semiconductor structure or device 1100B, e.g., a non-planar version of the device 1100A of Fig. 11A, a non-planar diffusion or active region 1104B (e.g., a fin structure) formed from the substrate 1102 and within the isolation region 1106. The gate line 1108B is disposed over the non-planar diffusion or active region 1104B as well as over a portion of the isolation region 1106. As shown, a gate line 1108B includes a gate electrode 1150 and a gate dielectric layer 1152 along with a dielectric cap layer 1154. The gate contact via 1116 is also visible from this perspective, along with an overlying metal interconnect 1160, both arranged in interlayer dielectric stacks or layers 1170. As also seen from the perspective of Fig. 11B, the gate contact via 1116 is disposed over the non-planar diffusion or active region 1104B.

[0078] Thus, with reference again to Fig. 11A and Fig. 11B, in one embodiment, trench contact vias 1112A, 1112B and a gate contact via 1116 are formed in the same layer and are substantially coplanar. Compared to Fig. 10A and Fig. 10B, the contact to the gate line would otherwise comprise an additional gate contact layer, which could, for example, run perpendicular to the corresponding gate line. In the structure(s) associated with the Fig. 11A and Fig. 11B, the fabrication of structures 1100A and / or 1100B enables the landing of a contact directly from a metal interconnect layer onto an active gate portion without shorting to adjacent source and drain regions. In one embodiment, such an arrangement provides a large reduction in area in circuit layout by eliminating the need to extend transistor gates in isolation to make reliable contact. As used throughout, in one embodiment, reference to an active portion of a gate refers to the portion of a gate line or structure disposed over (from a top-down perspective) an active or diffusion region of an underlying substrate.In one embodiment, reference to an inactive portion of a gate refers to the portion of a gate line or structure that is disposed above (from a top view perspective) an isolation region of an underlying substrate.

[0079] In one embodiment, the semiconductor structure or device 1100 is a non-planar device, such as, but not limited to, a Fin-FET or a Trigate device. In such an embodiment, a corresponding semiconductor channel region comprises or is formed within a three-dimensional body. In such an embodiment, the gate electrode stacks of the gate lines 1108A and 1108B surround at least a top surface and a pair of sidewalls of the three-dimensional body. In another embodiment, at least the channel region is fabricated as a discrete three-dimensional body, such as in a gate-all-around device. In such an embodiment, the gate electrode stacks of the gate lines 1108A and 1108B each completely surround the channel region.

[0080] More generally, one or more embodiments are directed to approaches for and structures formed by landing a gate contact via directly on an active transistor gate. Such approaches may eliminate the need for extending a gate line onto insulation for contact purposes. Such approaches may also eliminate the need for a separate gate contact layer (GCN) for conducting signals from a gate line or structure. In one embodiment, eliminating the above features is achieved by recessing contact metals in a trench contact (TCN) and introducing an additional dielectric material into the process flow (e.g., trench insulating layer (TILA)).The additional dielectric material is included as a trench contact dielectric capping layer with etch characteristics that differ from the gate material capping dielectric layer used for trench contact alignment in a gate-aligned contact process (GAP) processing scheme (e.g., GILA) (e.g., using a gate insulating layer (GILA)).

[0081] As an exemplary manufacturing scheme, a starting structure comprises one or more gate stack structures disposed above a substrate. The gate stack structures may include a gate dielectric layer and a gate electrode. Trench contacts, e.g., contacts to diffusion regions of the substrate or to epitaxial regions formed within the substrate, are spaced from gate stack structures by dielectric spacers. An insulating cap layer may be disposed on the gate stack structures (e.g., GILA). In one embodiment, contact blocking regions or "contact plugs," possibly made of an interlayer dielectric material, are included in regions where contact formation is to be blocked.

[0082] In one embodiment, the contact structure is substantially perfectly aligned with an existing gate structure while omitting the use of a lithographic operation with an overly tight registration budget. In such an embodiment, this approach enables the use of intrinsically highly selective wet etching (or anisotropic dry etching processes, some of which are non-plasma, gas-phase isotropic etching processes (e.g., in contrast to classical dry or plasma etching)) to create contact openings. In one embodiment, a contact structure is formed by using an existing gate structure in combination with a contact plug lithography operation. In such an embodiment, the approach enables the elimination of the need for an otherwise critical lithography operation to create a contact structure, as used in other approaches.This also enables perfect or near-perfect self-alignment with a larger edge placement error margin. In one embodiment, a trench contact grid is not patterned separately, but rather formed between poly (gate) lines. For example, in such an embodiment, a trench contact grid is formed after gate grid patterning but before gate grid dicing.

[0083] Furthermore, the gate stack structures can be fabricated using a gate replacement process. In such a scheme, a dummy gate material, such as polysilicon or silicon nitride pillar material, can be removed and replaced with permanent gate electrode material. In such an embodiment, a permanent gate dielectric layer is also formed during this process and is not carried through from prior processing. In one embodiment, dummy gates are removed using a dry etch or wet etch process. In one embodiment, dummy gates are made of polycrystalline silicon or amorphous silicon and are removed using a dry etch process including SF6. In another embodiment, dummy gates are made of polycrystalline silicon or amorphous silicon and are removed using a wet etch process including aqueous NH4OH or tetramethylammonium hydroxide.In one embodiment, dummy gates comprise silicon nitride and are removed with a wet etch comprising aqueous phosphoric acid. In one embodiment, one or more of the approaches described herein essentially contemplate a dummy and replacement gate process in combination with a dummy and replacement contact process. In such an embodiment, the contact replacement process is performed after the gate replacement process to allow a high temperature anneal of at least a portion of the permanent gate stack. For example, in such a specific embodiment, annealing of at least a portion of the permanent gate structures, e.g., after a gate dielectric layer is formed, is performed at a temperature higher than approximately 600 degrees Celsius. The annealing is performed prior to formation of the permanent contacts.

[0084] Next, the trench contacts may be recessed to provide recessed trench contacts having a height below the top surface of the adjacent spacers. An insulating cap layer is then formed on the recessed trench contacts (e.g., TILA). According to one embodiment of the present disclosure, the insulating cap layer on the recessed trench contacts is composed of a material that has different etch characteristics than the insulating cap layer on the gate stack structures.

[0085] The trench contacts may be recessed by a process that is selective for the materials of the spacers and the gate insulating cap layer. For example, in one embodiment, the trench contacts are recessed by an etching process, such as a wet etching process or a dry etching process. The trench contact insulating cap layer may be formed by a process suitable for providing a conformal and sealing layer over the exposed portions of the trench contacts. For example, in one embodiment, the trench contact insulating cap layer is formed by a chemical vapor deposition (CVD) process as a conformal layer over the entire structure. The conformal layer is then planarized, e.g.by chemical mechanical polishing (CMP) to provide the trench contact insulating cap layer material only above the recessed trench contacts.

[0086] Regarding suitable material combinations for gate or trench contact insulating cap layers, in one embodiment, one of the pair of gate versus trench contact insulating cap layers is composed of silicon oxide, while the other is composed of silicon nitride. In another embodiment, one of the pair of gate versus trench contact insulating cap materials is composed of silicon oxide, while the other is composed of carbon-doped silicon nitride. In another embodiment, one of the pair of gate versus trench contact insulating cap materials is composed of silicon oxide, while the other is composed of silicon carbide. In another embodiment, one of the pair of gate versus trench contact insulating cap materials is composed of silicon nitride, while the other is composed of carbon-doped silicon nitride.In another embodiment, one of the pair of gate-versus-trench contact insulation capping materials is composed of silicon nitride, while the other is composed of silicon carbide. In another embodiment, one of the pair of gate-versus-trench contact insulation capping materials is composed of carbon-doped silicon nitride, while the other is composed of silicon carbide.

[0087] Another aspect is backside source or drain contact selectivity with colored hard masks implemented with nanowire or nanoribbon structures. For example, the nanowire or nanoribbon release processing may be performed through a gate exchange trench. Examples of such release processes are described below. Additionally, in yet another aspect, backend (BE) interconnect scaling may result in lower performance and higher manufacturing costs due to patterning complexity. The embodiments described herein may be implemented to enable frontside and backside interconnect integration for nanowire transistors. Embodiments described herein may provide an approach to achieving a relatively wider interconnect pitch. The result may be improved product performance and lower patterning costs.Embodiments can be implemented to enable robust functionality of scaled low-power and high-performance nanowire or nanoribbon transistors.

[0088] One or more embodiments described herein are directional dual epitaxial (EPI) interconnects for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depth. In one embodiment, an integrated circuit structure is fabricated by forming source-drain openings of nanowire / nanoribbon transistors partially filled with SD epitaxy. A remainder of the opening is filled with a conductive material. Deep trenching on one of the source or drain sides enables direct contact to a backside interconnect level.

[0089] In an exemplary process flow for manufacturing another gate all-around component, Fig. 12A-12J are cross-sectional views representing various operations in a method of manufacturing a gate-all-around integrated circuit structure, according to an embodiment of the present disclosure.

[0090] Referring to Fig. 12A, a method of fabricating an integrated circuit structure includes forming a starting stack comprising alternating sacrificial layers 1204 and nanowires 1206 over a fin 1202, such as a silicon fin. The nanowires 1206 may be referred to as a vertical array of nanowires. A protective cap 1208 may be formed over the alternating sacrificial layers 1204 and nanowires 1206, as shown. A relaxed buffer layer 1252 and a defect modification layer 1250 may be formed beneath the alternating sacrificial layers 1204 and nanowires 1206, as also shown.

[0091] Referring to Fig. 12B, a gate stack 1210 is formed over the vertical array of horizontal nanowires 1206. Portions of the vertical array of horizontal nanowires 1206 are then exposed by removing portions of the sacrificial layers 1204 to provide recessed silicon layers 1204' and cavities 1212, as shown in Fig. 12C is shown.

[0092] It is noted that the structure of Fig. 12C can be fabricated without first performing the deep etch and asymmetric contact processing described below. In either case (e.g., with or without asymmetric contact processing), a fabrication process in one embodiment includes using a process scheme that provides a gate-all-around integrated circuit structure with epitaxial bumps that may be vertically discrete source or drain structures.

[0093] Referring to Fig. 12D, the upper gate spacers 1214 are formed on sidewalls of the gate structure 1210. Cavity spacers 1216 are formed in the cavities 1212 below the upper gate spacers 1214. A deep trench contact etch is then optionally performed to form the trenches 1218 and to form recessed nanowires 1206'. A patterned relaxed buffer layer 1252' and a patterned defect modification layer 1250' may also be present, as shown.

[0094] A sacrificial material 1220 is then formed in the trenches 1218, as in Fig. 12E. In other process schemes, an isolated trench bottom or a silicon trench bottom may be used.

[0095] Referring to Fig. 12F, a first epitaxial source or drain structure (e.g., left-side features 1222) is formed at a first end of the vertical array of horizontal nanowires 1206'. A second epitaxial source or drain structure (e.g., right-side features 1222) is formed at a second end of the vertical array of horizontal nanowires 1206'. In one embodiment, as shown, the epitaxial source or drain structures 1222 are vertically discrete source or drain structures and may be referred to as epitaxial bumps.

[0096] An inter-layer dielectric (ILD) material 1224 is then formed on the sides of the gate electrode 1210 and adjacent to the source or drain structures 1222, as shown in Fig. 12G. With reference to Fig. 12H, a gate replacement process is used to form a permanent gate dielectric 1228 and a permanent gate electrode 1226. The ILD material 1224 is then removed, as in Fig. 12I. The sacrificial material 1220 is then removed from one of the source-drain locations (e.g., right side) to form a trench 1232, but is not removed from the other of the source-drain locations to form a trench 1230.

[0097] Referring to Fig. 12J, a first conductive contact structure 1234 is formed that is coupled to the first epitaxial source or drain structure (e.g., left-side features 1222). A second conductive contact structure 1236 is formed that is coupled to the second epitaxial source or drain structure (e.g., right-side features 1222). The second conductive contact structure 1236 is formed deeper along the fin 1202 than the first conductive contact structure 1234. In one embodiment, although not shown in Fig. 12J, the method further comprises forming an exposed surface of the second conductive contact structure 1236 at a bottom of the fin 1202. Conductive contacts may include a contact resistance reducing layer and a primary contact electrode layer, where examples may include Ti, Ni, Co (for the former and for the latter W, Ru, Co).

[0098] In one embodiment, the second conductive contact structure 1236 is deeper along the fin 1202 than the first conductive contact structure 1234, as shown. In one such embodiment, the first conductive contact structure 1234 is not along the fin 1202, as shown. In another such embodiment, not shown, the first conductive contact structure 1234 is partially along the fin 1202.

[0099] In one embodiment, the second conductive contact structure 1236 is along an entirety of the fin 1202. In one embodiment, although not shown, in case the bottom of the fin 1202 is exposed by a backside substrate removal process, the second conductive contact structure 1236 has an exposed surface at a bottom of the fin 1202.

[0100] In another aspect, to enable access to both conductive contact structures of a pair of asymmetric source and drain contact structures, the integrated circuit structures described herein may be fabricated using a backside exposure-frontside fabrication approach. In some example embodiments, exposing the backside of a transistor or other device structure comprises wafer-level backside processing. In contrast to conventional TSV-type technology, exposing the backside of a transistor as described herein may be performed at the density of device cells and even within subregions of a device.Furthermore, such backside exposure of a transistor can be performed to essentially remove an entire donor substrate on which a device layer was deposited during frontside device processing. Therefore, a micrometer-deep TSV becomes unnecessary, as the thickness of the semiconductor in the device cells after backside exposure of a transistor is potentially only several tens or hundreds of nanometers.

[0101] The exposure techniques described herein can enable a paradigm shift from bottom-up device fabrication to center-out fabrication, where the center is any layer inserted during front-side fabrication, exposed from the back, and reinserted during backside fabrication. Processing both a front side and an exposed back side of a device structure can overcome many of the challenges associated with 3D IC fabrication when relying primarily on front-side processing.

[0102] For example, one approach to exposing the backside of a transistor can be used to remove at least a portion of a support layer and an interlayer of a donor-host substrate assembly. The process flow begins with an input of a donor-host substrate assembly. A thickness of a support layer in the donor-host substrate is polished (e.g., CMP) and / or etched using a wet or dry etching process (e.g., plasma). Any grinding, polishing, and / or wet / dry etching process known to be suitable for the composition of the support layer can be used. For example, if the support layer is a Group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning the semiconductor can be used. Likewise, any wet etchant or plasma etching process known to be suitable for thinning the Group IV semiconductor can be used.

[0103] In some embodiments, the foregoing is preceded by cleaving the support layer along a fracture plane that is substantially parallel to the intermediate layer. The cleaving or fracture process can be used to remove a substantial portion of the support layer as a bulk mass, thereby reducing the polishing or etching time required to remove the support layer. For example, where a support layer has a thickness of 400-900 µm, 100-700 µm can be cleaved away by performing any cap layer implant known to promote wafer-level fracture. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted to a uniform target depth within the support layer where the fracture plane is desired.After such a cleaving process, the thickness of the carrier layer remaining in the donor-host substrate assembly can then be polished or etched until completely removed. Alternatively, where the carrier layer is not fractured, grinding, polishing, and / or etching can be used to remove a greater thickness of the carrier layer.

[0104] Next, the exposure of an interlayer is detected. The detection is used to identify a point at which the backside surface of the donor substrate has penetrated almost to the device layer. Any endpoint detection technique known to be suitable for detecting a transition between the materials used for the support layer and the interlayer can be performed. In some embodiments, one or more endpoint criteria are based on detecting a change in the optical absorbance or emission of the backside surface of the donor substrate during the polishing or etching being performed. In some other embodiments, the endpoint criteria are associated with a change in the optical absorbance or emission of byproducts during the polishing or etching of the donor substrate backside surface.For example, the absorption or emission wavelengths associated with the carrier layer etch byproducts may change depending on the different compositions of the carrier layer and the interlayer. In other embodiments, the endpoint criteria are associated with a change in the mass of the species in byproducts of polishing or etching the backside surface of the donor substrate. For example, the processing byproducts may be sampled by a quadrupole mass analyzer, and a change in the species mass may be correlated with the different compositions of the carrier layer and the interlayer. In another exemplary embodiment, the endpoint criteria are associated with a change in friction between a backside surface of the donor substrate and a polishing surface in contact with the backside surface of the donor substrate.

[0105] Interlayer detection can be improved if the removal process is selective relative to the carrier layer, since inhomogeneity in the carrier removal process can be mitigated by an etch rate delta between the carrier layer and the interlayer. Detection can even be skipped if the grinding, polishing, and / or etching operation removes the interlayer at a rate sufficiently below the rate at which the carrier layer is removed. If no endpoint criteria are employed, a grinding, polishing, and / or etching operation of a predetermined fixed duration on the interlayer material can stop when the interlayer thickness is sufficient for etch selectivity. In some examples, the carrier etch rate:interlayer etch rate is 3:1-10:1 or more.

[0106] After exposing the interlayer, at least a portion of the interlayer may be removed. For example, one or more component layers of the interlayer may be removed. A thickness of the interlayer may be uniformly removed, for example, by polishing. Alternatively, a thickness of the interlayer may be removed using a masked or cap layer etch process. The process may employ the same polishing or etching process as that used to thin the carrier, or it may be a standalone process with distinct process parameters. For example, if the interlayer provides an etch stop for the carrier removal process, the latter operation may employ a different polishing or etching process that favors the removal of the interlayer over the removal of the device layer.Where less than a few hundred nanometers of interlayer thickness are to be removed, the removal process can be relatively slow, optimized for uniformity across the wafer, and more precisely controlled than that used for carrier layer removal. For example, a CMP process employed may employ a slurry that provides very high selectivity (e.g., 100:1–300:1 or more) between the semiconductor (e.g., silicon) and the dielectric material (e.g., SiO) surrounding the device layer and embedded in the interlayer, for example, as electrical insulation between adjacent device regions.

[0107] In embodiments where the device layer is exposed by completely removing the interlayer, backside processing may begin on an exposed backside of the device layer or specific device regions therein. In some embodiments, backside device layer processing includes further polishing or wet / dry etching through a thickness of the device layer located between the interlayer and a device region previously formed in the device layer, such as a source or drain region.

[0108] In some embodiments where the carrier layer, interlayer, or device layer backside is recessed with a wet and / or plasma etch, such etching may be a patterned etch or a material-selective etch that imparts significant non-planarity or topography into the device layer backside surface. As described further below, the patterning may be within a device cell (i.e., "intracellular" patterning) or across device cells (i.e., "intercellular" patterning). In some patterned etch embodiments, at least a partial thickness of the interlayer is used as a hard mask for the backside device layer patterning. Thus, a masked etch process may initiate a correspondingly masked device layer etch.

[0109] The processing scheme described above can result in a donor-host substrate assembly comprising IC devices having a backside of an interlayer, a backside of the device layer, and / or a backside of one or more semiconductor regions within the device layer, and / or exposed frontside metallization. Additional backside processing of any of these exposed regions can then be performed during downstream processing.

[0110] As described throughout the present application, a substrate may be comprised of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In one embodiment, a substrate described herein is a bulk substrate comprising a crystalline silicon, silicon / germanium, or germanium layer doped with a charge carrier, such as, but not limited to, phosphorus, arsenic, boron, or a combination thereof, to form an active region. In one embodiment, the concentration of silicon atoms in such a bulk substrate is greater than 97%. In another embodiment, a bulk substrate comprises an epitaxial layer grown on a single crystalline substrate, e.g., an epitaxial silicon layer grown on a boron-doped monocrystalline bulk silicon substrate. A bulk substrate may alternatively comprise a Group III-V material.In one embodiment, a bulk substrate comprises a Group III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, a bulk substrate is composed of a Group III-V material, and the charge carrier dopant impurity atoms are those such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0111] As described throughout the present application, isolation regions, such as shallow trench isolation regions or partial fin isolation regions, may be composed of a material suitable for ultimately electrically isolating or contributing to the isolation of portions of a permanent gate structure from an underlying bulk substrate or for isolating active regions formed within an underlying bulk substrate, such as isolating fin active regions. For example, in one embodiment, an isolation region comprises one or more layers of a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, carbon-doped silicon nitride, or a combination thereof.

[0112] As described throughout the present application, gate lines or gate structures may be composed of a gate electrode stack comprising a gate dielectric layer and a gate electrode layer. In one embodiment, the gate electrode of the gate electrode stack comprises a metal gate, and the gate dielectric layer comprises a high-k material. For example, in one embodiment, the gate dielectric layer comprises a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of the gate dielectric layer may comprise a layer of native oxide formed from the top few layers of a semiconductor substrate.In one embodiment, the gate dielectric layer comprises an upper high-k portion and a lower portion comprising an oxide of a semiconductor material. In one embodiment, the gate dielectric layer comprises an upper portion of hafnium oxide and a lower portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a "U"-shaped structure comprising a lower portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the upper surface of the substrate.

[0113] In one embodiment, a gate electrode comprises a metal layer, such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or conductive metal oxides. In a specific embodiment, the gate electrode comprises a non-work-function setting fill material formed over a metal work-function setting layer. The gate electrode layer may be composed of a P-type work-function metal or an N-type work-function metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may be composed of a stack of two or more metal layers, where one or more metal layers are work-function metal layers and at least one metal layer is a conductive fill layer.For a PMOS transistor, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. A P-type metal layer enables the formation of a PMOS gate electrode with a work function between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer enables the formation of an NMOS gate electrode with a work function between about 3.9 eV and about 4.2 eV.In some implementations, the gate electrode may have a "U"-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and may not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers.

[0114] As described throughout the present application, spacers associated with gate lines or electrode stacks may comprise a material suitable for ultimately electrically isolating, or contributing to the isolation of, a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers comprise a dielectric material, such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0115] In one embodiment, as used throughout this specification, an interlayer dielectric (ILD) material comprises or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon-doped oxides of silicon, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material may be formed using techniques such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition methods.

[0116] In one embodiment, as used throughout this specification, metal lines or interconnect material (and via material) are composed of one or more metals or other conductive structures. A common example is the use of copper lines and structures, which may or may not include barrier layers between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers (e.g., layers comprising one or more of Ta, TaN, Ti, or TiN), stacks of different metals or alloys, etc. Thus, the interconnect lines may be a single material layer or may be formed from multiple layers including conductive liner layers and fill layers.Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, can be used to form interconnect lines. In one embodiment, the interconnect lines comprise a conductive material, such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof. The interconnect lines are sometimes referred to in the art as traces, wires, lines, metal, or simply interconnect.

[0117] In one embodiment, as used throughout this description, hardmask materials include dielectric materials that are different from the interlayer dielectric material. In one embodiment, different hardmask materials may be used in different regions to provide different growth or etch selectivity to each other or to the underlying dielectric and metal layers. In some embodiments, a hardmask layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, a hardmask material includes a metal species.For example, a hard mask or other overlying material may include a layer of a nitride of titanium or another metal (e.g., titanium nitride). Potentially minor amounts of other materials, such as oxygen, may be included in one or more of these layers. Alternatively, other hard mask layers known in the art may be used, depending on the particular implementation. The hard mask layers may be formed by CVD, PVD, or other deposition methods.

[0118] In one embodiment, as used throughout this specification, lithographic operations are performed using 193 nm immersion lithography (i193), extreme ultraviolet (EUV) lithography, or electron beam direct write (EBDW) lithography, or the like. A positive-tone or negative-tone resist may be used. In one embodiment, a lithographic mask is a three-layer mask including a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In one particular such embodiment, the topographic masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0119] In one embodiment, approaches described herein may include forming a contact structure that is substantially highly aligned with an existing gate structure while eliminating the use of a lithographic operation with an excessively tight alignment budget. In one embodiment, this approach enables the use of an intrinsically highly selective wet etch (e.g., versus dry or plasma etching) to create contact openings. In one embodiment, a contact structure is formed by using an existing gate structure in combination with a contact plug lithography operation. In one embodiment, the approach enables the elimination of the need for an otherwise critical lithography operation to create a contact structure, as used in other approaches.In one embodiment, a trench contact grid is not patterned separately, but rather formed between poly (gate) lines. For example, in such an embodiment, a trench contact grid is formed after gate grid patterning but before gate grid dicing.

[0120] Furthermore, a gate stack structure may be fabricated using a gate replacement process. In such a scheme, a dummy gate material, such as polysilicon or silicon nitride pillar material, may be removed and replaced with permanent gate electrode material. In such an embodiment, a permanent gate dielectric layer is also formed during this process and is not carried through from prior processing. In one embodiment, dummy gates are removed using a dry etch or wet etch process. In one embodiment, dummy gates comprise polycrystalline silicon or amorphous silicon and are removed using a dry etch process involving the use of SF6. In another embodiment, dummy gates are made of polycrystalline silicon or amorphous silicon and are removed using a wet etch process involving the use of aqueous NH4OH or tetramethylammonium hydroxide.In one embodiment, dummy gates comprise silicon nitride and are removed with a wet etch comprising aqueous phosphoric acid.

[0121] In one embodiment, one or more of the approaches described herein essentially contemplate a dummy and replacement gate process in combination with a dummy and replacement contact process to obtain a structure. In such an embodiment, the contact replacement process is performed after the gate replacement process to allow for high temperature annealing of at least a portion of the permanent gate stack. For example, in such a specific embodiment, annealing of at least a portion of the permanent gate structures, e.g., after a gate dielectric layer is formed, is performed at a temperature higher than approximately 600 degrees Celsius. The annealing is performed prior to formation of the permanent contacts.

[0122] In some embodiments, the arrangement of a semiconductor structure or device places a gate contact over portions of a gate line or gate stack over isolation regions. However, such an arrangement may be considered an inefficient use of layout space. In another embodiment, a semiconductor device includes contact structures that contact portions of a gate electrode formed over an active region. Generally, prior to (e.g., in addition to) forming a gate contact structure (such as a via) over an active portion of a gate and in the same layer as a trench contact via, one or more embodiments of the present disclosure first include using a gate-aligned trench contact process. Such a process may be implemented to form trench contact structures for semiconductor structure fabrication, e.g.,for manufacturing integrated circuits. In one embodiment, a trench contact structure is formed in alignment with an existing gate structure. In contrast, other approaches typically involve an additional lithography process with close registration of a lithographic contact structure with an existing gate structure in combination with selective contact etching. For example, another process may involve patterning a poly (gate) grid with separate patterning of contact features.

[0123] It should be noted that pitch-splitting processing and patterning schemes may be implemented to enable embodiments described herein or may be included as part of embodiments described herein. Pitch-splitting patterning typically refers to pitch halving, pitch quartering, etc. Pitch-splitting schemes may be applicable to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. According to one or more embodiments described herein, optical lithography is first implemented to print unidirectional lines (e.g., either strictly unidirectional or predominantly unidirectional) at a predefined pitch. Pitch-splitting processing is then implemented as a technique for increasing line density.

[0124] In one embodiment, the term "grid structure" for fins, gate lines, metal lines, ILD lines, or hard mask lines is used herein to refer to a narrow-pitch grating structure. In such an embodiment, the narrow pitch is not directly achievable by a selected lithography. For example, a structure may first be formed based on a selected lithography, but the pitch may be halved by using spacer mask patterning, as is known in the art. Further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, grating-like structures described herein may include metal lines, ILD lines, or hard mask lines spaced at a substantially consistent pitch and having a substantially consistent width.For example, in some embodiments, the pitch variation would be within ten percent and the width variation would be within ten percent, and in some embodiments, the pitch variation would be within five percent and the width variation would be within five percent. The structure can be fabricated using a pitch halving, quartering, or other pitch division approach. In one embodiment, the grating is not necessarily at a single pitch.

[0125] In one embodiment, the capping film is patterned using lithography and etch processing, which may include, for example, spacer-based double patterning (SBDP) or pitch halving, or spacer-based quadruple patterning (SBQP) or pitch quartering. It should be noted that other pitch pitch approaches may also be implemented. In any case, in one embodiment, a grid-like layout may be fabricated using a selected lithography approach, such as 193nm immersion lithography (193i). Pitch pitch may be implemented to increase the density of lines in the grid-like layout by a factor of n. Forming the grid-like layout with 193i lithography plus pitch pitch by a factor of 'n' may be referred to as 193i + P / n pitch pitch.In such an embodiment, the 193nm immersion scaling can be extended for many generations with cost-effective pitch division.

[0126] It should be noted that not all aspects of the processes described above need to be practiced to fall within the spirit and scope of the embodiments of the present disclosure. For example, in one embodiment, dummy gates need not always be formed over active portions of the gate stacks prior to forming the gate contacts. The gate stacks described above may actually be permanent gate stacks as initially formed. Also, the processes described herein may be used to fabricate one or a plurality of semiconductor devices. The semiconductor devices may be transistors or similar devices. For example, in one embodiment, the semiconductor devices are metal-oxide-semiconductor (MOS) transistors for logic or memory, or are bipolar transistors.Also in one embodiment, the semiconductor devices comprise a three-dimensional architecture, such as a trigate device, an independently accessed dual-gate device, a FIN-FET, a nanowire, or a nanoribbon. One or more embodiments may be particularly useful for fabricating semiconductor devices at a 10-nanometer (10 nm) or sub-10-nanometer (10 nm) technology node.

[0127] Additional or intermediate operations for FEOL layer or structure fabrication may include standard microelectronic manufacturing processes, such as lithography, etching, thin-film deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, the use of sacrificial layers, the use of etch stop layers, the use of planarization stop layers, or any other action associated with microelectronic component fabrication. It is further noted that the process operations described for the preceding process flows may be performed in alternative sequences, and not every operation needs to be performed, or additional process operations may be performed, or both.

[0128] Embodiments disclosed herein may be used to fabricate a wide variety of different types of integrated circuits or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, a semiconductor memory may be fabricated. Furthermore, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the art. For example, in computer systems (e.g., desktop, laptop, server), mobile phones, personal electronics, etc. The integrated circuits may be coupled to a bus and other components in the systems. For example, a processor may be connected by one or more buses to a memory, a chipset, etc.Each of the processor, memory, and chipset can potentially be manufactured using the approaches disclosed herein.

[0129] Fig. 13 illustrates a computing device 1300 according to one implementation of the disclosure. Computing device 1300 houses a circuit board 1302. Circuit board 1302 may include a number of components, including, but not limited to, a processor 1304 and at least one communication chip 1306. Processor 1304 is physically and electrically coupled to circuit board 1302. In some implementations, at least one communication chip 1306 is further physically and electrically coupled to circuit board 1302. In other implementations, communication chip 1306 is part of processor 1304.

[0130] Depending on its applications, computing device 1300 may include other components that may or may not be physically and electrically coupled to circuit board 1302. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a GPS (global positioning system) component, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard disk drive, CD (compact disk), DVD (digital versatile disk), etc.).

[0131] The communication chip 1306 enables wireless communication for transferring data to and from the computing device 1300. The term "wireless" and its derivatives can be used to describe circuits, devices / apparatus, systems, methods, techniques, communication channels, etc., that can communicate data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not include any wires, although they may not in some embodiments. The communication chip 1306 can implement any number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols referred to as 3G, 4G, 5G, and beyond. Computing device 1300 may include a plurality of communication chips 1306. For example, a first communication chip 1306 may be dedicated for shorter-range wireless communication, such as Wi-Fi and Bluetooth, and a second communication chip 1306 may be dedicated for longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0132] The processor 1304 of the computing device 1300 includes an integrated circuit die packaged within the processor 1304. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor includes one or more structures, such as integrated circuit structures constructed according to implementations of the disclosure. The term "processor" may refer to any device or portion of a device, or both, that processes electronic data from registers or memory to transform that electronic data into other electronic data that may be stored in registers or memory, or both.

[0133] The communication chip 1306 also includes an integrated circuit die packaged within the communication chip 1306. According to another implementation of the disclosure, the integrated circuit die of the communication chip is constructed according to implementations of the disclosure.

[0134] In further implementations, another component packaged within the computing device 1300 may include an integrated circuit die incorporated in accordance with implementations of embodiments of the disclosure.

[0135] In various embodiments, computing device 1300 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a PDA (personal digital assistant), an ultramobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 1300 may be any other electronic device that processes data.

[0136] Fig. 14 illustrates an interposer 1400 incorporating one or more embodiments of the disclosure. The interposer 1400 is an intermediate substrate used to bridge a first substrate 1402 to a second substrate 1404. The first substrate 1402 may be, for example, an integrated circuit die. The second substrate 1404 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 1400 is to propagate an interconnect a further distance or to reroute an interconnect to a different interconnect. For example, an interposer 1400 may couple an integrated circuit die to a ball grid array (BGA) 1406, which may subsequently be coupled to the second substrate 1404.In some embodiments, the first and second substrates 1402 / 1404 are mounted on opposite sides of the interposer 1400. In other embodiments, the first and second substrates 1402 / 1404 are mounted on the same side of the interposer 1400. And in further embodiments, three or more substrates are connected using the interposer 1400.

[0137] The interposer 1400 may be formed from an epoxy resin, a glass-fiber-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 1400 may be formed from various rigid or flexible materials, which may include the same materials previously described for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials.

[0138] The interposer 1400 may include metal interconnects 1408 and vias 1410, including but not limited to through-silicon vias (TSVs) 1412. The interposer 1400 may further include embedded components 1414, including both passive and active components. Such components include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and ESD (electrostatic discharge) components. More complex components, such as radio frequency (RF) components, power amplifiers, power management components, antennas, arrays, sensors, and MEMS components, may also be formed on the interposer 1400.According to embodiments of the disclosure, devices or processes disclosed herein may be used in the manufacture of the interposer 1400 or in the manufacture of components included in the interposer 1400.

[0139] Fig. 15 is an isometric view of a mobile computing platform 1500 employing an integrated circuit (IC) manufactured according to one or more of the processes described herein or including one or more of the features described herein, according to an embodiment of the present disclosure.

[0140] The mobile computing platform 1500 may be any portable device configured for any of electronic data display, electronic data processing, and wireless electronic data transmission. For example, the mobile computing platform 1500 may be any of a tablet, a smartphone, a laptop computer, etc., and includes a display screen 1505, where the exemplary embodiment is a touchscreen (capacitive, inductive, resistive, etc.), an integrated system 1510 at the chip level (SoC) or package level, and a battery 1513. As illustrated, the greater the level of integration in the system 1510, enabled by the higher transistor packing density, the larger the portion of the mobile computing platform 1500 that may be occupied by the battery 1513 or non-volatile storage, such as a solid-state drive, or the larger the transistor gate count for improved platform functionality.Similarly, the greater the carrier mobility of each transistor in system 1510, the greater the functionality. As such, techniques described herein may enable performance and form factor improvements in mobile computing platform 1500.

[0141] The integrated system 1510 is further illustrated in the exploded view 1520. In the exemplary embodiment, the packaged device 1577 includes at least one memory chip (e.g., RAM) or at least one processor chip (e.g., a multi-core microprocessor and / or graphics processor) manufactured according to one or more of the processes described herein or comprising one or more of the features described herein. The packaged device 1577 is further coupled to the board 1560, along with one or more of a power management integrated circuit (PMIC) 1515, an RF (wireless) integrated circuit (RFIC) 1525 comprising a broadband RF (wireless) transmitter and / or receiver (e.g.,comprising a digital baseband and an analog front-end module, further comprising a power amplifier on a transmit path and a low-noise amplifier on a receive path), and a controller 1511 thereof. Functionally, the PMIC 1515 performs battery regulation, DC-DC conversion, etc., and thus has an input coupled to the battery 1513 and an output that provides power to all other functional modules. As further illustrated, in the exemplary embodiment, the RFIC 1525 includes an output coupled to an antenna to implement or provide any number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, and derivatives thereof, as well as any other wireless protocols referred to as 3G, 4G, 5G, and beyond. In alternative implementations, each of these board-level modules may be integrated onto separate ICs coupled to the package substrate of the packaged device 1577, or within a single IC (SoC) coupled to the package substrate of the packaged device 1577.

[0142] In another aspect, semiconductor packages are used to protect an integrated circuit (IC) chip or die and also to provide the die with an electrical interface to external circuitry. With the increasing demand for smaller electronic components, semiconductor packages are being designed to be even more compact and must support greater circuit density. Furthermore, the demand for higher-performance components is driving a need for an improved semiconductor package that enables a thin packaging profile and low overall warpage compatible with subsequent device processing.

[0143] In one embodiment, wire bonding to a ceramic or organic package substrate is used. In another embodiment, a C4 process is used to attach a die to a ceramic or organic package substrate. More specifically, C4 solder ball connections can be implemented to provide flip-chip connections between semiconductor devices and substrates. A flip-chip or controlled collapse chip connection (C4) is a type of attachment used for semiconductor devices, such as integrated circuit (IC) chips, MEMS, or components, that use solder bumps instead of wire bonding. The solder balls are deposited onto the C4 pads located on the top side of the substrate package. To attach the semiconductor device to the substrate, it is flipped over onto the attachment area with the active side facing down.The solder balls are used to connect the semiconductor device directly to the substrate.

[0144] Fig. 16 illustrates a cross-sectional view of a die attached to a flip chip, according to an embodiment of the present disclosure.

[0145] Referring to Fig.16, a device 1600 includes a die 1602, such as an integrated circuit (IC), fabricated according to one or more of the processes described herein or comprising one or more of the features described herein, according to an embodiment of the present disclosure. The die 1602 includes metallized pads 1604 thereon. A package substrate 1606, such as a ceramic or organic substrate, includes interconnects 1608 thereon. The die 1602 and the package substrate 1606 are electrically connected by solder balls 1610, which are coupled to the metallized pads 1604 and the interconnects 1608. An underfill material 1612 surrounds the solder balls 1610.

[0146] Processing a flip chip can be similar to conventional IC manufacturing, with a few additional operations. Near the end of the manufacturing process, the mounting pads are metallized to make them more receptive to solder. This typically consists of several treatments. A small dot of solder is then deposited on each metallized pad. The chips are then cut from the wafer as usual. To mount the flip chip into a circuit, the chip is flipped over to expose the solder pad to the connectors on the underlying electronics or circuit board. The solder is then reflowed to create an electrical connection, usually using an ultrasonic or, alternatively, a reflow soldering process. This also leaves a small space between the chip's circuitry and the underlying mount.In most cases, an electrically insulating adhesive is then “underfilled” to provide a stronger mechanical bond, provide a thermal bridge, and ensure that the solder joints are not stressed by differential heating of the chip and the rest of the system.

[0147] In other embodiments, newer packaging and die-to-die interconnect approaches, such as silicon vias (TSVs) and silicon interposers, are implemented to fabricate high-performance multi-chip modules (MCMs) and systems-in-packages (SiPs) incorporating an integrated circuit (IC) fabricated according to one or more of the processes described herein or comprising one or more of the features described herein, according to an embodiment of the present disclosure.

[0148] Therefore, embodiments of the present disclosure include integrated circuit structures with backside source or drain contact selectivity using colored hard masks.

[0149] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even if only a single embodiment is described with respect to a particular feature. Examples of features provided in the disclosure are intended to be illustrative and not restrictive unless otherwise stated. The above description is intended to cover such alternatives, modifications, and equivalents as would be obvious to one skilled in the art having the benefit of the present disclosure.

[0150] The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly) or any generalization thereof, whether or not alleviating any or all of the problems addressed herein. Accordingly, new claims may be drafted for any such combination of features during the prosecution of the present application (or an application claiming priority hereof). More specifically, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims, and features from corresponding independent claims may be combined in any suitable manner, and not only in the specific combinations enumerated in the appended claims.

[0151] The following examples relate to further embodiments. The various features of the different embodiments can be combined in various ways, including some features and excluding others, to suit a variety of different applications.

[0152] Embodiment 1: An integrated circuit structure comprises a first plurality of horizontally stacked nanowires laterally spaced from a second plurality of horizontally stacked nanowires. A gate stack is disposed above the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires. A first epitaxial source or drain structure is disposed at one end of the first plurality of horizontally stacked nanowires, with a first conductive source or drain contact vertically below and in contact with a bottom of the first epitaxial source or drain structure, and with a first hardmask material below and in contact with the first conductive source or drain contact.A second epitaxial source or drain structure is formed at one end of the second plurality of horizontally stacked nanowires, with a second conductive source or drain contact vertically below and in contact with a bottom of the second epitaxial source or drain structure, and with a second hardmask material below and in contact with the second conductive source or drain contact. The second hardmask material has a composition that differs from a composition of the first hardmask material. The first hardmask material extends laterally beyond the first conductive source or drain contact and is laterally continuous around the second hardmask material.

[0153] Embodiment 2: The integrated circuit structure according to Embodiment 1, wherein the second hard mask material is confined to the second conductive source or drain contact.

[0154] Embodiment 3: The integrated circuit structure according to embodiment 1 or 2, wherein the second hard mask material has a thickness equal to that of the first hard mask material.

[0155] Embodiment 4: The integrated circuit structure according to Embodiment 1, 2 or 3, wherein one of the first hard mask material or the second hard mask material comprises silicon and carbon and the other of the first hard mask material or the second hard mask material comprises silicon and nitrogen.

[0156] Embodiment 5: The integrated circuit structure according to embodiment 1, 2, 3 or 4, wherein the first conductive source or drain contact and the second conductive source or drain contact comprise tungsten.

[0157] Embodiment 6: An integrated circuit structure includes a first fin laterally spaced from a second fin. A gate stack is above the first fin and the second fin. A first epitaxial source or drain structure is at one end of the first fin, with a first conductive source or drain contact vertically below and in contact with a bottom of the first epitaxial source or drain structure, and with a first hard mask material below and in contact with the first conductive source or drain contact. A second epitaxial source or drain structure is at one end of the second fin, with a second conductive source or drain contact vertically below and in contact with a bottom of the second epitaxial source or drain structure, and with a second hard mask material below and in contact with the second conductive source or drain contact.The second hardmask material has a composition that differs from a composition of the first hardmask material. The first hardmask material extends laterally beyond the first conductive source or drain contact and is laterally continuous around the second hardmask material.

[0158] Embodiment 7: The integrated circuit structure according to Embodiment 6, wherein the second hard mask material is confined to the second conductive source or drain contact.

[0159] Embodiment 8: The integrated circuit structure according to embodiment 6 or 7, wherein the second hard mask material has a thickness equal to that of the first hard mask material.

[0160] Embodiment 9: The integrated circuit structure according to Embodiment 6, 7 or 8, wherein one of the first hard mask material or the second hard mask material comprises silicon and carbon and the other of the first hard mask material or the second hard mask material comprises silicon and nitrogen.

[0161] Embodiment 10: The integrated circuit structure according to embodiment 6, 7, 8 or 9, wherein the first conductive source or drain contact and the second conductive source or drain contact comprise tungsten.

[0162] Embodiment 11: A computing device includes a circuit board and a component coupled to the circuit board. The component includes an integrated circuit structure comprising a first plurality of horizontally stacked nanowires or a first fin laterally spaced from a second plurality of horizontally stacked nanowires or a second fin. A gate stack is disposed over the first plurality of horizontally stacked nanowires or the first fin and the second plurality of horizontally stacked nanowires or the second fin.A first epitaxial source or drain structure is provided at one end of the first plurality of horizontally stacked nanowires or the first fin, with a first conductive source or drain contact vertically below and in contact with a bottom of the first epitaxial source or drain structure, and with a first hard mask material below and in contact with the first conductive source or drain contact. A second epitaxial source or drain structure is provided at one end of the second plurality of horizontally stacked nanowires or the second fin, with a second conductive source or drain contact vertically below and in contact with a bottom of the second epitaxial source or drain structure, and with a second hard mask material below and in contact with the second conductive source or drain contact.The second hardmask material has a composition that differs from a composition of the first hardmask material. The first hardmask material extends laterally beyond the first conductive source or drain contact and is laterally continuous around the second hardmask material.

[0163] Embodiment 12: The computing device according to Embodiment 11, comprising the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires.

[0164] Embodiment 13: The computing device according to Embodiment 11, comprising the first fin and the second fin.

[0165] Embodiment 14: The computing device according to embodiment 11, 12 or 13, further comprising a memory coupled to the board.

[0166] Embodiment 15: The computing device according to embodiment 11, 12, 13 or 14, further comprising a communication chip coupled to the circuit board.

[0167] Embodiment 16: The computing device according to embodiment 11, 12, 13, 14 or 15, further comprising a battery coupled to the circuit board.

[0168] Embodiment 17: The computing device according to embodiment 11, 12, 13, 14, 15 or 16, further comprising a camera coupled to the circuit board.

[0169] Embodiment 18: The computing device according to embodiment 11, 12, 13, 14, 15, 16 or 17, further comprising a display coupled to the circuit board.

[0170] Embodiment 19: The computing device of embodiment 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die.

[0171] Embodiment 20: The computing device according to embodiment 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group comprising a processor, a communication chip and a digital signal processor.

Claims

[1] An integrated circuit structure comprising: a first plurality of horizontally stacked nanowires laterally spaced from a second plurality of horizontally stacked nanowires; a gate stack over the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires; a first epitaxial source or drain structure at one end of the first plurality of horizontally stacked nanowires, with a first conductive source or drain contact vertically below and in contact with a bottom of the first epitaxial source or drain structure and with a first hard mask material below and in contact with the first conductive source or drain contact; and a second epitaxial source or drain structure at one end of the second plurality of horizontally stacked nanowires, having a second conductive source or drain contact vertically below and in contact with a bottom of the second epitaxial source or drain structure, and having a second hard mask material below and in contact with the second conductive source or drain contact, the second hard mask material having a composition different from a composition of the first hard mask material, the first hard mask material extending laterally beyond the first conductive source or drain contact and being laterally continuous around the second hard mask material. [2] The integrated circuit structure of claim 1, wherein the second hard mask material is confined to the second conductive source or drain contact. [3] The integrated circuit structure of claim 1 or 2, wherein the second hard mask material has a thickness equal to that of the first hard mask material. [4] The integrated circuit structure of claim 1, 2 or 3, wherein one of the first hard mask material or the second hard mask material comprises silicon and carbon and the other of the first hard mask material or the second hard mask material comprises silicon and nitrogen. [5] The integrated circuit structure of claim 1, 2, 3 or 4, wherein the first conductive source or drain contact and the second conductive source or drain contact comprise tungsten. [6] An integrated circuit structure comprising: a first fin laterally spaced from a second fin; a gate stack above the first fin and the second fin; a first epitaxial source or drain structure at one end of the first fin, with a first conductive source or drain contact vertically below and in contact with a bottom of the first epitaxial source or drain structure and with a first hard mask material below and in contact with the first conductive source or drain contact; and a second epitaxial source or drain structure at one end of the second fin, having a second conductive source or drain contact vertically below and in contact with a bottom of the second epitaxial source or drain structure, and having a second hard mask material below and in contact with the second conductive source or drain contact, the second hard mask material having a composition different from a composition of the first hard mask material, the first hard mask material extending laterally beyond the first conductive source or drain contact and being laterally continuous around the second hard mask material. [7] The integrated circuit structure of claim 6, wherein the second hard mask material is confined to the second conductive source or drain contact. [8] The integrated circuit structure of claim 6 or 7, wherein the second hard mask material has a thickness equal to that of the first hard mask material. [9] The integrated circuit structure of claim 6, 7 or 8, wherein one of the first hard mask material or the second hard mask material comprises silicon and carbon and the other of the first hard mask material or the second hard mask material comprises silicon and nitrogen. [10] The integrated circuit structure of claim 6, 7, 8 or 9, wherein the first conductive source or drain contact and the second conductive source or drain contact comprise tungsten. [11] A computing device comprising: a circuit board; and a component coupled to the board, the component comprising an integrated circuit structure comprising: a first plurality of horizontally stacked nanowires or a first fin laterally spaced from a second plurality of horizontally stacked nanowires or a second fin; a gate stack over the first plurality of horizontally stacked nanowires or the first fin and the second plurality of horizontally stacked nanowires or the second fin; a first epitaxial source or drain structure at one end of the first plurality of horizontally stacked nanowires or the first fin, with a first conductive source or drain contact vertically below and in contact with a bottom of the first epitaxial source or drain structure and with a first hard mask material below and in contact with the first conductive source or drain contact; and a second epitaxial source or drain structure at one end of the second plurality of horizontally stacked nanowires or the second fin, having a second conductive source or drain contact vertically below and in contact with a bottom of the second epitaxial source or drain structure, and having a second hard mask material below and in contact with the second conductive source or drain contact, the second hard mask material having a composition different from a composition of the first hard mask material, the first hard mask material extending laterally beyond the first conductive source or drain contact and being laterally continuous around the second hard mask material. [12] The computing device of claim 11, comprising the first plurality of horizontally stacked nanowires and the second plurality of horizontally stacked nanowires. [13] The computing device according to claim 11, comprising the first fin and the second fin. [14] The computing device according to claim 11, 12 or 13, further comprising: a memory that is coupled to the circuit board. [15] The computing device according to claim 11, 12, 13 or 14, further comprising: a communication chip that is coupled to the circuit board. [16] The computing device according to claim 11, 12, 13, 14 or 15, further comprising: a battery that is coupled to the circuit board. [17] The computing device according to claim 11, 12, 13, 14, 15 or 16, further comprising: a camera that is coupled to the board. [18] The computing device according to claim 11, 12, 13, 14, 15, 16 or 17, further comprising: a display coupled to the circuit board. [19] The computing device of claim 11, 12, 13, 14, 15, 16, 17 or 18, wherein the component is a packaged integrated circuit die. [20] The computing device of claim 11, 12, 13, 14, 15, 16, 17, 18 or 19, wherein the component is selected from the group comprising a processor, a communications chip and a digital signal processor.

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