Source / drain epitaxy profiles and methods for their realization

Abstract

A method comprises fabricating a plurality of semiconductor nanostructures, wherein the upper layers of the plurality of semiconductor nanostructures overlap the respective lower layers of the plurality of semiconductor nanostructures. The method further comprises creating a source / drain cavity laterally of the plurality of semiconductor nanostructures; and fabricating a first semiconductor layer from the plurality of semiconductor nanostructures. The first semiconductor layer has a convex shape in cross-sectional view. A second semiconductor layer is fabricated above the first semiconductor layer. A silicide region is created above and in contact with the second semiconductor layer.

Description

Priority claim and cross-reference

[0001] The present application claims priority over the preliminary US patent application filed on November 22, 2024, with file number 63 / 723.675 and titled “PMOS SOURCE DRAIN EPITAXY FOR DEVICE BOOST ON FFBI NANOSHEET STRUCTURE” (“PMOS source / drain epitaxy for device boost on an FFBI nanosheet structure”), which is incorporated by reference into the present application. background

[0002] Technological advances in IC materials and designs (IC: integrated circuit) have produced generations of ICs, with each generation featuring smaller and more complex circuits than the previous ones. Throughout IC evolution, functional density (i.e., the number of interconnected devices per unit area) has generally increased, while feature sizes have decreased. This miniaturization process generally offers advantages by increasing production efficiency and reducing associated costs.

[0003] This miniaturization has also increased the complexity of IC processing and manufacturing, and similar developments in IC processing and manufacturing are necessary to realize these improvements. For example, gate-all-around transistors (GAA transistors) have been introduced to replace planar transistors. The structures of GAA transistors and the processes for their fabrication are currently being further developed. Brief description of the drawings

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. TheFig. Figures 1 to 4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B and 21 to 23 show representations of intermediate stages in the manufacture of a gate-all-around transistor (GAA transistor) according to some embodiments. The Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19 to Fig. Figure 20 shows representations of intermediate stages in the creation of a source / drain region according to some embodiments. The Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28 to Fig. Figure 29 shows representations of intermediate stages in the generation of a source / drain region according to alternative embodiments. Fig. Figure 30 shows a process flow for manufacturing a GAA transistor according to some embodiments. Detailed description

[0005] The disclosure below provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element above or on top of a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of one element or structural element to one or more other elements or structural elements depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90° or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0007] A GAA transistor and several fabrication methods for it are provided. According to some embodiments, the fabrication of a source / drain region of a GAA transistor involves producing a first epitaxial layer with convex sidewalls and producing a second epitaxial layer over the first epitaxial layer. The first epitaxial layer has a lower doping concentration of a dopant (such as boron) and optionally a lower percentage of germanium atoms than the second epitaxial layer. Accordingly, in the first epitaxial layer with a convex profile, the upper portions of the epitaxial layer are narrower, resulting in more space for the second epitaxial layer. A source / drain silicide region and a higher-lying source / drain contact pin are more likely to make contact on the second epitaxial layer than on the first. This reduces the source / drain resistance.

[0008] Although GAA transistors are used here as an example to discuss the principle of the present disclosure, the embodiments can also be used for other types of transistors, including planar transistors, fin field-effect transistors (FinFETs), complementary field-effect transistors (CFETs), and the like. The embodiments discussed here are intended to provide examples to enable the manufacture or use of the subject matter of the present disclosure, and a person skilled in the art should readily recognize modifications that can be made within the intended scope of protection of different embodiments. In all illustrations and explanatory embodiments, similar reference numerals are used to designate similar elements.While some process implementation forms can be discussed as embodiments that are carried out in a specific order, other process implementation forms can be carried out in any logical order.

[0009] Furthermore, although a p-transistor may be used as an example in some parts of the discussion, the principle of the present application can easily be used for the fabrication of n-transistors, with the conductivity types of the corresponding structural elements being reversed compared to the p-transistor.

[0010] The Fig. Figures 1 to 4, 5A, 5B, 6A, 6B, 7A, 7B, 8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B and 15 to 23 show sectional views of intermediate stages in the fabrication of a GAA transistor according to some embodiments of the present disclosure. The corresponding processes are also schematically indicated in a process flow 200, which is set out in Fig. 30 is shown.

[0011] In Fig. Figure 1 shows a perspective view of a wafer 10. The wafer 10 has a multilayer structure with a multilayer stack 22 on a substrate 20. In some embodiments, the substrate 20 is a semiconductor substrate, which may be a silicon substrate, a silicon-germanium substrate (SiGe substrate), or the like, but other substrates and / or structures could also be used, such as a semiconductor-on-insulator substrate / structure (SOI substrate / structure), a strained SOI substrate / structure, a silicon-germanium-on-insulator substrate / structure, or the like. The substrate 20 can be doped as a p-type semiconductor substrate, but in other embodiments, it can be doped as an n-type semiconductor substrate.

[0012] In some embodiments, the multilayer stack 22 is produced by a series of deposition processes for depositing different materials. The corresponding process is specified as process 202 in the process sequence 200, which is described in Fig. Figure 30 shows that in some embodiments the multilayer stack 22 has first layers 22A made of a first semiconductor material and second layers 22B made of a second semiconductor material different from the first semiconductor material.

[0013] In some embodiments, the first semiconductor material of a first layer 22A is SiGe, Ge, Si, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, or the like. In some embodiments, the first layers 22A (for example, SiGe) are deposited by epitaxial growth, and the corresponding deposition method may be vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), low-pressure gravity phosphorylation (LPCVD), atomic layer deposition (ALD), ultra-high vacuum CVD (UHV-CVD), low-pressure CVD (RPCVD), or the like. In some embodiments, the first layer 22A is produced with a first thickness of about 30 Å to about 300 Å. However, any suitable thickness may be used without deviating from the scope of protection of this disclosure.

[0014] After the first layer 22A has been deposited onto the substrate 20, a second layer 22B is deposited onto the first layer 22A. In some embodiments, the second layers 22B are made of or contain a second semiconductor material, such as Si, SiGe, Ge, GaAs, InSb, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, combinations thereof, or the like, wherein the second semiconductor material is different from the first semiconductor material of the first layer 22A. For example, in some embodiments where the first layer 22A is silicon germanium, the second layer 22B can be made of silicon, or vice versa. It is understood that any suitable combination of materials can be used for the first layers 22A and the second layers 22B.

[0015] In some embodiments, the second layer 22B is grown epitaxially on the first layer 22A using a similar deposition method to that used to produce the first layer 22A. In some embodiments, the second layer 22B is produced with a similar thickness to the first layer 22A. However, the second layer 22B can also be produced with a thickness different from that of the first layer 22A. For example, in some embodiments, the first layer 22A has a thickness of approximately 4 nm to 7 nm, while the second layer 22B has a thickness of approximately 8 nm to 12 nm.

[0016] After the second layer 22B has been deposited over the first layer 22A, the deposition process is repeated to produce the remaining layers of the multilayer stack 22 until the desired top layer of the multilayer stack 22 has been produced. In some embodiments, the first layers 22A have thicknesses that are equal to or similar to each other, and the second layers 22B also have thicknesses that are equal to or similar to each other. The first layers 22A may also have the same thickness as, or different thicknesses from, the second layers 22B. In some embodiments, the first layers 22A are removed in later processes and are therefore alternatively referred to as sacrificial layers 22A throughout this description. In alternative embodiments, the second layers 22B are sacrificial layers that are removed in later processes.

[0017] In some embodiments, one or more pad oxide layers and one or more hard mask layers (not shown) are produced over the multilayer stack 22. These layers are subsequently structured and used for later structuring of the multilayer stack 22.

[0018] In Fig. 2. The multilayer stack 22 and a portion of the underlying substrate 20 are structured in one or more etching processes, creating grooves 23. The corresponding process is specified as a process 204 in the process sequence 200, which is described in Fig. Figure 30 shows the trenches 23 extending into the substrate 20. The remaining parts of the multilayer stack are referred to below as multilayer stacks 22'. Beneath the multilayer stacks 22', some parts of the substrate 20 remain, which are referred to below as substrate strips 20'. The multilayer stacks 22' have semiconductor layers 22A and 22B. The semiconductor layers 22A are referred to below as sacrificial layers, and the semiconductor layers 22B are referred to below as nanostructures. The parts of the multilayer stacks 22' and the underlying substrate strips 20' are collectively referred to as semiconductor strips 24.

[0019] In the embodiments described above, the GAA transistor structures can be structured using any suitable method. For example, the structures can be structured using one or more photolithography processes, such as dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, pitches smaller than those achievable with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is produced over a substrate and then structured using a photolithography process. Spacers are produced along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can then be used to structure the GAA structure.

[0020] Fig. Figure 3 shows the creation of isolation zones 26, which are also referred to as STI zones (STI: shallow trench isolation) throughout this description. The corresponding process is specified as process 206 in process flow 200, which is described in Fig. Figure 30 shows that the STI regions 26 may have an oxide coating (not shown), which may be a thermal oxide produced by thermal oxidation of a surface layer of the substrate 20. The oxide coating may also be a deposited silicon oxide layer produced, for example, by ALD, high-density plasma deposition (HDP-CVD), CVD, or the like. Alternatively, the STI regions 26 may have a dielectric material overlying the oxide coating, the dielectric material being deposited by flowable CVD (FCVD), spin coating, HDP-CVD, or the like. Subsequently, a planarization process, such as a CMP process (chemical-mechanical polishing) or a machine grinding process, may be performed to level one top surface of the dielectric material, and the remaining portions of the dielectric material constitute the STI regions 26.

[0021] The STI regions 26 are then recessed, allowing upper portions of the semiconductor strips 24 to project over top surfaces 26T of the remaining portions of the STI regions 26, forming projecting fins 28. The projecting fins 28 feature the multilayer stacks 22' and the upper portions of the substrate strips 20'. The recession of the STI regions 26 can be performed using a dry etching process, in which, for example, NF3 and NH3 are used as etching gases. A plasma can be generated during the etching process. Argon can also be used. In alternative embodiments of the present disclosure, the recession of the STI regions 26 is performed using a wet etching process. Hydrogen fluoride (HF), for example, can be used as the etching chemical.

[0022] In Fig. 4. Dummy gate stacks 30 and gate spacers 38 are manufactured on the tops and side walls of the (protruding) fins 28. The corresponding process is specified as process 208 in process flow 200, which is described in Fig. Figure 30 shows that the dummy gate stacks 30 can have dummy gate dielectrics 32 and dummy gate electrodes 34 over the dummy gate dielectrics 32. The dummy gate dielectrics 32 can be produced by oxidizing surface portions of the protruding fins 28 to form oxide layers, or they can be produced by depositing a dielectric layer, such as a silicon oxide layer. The dummy gate electrodes 34 can be produced, for example, using polysilicon or amorphous silicon, but other materials, such as amorphous carbon, can also be used.

[0023] The dummy gate stacks 30 can each have one or more hard mask layers 36 over the dummy gate electrode 34. The hard mask layers 36 can be made of silicon nitride, silicon oxide, silicon carbonitride, silicon oxide carbonitride, or multilayers thereof. The dummy gate stacks 30 can extend over one or more projecting fins 28 and the STI regions 26 between the projecting fins 28. The dummy gate stacks 30 also have longitudinal directions that are perpendicular to the longitudinal directions of the projecting fins 28. The dummy gate stacks 30 are fabricated as follows: fabricating a dielectric dummy gate layer; depositing a dummy gate electrode layer over the dielectric dummy gate layer; depositing one or more hard mask layers; and subsequently structuring the fabricated layers using one or more structuring processes.

[0024] Gate spacers 38 are then fabricated on the side walls of the dummy gate stacks 30. In some embodiments of the present disclosure, the gate spacers 38 are made of a dielectric material such as silicon nitride (SiN), silicon carbide (SiC), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxide nitride (SiON), silicon oxide carbonitride (SiOCN), or the like, and they can have a single-layer structure or a multi-layer structure with a plurality of dielectric layers. The fabrication process for the gate spacers 38 can include depositing one or more dielectric layers and subsequently performing one or more anisotropic etching processes on the one or more dielectric layers. The remaining portions of the one or more dielectric layers are the gate spacers 38.

[0025] The Fig. 5A and Fig. 5B shows sectional views of the structure, which is located in Fig. 4 is shown. Fig. 5A shows a reference cross-section A1 - A1 of Fig. 4, which cuts through the parts of the protruding fins 28 that are not covered by the gate stacks 30 and the gate spacers 38 and which is perpendicular to the gate longitudinal direction. Fig. 5B shows a reference cross-section B - B of Fig. 4, which is parallel to the longitudinal directions of the projecting fins 28.

[0026] In the Fig. 6A and Fig. 6B parts of the protruding fins 28 ( Fig. 4), which are not directly beneath the dummy gate stacks 30 and the gate spacers 38, are recessed by an etching process to create recesses 42. The corresponding process is specified as a process 210 in the process flow 200, which is described in Fig. Figure 30 shows that, for example, a dry etching process using C2F6, CF4, SO2, a mixture of HBr, Cl2 and O2, a mixture of HBr, Cl2, O2 and CH2F2, or the like can be carried out to etch the multilayer semiconductor stacks 22' and the underlying substrate strips 20'. The undersides of the recesses 42 are at least level with the undersides of the multilayer semiconductor stacks 22', or they can be deeper than them (as shown in Figure 30). Fig. 6B). The etching can be anisotropic, so that the sidewalls of the multilayer semiconductor stacks 22' facing the recesses 42 are vertical and straight, as shown in Fig. 6B is shown.

[0027] In the Fig. 7A and Fig. 7B sacrificial semiconductor layers 22A are laterally recessed to create lateral recesses 41 that are recessed relative to the edges of the respective nanostructures 22B located above and below them. The corresponding process is specified as a process 212 in the process sequence 200, which is described in Fig. 30 is shown.

[0028] Lateral embedding of the sacrificial semiconductor layers 22A can be achieved using a wet etching process with an etchant that is more selective for the material, e.g., silicon germanium (SiGe), of the sacrificial semiconductor layers 22A than for the material, e.g., silicon (Si), of the nanostructures 22B and the substrate 20. For example, in an embodiment where the sacrificial semiconductor layers 22A are made of silicon germanium and the nanostructures 22B are made of silicon, the wet etching process can be carried out using an etchant such as hydrochloric acid (HCl). The wet etching process can be carried out by immersion, spraying, centrifugal, or similar methods.

[0029] In alternative embodiments, the lateral recession of the sacrificial semiconductor layers 22A is carried out using an isotropic dry etching process or a combination of a dry etching process and a wet etching process.

[0030] In the Fig. 8A and Fig. 8B internal spacers 44 are manufactured. The corresponding process is specified as process 214 in process flow 200, which is in Fig. Figure 30 shows that in some embodiments the manufacture of the internal spacers 44 includes the deposition of a conformal dielectric layer such that it extends into the lateral recesses 41 ( Fig. 7B). Then an etching process (also called a spacer trimming process) is carried out to trim the portions of the spacer layer outside the lateral recesses 41, leaving portions of the spacer layer within the lateral recesses 41. The remaining portions of the spacer layer are referred to as internal spacers 44. The internal spacers 44 can be single-layer spacers or can have multiple sublayers (e.g., two to three sublayers).

[0031] In alternative embodiments, no internal spacers 44 are produced, and subsequently generated source / drain areas can be in contact with dielectric high-k layers in substitute gate stacks.

[0032] In the Fig. 9A and Fig. 9B epitaxial source / drain regions 48 are created in the recesses 42, for example, using epitaxial processes. The details of the source / drain regions 48 are described in Fig. 23 or Fig. 29 shown according to some embodiments.

[0033] The Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19 to Fig. Figure 20 shows details of the generation of the source / drain areas 48 according to some embodiments. Fig. Figure 15 shows an enlarged view of area 47 of Fig. 8B, in which the recesses 42 and the internal spacers 44 were manufactured. In which in Fig. The example shown in Figure 15 depicts three stacked nanostructures of 22B as an example. The number of nanostructures of 22B in a stack can also be a different number, ranging, for example, from 2 to approximately 5.

[0034] In Fig. In step 16, a dielectric layer 49 is produced on the underside of the recess 42. The corresponding process is specified as process 216 in process sequence 200, which is described in Fig. Figure 30 shows that in some embodiments, the dielectric layer 49 comprises a silicon nitride layer. The dielectric layer 49 can have a single-layer structure or a multi-layer structure with multiple dielectric layers made of different dielectric materials. The material for the dielectric layer 49 can be selected from the group consisting of silicon oxide, silicon nitride, silicon carbide, silicon oxide nitride, or the like, or a combination thereof.

[0035] Fig. Figure 17 shows an epitaxy of semiconductor layers 48A (also referred to as layer 1 or L1). The corresponding process is specified as process 218 in process sequence 200, which is described in Fig. Figure 30 shows that the semiconductor layers 48A, which are grown from opposite sides of the recess 42, are referred to as a first and a second part of the semiconductor layer 48A. The semiconductor layers 48A are selectively grown from exposed sidewall surfaces of the nanostructures 22B. In some embodiments where the top surface of the semiconductor substrate 20 is located on a (100) surface plane, the sidewall surface of the semiconductor layers 48A may be located on (110) surface planes. In contrast, no part (or only a very small amount) of the semiconductor layers 48A is grown directly from the dielectric structural elements, such as the gate spacers 38 and the hard mask 36 (see Figure 30). Fig. 9).

[0036] If the source / drain region is a p-region of a p-transistor, the semiconductor layers can contain silicon, SiGe, or Ge, and they also contain a p-type dopant such as boron, indium, or combinations thereof. For example, the semiconductor layers can contain boron-doped SiGe. The semiconductor layers can have a p-type doping concentration of approximately 4 × 10²⁰ / cm². 3 up to about 7E20 / cm 3 The germanium atom content can range from approximately 0% to approximately 40%.

[0037] In alternative embodiments where the source / drain region is an n-region of an n-transistor, the semiconductor layers can contain 48A Si, SiC, or the like, and they also contain an n-doping element such as phosphorus, arsenic, antimony, or combinations thereof. For example, the semiconductor layers can contain 48A SiP. The n-doping concentration can also be approximately 4E20 / cm². 3 up to about 7E20 / cm 3 be.

[0038] In some embodiments, the fabrication of the semiconductor layers 48A is carried out at a first temperature (wafer temperature) that is relatively low. The first temperature can be approximately 400 °C to approximately 600 °C. During the epitaxial process, a silicon-containing precursor, such as silane (SiH4), disilane (Si2H6), dichlorosilane (DCS, SiH2Cl2), or the like, or a combination thereof, can be used as a deposition precursor. An etching gas such as HCl can be added. A throughput ratio FR E / FR D can be approximately 0.2 to approximately 0.4, where the value FR E the throughput of the etching gas and the value FR D The throughput of the deposition precursor containing silicon.

[0039] In some embodiments, there can be a plurality of individual semiconductor layers 48A, separated from one another and each epitaxially grown from one of the nanostructures 22B. The semiconductor layers 48A can have similar (and / or identical) sizes and shapes. Furthermore, upper semiconductor layers 48A can have the same sizes, and they can extend laterally into the recess 42 by the same or similar distances as their respective lower semiconductor layers 48A. As the epitaxial growth process progresses, the portions of the semiconductor layers 48A grown from different nanostructures 22B fuse to form integrated parts, as shown in Fig. Figure 17 shows that the sidewalls of the fused semiconductor layers 48A have an X-shape in a sectional view. Due to the lower growth rate in the (111) directions, there can be multiple chamfers.

[0040] Let's stay with Fig. 17. The epitaxy process is terminated, and a annealing process 112 is carried out to reshape the semiconductor layers 48A. The corresponding process is specified as a process 220 in the process flow 200, which is described in Fig. Figure 30 shows that in some embodiments, the wafer temperature during the annealing process 112 can be approximately 700 °C to approximately 850 °C. The process gas can contain inert gases and / or reducing gases that can prevent the semiconductor layers 48A from being oxidized. In some embodiments, the process gases can contain hydrogen (H₂), nitrogen (N₂), argon, or combinations thereof. The pressure of the process gas can be approximately 20 Torr to approximately 1 ATM. The annealing time can be approximately 30 s to approximately 120 s.

[0041] The reshaped semiconductor layers 48A are in Fig. Figure 18 shows that in the tempering process 112, the semiconductor layers 48A are not melted into a liquid. However, the temperature is so high and the tempering time is so long that migration and deformation of the semiconductor layers 48A occur. As a result, a middle section between the uppermost and lowermost ends of the semiconductor layers 48A becomes thicker, while the corresponding upper and lower sections become thinner.

[0042] The change in thickness of different portions of the semiconductor layers 48A at different levels can be continuous. The reduction in thickness from the thickest portions to the respective top and bottom edges can be gradual and continuous. Accordingly, the sidewall surfaces of the semiconductor layers 48A can be continuously convex. The thickest portions of the semiconductor layers 48A can be located in the middle (or near the middle, for example, with a deviation of less than approximately 10% of the height of the semiconductor layers 48A) between the top and bottom edges of the respective semiconductor layers 48A. The resulting semiconductor layers 48A are also referred to below as convex semiconductor layers 48A. The sidewalls of the semiconductor layers 48A can define an hourglass-shaped space between them.

[0043] In some embodiments, the tempering process 112 is terminated before the semiconductor layers 48A, which are grown from opposite sides of the recess 42, are fused, as in Fig. 18 is shown. In some embodiments, a distance S1 ( can be reached at the time of termination of the tempering process 112. Fig. 18) between adjacent semiconductor layers 48A are approximately 0 nm to approximately 13 nm.

[0044] In alternative embodiments, the annealing process 112 is extended. This causes the upper and lower parts of the semiconductor layers 48A to become progressively thinner, and the material of the semiconductor layers 48A increasingly migrates towards the middle layer. The middle parts of the semiconductor layers 48A, which are grown from the opposite sides of the recess 42, eventually fuse together. The extended annealing process 112 in Fig. Figure 18 is shown with a dashed line to indicate that the tempering process 112 can be extended to bring about fusion. The resulting structure is shown in Fig. Figure 19 shows the sidewalls of the fused semiconductor layers 48A having an X-shape in the sectional view. Fig. Figure 19 also shows dashed lines representing the sidewalls of the semiconductor layers 48A in embodiments where the semiconductor layers 48A are not to be fused. In some embodiments, a distance S2 between the fused semiconductor layers 48A can be approximately 5 nm to approximately 18 nm, where the distance S2 is measured at the mid-level of the topmost nanostructures 22B. An overlap height OLH of the fused semiconductor layers 48A can be approximately 0 nm to approximately 20 nm.

[0045] In some embodiments, the fabrication of the convex semiconductor layers 48A comprises a single deposition and annealing cycle, which includes one or more deposition processes and a single annealing process 112 for forming. In alternative embodiments, the fabrication of the convex semiconductor layers 48A comprises a plurality of deposition and annealing cycles, each of which includes a deposition process and a subsequent annealing process for forming. The very first annealing process 112 is performed after the semiconductor layers 48A, which are grown from the same side of the recesses, have all fused into a single layer. Otherwise, the migrated materials do not migrate to the central plane of the respective semiconductor layers 48A.The majority of deposition and tempering cycles can improve the forming profile and make the shapes of the semiconductor layers 48A more convex, which comes at the expense of higher manufacturing costs and lower throughput.

[0046] Fig. Figure 20 shows the epitaxial growth of a semiconductor layer 48B (also referred to as layer 2 or L2). The corresponding process is specified as process 222 in process flow 200, which is described in Fig. Figure 30 shows that the resulting semiconductor layer 48B is grown from and differs from the semiconductor layers 48A. Semiconductor layer 48B can have a higher p-type doping concentration than semiconductor layers 48A. For example, if the transistor in question is a p-type transistor, the boron concentration in semiconductor layer 48B can be approximately 5 × 10²⁰ / cm². 3 up to about 3E21 / cm 3If the transistor in question is an n-transistor, the dopant is an n-dope, and the n-dope in semiconductor layer 48B can also have a higher doping concentration than that in semiconductor layers 48A.

[0047] It is understood that - although the semiconductor layers 48A can merge, since the space under the fusion point is accessible from cross-sections different from the cross-section shown - the semiconductor layer 48B can be filled into the space under the fusion point.

[0048] In some embodiments, the fabrication of semiconductor layer 48B is carried out at a second temperature (wafer temperature), which may be in the same or a similar temperature range as that used to fabricate semiconductor layers 48A. The second temperature may, for example, be in the range of approximately 400 °C to approximately 600 °C.

[0049] Semiconductor layer 48B can contain SiGe with a germanium atom content higher than that of semiconductor layer 48A. For example, the germanium atom content in semiconductor layer 48B can range from approximately 40% to approximately 90%. The top surface of semiconductor layer 48B is higher than the top edges of semiconductor layer 48A and the top surfaces of the top nanostructures 22B.

[0050] Fig. Figure 21 shows the fabrication of a semiconductor layer (capping layer) 48C according to some embodiments, for example with a selective epitaxy process. The corresponding process is specified as a process 224 in the process sequence 200, which is described in Fig. Figure 30 shows that in some embodiments, the capping layer 48C contains silicon but no germanium. The capping layer 48C may also contain SiGe, but with a lower percentage of germanium atoms than the semiconductor layers 48A and 48B. The boron concentration in the capping layer 48C may also be lower than or equal to the boron concentration in the semiconductor layer 48B. In alternative embodiments, the capping layer 48C is not produced. Throughout this description, the semiconductor layers 48A, 48B, and 48C are collectively referred to as source / drain regions 48.

[0051] Let's return to the Fig. 10A and Fig. 10B, in which a contact etch stop layer (CESL) 50 and an interlayer dielectric (ILD) 52 are produced. The corresponding process is specified as process 226 in process flow 200, which is described in Fig. 30 is shown. The corresponding structure is also in Fig. Figure 21 shows that CESL 50 can be produced from silicon oxide, silicon nitride, silicon carbonitride, or the like by CVD, ALD, or the like. ILD 52 can be a dielectric material produced, for example, by FCVD, spin coating, CVD, or another suitable deposition process. ILD 52 can be produced from an oxygen-containing dielectric material, which may be silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

[0052] The CESL 50 and the ILD 52 are structured using a planarization process, such as a CMP process or a machine grinding process. In some embodiments, the planarization process can remove the hard masks 36 to expose the dummy gate electrodes 34, as shown in Fig. Figure 10A shows this. In alternative embodiments, the planarization process can expose the hard masks 36, and it terminates thereon. In some embodiments, after the planarization process, the top surfaces of the dummy gate electrodes 34 (or the hard masks 36), the gate spacers 38, and the ILD 52 are at the same level within process variations.

[0053] Then the dummy gate electrodes 34 and the dummy gate dielectrics 32 (and the hard masks 36, if still present) are removed in one or more etching processes, creating recesses as shown in the Fig. 11A and Fig. 11B is shown. The corresponding process is specified as process 228 in process flow 200, which is shown in Fig. 30 is shown.

[0054] Then the sacrificial layers 22A are removed to enlarge the voids 58 between nanostructures 22B. The corresponding process is specified as a process 230 in the process flow 200, which is described in Fig. Figure 30 shows that the sacrificial layers 22A can be removed by performing an isotropic etching process, such as a wet etching process, using etchants that are selective for the materials of the sacrificial layers 22A, while the nanostructures 22B, the substrate 20 and the STI regions 26 remain relatively unetched compared to the sacrificial layers 22A.

[0055] In the Fig. 12A and Fig. In step 12B, gate dielectrics 62 and gate electrodes 68 are produced, resulting in replacement gate stacks 70. The corresponding process is specified as process 232 in process sequence 200, which is described in Fig. 30 is shown. The corresponding structure is in Fig. Figure 22 shows that in some embodiments, each gate dielectric 62 has an interface layer and a high-k dielectric layer on the interface layer. The interface layer may be made of or contain silicon oxide. In some embodiments, the high-k dielectric layer may comprise one or more dielectric layers. The high-k dielectric layer may, for example, contain a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, or combinations thereof.

[0056] Furthermore, gate electrodes 68 are manufactured. In the manufacturing process, conductive layers are first produced on the dielectric high-k layer, and the remaining portions of the recesses 58 are filled. The gate electrodes 68 can contain a metal-containing material such as TiN, TaN, TiAl, TiAlC, cobalt, ruthenium, aluminum, tungsten, combinations thereof, and / or multilayers thereof.

[0057] In the processes that took place in the Fig. 13A and Fig. As shown in Figure 13B, the gate stacks 70 are recessed, creating recesses directly above the gate stacks 70 and between opposing parts of the gate spacers 38. A gate mask 74, comprising one or more layers of a dielectric material such as silicon nitride, silicon oxide nitride, or the like, is filled into each of the recesses, and subsequently a planarization process is performed to remove excess dielectric material located above the ILD 52.

[0058] As also in the Fig. 13A and Fig. As shown in Figure 13B, an ILD 76 is deposited over the ILD 52 and the gate masks 74. An etch stop layer (not shown) may (or may not) be deposited prior to the deposition of the ILD 76. In some embodiments, the ILD 76 is deposited by FCVD, CVD, PECVD, or the like. The ILD 76 is made from a dielectric material from the group consisting of silicon dioxide, PSG, BSG, BPSG, USG, or the like.

[0059] In the Fig. 14A and Fig. In step 14B, the ILD 76, the ILD 52, the CESL 50, and the gate masks 74 are etched to create recesses (occupied by contact pins 80A and 80B) that expose the surfaces of the source / drain regions 48 and / or the gate stack 70. The recesses can be created by etching with an anisotropic etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like. Fig. Although Figure 14B shows that the contact pins 80A and 80B are in the same cross-section, in different embodiments the contact pins 80A and 80B can also be manufactured in different cross-sections, thereby reducing the risk of them being short-circuited together.

[0060] After the recesses have been created, silicide zones 78 are created above the source / drain zones 48. The corresponding process is specified as process 234 in process flow 200, which is in Fig. Figure 30 shows that contact pins 80B are then fabricated over the silicide areas 78. Additionally, contacts 80A (which can also be called gate contact pins) are fabricated in the recesses so that they are located over and contact the gate electrodes 68. The corresponding structure is also shown in Fig. 23 is shown. This creates a transistor 82.

[0061] Fig. Figure 23 shows parts of transistor 82, which are also found in the Fig. 14A and Fig. Figure 14B shows the following. It is understood that if the shaping process for the semiconductor layers 48A is not performed, some parts of the silicide regions 78 and the (source / drain) contact pin 80B (also referred to as a contact structure 80B) may be located on the semiconductor layers 48A instead of on the semiconductor layer 48B. The semiconductor layer 48B may have a higher boron doping concentration and / or a higher percentage of germanium atoms than the semiconductor layers 48A. Accordingly, by reshaping the semiconductor layers 48A and reducing the size of their upper portions, it is more likely that the silicide regions 78 will be located on the semiconductor layer 48B than on the semiconductor layers 48A. This reduces the source / drain resistance.

[0062] The Fig. 24, Fig. 25, Fig. 26, Fig. 27, Fig. 28 to Fig. Figure 29 shows the fabrication of a GAA transistor 82 according to alternative embodiments. These embodiments are essentially the same as the preceding embodiments, except that the forming of the semiconductor layers 48A is carried out simultaneously with (rather than after) the deposition of the semiconductor layers 48A. Unless otherwise specified, the materials, structures, and fabrication processes for the components in these embodiments are essentially the same as for the similar components designated by similar reference numerals in the preceding embodiments. The details of the materials, structures, and fabrication processes given throughout the description in each embodiment may also be used for another embodiment, if applicable.

[0063] The first steps of these embodiments are essentially the same as those described in the Fig. 1 to 8B are shown. Then in Fig. 24 The semiconductor layers 48A are deposited by epitaxy. In some embodiments, the semiconductor layers 48A are deposited with convex shapes, the middle parts being thicker than the corresponding upper and lower parts.

[0064] In some embodiments, the fabrication of the semiconductor layers 48A is carried out at a relatively high temperature, which can cause migration of the semiconductor layers 48A, resulting in semiconductor layers 48A with convex shapes. The convex shapes also increase as the fabrication process progresses. The temperature is higher than the temperature used to fabricate the semiconductor layers 48A that are in Fig. Figure 17 shows that in some embodiments the temperature for producing the semiconductor layers 48A can be approximately 700 °C to approximately 850 °C.

[0065] During the epitaxy process, a silicon-containing precursor, such as silane (SiH4), disilane (Si2H6), dichlorosilane (SiH2Cl2), or the like, or a combination thereof, can be used as a deposition precursor. An etching gas such as HCl can be added. The throughput ratio FR can also be used to produce the convex semiconductor layers 48A. E / FR D can be increased, and it can be greater than the throughput ratio FR E / FR D in the separation process that is in Fig. Figure 17 shows, for example, the throughput ratio FR. E / FR D in which Fig. The process shown in Figure 24 will be approximately 0.4 to approximately 0.9.

[0066] There are other process parameters that can influence the profile of the 48A semiconductor layers, including chamber pressure, deposition rate, and similar factors. By selecting a suitable combination of these process parameters, the desired convex profile for the 48A semiconductor layers can be achieved.

[0067] As the epitaxial process progresses, the semiconductor layers 48A become thicker and larger, as shown in Fig. Figure 25 shows that during the epitaxy process, the semiconductor layers 48A retain their convex shape. In some embodiments, the semiconductor layers 48A can be grown until their opposing parts fuse together, and the resulting structure is shown in Fig. 26. In alternative embodiments, the fabrication of the semiconductor layers 48A is terminated before they fuse, as shown in Fig. 25 is shown. Fig. Figure 26 shows dashed lines to represent the sidewalls of semiconductor layers 48A in the case that they are not to be fused at the time semiconductor layer 48B is produced.

[0068] As also in the Fig. 25 and Fig. As shown in Figure 26, in some embodiments an annealing process 112 may (or may not) be performed (once the growth of the semiconductor layers 48A is complete) to reshape the semiconductor layers 48A so that their upper portions become thinner. A single deposition and annealing cycle can be used to grow the semiconductor layers 48A and subsequently perform an annealing process 112 if no precursors are introduced for growth. Alternatively, multiple deposition and annealing cycles can be used, each comprising a deposition process and a subsequent annealing process.

[0069] The tempering process 112 can be started either before or after the fusion of the semiconductor layers 48A. Furthermore, if the semiconductor layers 48A have not fused by the time a subsequent tempering process 112 is started, the tempering process 112 may or may not result in fusion, as shown in the Fig. 25 and Fig. Figure 26 is shown. In alternative embodiments, the tempering process 112 is not carried out.

[0070] Fig. Figure 27 shows the fabrication of the semiconductor layers 48B and 48C according to some embodiments. Then the CESL 50 and the ILD 52 are fabricated. These processes are essentially the same as those described with reference to the Fig. 20, Fig. 21 to Fig. 22 have been discussed, and they will not be repeated here.

[0071] Fig. Figure 28 shows the production of the replacement gate stack 70. Fig. Figure 29 shows the production of the silicide sections 78 and the source / drain contact pin 80B. The processes are described with reference to Fig. Points 23 have been discussed and will not be repeated here.

[0072] The embodiments of the present disclosure have several advantages. By fabricating first semiconductor layers in a source / drain region such that they have convex cross-sectional shapes, the upper portions of the semiconductor layers are narrower. The spaces created by the narrower upper portions are occupied by a second semiconductor layer, which has a lower resistivity than the first semiconductor layers. It is therefore more likely that the source / drain silicide region will be located on top of the second semiconductor layer. This reduces the resistance of the conductive path comprising the source / drain region, the silicide region, and the source / drain contact pin, and improves the transistor's drive current. These embodiments yield even more significant results when dielectric layers are fabricated beneath the source / drain regions.Due to the dielectric layers that can be produced on the underside of the source / drain regions, a lower voltage can be introduced into the channel regions, and it is more necessary to improve the drive current by reducing the resistance, and this requirement can be met with the embodiments of the present disclosure.

[0073] In some embodiments of the present disclosure, a method comprises: fabricating a plurality of semiconductor nanostructures, wherein the upper of the plurality of semiconductor nanostructures overlaps the respective lower of the plurality of semiconductor nanostructures; creating a source / drain recess laterally of the plurality of semiconductor nanostructures; fabricating a first semiconductor layer from the plurality of semiconductor nanostructures, wherein the first semiconductor layer has a convex shape in its cross-sectional view; fabricating a second semiconductor layer above the first semiconductor layer; and creating a silicide region above and in contact with the second semiconductor layer.

[0074] In one embodiment, the fabrication of the first semiconductor layer comprises: depositing the first semiconductor layer; and performing a tempering process to thicken a central portion of the first semiconductor layer. In one embodiment, the first semiconductor layer, at a time point after its deposition, has: a first plurality of parts grown from a plurality of semiconductor nanostructures; and a second plurality of parts between the first parts, the second parts being thinner than the first parts.

[0075] In one embodiment, the first semiconductor layer is deposited at a first wafer temperature, and the second semiconductor layer is deposited at a second wafer temperature that is equal to or higher than the first wafer temperature. In another embodiment, the first semiconductor layer has a first part and a second part that are grown towards each other, with the first part fusing with the second part at the end of the annealing process.

[0076] In one embodiment, the first semiconductor layer has a first part and a second part that are grown towards each other, with the first part being physically separated from the second part at the end of the annealing process. In another embodiment, at the time of deposition of the first semiconductor layer, a middle part of the first semiconductor layer is thicker than the corresponding upper and lower parts of the first semiconductor layer.

[0077] In one embodiment, the first semiconductor layer is deposited at a first wafer temperature, and the second semiconductor layer is deposited at a second wafer temperature that is lower than the first wafer temperature. In another embodiment, the process further includes, prior to the fabrication of the first semiconductor layer, the fabrication of a dielectric layer on the underside of the source / drain cavity. In yet another embodiment, the first semiconductor layer is spaced apart from the dielectric layer by the second semiconductor layer. In yet another embodiment, the second semiconductor layer has a higher boron concentration than the first semiconductor layer.

[0078] In some embodiments of the present disclosure, a method comprises: fabricating a semiconductor stack having a plurality of semiconductor nanostructures; and generating a source / drain region. Generating the source / drain region comprises: epitaxially growing a first semiconductor layer having a first part and a second part on the same plane, wherein the first and second parts are grown towards each other and the first part has a lower, an upper, and a middle part between the lower and upper parts; annealing the first semiconductor layer, increasing the first thickness of the middle part and decreasing the second thicknesses of the upper and lower parts; and epitaxially growing a second semiconductor layer over the first semiconductor layer.

[0079] In one embodiment, after annealing the first semiconductor layer, the first part is spaced apart from the second part. In another embodiment, before annealing the first semiconductor layer, the first part has a non-convex profile, and the first semiconductor layer has an X-shaped sidewall after fusion. In yet another embodiment, both the first and second parts of the first semiconductor layer have convex profiles both at a first time point before annealing the first semiconductor layer and at a second time point after annealing the first semiconductor layer. In yet another embodiment, the first semiconductor layer is deposited at a first temperature, and the second semiconductor layer is deposited at a second temperature that is lower than the first temperature.

[0080] According to some embodiments of the present disclosure, a structure comprises a semiconductor stack with a plurality of semiconductor nanostructures, wherein the plurality of semiconductor nanostructures includes a first semiconductor nanostructure and a second semiconductor nanostructure overlapping the first semiconductor nanostructure. The structure further comprises a source / drain region laterally adjacent to the semiconductor stack, the source / drain region comprising: a first semiconductor layer with a first part and a second part, wherein the first part includes a middle part having the greatest thickness of the first part, the thicknesses of the first part gradually decreasing towards the respective upper and lower parts of the first part; and a second semiconductor layer between the first part and the second part of the first semiconductor layer.The structure further comprises: a source / drain silicide region above and in contact with the second semiconductor layer, wherein the source / drain silicide region is spaced away from the first semiconductor layer; and a source / drain contact pin above and in contact with the source / drain silicide region.

[0081] In one embodiment, the first part is connected to the second part, such that, in a cross-sectional view of the structure, a first side wall of the first part is connected to a second side wall of the second part in such a way as to form an X-shape. In another embodiment, the first part is spaced apart from the second part, and a portion of the second semiconductor layer between the first and second parts has an hourglass shape in a cross-sectional view of the structure. In yet another embodiment, the structure further comprises a dielectric layer beneath the first and second semiconductor layers, wherein the first semiconductor layer is spaced apart from the dielectric layer by a lower portion of the second semiconductor layer.

[0082] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present invention. It should be clear to those skilled in the art that they can readily use the present invention as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent designs do not deviate from the fundamental concept and scope of protection of the present invention and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present invention.

Claims

[1] Procedure, encompassing: Fabricating a plurality of semiconductor nanostructures, wherein the upper portions of the plurality of semiconductor nanostructures overlap the respective lower portions of the plurality of semiconductor nanostructures; Creating a source / drain cavity laterally of the majority of semiconductor nanostructures; Fabricating a first semiconductor layer from the plurality of semiconductor nanostructures, wherein the first semiconductor layer has a convex shape in its cross-sectional view; Creating a second semiconductor layer over the first semiconductor layer; and Creating a silicide region above and in contact with the second semiconductor layer. [2] The method of claim 1, wherein the production of the first semiconductor layer comprises: Deposition of the first semiconductor layer; and Performing a tempering process to thicken a central part of the first semiconductor layer. [3] The method of claim 2, wherein the first semiconductor layer at a time point after its deposition has the following: a first plurality of parts that have grown from the plurality of semiconductor nanostructures; and a second plurality of parts between the first parts, the second parts being thinner than the first parts. [4] Method according to claim 2 or 3, wherein the first semiconductor layer is deposited at an initial wafer temperature, and the second semiconductor layer is deposited at a second wafer temperature that is equal to or higher than the first wafer temperature. [5] Method according to any one of claims 2 to 4, wherein the first semiconductor layer has a first part and a second part that grow towards each other, and At the point when the tempering process is completed, the first part is fused with the second part. xxx [6] Method according to any one of claims 2 to 4, wherein the first semiconductor layer has a first part and a second part that grow towards each other, and At the point when the tempering process is completed, the first part is physically separated from the second part. [7] Method according to one of the preceding claims, wherein at a time of deposition of the first semiconductor layer a middle part of the first semiconductor layer is thicker than the corresponding upper parts and the corresponding lower parts of the first semiconductor layer. [8] Method according to any one of the preceding claims, wherein the first semiconductor layer is deposited at an initial wafer temperature, and the second semiconductor layer is deposited at a second wafer temperature that is lower than the first wafer temperature. [9] Method according to any of the preceding claims, further comprising producing a dielectric layer on an underside of the source / drain recess before producing the first semiconductor layer. [10] Method according to claim 9, wherein the first semiconductor layer is spaced apart from the dielectric layer by the second semiconductor layer. [11] Method according to any of the preceding claims, wherein the second semiconductor layer has a higher boron concentration than the first semiconductor layer. [12] Procedures, including: Fabricating a semiconductor stack that features a plurality of semiconductor nanostructures; and Creating a source / drain area using the following steps: epitaxial growth of a first semiconductor layer having a first part and a second part on the same plane, wherein the first and second parts are grown towards each other and the first part has a lower part, an upper part and a middle part between the lower and the upper part, Annealing of the first semiconductor layer, whereby a first thickness of the middle part is increased and second thicknesses of the upper and lower parts are decreased, and Epitaxial growth of a second semiconductor layer over the first semiconductor layer. [13] Method according to claim 12, wherein after annealing the first semiconductor layer the first part is spaced apart from the second part. [14] Method according to claim 12 or 13, wherein Before the annealing of the first semiconductor layer, the first part has a non-convex profile, and The first semiconductor layer, after it has fused, has an X-shaped sidewall. [15] Method according to any one of claims 12 to 14, wherein the first and second part of the first semiconductor layer have convex profiles both at a first time before annealing the first semiconductor layer and at a second time after annealing the first semiconductor layer. [16] Method according to any one of claims 12 to 15, wherein the first semiconductor layer is deposited at a first temperature, and The second semiconductor layer is deposited at a second temperature that is lower than the first temperature. [17] Structure with: a semiconductor stack comprising a plurality of semiconductor nanostructures, wherein the plurality of semiconductor nanostructures comprises the following: a first semiconductor nanostructure, and a second semiconductor nanostructure that overlaps the first semiconductor nanostructure; a source / drain region located laterally to the semiconductor stack, wherein the source / drain region contains the following: a first semiconductor layer comprising a first part and a second part, wherein the first part includes a middle part having the greatest thickness of the first part, and the thicknesses of the first part gradually decrease towards the respective upper and lower parts of the first part, and a second semiconductor layer between the first part and the second part of the first semiconductor layer; a source / drain silicide region above and in contact with the second semiconductor layer, wherein the source / drain silicide region is spaced apart from the first semiconductor layer; and a source / drain contact pin over and in contact with the source / drain silicide area. [18] Structure according to claim 17, wherein the first part is connected to the second part, and In a cross-sectional view of the structure, a first side wall of the first part is connected to a second side wall of the second part in such a way that an X-shape is created. [19] Structure according to claim 17, wherein the first part is separated from the second part, and Part of the second semiconductor layer between the first part and the second part has an hourglass shape in a cross-sectional view of the structure. [20] Structure according to one of claims 17 to 19, further comprising a dielectric layer below the first and second semiconductor layers, wherein the first semiconductor layer is spaced apart from the dielectric layer by a lower part of the second semiconductor layer.

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