Hole preloading from the data line side to enable a program subblock mode in a completely reverse order

Abstract

This document discloses a memory device. The memory device includes memory cells, each connected to one of a plurality of word lines and configured to maintain a threshold voltage corresponding to one of a plurality of data states. The memory cells are arranged in memory holes that define channels. A control device is configured to create holes by applying a hole preload voltage to the channels of the memory holes during a preload phase of a programming operation of the memory cells in the memory holes. Following the preload phase, the control device applies one of a series of programming pulses of a programming voltage to selected of the plurality of word lines to program the associated memory cells.

Description

AREA

[0001] This application relates to non-volatile storage devices and the operation of non-volatile storage devices. BACKGROUND

[0002] This section provides background information on related technology associated with the present disclosure and is therefore not necessarily prior art.

[0003] Semiconductor memory devices are becoming increasingly popular in various electronic devices. Non-volatile semiconductor memory is used, for example, in mobile phones, digital cameras, PDAs, portable computing devices, stationary computing devices, and other devices.

[0004] In such storage devices, a charge storage material, such as a floating gate or a charge-trapping material, can be used to store a charge representing a data state. A charge-trapping material can be arranged vertically in a three-dimensional (3D) stacked storage structure or horizontally in a two-dimensional (2D) storage structure. An example of a 3D storage structure is the Bit Cost Scalable (BiCS) architecture, which comprises a stack of alternating conductive and dielectric layers. SUMMARY

[0005] This section provides a general summary of the present disclosure and is not a comprehensive disclosure of its entire scope of protection or all of its features and benefits.

[0006] One purpose of the present disclosure is to provide a storage device and a method for operating the storage device that address and overcome the deficiencies described herein.

[0007] Accordingly, one aspect of the present disclosure is to provide a memory device comprising memory cells, each connected to one of a plurality of word lines and configured to maintain a threshold voltage corresponding to one of a plurality of data states. The memory cells are arranged in memory holes that define channels. A control device is configured to create holes by applying a hole preload voltage to the channels of the memory holes in a preload phase of a programming operation of the memory cells in the memory holes. Following the preload phase, the control device applies one of a series of programming pulses of a programming voltage to selected of the plurality of word lines to program the associated memory cells.

[0008] According to another aspect of the disclosure, a controller is provided that communicates with a memory device comprising memory cells, each connected to one of a plurality of word lines. The memory cells are configured to maintain a threshold voltage corresponding to one of a plurality of data states and are arranged in memory holes that define channels. The controller is configured to instruct the memory device to generate holes by directing the memory device to apply a hole preload voltage to the channels of the memory holes during a preload phase of a programming operation of the memory cells in the memory holes. Following the preload phase, the controller directs the memory device to apply one of a series of programming pulses of a programming voltage to selected of the plurality of word lines to program the associated memory cells.

[0009] According to an additional aspect of the disclosure, a method for operating a memory device is provided. The memory device includes memory cells, each connected to one of a plurality of word lines. The memory cells are configured to maintain a threshold voltage corresponding to one of a plurality of data states and are arranged in memory holes that define channels. The method includes the step of generating holes by applying a hole preload voltage to the channels of the memory holes in a preload phase of a programming operation of the memory cells in the memory holes. The method also includes, after the preload phase, the step of applying one of a series of programming pulses of a programming voltage to selected of the plurality of word lines to program the memory cells connected thereto.

[0010] Further areas of application will become apparent from the description given here. The description and specific examples in this summary are intended solely for illustrative purposes and are not intended to limit the scope of protection of this disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] For a detailed description of example designs, please refer to the accompanying drawings, which show: Fig. 1A is a block diagram of an example storage device according to aspects of the disclosure; Fig. 1B is a block diagram of an example control circuit which, according to aspects of the disclosure, includes a programming circuit, a counting circuit and a determining circuit; Fig. 2 blocks of memory cells in a two-dimensional example configuration of the memory array of Fig. 1A represents aspects of the revelation; Fig. 3A presents a cross-sectional view of example floating-gate memory cells in NAND strings according to aspects of the disclosure; Fig. 3B a cross-sectional view of the structure of Fig. 3A along line 329 represents aspects of the revelation; Fig. 4A shows a cross-sectional view of example charge capture memory cells in NAND strings according to aspects of the disclosure; Fig. 4B a cross-sectional view of the structure of Fig. 4A along line 429 represents aspects of the revelation; Fig. 5A an example block diagram of the acquisition block SB1 from Fig. 1A represents aspects of the revelation; Fig. 5B another example block diagram of the data acquisition block SB1 from Fig. 1A represents aspects of the revelation; Fig. 6A a perspective view of a set of blocks in a three-dimensional example configuration of the memory array of Fig. 1A according to aspects of revelation; Fig. 6B an example cross-sectional view of a section of one of the blocks of Fig. 6A represents aspects of the revelation; Fig. 6C a representation of the memory hole diameter in the stack of Fig. 6B represents aspects of the revelation; Fig. 6D a close-up of area 622 of the stack of Fig. 6B represents aspects of the revelation; Fig. 7A shows a top view of an example word management layer WLLO of the stack of Fig. 6B represents aspects of the revelation; Fig. 7B a top view of an upper dielectric example layer DL19 of the stack of Fig. 6B represents aspects of the revelation; Fig. 8A Example NAND strings in subblocks SBa to SBd of Fig. 7A represents aspects of the revelation; Fig. 8B presents another example view of NAND strings in subblocks according to aspects of the revelation; Fig. 8C presents a top view of example word-lead layers of a stack according to aspects of revelation; Fig. 9 represents the Vth distributions of memory cells in an example one-pass programming operation with four data states according to aspects of the revelation; Fig. 10 represents the Vth distributions of memory cells in an example one-pass programming operation with eight data states according to aspects of the disclosure; Fig. 11 presents the Vth distributions of memory cells in an example one-pass programming operation with sixteen data states according to aspects of the disclosure; Fig. 12 is a flowchart of an example programming process in a storage device; Fig. 13A and Fig. 13B represent the Vth distributions of memory cells according to aspects of the revelation; Fig. 14A and Fig. 14B presents an example BiCS structure according to aspects of the revelation; Fig. 15A to 15D provide different diagrams illustrating the implementation of a hole pre-charge scheme using gate-induced drain leakage current generation according to aspects of the disclosure; Fig. 16 a diagram of a block of memory cells which is divided into two subblocks, subblock 0 and subblock 1, and illustrates the programming direction for the reverse order of programming (ROP) as well as the preload path in the channel which is truncated by one or more of the memory cells which are programmed to a highest data state according to aspects of the disclosure; Fig. 17 a diagram of the voltages applied to a selected drain-side select-gate transistor, an unselected word line, a selected word line and a bit line during an electron precharge according to aspects of the disclosure; Fig. 18 a diagram of the channel potential for a normal block and a ROP-programmed sub-block according to aspects of the revelation; Fig. 19 shows a diagram of threshold voltage distribution widths of a multitude of data states versus the word line number for ROP, programming subblock 0 before subblock 1 and programming subblock 1 before subblock 0 according to aspects of the disclosure; Fig. 20 a diagram of the threshold voltage distributions using an electron precharge in a subblock mode according to aspects of the disclosure; Fig. 21 is a diagram showing a comparison of the process of precharging using electrons and holes according to aspects of the revelation; Fig. 22 is a table summarizing some differences between the precharge of electrons and holes according to aspects of the revelation; Fig. 23 a diagram of a memory hole channel showing gate-induced hole creation during preloading in an emulation according to aspects of the disclosure; Fig. 24 shows an example group of transistors of a memory hole together with a cleared memory cell and a source-side selection gate transistor according to aspects of the disclosure; Fig. 25 a diagram of the word lines in a sub-block arrangement, which are programmed for emulation according to aspects of the revelation; Fig. 26 shows the tensions of the target or selected word line together with a tension of the source line during emulation according to aspects of the revelation; Fig. 27 Two diagrams of a source line, a stack, a memory hole, a local intermediate connection and a charging pump of an example storage device with and without a pump isolation transistor are illustrated according to aspects of the disclosure; Fig. 28A a diagram of voltages applied to a selected drain-side selection gate transistor, a non-selected drain-side selection gate transistor, a first neighboring word line, the selected word line, a second neighboring word line, a bit line coupled to memory cells to be programmed, and a bit line coupled to memory cells prevented from being programmed, during a verification of a programming operation, a pre-charge phase for pre-charging electrons, and a programming pulse of the programming operation according to aspects of the disclosure; Fig. 28B a diagram of voltages applied to a selected drain-side select-gate transistor, a non-selected drain-side select-gate transistor, a first neighboring word line, the selected word line, a second neighboring word line, a bit line coupled to memory cells to be programmed, and a bit line coupled to memory cells prevented from being programmed during a verification of a programming operation, a preload phase for preloading holes, and a programming pulse of the programming operation according to aspects of the disclosure; and Fig. 29 steps of a procedure for operating a storage facility are illustrated according to aspects of the disclosure. DETAILED DESCRIPTION

[0012] The following description provides details to facilitate an understanding of the present disclosure. In some cases, certain circuits, structures, and techniques have not been described or shown in detail so as not to obscure the disclosure.

[0013] In general, this disclosure relates to non-volatile storage devices of a type well suited for use in many applications. The non-volatile storage device and the associated methods for forming this disclosure are described in conjunction with one or more exemplary embodiments. However, the specific exemplary embodiments disclosed are provided only to describe the inventive concepts, features, advantages, and objectives with sufficient clarity to enable the person skilled in the art to understand and put the disclosure into practice. In particular, the exemplary embodiments are provided to ensure that this disclosure is thorough and fully conveys the scope of protection to the person skilled in the art.Numerous specific details are presented, such as examples of specific components, devices, and methods, to provide a thorough understanding of embodiments of the present disclosure. It is evident to the person skilled in the art that no specific details need be included, that exemplary embodiments can be embodied in many different forms, and that none of these should be interpreted as limiting the scope of protection of the disclosure. In some exemplary embodiments, known processes, known device structures, and known technologies are not described in detail.

[0014] Various terms are used to describe certain system components. Different companies may refer to a component by different names—this document does not distinguish between components that differ in name but not in function. In the following discussion and in the claims, the terms "including" and "comprehensive" are used openly and should therefore be interpreted as "including, but not limited to...". Furthermore, the term "coupler" or "couplers" is intended to mean either an indirect or a direct connection. Thus, if a first device is coupled to a second device, this connection may be via a direct connection or via an indirect connection through other devices and connections.

[0015] If a layer or element is additionally described as being "on" another layer or substrate, it may be located directly on top of the other layer of the substrate, or there may be intervening layers. Furthermore, it is understood that if a layer is described as being "under" another layer, it may be located directly beneath it, and there may also be one or more intervening layers. Moreover, if a layer is described as being "between" two layers, it may be the only layer between the two layers, or there may also be one or more intervening layers.

[0016] As described, non-volatile memory systems are a type of storage that retains stored information without requiring an external power source. Non-volatile memory is widely used in various electronic devices and standalone storage devices. Examples of non-volatile memory include laptops, digital audio players, digital cameras, smartphones, video games, scientific instruments, industrial robots, medical electronics, solid-state drives, USB drives, memory cards, and the like. Non-volatile memory can be electronically programmed / reprogrammed and erased.

[0017] Examples of non-volatile memory systems include flash memory such as NAND flash or NOR flash. NAND flash memory structures typically arrange multiple memory cell transistors (e.g., floating-gate transistors or charge-trapping transistors) in series with and between two select gates (e.g., a drain-side select gate and a source-side select gate). The series-connected memory cell transistors and the select gates can be referred to as a NAND string. NAND flash memory can be scaled to reduce the cost per bit.

[0018] A programming operation for a set of memory cells in a storage device typically involves applying a series of programming voltages to the memory cells after they have been provided in an erased state. Each programming voltage is applied in a programming loop, also known as a programming verification iteration. For example, the programming voltage might be applied to a word line connected to control gates of the memory cells. One approach uses incremental step-pulse programming, where the programming voltage is increased by one step in each programming loop. After each programming voltage, verification operations can be performed to determine whether the programming of the memory cells is complete.When the programming of a memory cell is complete, it can be locked for further programming, while the programming of other memory cells continues in subsequent programming loops.

[0019] Each memory cell can be assigned a data state according to the write data in a programming instruction. Based on its data state, a memory cell either remains in the erased state or is programmed into a data state (a programmed data state) that differs from the erased state. For example, in a storage device with one bit per cell (Single-Level Cell (SLC)), there are two data states, including the erased state and a higher-level data state. In a storage device with two bits per cell (Multi-Level Cell (MLC)), there are four data states, including the erased state and three higher-level data states, designated as data states A, B, and C (see Fig. 9) In a storage device with three bits per cell (Triple-Level Cell (TLC)), there are eight data states, including the erased state, and seven higher data states, which are designated as data states A, B, C, D, E, F and G (see Fig. 10) In a storage device with four bits per cell (Quad-Level Cell (QLC)) there are sixteen data states, including the erased state, and fifteen higher data states, which are designated as data states Er, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E and F (see Fig. 11) Each memory cell can store a data state (e.g., a binary value) and is programmed to a threshold voltage state corresponding to that data state. Each state represents a different value and is assigned to a voltage window with a range of possible threshold voltages.

[0020] When a programming instruction is issued, the write data is stored in the latches associated with the memory cells. During programming, the latches of a memory cell can be read to determine the data state to which the cell is to be programmed. Each programmed data state is associated with a verification voltage, so the programming of a memory cell with a given data state is considered complete when a capture operation determines that its threshold voltage (Vth) is above the associated verification voltage. A capture operation can determine whether a memory cell has a Vth above the associated verification voltage by applying the associated verification voltage to the control gate and detecting a current through the memory cell.If the current is relatively high, this indicates that the memory cell is in a conductive state, so Vth is less than the control gate voltage. If the current is relatively low, this indicates that the memory cell is in a conductive state, so Vth is greater than the control gate voltage.

[0021] The verification voltage used to determine that the programming of a memory cell is complete can be called the final or lock verification voltage. In some cases, an additional verification voltage can be used to determine that the programming of a memory cell is nearing completion. This additional verification voltage can be called the offset verification voltage and may be lower than the final verification voltage. When the programming of a memory cell is nearly complete, the programming speed of the memory cell can be reduced, for example, by raising the voltage on a particular bit line during one or more subsequent programming voltages. For example, in Fig. 9 a memory cell to be programmed into data state A, subjected to verification tests at VvAL, an offset verification voltage of data state A, and VvA, a final verification voltage of data state A.

[0022] A programming operation can include a preload phase. During the preload phase, a channel of a NAND string in a 3D stacked memory device can be prepared for programming. For example, electron preload techniques can be used; however, when programming memory cells of a memory device operating in subblock mode using reverse order programming (ROP), one or more of the subblocks may not be preloaded using electron preload.

[0023] To further illustrate the above, Fig. 1A is now described. Fig. Figure 1A is a block diagram of an example storage device. The storage device 100 can include one or more storage dies 108. The storage die 108 includes a memory structure 126 consisting of memory cells, such as an array of memory cells, control logic 110, and read / write circuits 128. The memory structure 126 is addressable via word lines through a row decoder 124 and via bit lines through a column decoder 132. The read / write circuits 128 include several capture blocks SB1, SB2, ..., SBp (capture logic) and enable parallel reading or programming of a side of memory cells. Typically, a controller 122 is included in the same storage device 100 (e.g., a removable storage card) as the one or more storage dies 108.Commands and data are transmitted between the host 140 and the controller 122 via a data bus 120 and between the controller and the one or more memory dies 108 via lines 118.

[0024] The memory structure can be 2D or 3D. It can comprise one or more arrays of memory cells, including a 3D array. The memory structure can be a monolithic three-dimensional structure in which multiple memory layers are formed on top of (and not within) a single substrate, such as a wafer, without intervening substrates. The memory structure can include any type of non-volatile memory monolithically formed in one or more physical layers of arrays of memory cells, each with an active area arranged on top of a silicon substrate. The memory structure can be contained within a non-volatile memory device that includes switching logic associated with the operation of the memory cells, regardless of whether the associated switching logic is located on top of or within the substrate.

[0025] The control logic 110 works in conjunction with the read / write circuits 128 to perform memory operations on the memory structure 126 and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip-level control of memory operations. A memory area 113 can be provided, for example, for the verification parameters described herein.

[0026] The on-chip address decoder 114 provides an address interface between the hardware address used by the host or a memory controller and the hardware address used by decoders 124 and 132. The power control module 116 controls the power and voltages supplied to the word lines and bit lines during memory operations. It may include drivers for word lines, SGS and SGD transistors, and source lines. In one approach, the capture blocks may include bit line drivers. An SGS transistor is a select-gate transistor at the source end of a NAND string, and an SGD transistor is a select-gate transistor at the drain end of a NAND string.

[0027] In some implementations, some of the components can be combined. In various designs, one or more of the components (alone or in combination), with the exception of the memory structure 126, can be considered as at least one control circuit configured to perform the actions described herein. For example, a control circuit can include any or a combination of the control switching logic 110, the state machine 112, the decoders 114 / 132, the power control module 116, the acquisition blocks SBb, SB2, ..., SBp, the read / write circuits 128, the controller 122, and so on.

[0028] The control circuitry can include a programming circuit configured to program memory cells of a word line within a block and to verify the set of memory cells. The control circuitry can also include a counting circuit configured to determine the number of memory cells verified as being in a data state. Furthermore, the control circuitry can include a determination circuit configured to determine, based on this count, whether the block is faulty.

[0029] For example, Fig. Figure 1B shows a block diagram of an example control circuit 150, comprising a programming circuit 151, a counting circuit 152, and a determination circuit 153. The programming circuit can include software, firmware, and / or hardware. The counting circuit can include software, firmware, and / or hardware. The determination circuit can include software, firmware, and / or hardware.

[0030] The off-chip controller 122 can include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, and an error correction code engine (ECC engine) 245. The ECC engine can correct a number of read errors caused by the upper bound of a Vth distribution becoming too high. However, in some cases, uncorrectable errors may occur. The techniques provided here reduce the probability of uncorrectable errors.

[0031] The storage device comprises code, such as a set of instructions, and the processor is operable to execute the set of instructions to provide the functionality described herein. Alternatively or additionally, the processor can access code from a storage device 126a of the memory structure, such as a reserved area of ​​memory cells in one or more word lines.

[0032] For example, the controller 122 can use code to access the memory structure, such as for programming, reading, and erasing operations. The code can include boot code and control code (e.g., instruction sets). The boot code is software that initializes the controller during a boot or startup process and allows the controller access to the memory structure. The controller can use this code to control one or more memory structures. After power-up, the processor 122c retrieves the boot code from the ROM 122a or the storage device 126a for execution. The boot code initializes the system components and loads the control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor.The control code includes drivers to perform basic tasks such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0033] In one embodiment, the host is a computing device (e.g., laptop, desktop, smartphone, tablet, digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) that store processor-readable code (e.g., software) for programming the one or more processors to perform the procedures described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0034] Besides NAND flash memory, other types of non-volatile memory can also be used.

[0035] Semiconductor memory devices include volatile memory devices such as dynamic random-access memory (DRAM) or static random-access memory (SRAM), non-volatile memory devices such as resistive random-access memory (ReRAM), electrically erasable programmable read-only memory (EEPROM), flash memory (which can also be considered a subset of EEPROM), ferroelectric random-access memory (FRAM), and magnetoresistive random-access memory (MRAM), and other semiconductor devices capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in a NAND or NOR configuration.

[0036] The memory devices can be composed of passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistive switching storage element, such as an anti-fuse or a phase-change material, and optionally a control element, such as a diode or a transistor. As another non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a dielectric charge storage material.

[0037] Multiple memory elements can be configured to be connected in series or so that each element is individually accessible. As a non-restrictive example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND string is an example of a set of transistors connected in series, comprising memory cells and SG transistors.

[0038] A NAND memory array can be configured so that the array consists of multiple strings of memory, where a string is composed of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured so that each element can be accessed individually, such as a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways as well.

[0039] The semiconductor memory elements, which are located within and / or above a substrate, can be arranged in two or three dimensions, such as a two-dimensional memory structure or a three-dimensional memory structure.

[0040] In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device plane. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane (e.g., in a plane in the xy direction) that extends substantially parallel to a major surface of a substrate that supports the memory elements. The substrate can be a wafer over or in which the layer of memory elements is formed, or it can be a support substrate that is attached to the memory elements after they have been formed. As a non-restrictive example, the substrate can contain a semiconductor such as silicon.

[0041] The memory elements can be arranged in an ordered array within a single storage device level, such as in a multitude of rows and / or columns. However, the memory elements can also be arranged in irregular or non-orthogonal configurations. Each memory element can have two or more electrodes or contact lines, for example, bit lines and word lines.

[0042] A three-dimensional storage array is arranged such that storage elements occupy multiple levels or multiple storage device levels, thereby forming a structure in three dimensions (i.e., in the x, y, and z directions, with the z direction being essentially perpendicular and the x and y directions being essentially parallel to the main surface of the substrate).

[0043] As a non-restrictive example, a three-dimensional storage structure can be arranged vertically as a stack of multiple two-dimensional storage device levels. As another non-restrictive example, a three-dimensional storage array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), with each column containing multiple storage elements. The columns can be arranged in a two-dimensional configuration, e.g., in an xy-plane, resulting in a three-dimensional array of storage elements with elements on multiple vertically stacked storage levels. Other configurations of storage elements in three dimensions can also form a three-dimensional storage array.

[0044] As a non-restrictive example, in a three-dimensional NAND memory array, the memory elements can be coupled to form a NAND string within a single horizontal (e.g., xy) memory device plane. Alternatively, the memory elements can be coupled to form a vertical NAND string that traverses multiple horizontal memory device planes. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements in a single memory plane, while other strings contain memory elements spanning multiple memory planes. Three-dimensional memory arrays can also be designed in a NOR configuration and in a ReRAM configuration.

[0045] Typically, in a monolithic three-dimensional storage array, one or more storage device layers are formed on top of a single substrate. Optionally, the monolithic three-dimensional storage array can also have one or more storage layers at least partially within the single substrate. As a non-restrictive example, the substrate can contain a semiconductor such as silicon. In a monolithic three-dimensional array, the layers that constitute each storage device layer of the array are usually formed on top of the layers of the underlying storage device layers of the array. However, layers of adjacent storage device layers in a monolithic three-dimensional storage array can be shared, or there can be intermediate layers between the storage device layers.

[0046] On the other hand, two-dimensional arrays can be fabricated separately and then packed together to form a non-monolithic, multi-layered memory device. For example, non-monolithic stacked memories can be constructed by fabricating memory layers on separate substrates and then stacking the memory layers on top of each other. The substrates can be thinned or removed from the memory device layers before stacking, but because the memory device layers are initially fabricated on separate substrates, the resulting memory arrays are not monolithic three-dimensional memory arrays. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be fabricated on separate chips and then packed together to form a stacked-chip memory device.

[0047] Operating and communicating with memory elements typically requires associated switching logic. Non-restrictive examples include switching logic used to control and manage memory elements to perform functions such as programming and reading. This associated circuitry may reside on the same substrate as the memory elements and / or on a separate substrate. For instance, a memory read / write controller may reside on a separate controller chip and / or on the same substrate as the memory elements.

[0048] The person skilled in the art will recognize that this technology is not limited to the two-dimensional and three-dimensional exemplary structures described, but covers all relevant storage structures within the meaning and scope of protection of the technology described herein and understandable to the person skilled in the art.

[0049] Fig. 2 represents blocks of memory cells in a two-dimensional example configuration of the memory array 126 of Fig. 1A represents the memory array, which can contain many blocks. Each example block 200, 210 contains a number of NAND strings and corresponding bit lines, e.g., BL0, BL1, ..., which are shared among the blocks. Each NAND string is connected at one end to a drain selector gate (SGD), and the control gates of the drain selector gates are connected via a common SGD line. The NAND strings are connected at their other end to a source selector gate, which in turn is connected to a common source line 220. Sixteen word lines, for example, WL0 to WL15, extend between the source selector gates and the drain selector gates. In some cases, dummy word lines, which do not contain user data, can be used in the memory array in addition to the selector gate transistors. Such dummy word lines can protect the edge data word line from certain edge effects.

[0050] One type of non-volatile memory that can be provided in the memory array is floating-gate memory. See Fig. 3A and Fig. 3B. Other types of non-volatile memory can also be used. For example, a charge-trapping storage cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge non-volatilely. See Fig. 4A and Fig. 4B. A three-layer dielectric consisting of silicon oxide, silicon nitride, and silicon oxide (“ONO”) is positioned between a conductive control gate and the surface of a semiconductor substrate over the memory cell channel. Programming the cell is achieved by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a limited region. This stored charge then modifies the threshold voltage of a portion of the cell channel in a detectable manner. Erasing the cell is accomplished by injecting hot holes into the nitride. A similar cell can be provided in a split-gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate selection transistor.

[0051] Another approach uses NROM cells. For example, each NROM cell stores two bits, with a dielectric ONO layer extending across the channel between source and drain diffusions. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multistate data storage is achieved by separately reading the binary states of the spatially separated charge storage regions within the dielectric. Other types of non-volatile memory are also known.

[0052] Fig. Figure 3A shows a cross-sectional view of example floating-gate memory cells in NAND strings. The direction of a bit line or NAND string is inward, and the direction of a word line is from left to right. For example, word line 324 extends across NAND strings that enclose the respective channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and channel region 326. Each memory cell is located in a separate NAND string. An inter-polydielectric layer (IPD layer) 328 is also shown. The control gates are part of the word line.A cross-sectional view along line 329 is in . Fig. 3B provided.

[0053] The control gate wraps around the floating gate, thus increasing the surface contact area between them. This results in a higher IPD capacity and therefore a higher coupling ratio, which facilitates programming and erasing. However, as the size of NAND flash memory devices decreases, the distance between adjacent cells also decreases, leaving almost no space between two adjacent floating gates for the control gate and the IPD. Alternatively, as in Fig. 4A and Fig. Figure 4B shows the flat or planar memory cell developed in which the control gate is flat or planar; that is, it does not wrap around the floating gate and its only contact with the charge storage layer is from above. In this case, a tall floating gate offers no advantage. Instead, the floating gate is made much thinner. Furthermore, the floating gate can be used to store charge, or a thin charge-trapping layer can be used to trap charge. This approach avoids the problem of ballistic electron transport, where an electron can migrate through the floating gate after tunneling through the tunnel oxide during programming.

[0054] Fig. 3B shows a cross-sectional view of the structure of Fig. 3A along line 329. The NAND string 330 includes an SGS transistor 331, example memory cells 300, 333, ... , 334 and 335, and an SGD transistor 336. Memory cell 300 includes, as an example for each memory cell, the control gate 302, the IPD layer 328, the floating gate 304, and the tunnel oxide layer 305, in accordance with Fig. 3A. Through-holes in the IPD layer of the SGS and SGD transistors enable communication between the control-gate and floating-gate layers. The control-gate and floating-gate layers can be made of polysilicon, for example, and the tunnel oxide layer can be made of silicon oxide. The IPD layer can be a stack of nitrides (N) and oxides (O), as in a NONON configuration.

[0055] The NAND string can be formed on a substrate comprising a p-type substrate region 355, an n-type well 356, and a p-type well 357. Within the p-type well, n-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed. A channel voltage Vch can be applied directly to the channel region of the substrate.

[0056] Fig. Figure 4A shows a cross-sectional view of example charge-trapping memory cells in NAND strings. The view is word-directed of memory cells, which include a flat control gate and charge-trapping areas as a 2D example of memory cells in the memory cell array 126 of Fig. 1A. Charge-trapping memory can be used in NOR and NAND flash memory devices. This technology uses an insulator, such as a SiN film, to store electrons, in contrast to a floating-gate MOSFET technology, which uses a conductor, such as doped polycrystalline silicon, to store electrons. As an example, a word line (WL) 424 extends across NAND strings, enclosing respective channel regions 406, 416, and 426. Sections of the word line provide control gates 402, 412, and 422. Beneath the word line are an IPD layer 428, charge-trapping layers 404, 414, and 421, polysilicon layers 405, 415, and 425, and tunnel layer layers 409, 407, and 408. Each charge-trapping layer extends continuously across a respective NAND string.

[0057] A memory cell 400 includes the control gate 402, the charge trap layer 404, the polysilicon layer 405, and a section of the channel region 406. A memory cell 410 includes the control gate 412, the charge trap layer 414, a polysilicon layer 415, and a section of the channel region 416. A memory cell 420 includes the control gate 422, the charge trap layer 421, the polysilicon layer 425, and a section of the channel region 426.

[0058] Here, a flat control gate is used instead of a control gate that wraps around a floating gate. One advantage is that the charge trap layer can be made thinner than with a floating gate. Furthermore, the memory cells can be placed closer together.

[0059] Fig. Figure 4B shows a cross-sectional view of the structure of Fig. 4A along line 429. The view shows a NAND string 430 with a flat control gate and a charge trap layer. The NAND string 430 includes an SGS transistor 431, example memory cells 400, 433, ... , 434 and 435, and an SGD transistor 436.

[0060] The NAND string can be formed on a substrate comprising a p-type substrate region 455, an n-type well 456, and a p-type well 457. Within the p-type well 457, n-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed. A channel voltage Vch can be applied directly to the channel region of the substrate. The memory cell 400 includes the control gate 402 and the IPD layer 428 above the charge trap layer 404, the polysilicon layer 405, the tunnel layer 409, and the channel region 406.

[0061] The control gate layer can be, for example, polysilicon and the tunnel layer silicon oxide. The IPD layer can be a stack of high-k dielectrics such as AlOx or HfOx, which help to increase the coupling ratio between the control gate layer and the charge-trapping or charge-storage layer. The charge-trapping layer can be, for example, a mixture of silicon nitride and silicon oxide.

[0062] The SGD and SGS transistors have the same configuration as the memory cells, but a longer channel length to ensure that the current is cut off in an inhibited NAND string.

[0063] In this example, layers 404, 405, and 409 extend continuously into the NAND string. Alternatively, sections of layers 404, 405, and 409 located between control gates 402, 412, and 422 can be removed, exposing the top surface of channel 406.

[0064] Fig. 5A presents an example block diagram of the data acquisition block SB 1 of Fig. 1A. In one approach, a capture block comprises multiple capture circuits. Each capture circuit is associated with data latches. For example, the example capture circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different subsets of bit lines can be captured using different respective capture blocks. This allows the processing load associated with the capture circuits to be distributed and handled by a separate processor in each capture block. For example, a capture circuit controller 560 in SB 1 can communicate with the set of capture circuits and latches. The capture circuit controller can include a preload circuit 561, which provides a voltage to each capture circuit to set a preload voltage. In one possible approach, the voltage is provided independently to each capture circuit, e.g.,via the data bus DBUS 503 and a local bus such as LBUS1 or LBUS2 in . Fig. 5B. In another possible approach, a common voltage is supplied to each detection circuit simultaneously, e.g. via line 505 in Fig. 5B. The detection circuit controller can also include a memory chip 562 and a processor 563. As also in conjunction with Fig. As mentioned in Section 2, memory 562 can store code that can be executed by the processor to perform the functions described herein. These functions may include reading latches associated with the capture circuits, setting bit values ​​in the latches, and providing voltages to set preload levels in the capture nodes of the capture circuits. Further example details of the capture circuit controller and the 550a and 551a capture circuits are provided below.

[0065] Fig. 5B presents another example block diagram of the data acquisition block SB1 from Fig. 1A. The 560 acquisition circuit controller communicates with several acquisition circuits, including the example acquisition circuits 550a and 551a, also shown in Fig. 5A. The capture circuit 550a includes latches 550b, including a trigger latch 526, an offset verification latch 527, and data state latches 528. The capture circuit further includes a voltage terminal 521, such as a transistor, which sets a pre-charge voltage at a capture node 522. A capture node-to-bit-line switch (BL switch) 523 allows the capture node to selectively communicate with a bit line 525, e.g., the capture node is electrically connected to the bit line so that the capture node voltage can drop. The bit line 525 is connected to one or more memory cells, such as memory cell MC1. A voltage terminal 524 can set a voltage on the bit line, such as during a capture operation or during a programming voltage.A local bus, LBUS1, allows the acquisition circuit controller to communicate with components in the acquisition circuit, such as the latches 550b and, in some cases, the voltage terminal. To communicate with the acquisition circuit 550a, the acquisition circuit controller applies a voltage via line 502 to a transistor 504 to connect LBUS1 to a data bus, DBUS 503. Communication can include sending data to the acquisition circuit and / or receiving data from the acquisition circuit.

[0066] The acquisition circuit controller can, for example, communicate with different acquisition circuits in a time-division multiplex. In one approach, a 505 line can be connected to the voltage terminal in each acquisition circuit.

[0067] The capture circuit 551a includes latches 551b, including a trigger latch 546, an offset verification latch 547, and data state latches 548. A voltage terminal 541 can be used to set a pre-charge voltage at a capture node 542. A capture node-to-bit-line switch (BL switch) 543 allows the capture node to selectively communicate with a bit line 545, and a voltage terminal 544 can set a voltage on the bit line. The bit line 545 is connected to one or more memory cells, such as a memory cell MC2. A local bus, LBUS2, allows the capture circuit controller to communicate with components in the capture circuit, such as the latches 551b and, in some cases, the voltage terminal. To communicate with the sensing circuit 551a, the sensing circuit controller provides a voltage to a transistor 506 via a line 501 to connect LBUS2 to DBUS.

[0068] The detection circuit 550a can be a first detection circuit comprising a first release latch 526, and the detection circuit 551a can be a second detection circuit comprising a second release latch 546.

[0069] The acquisition circuit 550a is an example of a first acquisition circuit comprising a first acquisition node 522, where the first acquisition circuit is associated with a first memory cell MC1 and a first bit line 525. The acquisition circuit 551a is an example of a second acquisition circuit comprising a second acquisition node 542, where the second acquisition circuit is associated with a second memory cell MC2 and a second bit line 545.

[0070] Fig. Figure 6A is a perspective view of a set of blocks 600 in a three-dimensional example configuration of the memory array 126 of Fig. 1A. On the substrate are example blocks BLK0, BLK1, BLK2, and BLK3 of the memory cells (storage elements) and a peripheral area 604 containing switching logic for use by the blocks. For example, the switching logic can include voltage drivers 605 that can be connected to control gate layers of the blocks. In one approach, control gate layers at a common level in the blocks are jointly driven. The substrate 601 can also carry switching logic below the blocks, along with one or more lower metal layers structured in conductive paths to carry signals from the switching logic. The blocks are formed in an intermediate area 602 of the memory device. In an upper area 603 of the memory device, one or more upper metal layers are structured in conductive paths to carry signals from the switching logic.Each block comprises a stacked array of memory cells, with alternating levels of the stack representing word paths. In one possible approach, each block has opposing layered sides from which vertical contacts extend upward to an upper metal layer to form connections to conductive paths. While four blocks are shown as an example, two or more blocks extending in the x and / or y direction can be used.

[0071] In one possible approach, the length of the plane in the x-direction represents a direction in which signal paths extend to word lines in the one or more upper metal layers (a word line or SGD line direction), and the width of the plane in the y-direction represents a direction in which signal paths extend to bit lines in the one or more upper metal layers (a bit line direction). The z-direction represents a height of the storage device.

[0072] Fig. Figure 6B shows an example cross-sectional view of a section of one of the blocks of Fig. 6A. The block comprises a stack 610 of alternating conductive and dielectric layers. In this example, the conductive layers comprise two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1, in addition to the data word line layers (word lines) WLLO to WLL10. The dielectric layers are labeled DL0 to DL19. Also shown are regions of the stack containing the NAND strings NS1 and NS2. Each NAND string surrounds a memory hole 618 or 619, which is filled with materials forming memory cells adjacent to the word lines. A region 622 of the stack is shown in detail in Fig. 6D.

[0073] The stack includes a substrate 611, an insulating film 612 on the substrate, and a section of a source line SL. NS 1 has a source end 613 at the bottom 614 of the stack and a drain end 615 at the top 616 of the stack. Metal-filled slots 617 and 620 may be provided periodically across the stack as intermediate connections extending through the stack, such as to connect the source line to a line above the stack. The slots may be used during the formation of the word lines and subsequently filled with metal. A section of a bit line BL0 is also shown. A conductive via 621 connects the drain end 615 to BL0.

[0074] Fig. 6C presents a diagram of the memory hole diameter in the stack of Fig. 6B represents the vertical axis aligned with the stack of Fig. 6B and represents a width (wMH), e.g., the diameter, of memory holes 618 and 619. The word line layers WLLO to WLL10 of Fig. 6A are repeated as an example and are located at respective heights z0 to z10 in the stack. In such a storage device, the storage holes etched through the stack have a very high aspect ratio. A depth-to-diameter ratio of approximately 25 to 30 is common, for example. The storage holes can have a circular cross-section. Due to the etching process, the width of the storage hole can vary along its length. Typically, the diameter gradually decreases from top to bottom within the storage hole. That is, the storage holes are conical and narrow towards the bottom of the stack. In some cases, there is a slight constriction at the top of the hole near the select gate, so that the diameter initially becomes somewhat larger before gradually decreasing from top to bottom within the storage hole.

[0075] Due to the uneven width of the memory hole, the programming speed, including the programming slope and erase speed of the memory cells, can vary depending on their position along the memory hole, e.g., based on their height in the stack. For a memory hole with a smaller diameter, the electric field across the tunnel oxide is relatively stronger, resulting in relatively higher programming and erase speeds. One approach is to define groups of adjacent word lines with similar memory hole diameters, e.g., within a defined diameter range, and to apply an optimized verification scheme to each word line in a group. Different groups can have different optimized verification schemes.

[0076] Fig. 6D shows a close-up of area 622 of the stack of Fig. 6B. Memory cells are formed at the different levels of the stack at the interface of a word line layer and a memory hole. In this example, the SGD transistors 680 and 681 are provided above the dummy memory cells 682 and 683 and a data memory cell MC. A number of layers can be deposited along the side wall (SW) of the memory hole 630 and / or within each word line layer, for example, using atomic layer deposition. For example, each column (e.g., the support formed by the materials within a memory hole) can include a charge-trapping layer or film 663 such as SiN or another nitride, a tunnel layer 664, a polysilicon body or channel 665, and a dielectric core 666. A word conduction layer can include a high k-value barrier oxide / block material 660, a metal barrier 661, and a conductive metal 662 such as tungsten as a control gate.For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal are provided in the memory hole. In other approaches, some of the layers may be located in the control gate layer. Similarly, additional supports are created in the different memory holes. A support can form a columnar active region (AA) of a NAND string.

[0077] When a memory cell is programmed, electrons are stored in a section of the charge-trapping layer associated with that cell. These electrons are drawn from the channel and through the tunneling layer into the charge-trapping layer. The Vth of a memory cell increases proportionally to the amount of stored charge. During an erasure operation, the electrons return to the channel.

[0078] Each of the storage holes can be filled with a variety of ring-shaped layers, including a barrier oxide layer, a charge-trapping layer, a tunneling layer, and a channeling layer. A core region of each storage hole is filled with a body material, and the variety of ring-shaped layers are located between the core region and the word lead in each of the storage holes.

[0079] It can be assumed that the NAND string has a floating-body channel, since the channel length is not formed on a substrate. Furthermore, the NAND string is provided by a multitude of word conduction layers stacked on top of each other and separated by dielectric layers.

[0080] Fig. 7A shows a top view of an example word management layer WLLO of the stack of Fig. Figure 6B represents the process. As mentioned, a 3D memory device can comprise a stack of alternating conductive and dielectric layers. The conductive layers provide the control gates for the SG transistors and memory cells. The layers used for the SG transistors are SG layers, and the layers used for the memory cells are word line layers. Furthermore, memory holes are formed in the stack and filled with a charge-trapping material and a channel material. As a result, a vertical NAND string is formed. Source lines are connected to the NAND strings below the stack, and bit lines are connected to the NAND strings above the stack.

[0081] A BLK block in a 3D storage device can be subdivided into subblocks, each subblock comprising a set of NAND strings sharing a common SGD control line. For example, see the SGD lines / control gates SGD0, SGD1, SGD2, and SGD3 in subblocks SBa, SBb, SBc, and SBd, respectively. The subblocks SBa, SBb, SBc, and SBd can also be referred to here as a word line memory string. As described, a word line memory string can include a plurality of memory cells that are part of the same subblock and are also located in the same word line layer and / or are configured so that their control gates are biased by the same word line and / or with the same word line voltage.

[0082] Furthermore, a word-conductor layer within a block can be subdivided into regions. Each region is located within a separate subblock and can extend between slots formed at regular intervals in the stack to process the word-conductor layers during the storage device manufacturing process. This processing may include replacing sacrificial material within the word-conductor layers with metal. Generally, the spacing between the slots should be relatively small to accommodate the limited distance an etching agent can travel laterally to remove the sacrificial material and the distance the metal can travel to fill a cavity created by the removal of the sacrificial material. For example, the slot spacing may allow for several rows of storage holes between adjacent slots.When designing the memory holes and slots, consideration should also be given to limiting the number of bit lines that can span the area, with each bit line connected to a different memory cell. After the word line layers have been processed, the slots can optionally be filled with metal to provide an intermediate connection through the stack.

[0083] These and other figures are not necessarily to scale. In practice, the areas in the x-direction may be much longer relative to the y-direction than depicted, in order to accommodate additional memory slots.

[0084] In this example, there are four rows of memory holes between adjacent slots. A row is a group of memory holes aligned in the x-direction. Furthermore, the rows of memory holes are staggered to increase the memory hole density. The word line layer, or word line, is divided into regions WLLO a, WLLO b, WLLO c, and WLLO d, each connected by a connector 713. In one approach, the last region of a word line layer in a block can be connected to the first region of a word line layer in the next block. The connector, in turn, is connected to a voltage driver for the word line layer. Region WLLO a contains example memory holes 710 and 711 along a line 712. Region WLLO b contains example memory holes 714 and 715. Region WLLO c contains example memory holes 716 and 717.The WLLO d area contains example memory holes 718 and 719. These memory holes are also shown in [reference missing]. Fig. 7B. Each memory hole can be part of a respective NAND string. For example, memory holes 710, 714, 716, and 718 can be part of the NAND strings NS0_SBa, NS0_SBb, NS0_SBc, and NS0_SBd, respectively.

[0085] Each circle represents the cross-section of a memory hole in a word-line layer, or SG layer. Example circles shown with dashed lines represent memory cells provided by the materials in the memory hole and by the adjacent word-line layer. For example, memory cells 720 and 721 are in WLLO a, memory cells 724 and 725 are in WLLO b, memory cells 726 and 727 are in WLLO c, and memory cells 728 and 729 are in WLLO d. These memory cells are located at a common height in the stack.

[0086] Metal-filled slots 701, 702, 703, and 704 (e.g., metal intermediate connections) can be arranged between and adjacent to the edges of regions WLLO a to WLLO d. The metal-filled slots provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack can be connected to a conductive line above the stack, with the conductive line being connected to a voltage driver in a peripheral region of the storage device. See also Fig. 8A for further details on sub-blocks SBa to SBd of Fig. 7A.

[0087] Fig. Figure 7B shows a top view of an upper dielectric example layer DL19 of the stack of Fig. Figure 6B represents the dielectric layer, which is divided into regions DL19a, DL19b, DL19c, and DL19d. Each region can be connected to a corresponding voltage driver. This allows a set of memory cells in a region of a word line layer to be programmed simultaneously, with each memory cell located in a separate NAND string connected to a separate bit line. A voltage can be set on each bit line to allow or inhibit programming during each programming voltage.

[0088] The area DL19a features example memory holes 710 and 711 along a line 712a that coincides with a bit line BL0. A number of bit lines extend over and are connected to the memory holes, as indicated by the "X" symbols. BL0 is connected to a set of memory holes that includes memory holes 711, 715, 717, and 719. Another example bit line, BL1, is connected to a set of memory holes that includes memory holes 710, 714, 716, and 718. The metal-filled slots 701, 702, 703, and 704 of Fig. 7A are also shown, as they extend vertically through the stack. The bit lines can be numbered in sequence BL0 to BL23 across the DL19 layer in the -x direction.

[0089] Different subsets of bit lines are connected to cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, and BL20 are connected to cells in the first row at the right edge of each area. BL2, BL6, BL10, BL14, BL18, and BL22 are connected to cells in an adjacent row that is connected to the first row at the right edge. BL3, BL7, BL11, BL15, BL19, and BL23 are connected to cells in the first row at the left edge of each area. BL1, BL5, BL9, BL13, BL17, and BL21 are connected to cells in an adjacent row that is connected to the first row at the left edge.

[0090] Fig. 8A provides example NAND strings in subblocks SBa to SBd of Fig. 7A represents the sub-blocks corresponding to the structure of Fig. 6B. The conductive layers in the stack are shown on the left for reference. Each subblock contains multiple NAND strings, with one example NAND string shown. For example, SBa contains an example NAND string NS0_SBa, SBb contains an example NAND string NS0_SBb, SBc contains an example NAND string NS0_SBc, and SBd contains an example NAND string NS0_SBd.

[0091] Additionally, NS0_SBa includes SGS transistors 800 and 801, dummy memory cells 802 and 803, data memory cells 804, 805, 806, 807, 808, 809, 810, 811, 812, 813 and 814, dummy memory cells 815 and 816, and SGD transistors 817 and 818.

[0092] NS0_SBa includes SGS transistors 820 and 821, dummy memory cells 822 and 823, data memory cells 824, 825, 826, 827, 828, 829, 830, 831, 832, 833 and 834, dummy memory cells 835 and 836, and SGD transistors 837 and 838.

[0093] NS0_SBc includes SGS transistors 840 and 841, dummy memory cells 842 and 843, data memory cells 844, 845, 846, 847, 848, 849, 850, 851, 852, 853 and 854, dummy memory cells 855 and 856, and SGD transistors 857 and 858.

[0094] NS0_SBd includes SGS transistors 860 and 861, dummy memory cells 862 and 863, data memory cells 864, 865, 866, 867, 868, 869, 870, 871, 872, 873 and 874, dummy memory cells 875 and 876, and SGD transistors 877 and 878.

[0095] For a given height in the block, a set of memory cells in each subblock is located at a common height. For example, one set of memory cells (including memory cell 804) is formed among a multitude of memory cells along tapered memory holes in a stack of alternating conductive and dielectric layers. One set of memory cells is located at a specific height z0 in the stack. Another set of memory cells (including memory cell 824), associated with one word line (WLL0), is also located at that specific height. In another approach, the set of memory cells (e.g., including memory cell 812), associated with another word line (e.g., WLL8), is located at a different height (z8) in the stack.

[0096] Fig. Figure 8B presents another example view of NAND strings in subblocks. The NAND strings include NS0_SBa, NS0_SBb, NS0_SBc, and NS0_SBd, which in this example have 48 word lines, WL0 to WL47. Each subblock comprises a set of NAND strings extending in the x-direction and sharing a common SGD line, such as SGD0, SGD1, SGD2, or SGD3. In this simplified example, there is only one SGD transistor and one SGS transistor in each NAND string. The NAND strings NS0_SBa, NS0_SBb, NS0_SBc, and NS0_SBd are each located in the subblocks SBa, SBb, SBc, and SBd, respectively. Furthermore, groups of word lines G0, G1, and G2 are shown as examples.

[0097] Fig. Figure 8C illustrates a general schematic view of three versions of a staggered string architecture 101, 103, and 105 for BiCS memory, e.g., NAND. Referring to string architecture 101, the strings in rows 107-0 to 107-7 of architecture 101 are shown. Each row is shown with four string ends. A string may be joined at one end to an adjacent string (not visible below this view). A first group of rows, 107-0 to 107-3, is shown on the left side of a dummy row 108. A second group of rows, 107-4 to 107-7, is shown on the right side of dummy row 108. Dummy row 108 separates the two row groups in the staggered eight rows. Source line 109 is positioned at one edge of the first group and is located away from dummy line 108. Source line 110 is positioned at one edge of the second group and is located away from dummy line 108 and source line 109.

[0098] The staggered string architectures 103 and 105 for BiCS storage are similar to architecture 101, except that additional groups are added. Architecture 103 is twice the size of architecture 101 and includes sixteen lines of strings, with each group of four lines separated by a dummy line. Architecture 105 is larger than both architecture 101 and architecture 103. Architecture 105 includes twenty lines of strings, with each group of four lines separated by a dummy line (108).

[0099] These architectures 101, 103, and 105 can incorporate a chip-under-array structure, meaning the control switching logic resides beneath the memory array, which can contain groups of memory strings. In the chip-under-array structure, the strings can include a direct strap contact for the source line for read and erase operations.

[0100] Fig. Figure 12 shows a waveform of an example programming operation. The horizontal axis represents the number of programming loops, and the vertical axis represents the control gate or word line voltage. In general, a programming operation can involve applying a pulse train to a selected word line, where the pulse train includes multiple programming loops or programming verification iterations (PV iterations). The programming portion of the programming verification iteration includes a programming voltage, and the verification portion of the programming verification iteration includes one or more verification voltages.

[0101] For simplicity, a square waveform is shown for each programming voltage, although other shapes are possible, such as a multi-stage waveform or a ramp waveform. Furthermore, this example uses incremental step-pulse programming (ISPP), where the programming voltage is increased in each successive programming loop. This example uses ISPP in a single programming stage, in which the programming is completed. ISPP can also be used in any programming stage of a multi-stage operation.

[0102] A pulse train typically includes programming voltages whose amplitude incrementally increases in each programming verification iteration, using a fixed or varying step size. A new pulse train can be applied at each programming stage of a multi-stage programming process, starting at an initial Vpgm level and ending at a final Vpgm level that does not exceed a maximum allowable level. The initial Vpgm levels can be the same or different at different programming stages. The final Vpgm levels can also be the same or different at different programming stages. The step size can be the same or different at different programming stages. In some cases, a smaller step size is used in a final programming stage to reduce the Vth distribution widths.

[0103] The pulse sequence 900 includes a series of programming voltages 901, 902, 903, 904, 905, 906, 907, 908, 909, 910, 911, 912, 913, 914, and 915, which are applied to a word line selected for programming and an associated set of non-volatile memory cells. Based on the target data states to be verified, one, two, or three verification voltages are provided after each programming voltage, as an example. 0 V can be applied to the selected word line between the programming and verification voltages. For example, an A-state verification voltage of VvA (e.g., waveform or programming signal 916) can be applied after each of the first, second, and third programming voltages 901, 902, and 903, respectively. A and B state verification voltages of VvA and VvB (e.g. programming signal 917) can each be applied after each of the fourth, fifth and sixth programming voltages 904, 905 and 906.A, B, and C state verification voltages of VvA, VvB, and VvC (e.g., programming signal 918) can each be applied after each of the seventh and eighth programming voltages 907 and 908. B and C state verification voltages of VvB and VvC (e.g., programming signal 919) can each be applied after each of the ninth, tenth, and eleventh programming voltages 909, 910, and 911. Finally, a C state verification voltage of VvC (e.g., programming signal 1020) can be applied after each of the twelfth, thirteenth, fourteenth, and fifteenth programming voltages 912, 913, 914, and 915, respectively.

[0104] Fig. 13A and Fig. Figure 13B shows threshold voltage distributions (Vth distributions) of memory cells in a two-stage example programming process. In particular, the memory cells are initially in the erased state (bits 11), as represented by the Vth distribution 1000, which is shown in Fig. 13A is shown. Fig. Figure 13B presents Vth distributions of memory cells after a first programming stage and a second programming stage of the two-stage example programming process with four data states. Although two programming stages and four data states are shown, it is understood that any number of programming stages can be used (e.g., three or four programming stages) and any number of data states can be considered.

[0105] In this example, the first programming stage causes the Vth of the cells in states A, B, and C to reach the Vth distributions 1002a, 1004a, and 1006a, using initial verification voltages of VvAf, VvBf, and VvCf, respectively. This first programming stage can be a coarse programming approach, for example, using a relatively large step size, so that the Vth distributions 1002a, 1004a, and 1006a are relatively wide. The second programming stage can use a smaller step size and causes the Vth distributions 1002a, 1004a, and 1006a to transition to the final Vth distributions 1002, 1004, and 1006 using second verification voltages of VvA, VvB, and VvC, respectively (e.g., narrower than Vth distributions 1002a, 1004a, and 1006a). This two-stage programming process allows for the achievement of relatively narrow Vth distributions. A small number of cells in state A, B, and C (e.g.,(smaller than a predetermined number of the multitude of memory cells) can have a Vth that is below VvA, VvB or VvC due to a bit-ignoring criterion.

[0106] Furthermore, a programming process can also include a preload phase. During the preload phase, a channel of a NAND string in a 3D stacked memory device can be prepared for programming. For example, the CPWELL preload technique can be used to improve top-end erasure during reverse order programming (ROP) by introducing holes into the channel. To illustrate, a common architecture for a memory device using a NAND flash memory structure includes a multitude of NAND strings within a single memory block. In some cases, the NAND strings within a memory block can share a common well (e.g., a p-well). As in Fig. As shown in Figure 14A, the BiCS cell-next-array (CNA) structure encloses a p-well beneath a vertical memory hole or support. The memory hole extends vertically into the stack and encompasses memory cells, as in a vertical NAND string. As shown in Fig. As shown in 14A, applying a positive voltage (e.g. 2.2 V) to the p-tub forces holes into the channel, which helps to pre-charge the channel and improves the boosting potential.

[0107] Fig. Figure 14B provides an exemplary embodiment of a BiCS-CMOS under-array (CUA) structure. Fig. 14B is a NAND string connected to a common source line via its source-side select transistor SGS1 (e.g., controlled by the select line SGS1) and to its corresponding bit line via its drain-side select transistor SGD1 (e.g., controlled by the select line SGD1). For illustrative purposes, the BiCS-CMOS-CUA structure of Fig. Figure 14B shows the selection gates SGS0, SGS1, SGD0, and SGD1. However, according to the embodiments described herein, the BiCS CMOS CUA structure can have any number of selection gates.

[0108] As further in Fig. As shown in Figure 14B, the BiCS-CUA structure does not include a p-tub for hole supply. Therefore, the CPWELL preloading technique cannot be implemented on the BiCS-CUA structure.

[0109] The embodiments described herein provide alternative techniques for increasing the ROP potential of the BiCS-CUA architecture. More specifically, the embodiments described herein are directed towards pre-load schemes using gate-induced drain leakage current (GIDL) generation. For example, a select-gate transistor of a NAND string can be used to generate a hole current via GIDL during a pre-load period or phase of the programming process.

[0110] In some embodiments, such as in Fig. As shown in Figure 14B, a negative bias (e.g., -Ve) can be applied to a gate of the selection transistor SGS1 of the NAND string to generate GIDL during the pre-load phase of the programming process. In some embodiments, the SDS / WLDS of the NAND string are biased to ground. Furthermore, in some embodiments and with further reference to Figure 14B, a negative bias (e.g., -Ve) can be applied to a gate of the selection transistor SGS1 of the NAND string to generate GIDL during the pre-load phase of the programming process. Fig. 14B A more positive voltage is applied to the source line connected to one end of the select-gate transistor SGS1 to generate GIDL. These pre-charge schemes achieve a gate-source voltage difference that can induce a GIDL current on the drain side of the SGS1 transistor. However, in some embodiments and with continued reference to Fig. 14B A negative bias voltage is applied to the gate of the select-gate transistor SGD1 of the NAND string to generate GIDL. This pre-charge scheme achieves a gate-source voltage difference that can induce a GIDL current on the drain side of the SGD1 transistor.

[0111] In some embodiments, the foregoing can be implemented by a controller, control logic, a processor, and / or the like, as described elsewhere herein. For example, the control logic 110 in Fig. 1A can be configured to perform a pre-charge operation prior to a programming operation. This pre-charge operation involves applying a voltage to a select line connected to the gate of select transistor SGS1 to generate GIDL. As another example, the control switching logic 110 can be used in Fig. 1A can be configured to perform a pre-charge operation, comprising applying a voltage to a source line connected to one end of the selection transistor SGS1 to generate GIDL. In another example, the control switching logic 110 in Fig. 1A is configured to perform a pre-charging operation, comprising applying a voltage to a gate of the selection transistor SGD1 to generate GIDL.

[0112] To investigate this further, the following will now be Fig. Described in sections 15A to 15D. Fig. 15A, Fig. 15B, Fig. 15C and Fig. Figure 15D are signal timing diagrams for example implementations of the hole preload schemes using GIDL generation for the BiCS-CUA architecture described above. For example, it shows Fig. 15A the hole precharge (also known as “SGS1-GIDL”) after a conventional CELSRC precharge. As in Fig. As shown in Figure 15A, the CELSRC precharge is performed from P4 to P7, and the hole precharge is performed from P8 to P9 (by biasing the gate of SGS1 to -Ve). For example, the hole precharge is performed after the CELSRC precharge by setting the select line connected to the gate of selector transistor SGS1 to a negative bias. In contrast, in Fig. In 15B, there is no CELSRC pre-charge, and a hole pre-charge from P4 to P9 takes place (by biasing the gate of SGS1 to -Ve). In this particular embodiment, a longer time is provided to generate the hole GIDL current, thus improving the boosting potential. A similar scheme can be implemented using the selection transistor SGD1; see [reference]. Fig. 14A and Fig. 14B.

[0113] In Fig. At 15C, CELSRC pre-charging occurs from P4 to P7, and hole pre-charging occurs from P8 to P9 (by applying PROGSRC_PCH2 at P8 to the source line connected to the source side of SGS1, where PROGSRC_PCH2 > PROGSRC_PCH1). In contrast, in Fig. 15D no CELSRC preload, and a hole preload is performed from P4 to P9 (by applying PROGSRC_PCH2 at P5 to the source line connected to the source side of SGS1). Fig. Figures 15A to 15D are provided for illustrative purposes only. In some embodiments, the hole preloading can occur at other times during a preloading phase of a programming process.

[0114] As described, GIDL current can be generated by applying a negative bias voltage to the gate of a NAND string selector transistor or by applying a more positive source voltage to the source line connected to the source side of a NAND string selector transistor. A higher GIDL current reduces the electron density in the channel after precharging and improves the boosting potential under the channel. However, to reduce the GIDL requirement, a longer precharging time can be used (as in Fig. 15B and Fig. 15D shown).

[0115] As discussed above, when memory cells of a memory device operating in sub-block mode (SBM) are programmed using reverse-order programming (ROP), one or more of the sub-blocks may not be pre-charged using electron pre-charging. ROP is typically used because normal-order programming (NOP) causes significant neighbor word line (NWI) interference compared to ROP. Fig. Figure 16 is a diagram of a block of memory cells divided into two subblocks, subblock 0 (SB0) and subblock 1 (SB1), illustrating the programming direction for reverse order programming (ROP) and the preload path in the channel that is cut off by one or more of the memory cells that are programmed to a highest data state (e.g., G data state). Fig. Figure 17 is a diagram of the voltages applied to a selected drain-side select-gate transistor, an unselected word line (UCG), a selected word line (CG), and a bit line during an electron precharge. Fig. Figure 18 shows a diagram of the channel potential for a normal block and a sub-block programmed with ROP. As shown, the channel is cut off early and coupled to the word line potential. Fig. Figure 19 shows a diagram of the threshold voltage distribution widths of a multitude of data states versus the word line number for ROP, programming subblock 0 (SB0) before subblock 1 (SB1) and programming subblock 1 before subblock 0. Fig. Figure 20 shows a diagram of the threshold voltage distributions using electron precharging in subblock mode. As shown, SB1 cannot be electron precharged in SBM due to negative coupling problems and severe program disturbances (PD). Alternatively, the negative coupling problems can be avoided by hole precharging, and SBM-ROP precharging can be used. Fig. Figure 21 is a diagram showing a comparison of the precharging process using electrons and holes. Fig. 22 is a table summarizing some differences between the precharging of electrons and holes.

[0116] Fig. Figure 23 is a diagram of a memory hole channel showing gate-induced hole creation during preloading in an emulation. Fig. Figure 24 shows an example group of transistors of a memory hole together with one erased memory cell and a source-side select-gate transistor. As shown, the gate-source voltage of the erased memory cell is sufficient to overcome the threshold voltage in the erasure state, and due to the gate-source voltage of the source-side select-gate transistor, a sufficient gate-induced drain leakage current is present. Fig. 25 is a diagram of the word lines in a sub-block arrangement programmed for emulation. In emulation, and as in Fig. As shown in Figure 25, word lines WL 161 to WL 121 are randomly programmed as TLC. Word lines WL80 to WL0 are randomly programmed as TLC. Word line 120 is read and a weak erase operation (one loop, erase voltage approximately 8 V) is performed. Then, word line WL 120 is programmed and its threshold voltage is measured. Fig. Figure 26 shows the voltages of the destination or selected word line along with a voltage of the source line during emulation. During emulation, a weak erase pulse is used before each programming pulse. Therefore, a pulse program must be used for the destination word line. The erase pulse should not affect the data pattern of the closed word lines. From the emulation, it can be concluded that hole precharging is very effective in getting all ROP-SBMs to operate.

[0117] Consequently, a storage device is described herein (e.g., storage device 100 of Fig. 1A) including memory cells (e.g. data storage cell MC of Fig. 6D), each of which is connected to one of a multitude of word lines (e.g., word line layers WLLO to WLL10 of Fig. 6B or WLL10 from Fig. 6D). The memory cells are configured to maintain a threshold voltage Vt or Vth corresponding to one of a variety of memory or data states (e.g. Fig. 9, Fig. 10 to Fig. 11) The memory cells are arranged in memory holes (e.g. memory hole 630 of Fig. 6D), which define the channels (e.g., channel 665 of Fig. 6D). The storage device also includes a control circuit or means (e.g., one or any combination of control switching logic 110, decoders 124, 132, acquisition blocks SB1 to SBp, read / write circuits 128, controller 122 of Fig. 1A, control circuit 150 of Fig. 1B and so forth) which are configured to create holes by applying a hole pre-charge voltage to the memory hole channels during a pre-charge phase of a programming operation of the memory cells in the memory holes. After the pre-charge phase, the control device is also configured to apply one of a series of programming pulses of a programming voltage VPGM to selected of the multitude of word lines to program the associated memory cells.

[0118] With renewed reference to Fig. 6B, Fig. 6D and Fig. 8A and according to aspects of revelation, the multitude of word-directions (e.g., word-direction layers WLLO to WLL10 of Fig. 6B) and a variety of dielectric layers (e.g. dielectric layers DL0 to DL19 of Fig. 6B) extend horizontally and alternately stack them on top of each other (e.g., stack 610 of Fig. 6B). The memory holes extend vertically through the stack. The memory cells are located between at least one drain-side select-gate transistor (e.g., SGD transistors 680 and 681 from [manufacturer name]). Fig. 6D) on a drain side of each of the memory holes and a source-side select-gate transistor (e.g., SGS transistors 800 and 801 from Fig. 8A) on a source side of each of the memory holes is connected in series. The at least one drain-side select-gate transistor of each of the memory holes is connected to one of a plurality of bit lines (e.g., bit line BL0 in Fig. 6B), and the source-side selection gate transistor of each of the memory holes is coupled to a source line (e.g., substrate 611 of Fig. 6B). The memory cells are grouped into a multitude of subblocks (e.g., subblocks SBa to SBd of Fig. 8A), which are vertical (as below, for example, in relation to Fig. 16 discussed) is arranged in the stack. The programming operation is a programming operation in reverse order. Thus, the control means is further configured to program the memory cells in reverse order of the programming operation, starting with the memory cells connected to one of the multitude of word lines adjacent to a top of the stack, and then proceeding vertically downwards through the stack.

[0119] Hole precharging is similar to a weak erase operation performed before each programming pulse. One challenge with hole precharging is timing, specifically how quickly the source line CELSRC can be ramped up to its target voltage. A minimum voltage is required for effective hole precharging. However, precharging takes a considerable amount of time, in some cases longer than electron precharging. Furthermore, if the ramp rate is too high, the current consumption (ICC) becomes a problem. Therefore, the ramp time presents difficulties in implementing hole precharging, especially when voltage is applied to the channels from the source side to generate the holes. An erase voltage is typically supplied to the channel from the local intermediate connection to the source line CELSRC or from the bit line (connected to the drain side of the memory hole).In some storage devices, the capacity of the local intermediate connection to the word line (LI-WL) and the CELSRC capacity of the source line are quite large, so the ramp rate / time from the source side may be limited. On the other hand, in some storage devices, the bit line is directly connected to the VERA pump or charge pump. As is known, the bit line capacity can be neglected when all bit lines are started up together. Furthermore, the bit line-side ramp-up can be very fast and does not have a significant impact on ICC power consumption. Therefore, hole pre-charging may be more practical if it is performed only from the bit line side.Accordingly, the control device can further be configured to apply the hole pre-charge voltage to each of the multitude of bit lines connected to the memory holes, including the memory cells being programmed, during the pre-load phase of the programming process.

[0120] As discussed above, and according to one aspect, the storage device further includes a local intermediate connection (e.g., LI from Fig. 14A), which extends vertically along the stack and is connected to the source line. The storage device also includes a charge pump or driver (e.g., part of the power control module 116 of Fig. 1A) which are coupled to the multitude of bit lines and configured to supply the hole pre-charge voltage. According to another aspect, the storage device includes BL-HC pump isolation transistors, each coupled between the charge pump and the local intermediate connection and configured to selectively connect and disconnect the charge pump from the local intermediate connection. Fig. Figure 27 illustrates two diagrams of a bit line BL, a source line 2700 (SRC line), a stack 2702, a memory hole 2704, a local intermediate link LI and a charging pump 2706 of an example memory device with and without a pump isolation transistor BL-HC.

[0121] Thus, the control device is further configured to control the pump isolation transistors BL-HC to connect the charging pump 2706 to the local intermediate LI during an erase operation. The control device also controls the pump isolation transistors BL-HC to disconnect the charging pump 2706 from the local intermediate LI during the programming operation. The pump isolation transistor BL-HC therefore controls the connection between VERA or charging pump 2706 and the local intermediate LI. During an erase operation, the pump isolation transistor BL-HC is turned on. During hole pre-charging, the pump isolation transistor BL-HC is turned off. This transistor BL-HC can be a global signal transistor; for example, it is independent of the bit line levels. Therefore, there is essentially no area loss.As discussed, some of the multiple subblocks comprise one of multiple blocks, and some of the multiple blocks comprise one of multiple levels. Therefore, according to one aspect, one of the BL-HC pump isolation transistors can be used for each of the multiple levels. According to another aspect, one of the BL-HC pump isolation transistors can be used for each of the multiple blocks.

[0122] Fig. Figure 28A is a diagram of the voltages applied to a selected drain-side selection gate transistor, a non-selected drain-side selection gate transistor, a first neighboring word line (immediately below a selected word line in a stack), the selected word line, a second neighboring word line (immediately above a selected word line in the stack), a bit line coupled to memory cells to be programmed, and a bit line coupled to memory cells to be programmed during a verification of a programming operation, a pre-charge phase for electron pre-charging, and a programming pulse of the programming operation. Fig. Figure 28B is a diagram of the voltages applied to a selected drain-side select-gate transistor, a non-selected drain-side select-gate transistor, a first neighboring word line (CG N-), the selected word line, a second neighboring word line (CG N+), a bit line coupled to memory cells to be programmed, and a bit line coupled to memory cells prevented from being programmed during a verification of a programming operation, a preload phase for preloading holes, and a programming pulse of the programming operation. The one or more drain-side select-gate transistors may include an upper drain-side select-gate transistor and one or more other drain-side select-gate transistors arranged vertically below the upper drain-side select-gate transistor. According to one aspect and with reference to Fig. 28B, the control device is further configured to apply a select-gate pre-charge voltage VSGDPCH to one or more other drain-side select-gate transistors of the memory holes, including the memory cells being programmed, during the pre-charge phase of the programming operation. The control device also applies the select-gate pre-charge voltage VSGDPCH to one or more other drain-side select-gate transistors of the memory holes, including the memory cells not being programmed. Additionally, the control device applies a continuous operating voltage VSS (e.g., 0 volts) to the selected of the plurality of word lines and to the unselected of the plurality of word lines. The control device is also configured to apply the hole pre-charge voltage (e.g., about 9 volts) to each of the plurality of bit lines connected to the memory holes, including the memory cells not being programmed.The control device also applies a negative selection gate voltage (e.g., about -3 volts) to the upper drain-side selection gate transistor and the continuous operating voltage VSS to the pump isolation transistors BL-HC.

[0123] Fig. Figure 29 illustrates the steps of a procedure for operating a storage device. As discussed above, the storage device (e.g., storage device 100 of Fig. 1A) Memory cells (e.g., data storage cell MC of Fig. 6D) each of which is connected to one of a multitude of word lines (e.g., word line layers WLLO to WLL10 of Fig. 6B or WLL10 from Fig. 6D). The memory cells are configured to maintain a threshold voltage Vt or Vth corresponding to one of a variety of memory or data states (e.g. Fig. 9, Fig. 10 to Fig. 11) The memory cells are arranged in memory holes (e.g. memory hole 630 of Fig. 6D), which define the channels (e.g., channel 665 of Fig. 6D). The method includes step 2900 of generating holes by applying a hole pre-charge voltage to the memory hole channels in a pre-charge phase of a programming operation of the memory cells in the memory holes. The method also includes, after the pre-charge phase, step 2902 of applying a programming voltage VPGM from a series of programming pulses to selected of the plurality of word lines in order to program the associated memory cells.

[0124] With renewed reference to Fig. 6B, Fig. 6D and Fig. 8A and according to aspects of revelation, the multitude of word-directions (e.g., word-direction layers WLLO to WLL10 of Fig. 6B) and a variety of dielectric layers (e.g. dielectric layers DL0 to DL19 of Fig. 6B) extend horizontally and alternately stack them on top of each other (e.g., stack 610 of Fig. 6B). The memory holes extend vertically through the stack. The memory cells are located between at least one drain-side select-gate transistor (e.g., SGD transistors 680 and 681 from [manufacturer name]). Fig. 6D) on a drain side of each of the memory holes and a source-side select-gate transistor (e.g., SGS transistors 800 and 801 from Fig. 8A) on a source side of each of the memory holes is connected in series. The at least one drain-side select-gate transistor of each of the memory holes is connected to one of a plurality of bit lines (e.g., bit line BL0 in Fig. 6B), and the source-side selection gate transistor of each of the memory holes is coupled to a source line (e.g., substrate 611 of Fig. 6B). The memory cells are grouped into a multitude of subblocks (e.g., subblocks SBa to SBd of Fig. 8A), which are vertical (as below, for example, in relation to Fig. 16 discussed) is arranged in the stack. The programming process is a programming process in reverse order. Therefore, the procedure may further include the step of programming the memory cells in reverse order, starting with the memory cells connected to one of the multitude of word lines adjacent to a top of the stack, and then proceeding vertically downwards through the stack.

[0125] As discussed above, hole precharging may be more practical if performed only from the bitline side. Accordingly, the procedure may further include the step of applying the hole precharging voltage to each of the plurality of bitlines connected to the memory holes, including the memory cells being programmed, during the precharging phase of the programming process.

[0126] Furthermore, the storage device can again use a local intermediate connection (e.g., LI from Fig. 14A) which extends vertically along the stack and is connected to the source line. The storage device may also include a charge pump or driver (e.g., part of the power control module 116 of Fig. 1A) include, which are coupled and configured with the multitude of bit lines to supply the hole pre-charge voltage. Also, with renewed reference to Fig.27 and, according to another aspect, the storage device includes pump isolation transistors BL-HC, each coupled between the charging pump 2706 and the local intermediate connection LI, and configured to selectively connect the charging pump 2706 to and disconnect the charging pump 2706 from the local intermediate connection LI. Therefore, the method may further include the step of controlling the pump isolation transistors BL-HC to connect the charging pump 2706 to the local intermediate connection LI during an erase operation. The method may further include the step of controlling the pump isolation transistors BL-HC to disconnect the charging pump 2706 from the local intermediate connection LI during the programming operation. As above, some of the plurality of subblocks comprise one of a plurality of blocks, and some of the plurality of blocks comprise one of a plurality of levels.Therefore, according to one aspect, one of the BL-HC pump isolation transistors can be used for each of the multiple levels. According to another aspect, one of the BL-HC pump isolation transistors can be used for each of the multiple blocks.

[0127] As discussed, the at least one drain-side select gate transistor can include an upper drain-side select gate transistor and one or more other drain-side select gate transistors arranged vertically below the upper drain-side select gate transistor. Thus, according to one aspect, during the pre-charge phase of the programming process, the method can include the step of applying a select gate pre-charge voltage VSGDPCH to one or more of the other drain-side select gate transistors of the memory holes, including the memory cells being programmed. Additionally, the method can include the step of applying the select gate pre-charge voltage VSGDPCH to one or more of the other drain-side select gate transistors of the memory holes, including the memory cells not being programmed.Furthermore, the method can include the step of applying a continuous operating voltage VSS to the selected word lines. Additionally, the method can include the step of applying the continuous operating voltage VSS to unselected word lines. The method can also include the step of applying the hole pre-charge voltage to each of the bit lines connected to the memory holes, including those memory cells that are not programmed. Additionally, the method can include the step of applying a negative select-gate voltage to the upper drain-side select-gate transistor. Finally, the method can include the step of applying the continuous operating voltage VSS to the pump-isolation transistors BL-HC.

[0128] The foregoing detailed description of the invention is provided for illustrative and descriptive purposes. It makes no claim to completeness or to limit the invention to the exact form disclosed. In light of the above teachings, many modifications and variations are possible. The described embodiments were chosen to best explain the principles of the invention and its practical application, thereby enabling other skilled persons to make optimal use of the invention in various embodiments and with various modifications, as suitable for the respective intended use. The scope of protection of the invention is to be defined by the appended claims.

Claims

[1] Storage device comprising: Memory cells, each connected to one of a plurality of word lines and configured to maintain a threshold voltage corresponding to one of a plurality of data states, the memory cells being arranged in memory holes that define channels; and a control mechanism configured to: Generating holes by applying a hole pre-charge voltage to the memory hole channels during a pre-charge phase of a programming process of the memory cells in the memory holes, and After the pre-loading phase, a programming voltage from a series of programming pulses is applied to selected of the multitude of word lines in order to program the associated memory cells. [2] Memory device according to claim 1, wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and are alternately superimposed in a stack, the memory holes extend vertically through the stack, the memory cells are connected in series between at least one drain-side select-gate transistor on a drain side of each of the memory holes and one source-side select-gate transistor on a source side of each of the memory holes, the at least one drain-side select-gate transistor of each of the memory holes is coupled to one of a plurality of bit lines and the source-side select-gate transistor of each of the memory holes is connected to a source line, the memory cells are grouped into a plurality of sub-blocks arranged vertically in the stack,The programming operation is a reverse programming operation, and the control means is further configured to program the memory cells in the programming operation in reverse order, starting with the memory cells connected to one of the multiple word lines adjacent to a top of the stack and proceeding vertically downwards through the stack. [3] Memory device according to claim 2, wherein the control means is further configured to apply the hole pre-charge voltage to each of the plurality of bit lines connected to the memory holes including the memory cells to be programmed during the pre-load phase of the programming process. [4] Storage device according to claim 3, further comprising a local intermediate extending vertically along the stack and connected to the source line, wherein the storage device includes a charge pump coupled to the plurality of bit lines and configured to supply the hole pre-charge voltage, wherein the storage device includes pump isolation transistors, each coupled between the charge pump and the local intermediate and configured to selectively connect and disconnect the charge pump to the local intermediate, and wherein the control means is further configured to: Controlling the pump isolation transistors to connect the charging pump to the local intermediate connection during a quenching operation; and Controlling the pump isolation transistors to disconnect the charging pump from the local intermediate connection during the programming process. [5] Storage device according to claim 4, wherein some of the plurality of subblocks comprise one of a plurality of blocks and some of the plurality of blocks comprise one of a plurality of levels, and one of the pump isolation transistors is used for each of the plurality of levels. [6] Storage device according to claim 4, wherein some of the plurality of subblocks comprise one of a plurality of blocks and one of the pump isolation transistors is used for each of the plurality of blocks. [7] Memory device according to claim 4, wherein the at least one drain-side select gate transistor includes an upper drain-side select gate transistor and one or more other drain-side select gate transistors arranged vertically below the upper drain-side select gate transistor, and wherein the control means is further configured during the preload phase of the programming process to: Applying a select-gate pre-charge voltage to one or more other drain-side select-gate transistors of the memory holes, including the memory cells being programmed; Applying the select gate pre-charge voltage to one or more other drain-side select gate transistors of the memory holes, including the memory cells that are not programmed; Applying a continuous operating voltage to the selected of the numerous word lines; Applying continuous operating voltage to unselected of the multitude of word lines; Applying the hole pre-charge voltage to each of the multitude of bit lines connected to the memory holes, including the memory cells that are not programmed; Applying a negative select-gate voltage to the upper drain-side select-gate transistor; and Applying the continuous operating voltage to the pump isolation transistors. [8] Controller in communication with a storage device including memory cells, each connected to one of a plurality of word lines and configured to maintain a threshold voltage corresponding to one of a plurality of data states, the memory cells being arranged in memory holes defining channels, the controller being configured to: Generating holes by instructing the memory device to apply a hole pre-charge voltage to the memory hole channels during a pre-charge phase of a programming operation of the memory cells in the memory holes; and After the pre-loading phase, the memory device is instructed to apply a programming voltage from a series of programming pulses to selected of the multitude of word lines in order to program the associated memory cells. [9] Controller according to claim 8, wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and are alternately superimposed in a stack, the memory holes extend vertically through the stack, the memory cells are connected in series between at least one drain-side select-gate transistor on a drain side of each of the memory holes and one source-side select-gate transistor on a source side of each of the memory holes, the at least one drain-side select-gate transistor of each of the memory holes is coupled to one of a plurality of bit lines and the source-side select-gate transistor of each of the memory holes is connected to a source line, the memory cells are grouped into a plurality of sub-blocks arranged vertically in the stack, the programming operation is a reverse-order programming operation and the controller is further configured,to instruct the memory device to program the memory cells in reverse order during the programming process, starting with the memory cells connected to one of the multiple word lines adjacent to a top of the stack and proceeding vertically downwards through the stack. [10] Controller according to claim 9, wherein the controller is further configured to instruct the memory device during the preload phase of the programming process to apply the hole preload voltage to each of the plurality of bit lines connected to the memory holes including the memory cells to be programmed. [11] Controller according to claim 10, wherein the memory device further includes a local intermediate extending vertically along the stack and connected to the source line, wherein the memory device includes a charge pump coupled to the plurality of bit lines and configured to supply the hole pre-charge voltage, wherein the memory device includes pump isolation transistors, each coupled between the charge pump and the local intermediate and configured to selectively connect and disconnect the charge pump to the local intermediate, and wherein the controller is further configured to: Instructing the storage device to control the pump isolation transistors to connect the charging pump to the local intermediate connection during a quenching operation; and Instructing the memory device to control the pump isolation transistors to disconnect the charging pump from the local intermediate connection during the programming process. [12] Controller according to claim 11, wherein some of the plurality of subblocks comprise one of a plurality of blocks and some of the plurality of blocks comprise one of a plurality of levels, and one of the pump isolation transistors is used for each of the plurality of levels. [13] Controller according to claim 11, wherein the at least one drain-side select gate transistor includes an upper drain-side select gate transistor and one or more other drain-side select gate transistors arranged vertically below the upper drain-side select gate transistor, and wherein the controller is further configured during the pre-load phase of the programming process to: Instructing the memory device to apply a select-gate pre-charge voltage to one or more other drain-side select-gate transistors of the memory holes, including the memory cells to be programmed; Instructing the memory device to apply the select-gate pre-charge voltage to one or more other drain-side select-gate transistors of the memory holes, including the memory cells that are not programmed; Instructing the storage device to apply a continuous operating voltage to the selected of the multitude of word lines; Instructing the storage device to apply the continuous operating voltage to unselected of the multitude of word lines; Instructing the memory device to apply the hole pre-charge voltage to each of the plurality of bit lines connected to the memory holes, including the memory cells that are not programmed; Instructing the memory device to apply a negative selection gate voltage to the upper drain-side selection gate transistor; and instructing the memory device to apply the continuous operating voltage to the pump isolation transistors. [14] Method for operating a storage device including memory cells, each connected to one of a plurality of word lines and configured to maintain a threshold voltage corresponding to one of a plurality of data states, wherein the memory cells are arranged in memory holes defining channels, the method comprising the steps: Generating holes by applying a hole pre-charge voltage to the memory hole channels during a pre-charge phase of a programming process of the memory cells in the memory holes; and After the pre-loading phase, a programming voltage from a series of programming pulses is applied to selected of the multitude of word lines in order to program the associated memory cells. [15] Method according to claim 14, wherein the plurality of word lines and a plurality of dielectric layers extend horizontally and are alternately superimposed in a stack, the memory holes extend vertically through the stack, the memory cells are connected in series between at least one drain-side select-gate transistor on a drain side of each of the memory holes and one source-side select-gate transistor on a source side of each of the memory holes, the at least one drain-side select-gate transistor of each of the memory holes is coupled to one of a plurality of bit lines and the source-side select-gate transistor of each of the memory holes is connected to a source line, the memory cells are grouped into a plurality of sub-blocks arranged vertically in the stack,the programming process is a programming process in reverse order and the procedure further includes the step of programming the memory cells in the programming process in reverse order, starting with the memory cells that are connected to one of the plurality of word lines adjacent to a top of the stack and proceeding vertically downwards through the stack. [16] Method according to claim 15, further comprising the step of applying, during the pre-load phase of the programming process, the hole pre-load voltage to each of the plurality of bit lines connected to the memory holes including the memory cells to be programmed. [17] Method according to claim 16, wherein the storage device further includes a local intermediate connection extending vertically along the stack and connected to the source line, wherein the storage device includes a charge pump coupled to the plurality of bit lines and configured to supply the hole pre-charge voltage, wherein the storage device includes pump isolation transistors, each coupled between the charge pump and the local intermediate connection and configured to selectively connect and disconnect the charge pump from the local intermediate connection, and wherein the method further includes the steps: Controlling the pump isolation transistors to connect the charging pump to the local intermediate connection during a quenching operation; and Controlling the pump isolation transistors to disconnect the charging pump from the local intermediate connection during the programming process. [18] Method according to claim 17, wherein some of the plurality of subblocks comprise one of a plurality of blocks and some of the plurality of blocks comprise one of a plurality of levels, and one of the pump isolation transistors is used for each of the plurality of levels. [19] Method according to claim 17, wherein some of the plurality of subblocks comprise one of a plurality of blocks and one of the pump isolation transistors is used for each of the plurality of blocks. [20] Method according to claim 17, wherein the at least one drain-side select gate transistor includes an upper drain-side select gate transistor and one or more other drain-side select gate transistors arranged vertically below the upper drain-side select gate transistor, and wherein the method includes the following steps during the pre-load phase of the programming process: Applying a select-gate pre-charge voltage to one or more other drain-side select-gate transistors of the memory holes, including the memory cells being programmed; Applying the select gate pre-charge voltage to one or more other drain-side select gate transistors of the memory holes, including the memory cells that are not programmed; Applying a continuous operating voltage to the selected of the numerous word lines; Applying continuous operating voltage to unselected of the multitude of word lines; Applying the hole pre-charge voltage to each of the multitude of bit lines connected to the memory holes, including the memory cells that are not programmed; Applying a negative select-gate voltage to the upper drain-side select-gate transistor; and Applying the continuous operating voltage to the pump isolation transistors.

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