Methods and devices for testing de-energized circuits based on a driver-induced electrical quantity

Abstract

A method and a device for testing a circuit are described. The circuit comprises two terminals, a capacitor coupled between the two terminals, and a plurality of series-connected transistors connected in parallel with the capacitor between the two terminals. The method includes driving the plurality of series-connected transistors in a complementary manner while the two terminals are in a de-energized state, sensing an electrical parameter of the circuit, and determining whether the circuit is intact or not using this electrical parameter.

Description

Technical field

[0001] Embodiments according to the invention include methods and devices for testing de-energized circuits based on a driver-induced electrical quantity. Further embodiments according to the invention include methods and corresponding devices for detecting and locating faults in isolated-gate power semiconductor devices in a power electronics converter before the converter is switched on. Further embodiments according to the invention include methods and devices for driver-induced detection of switching cell faults based on the residual DC link voltage. Background of the invention

[0002] Existing fault diagnosis procedures for power converter systems require switching on the power circuit or complex measurement systems. Therefore, such conventional approaches result in considerable testing and hardware costs, especially in cascaded systems with a large number of modular cells.

[0003] Therefore, it is desirable to obtain a concept that achieves a better compromise between the effectiveness of circuit testing, for example with regard to different fault modes, hardware complexity and the computational effort for test execution and evaluation, as well as reliability, time expenditure and thus efficiency of the test.

[0004] This is achieved by the subject matter of the independent claims of the present application. Further embodiments of the invention are defined by the subject matter of the dependent claims of the present application. Summary of the invention

[0005] Exemplary embodiments according to the invention include a method for testing a circuit, wherein the circuit has two terminals, a capacitor coupled between the two terminals, and a plurality of series-connected transistors coupled in parallel with the capacitor between the two terminals. The method comprises the complementary driving of the plurality of series-connected transistors, with the two terminals in a currentless state, the detection of an electrical parameter of the circuit, and the determination of whether the circuit is intact or not using this electrical parameter.

[0006] Optionally, the electrical quantity detection can include one or more of the following features: detection of a voltage across the capacitor, for example by connecting a voltage measuring device to the two terminals, detection of a voltage across the terminals and / or detection of a voltage across one or more individual elements in the circuit (for example, across one or more of the transistors, for example, across a resistor implemented in the circuit).

[0007] The circuit can, for example, include or be a switching cell, such as a two-stage switching cell. The connections can be, for example, GS-bus voltage connections, and the transistors can be, for example, isolated-gate transistors, such as MOSFETs and / or IGBTs.

[0008] For example, load paths, such as collector-emitter paths, such as drain-source paths (which, for example, form a power loop of the circuit) of the two transistors, can be connected between the first and second terminals and in parallel to the capacitor.

[0009] Controlling the majority of transistors connected in series can be achieved, for example, with complementary gate signals, such as complementary pulse signals, which may have a dead time between complementary signal sections to allow a signal (for example, a voltage signal, for example, v) to pass through. f , for example, a current signal, for example, a residual voltage induced by a gate driver, for example, GIRV), in a load path of the circuit (for example, power loop of the circuit) while the first and second terminals are in a voltage-free state.

[0010] The no-current state can be, for example, a state in which the circuit's power loop is not externally switched on (e.g., only switched on by parasitic or coupling effects from a gate-loop pulse). The no-current state can also be a state in which the terminals are not supplied with an external voltage, an external test signal, an external load signal, and / or an external load signal.

[0011] The voltage across the capacitor can, for example, be an accumulated voltage induced in the power loop or load path of the circuit by the complementary drive signals of the transistors, thus, for example, by the gate loop of the circuit.

[0012] The inventors realized that by driving the transistors complementarily, a voltage can be induced across the capacitor, for example, accumulated, without requiring an additional signal at the terminals, and that the circuit's integrity status can be determined based on an evaluation of this voltage. This allows the coupling between a control path and a load path, such as between a gate loop and a power loop, to be exploited. The inventors recognized that prior knowledge of the coupling between these loops or paths can be used to categorize the circuit as intact, meaning functioning within predefined tolerances, or as non-intact or faulty, meaning functioning outside of predefined tolerances.For example, based on an evaluation of the electrical quantity induced from a control side of the circuit to a current side of the circuit, a metric for the quality of the circuit can be determined, for example by evaluating a difference between a measured voltage and a threshold.

[0013] The voltage across the capacitor, for example between the de-energized terminals, can be referred to here as the gate driver-induced residual voltage (GIRV). The inventors recognized that this voltage can occur at the de-energized terminals, such as the GS bus terminals, and that it can be measured and thus used to distinguish between intact and damaged circuits, i.e., to determine whether the circuit is a functioning or faulty switching cell. Exemplary embodiments can enable not only the identification of faults (e.g., of one type), but especially of faults of different types, which, for example, are based on different fault mechanisms (i.e., are of different types).

[0014] To quantify the voltage, the operating modes of the currentless circuits can be analyzed, for example, in the time domain. Optionally, the device can be configured to analyze short-circuit, open-circuit, and gate fault conditions, and thus optionally be capable of detecting faulty circuits of all three types.

[0015] The embodiments according to the invention can be implemented with low hardware complexity. In particular, the devices according to the embodiments can be implemented, for example, using only a measuring device, such as a voltage sensor (for example, a GS-bus voltage sensor) and a gate driver (and optional processing means for evaluating the measurement result), or require only these.

[0016] The inventors have recognized that detecting circuit interruption and short-circuit faults in devices, which may primarily be power loop effects (e.g., in a load path of the circuit), using a gate loop activation (e.g., a driver loop activation) can or even must be based on a coupling between these two loops.

[0017] This type of coupling between gate and power loops is present in transistors, such as MOSFETs, in the form of the gate-drain junction capacitance. The inventors recognized that this coupling can lead to the previously described gate driver-induced residual voltage (GIRV) across the circuit's capacitor, for example, a GS bus capacitor in a MOSFET-based switching cell, when the power loop is de-energized. The inventors realized that, in particular, the GIRV can be used to distinguish between intact and damaged switching cells.

[0018] According to exemplary embodiments of the invention, determining whether the circuit is intact or not involves comparing a voltage, for example the voltage across the capacitor, with a threshold voltage and determining, using the comparison, whether the circuit is intact or not.

[0019] This means that the integrity of the circuit can be evaluated, for example, by comparing the voltage across the capacitor with a threshold. This allows for obtaining circuit integrity information with low latency and low computational and hardware complexity. Furthermore, the threshold can be defined to take into account predetermined test parameters, such as test robustness. This means defining thresholds to achieve a certain level of robustness with respect to false positive or false negative results and / or to categorize the circuit into different quality classes.

[0020] According to exemplary embodiments of the invention, the threshold voltage is determined using one or more properties of the transistors, for example, a forward voltage of a diode connected to the transistors. For example, if the circuit is intact, the complementary driving (720) of the plurality of series-connected transistors, with the two terminals (10, 11, 410, 411) in a currentless state, produces an expected voltage (V f ) at the two terminals (10, 11, 410, 411) and the threshold voltage (14) can have a value equal to the expected voltage (V f ) is, so that by measuring the voltage at the two terminals (10, 11, 410, 411) intact circuits can be distinguished from faulty circuits.

[0021] Thus, in such embodiments, the inventive approach enables the differentiation between intact / non-faulty and non-intact / faulty circuits, such as circuits or modules for modular power converters, for example, modular multi-level converters (MCMs). When such a circuit is operated by exclusively complementary driving of the transistors, which are connected in series with the terminals of the de-energized circuit, a specific or expected voltage is generated due to the charge transfer from the transistors to the capacitor, and based on this voltage, the circuit can be determined as intact or faulty by comparison with a threshold.The threshold can be set according to the properties of the circuit elements, such as the transistors, on the basis of which the expected voltage for an intact circuit can be determined, and the threshold has a value that is equal to this expected voltage, so that by comparing the measured voltage with the expected voltage a circuit can be determined as fully functional, i.e. intact, or non-functional or faulty.

[0022] According to exemplary embodiments of the invention, the threshold voltage is determined as a fraction of an expected voltage across the capacitor, for example 1 / 2 or 4 / 5 of the expected voltage across the capacitor. For example, if the circuit is intact, the complementary driving (720) of the plurality of series-connected transistors, with the two terminals (10, 11, 410, 411) in a currentless state, causes the expected voltage (V) f) at the two terminals (10, 11, 410, 411) and the threshold voltage (14) can have a value equal to the fraction of the expected voltage (V f ) is to be able to distinguish between intact circuits that are impaired by less than a certain degree and non-intact circuits that are impaired by the certain degree or by more than the certain degree by measuring the voltage at the two terminals (10, 11, 410, 411).

[0023] Thus, this embodiment, in addition to the preceding embodiments, allows for the differentiation between intact / fully functional and non-intact / non-functional or faulty circuits, and enables the differentiation between circuits that are not yet impaired beyond a certain degree and circuits that are actually impaired beyond that degree. That is, a circuit is considered intact if it is determined that it is not impaired beyond a certain degree, while it is considered non-intact if the circuit is impaired beyond that degree.When a functioning system is operating, the complementary driving of the transistors, with the terminals in a currentless state or a state of open circuit, generates a voltage across the terminals through charge transfer. This voltage is also known as the expected voltage for the functioning system. The threshold for determining whether the system is still functioning (i.e., not excessively impaired) or no longer functioning (i.e., impaired beyond a certain degree) can be defined as a specific fraction of the expected voltage, for example, 4 / 5 or 1 / 2. Depending on this threshold, against which a measured voltage across the terminals is compared, the circuit is classified as functioning or functioning.The selected fraction represents a circuit state which, despite the deviation from the expected voltage, is still a functional circuit, so that this embodiment not only allows the distinction between fully functional and non-functional circuits, but also enables consideration of the fact that the circuit can remain functional despite a certain degree of impairment that the circuit experiences, for example, during its lifetime.

[0024] According to exemplary embodiments of the invention, the circuit is determined to be non-functional or faulty, for example, if a comparison of the voltage, such as the voltage across the capacitor, and the threshold voltage yields a comparison signal with a first logic level, such as a high level, and / or the circuit is determined to be functional if the comparison of the voltage, such as the voltage across the capacitor, and the threshold voltage yields a comparison signal with a second logic level, such as a low level. This can enable a simple yet efficient evaluation of the measured voltage.

[0025] According to exemplary embodiments of the invention, the method further comprises the logical combination of the comparison signal and a gate driver activation signal which drives the transistors and has the first logic level, and the method further comprises, if the comparison signal and the gate driver activation signal have different logic levels, indicating that the circuit is intact, and if the comparison signal and the gate driver activation signal have the same logic levels, indicating that the circuit is not intact or is faulty.

[0026] This means that the comparison result and the gate driver activation signal can be logically combined. Thus, the method can, for example, involve the joint evaluation of information about the electrical quantity induced in the load path or power loop of the circuit and control path or control loop information, such as a gate driver activation signal or a delayed version of the gate driver activation signal, to obtain the test result for the transistors.

[0027] This enables a robust execution of the test, as not only the measurement result but also a test status, such as information "Test has already started", can be taken into account, for example information "A test pulse signal is being provided correctly".

[0028] According to exemplary embodiments of the invention, the logical combination of the comparison signal and the gate driver activation signal involves applying the comparison signal and the gate driver activation signal to an AND gate. This enables the evaluation of the test with low hardware complexity and good speed.

[0029] According to exemplary embodiments of the invention, the method further features a delay of the gate driver activation signal before its logical combination with the comparator output signal. This can allow sufficient build-up time to accumulate an adequate voltage across the capacitor so that the integrity information can be reliably obtained.

[0030] According to exemplary embodiments of the invention, a delay for delaying the gate driver activation signal is determined using one or more characteristics of the circuit, for example, one or more of the following: a switching frequency of the circuit, a capacitance of the capacitor, one or more capacitances of the transistors, such as a gate-drain capacitance or a drain-source capacitance, and / or a resistance in the circuit. The inventors have recognized that such an approach enables simple yet efficient test parameterization.

[0031] According to exemplary embodiments of the invention, controlling the plurality of series-connected transistors involves applying complementary gate driver signals to corresponding terminals of the series-connected transistors for the complementary switching on and off of the transistors.

[0032] For example, the transistors can be driven with complementary gate signals, such as a complementary pulse signal, where the signals have a dead time between complementary signal segments. This can make it possible to induce a gate-driven residual voltage (GIRV) in a load path of the circuit and thus obtain reliable information about the integrity of the circuit, for example, the switching cell.

[0033] According to exemplary embodiments of the invention, controlling the plurality of series-connected transistors involves activating a plurality of gate drivers coupled to the respective transistors using the gate driver activation signal.

[0034] According to exemplary embodiments of the invention, the majority of series-connected transistors comprise an insulated gate bipolar transistor (IGBT) and / or a metal oxide semiconductor field-effect transistor (MOSFET). Thus, the exemplary embodiments according to the invention are not limited to a specific type of transistor.

[0035] According to exemplary embodiments of the invention, the majority of series-connected transistors comprise two IGBTs or two MOSFETs connected in series, which are connected in parallel with the capacitor between the two terminals. The inventors have recognized that a series connection of identical transistors results in particularly good test reliability.

[0036] Exemplary embodiments according to the invention include a device for testing a circuit, wherein the circuit has two terminals, a capacitor coupled between the two terminals, and a plurality of series-connected transistors coupled in parallel with the capacitor between the two terminals. Furthermore, the device includes a driver circuit that can be connected to the plurality of series-connected transistors for driving the plurality of series-connected transistors of the circuit in a complementary manner, a measuring device for detecting an electrical quantity of the circuit, wherein the two terminals are in a de-energized state and the plurality of series-connected transistors of the circuit are driven in a complementary manner, and a signal processing circuit coupled to the measuring device for determining, using the electrical quantity, whether the circuit is intact or not.

[0037] According to exemplary embodiments, the measuring device is configured to measure a voltage in order to detect the electrical quantity, and the voltage is at least one of the voltages of the group which includes a voltage at the terminals, a voltage at the capacitor and a voltage at one or more individual elements in the circuit.

[0038] According to exemplary embodiments of the invention, the signal processing circuit has a comparator for comparing the voltage, for example the voltage across the capacitor, with a threshold voltage, outputs a first signal (is, for example, configured to output) indicating that the circuit is not intact or faulty when the comparator outputs a comparison signal having a first logic level, for example a high level, and outputs a second signal (is, for example, configured to output) indicating that the circuit is intact when the comparator outputs a comparison signal having a second logic level, for example a low level.

[0039] This means that the device (i.e., a signal processing circuit) can, for example, include a comparator for comparing the integrity of the circuit by comparing the voltage across the capacitor with a threshold.

[0040] According to exemplary embodiments of the invention, the signal processing circuit further comprises a logic gate for logically combining the comparator's comparison signal and a gate driver activation signal, which drives the transistors and has the first logic level. Furthermore, the logic gate outputs the first signal (i.e., is configured to output) when the comparison signal and the gate driver activation signal have the same logic levels, and the logic gate outputs the second signal (i.e., is configured to output) when the comparison signal and the gate driver activation signal have different logic levels.

[0041] This means that the device (i.e., the signal processing circuit) may, for example, include a logic gate for combining the comparison result and the gate driver activation signal.

[0042] According to exemplary embodiments of the invention, the logic gate has an AND gate.

[0043] According to exemplary embodiments of the invention, the signal processing circuit further comprises a delay element for delaying the gate driver activation signal before applying the gate driver activation signal to the logic gate.

[0044] According to exemplary embodiments of the invention, the driver circuit has corresponding gate drivers that can be connected to the transistors in order to apply complementary gate driver signals to corresponding control terminals of transistors connected in series in order to switch the transistors on and off in a complementary manner.

[0045] The device described above is based on the same considerations as the method described above. Furthermore, the device can be equipped with all the features and functionalities described in relation to the method, and vice versa. Brief description of the drawings

[0046] The drawings are not necessarily to scale, as the focus is generally on illustrating the principles of the invention. The following description presents different embodiments of the invention with reference to the following drawings. Fig. Figure 1 shows a device for testing a circuit with additional, optional features according to exemplary embodiments of the invention. Fig. Figure 2 shows a schematic drawing of example signals for the in Fig. 1 Device shown, when the circuit is intact, according to embodiments of the invention. Fig. Figure 3 shows a schematic drawing of signals for the in Fig. 1. The device shown represents the circuit when it is faulty, according to exemplary embodiments of the invention. Fig. Figure 4 shows schematic views of a two-stage MOSFET-based switching cell according to exemplary embodiments of the invention. Fig. Figure 5 shows a schematic view of waveforms according to embodiments of the present invention. Fig. Figure 6 shows schematic views of corresponding circuits of a currentless cell in a fault condition according to exemplary embodiments of the invention. Fig. Figure 7 shows a schematic flow diagram of an error detection strategy according to exemplary implementations. Fig. Figure 8 shows schematic views of circuits in different intactness states together with examples of corresponding signals according to embodiments of the invention. Detailed description of the exemplary implementations

[0047] Identical or equivalent elements, or elements with the same or equivalent functionality, are designated by the same or equivalent reference symbols in the following description, even if they are contained in different figures.

[0048] The following description presents a number of details to provide a more comprehensive explanation of embodiments of the present invention. However, it is clear to a person skilled in the art that embodiments of the present invention can be implemented without these specific details. In other cases, known structures and devices are shown in block diagrams rather than in detail to avoid making embodiments of the present invention unclear. Furthermore, features of the different embodiments described herein can be combined unless expressly stated otherwise.

[0049] Fig. Figure 1 shows a schematic view of a device for testing a circuit with additional, optional features according to exemplary embodiments of the invention. Fig. Figure 1 shows a device 100 for testing a circuit 200, wherein the circuit has two terminals 10, 11, a capacitor 3 coupled between the two terminals 10, 11, and a plurality of series-connected transistors 1, 2 coupled in parallel with the capacitor 3 between the two terminals 10, 11. The device 100 includes a driver circuit 110 that can be connected to the plurality of series-connected transistors 1, 2 to control the plurality of series-connected transistors of the circuit 200 in a complementary manner.

[0050] The device 100 has a measuring device 12 for detecting an electrical quantity of the circuit, wherein the two terminals 10, 11 are in a currentless state and the majority of series-connected transistors 1, 2 of the circuit are controlled complementarily.

[0051] Furthermore, the device 100 has a signal processing circuit 120, which is coupled to the measuring device 12, for determining, using the electrical quantity 13, for example a voltage across the capacitor 3, whether the circuit 200 is intact or not.

[0052] The example of Fig. Figure 1 shows a measurement of an electrical quantity in the form of a voltage at terminals 10, 11, representing a voltage across capacitor 3. However, the embodiments are not limited to such approaches. Optionally, a voltage across one or more individual elements in the circuit can also be measured and evaluated. For example, any electrical quantity (e.g., a voltage and / or a current) in a load path or power loop of the circuit (e.g., across capacitor 3, an additional resistor, or a transistor 1, 2) induced by the complementary driving of the plurality of series-connected transistors 1, 2, can be measured and analyzed. Such measurements can include voltage measurements, current measurements, or other measurements related to an electrical quantity suitable for the specific application.

[0053] In this context, it should be noted that in Fig. Figure 1 shows a number of optional, additional features, which are explained below. In particular, the specific details of the signal processing circuit 120, for example, with a fixed threshold voltage 14, a comparator block 15, and a time delay block 17, are optional. That is, the measurement signal 13 can be any measurement signal about an electrical quantity of the circuit 200, which is influenced by a coupling between a control loop and a power loop of the circuit, and can thus be evaluated in any way that allows this measurement signal to be analyzed to determine whether the coupling corresponds to an intact circuit or not.

[0054] For a better understanding of implementation examples, the following is provided. Fig. 1 explained according to a first example with a plurality of optional features.

[0055] For example, transistors 1, 2 can be semiconductor devices with an insulated gate, which can be arranged together with a capacitor 3 to form a switching cell 4 as a structural and functional unit of a power converter.

[0056] Gate driver signals 5 and 6 for semiconductor devices 1 and 2 can be used to switch the devices on and off. Gate driver signals 5 and 6 can be generated by the respective gate drivers 7 and 8. Driver circuits 110 can therefore include gate drivers 7 and 8. Gate drivers 7 and 8 can be activated by an activation signal 9.

[0057] It should be noted that transistors may be referred to here as a "device".

[0058] According to the inventive method, the terminals 10, 11 (for example, the DC terminals of the switching cell 4) can be de-energized and the current measuring device 12 can be connected to the terminals 10, 11. The voltage 13 across the capacitor 3 can thus be measured by the measuring device 12.

[0059] The measured voltage 13 can optionally be fed to a comparator block 15 together with a fixed threshold voltage 14. The output 16 of the comparator block 15 can be high if the measured voltage 13 is higher than the threshold 14; otherwise, the output of the comparator block can be low. It should be noted, however, that the embodiments are not limited to this type of comparison; in addition to thresholds, gradients or statistical analyses of signal developments can also be performed.

[0060] The gate driver activation signal 9 can optionally be passed through a time delay block 17 to obtain the delayed gate driver activation signal 18. The comparison output 16 can be ANDed with the delayed gate driver activation signal 18 using the AND block 19. If the fault indication output 20 of the AND block is high, a fault in one or both devices of the switching cell 4 can be indicated; conversely, if the AND block output 18 is low, it can be indicated that the switching cell 4 is intact. Other integrity indications are also possible. Processing can be performed using analog or digital processing equipment.

[0061] The following will be discussed Fig. 2 and Fig. 3 referred to the schematic views of examples of signals for the in Fig. Figure 1 shows the device according to exemplary embodiments of the invention.

[0062] As in Fig. 2 and Fig. As shown in Figure 3, the activation signal 9 can be set to a high level. The gate driver signals 5 and 6 for devices 1 and 2 can thus be activated. The threshold 14 can have a constant value, for example, minus 0.2 volts.

[0063] As in Fig. As shown in Figure 2, a negative voltage value 13 of less than -0.2 volts can be measured in an intact cell after the gate driver activation signal 9 has been activated. It should be noted again (as in the previous section) that -0.2 volts is an example value here. Other values ​​are, of course, also possible. Thus, the threshold comparison output 16 can become low. The delay Td in the delayed activation signal 18 can be adjusted or set so that the delayed signal 18 only becomes high when the comparison output 16 becomes low. Therefore, the fault indication output 20 can remain low, indicating an intact switching cell.

[0064] As in Fig. As shown in Figure 3, if the cell is damaged, a non-negative voltage value 13, for example higher than minus 0.2 volts, can be measured after the gate driver activation signal 9 has been activated. Thus, the threshold comparison output 16 can remain high. If the delayed gate driver activation signal 18 becomes high, the fault indication output 20 can also become high, indicating a fault within the switching cell. Advantages of exemplary implementations

[0065] For a better understanding of the advantages of methods and devices according to the exemplary embodiments, reference is made to the conventional approaches.

[0066] According to a first group of conventional approaches, semiconductor device faults are detected by measuring the gate currents in the on and off states of a power semiconductor device with an insulated gate. A device is classified as faulty if its gate current in the on state is higher than the gate current in the on state of an intact device, or if its gate current in the off state is lower than the gate current in the off state of an intact device. The embodiments according to the invention have the following advantages over such approaches: Methods according to the exemplary embodiments do not require measurement of the gate currents of the semiconductor devices and are therefore non-invasive. Gate current sensors are not part of the normal operation of power converters, and thus it is not desirable to use them "only" or primarily for testing purposes. Accordingly, these exemplary embodiments enable a reduction in the hardware complexity for testing.

[0067] Methods according to the exemplary embodiments can be used to detect gate faults of the semiconductor device and faults caused by circuit interruption, i.e., interruption faults, as well as faults caused by short circuits of the semiconductor device, which is not possible with the approaches of the first group, since these only allow the detection of gate faults.

[0068] Methods according to the exemplary embodiments do not require knowledge of the turn-on and turn-off gate currents of an intact device. Therefore, according to the exemplary embodiments, no additional precautions or preliminary tests are required to determine the gate currents in the on and off states of the intact device, which reduces the testing effort.

[0069] According to a second group of conventional approaches, a gate fault in semiconductor devices with an insulated gate is detected by a deviation between the actual gate voltage and the gate voltage setpoint. The embodiments according to the invention have the following advantages over such approaches: Methods according to the exemplary embodiments do not require measurement or adjustment of the gate currents of the semiconductor devices and are therefore non-invasive. Gate current sensors are not part of the normal operation of power converters, and thus it is not desirable to use them "only" or primarily for testing purposes. Accordingly, these exemplary embodiments enable a reduction in the hardware complexity for testing.

[0070] Methods according to the exemplary embodiments can be used to detect short-circuit faults and faults due to open circuits in the semiconductor device, in contrast to the second group of conventional approaches, which are only suitable for detecting gate faults in the semiconductor devices.

[0071] According to a third group of conventional approaches, an excessive voltage in the semiconductor device in the on-state is used as an indicator of a device fault or a power loop fault. The embodiments according to the invention have the following advantages over such approaches: Methods according to the exemplary embodiments do not require any additional components in the gate driver circuit of the semiconductor device and are therefore non-invasive.

[0072] Methods according to exemplary embodiments can be used to detect short-circuit faults and gate faults of the semiconductor device in currentless power converters, whereas approaches according to the third group can only be used to detect faults caused by circuit interruption of semiconductor devices.

[0073] The previously described technical characteristics, especially in connection with Fig. 1, Fig. 2 to Fig. 3. may have one or more of the following effects and benefits: Embodiments according to the invention enable the detection and localization of at least three principal fault modes—open circuit faults, short circuit faults, and gate faults—of transistors, such as semiconductor devices with insulated gates, before the circuit is switched on, for example, in the form of a power converter, in contrast to conventional approaches according to the first, second, and / or third groups, none of which is suitable for detecting all three fault modes. This may be one of, or even the most important, advantages of embodiments according to the invention.

[0074] The process, for example, a test procedure according to exemplary embodiments, can be performed non-invasively, as it does not require access to additional signals within the circuit, such as the power converter. The measured voltage used for detection can be derived from existing voltage sensors, for example, voltage sensors connected to a power converter used, for instance, for normal operation of the power converter, and thus do not require implementation as additional test-specific hardware. Even if such a sensor is not present, it can be connected to the circuit, for example, to the terminals of the power converter, according to exemplary embodiments, and does not require access to the internal circuitry of the power converter. Thus, the exemplary embodiments according to the invention can be cost-effective and easy to implement.In contrast, the state of the art of the first, second and / or third group requires access to and penetration of the gate driver circuit of the semiconductor device.

[0075] Embodiments according to the invention can operate with few or even minimal components. For example, these embodiments can utilize a voltage threshold generator, an AND gate, a time delay block, and a comparator. These embodiments do not require extensive prior measurements (such as those required by conventional approaches of the first group).

[0076] In particular, embodiments according to the invention enable the detection of faults in devices in de-energized power converter systems and thus reduce the risk of multiple, successive faults after switching on.

[0077] It should also be noted that the exemplary implementations are not limited to measuring the capacitor voltage. Another possibility is to use a different voltage instead of the measured voltage (for example, 13 in Fig. 1) To use other physical quantities at the terminals (for example, the switching cell terminals) to draw the same conclusions regarding the integrity of the circuit (for example, the switching cell). The voltage across the individual devices in the switching cell could be one possible quantity.

[0078] A method according to exemplary embodiments can, for example, involve driving two series-connected transistors with insulated gates using complementary gate signals, for example a complementary pulse signal, for example with a dead time between complementary signal sections, in order to generate a signal (for example a voltage signal, for example v). fFor example, to induce a current signal (e.g., a residual voltage induced by a gate driver, such as GIRV, in a load path, such as a power loop) of the switching cell while the first and second terminals are in a de-energized state (e.g., not supplied with a voltage, not supplied with a test signal, or not supplied with a load path test signal). Furthermore, the method can include obtaining and evaluating information, such as an accumulated voltage in the conductor, via the signal induced from a control or gate path to the load path of the switching cell, in order to obtain a test result for the isolated-gate transistors.

[0079] Obtaining and evaluating the information can involve measuring at least one element of the group, which measures a voltage in a load path, at least one of the transistors with an insulated gate, a voltage between the first and second terminals, a voltage, for example V f , of the capacitor, a state of charge of the capacitor and / or a current induced in the load path of the switching cell.

[0080] Furthermore, it should be noted again that methods according to exemplary embodiments may include the joint evaluation of information about the signal induced in the load path of the switching cell and a control path information, for example a gate driver activation signal or a delayed version of the gate driver activation signal, of the switching cell in order to obtain the test result for the transistors with isolated gates.

[0081] Optionally, the processing means of a device according to exemplary embodiments can be configured to evaluate the information about the signal induced in the load path of the switching cell in order to falsify that the insulated gate transistors have an open circuit fault, a short circuit fault and a gate fault.

[0082] At least some devices according to exemplary embodiments can (a) feature or even rely on the activation of the gate drivers, but not the power loop circuits of the transistors (for example, semiconductor device with isolated gate), and (b) can measure the voltage (for example, 13 in Fig. 1) to use in the circuit or switching cell to distinguish intact from damaged devices, for example in a power converter.

[0083] Thus, exemplary embodiments can have a fault detection strategy that both (a) works, for example, only when gate driver signals are activated, and (b) distinguishes damaged devices from intact ones when the switching cell connections (for example, 10 and 11 in Fig. 1) remain separate, but does not distinguish damaged devices from intact ones when the terminals (10 and 11) are connected to an external voltage source whose polarity is such that the terminal designated 10 is at a higher electrical potential.

[0084] Exemplary embodiments according to the invention can generally be suitable for all power converter systems with a large number of modular switching cells where the detection, localization, and isolation of faulty switching cells before power-up is advantageous or even necessary to prevent cascade faults in the system. Examples include: a. modular DC / DC inverters for medium-voltage drives and high-voltage direct current transmission, b. solid-state converters and DC energy hubs for smart distribution systems, c. two-stage voltage source inverter applications, for example, for grid-connected and solar micro-inverter applications.

[0085] The exemplary embodiments are explained in more detail below. In particular, the principles of the exemplary embodiments with regard to the detection of switching cell faults by the driver-induced DC link residual voltage are described in more detail.

[0086] As previously described, exemplary embodiments enable the detection of faulty switching cells, for example, before the power loop is switched on, without additional hardware (i.e., exclusively or primarily test-specific). The inventors have recognized that using a gate driver-induced residual voltage (GIRV) that occurs on the de-energized GS bus allows differentiation between intact and damaged cells and thus the identification of faults. The GIRV can be quantified by analyzing the operating modes of the de-energized switching cell (e.g., in the time domain). The exemplary embodiments described below can be implemented with low hardware complexity and, for example, include only a measuring device, a driver circuit, and a signal processing circuit.

[0087] The following example describes the detection of device faults (such as transistor faults) in a general two-stage switching cell, which can be a common component of power converters. However, the implementations are not limited to such circuits. Furthermore, power MOSFETs are considered in particular due to their wide range of applications, especially with the advent of wide-bandgap devices. It should also be noted that the implementations can be based on a variety of transistor designs and are not limited to MOSFETs.

[0088] First, an overview of one approach is given according to examples of implementation: (i) The gate driver induced residual voltage (GIRV) that occurs due to the coupling between the gate and the power loop in the intermediate circuit of a currentless MOSFET-based two-stage switching cell can be used. (ii) The GIRV can be quantified based on a time-domain analysis of the operation of the de-energized switching cell, taking into account the parasitic elements of the device. Further embodiments can exploit dependencies of the GIRV on various device, circuit, and modulation parameters, on the basis of which, for example, an evaluation of the electrical quantity can be carried out or adjusted, for example, to define voltage thresholds for comparison. (iii) The evaluation of the electrical quantity can be based on the finding that the GIRV can change in the event of a short circuit, an open circuit and / or a gate fault of the device. (iv) Thus, exemplary embodiments may include a strategy for identifying and locating faults in switching cells that utilizes the difference in the GIRV between intact and damaged switching cells. Accordingly, exemplary embodiments may provide a device for implementing the proposed strategy, using, as an example, only the switching cell's GS bus voltage sensor. (v) The analysis of the GIRV was verified in both circuit simulations and experiments. (vi) The proposed fault detection strategy according to the embodiments was also validated in simulation and on existing converter hardware without the use of any additional components.

[0089] In general, the analysis of the electrical unit can be carried out using the parameters of the circuit and, in particular, the device, driver circuit and modulation parameters that may have an influence on the GIRV, as specified by the manufacturer.

[0090] The following will be discussed Fig. Reference is made to Figure 4, which presents schematic views of a two-stage MOSFET-based switching cell according to exemplary embodiments. Fig. Figure 4 shows: (a) a schematic of a canonical two-stage switching cell, with (b) the gate driver and the coupling between the GS bus voltage and the gate driver activation; (c) a detailed corresponding circuit diagram of the switching cell showing the gate driver and the junction capacitances.

[0091] Fig. Figure 4a shows a two-stage MOSFET-based switching cell, referred to simply as the cell. The cell comprises two MOSFETs 401, 402 (S1 and S2), body diodes and / or external antiparallel diodes 431, 432 (D1 and D2), and the DC link capacitor 403, C. f The isolated gate driver 407, 408 (GD) for each MOSFET is in Fig. 4b is represented as a general block. Activating the drive signals for the MOSFETs generates a voltage, v f , at the intermediate circuit capacitor 403 as in Fig. 4b shows the detailed corresponding circuit of the cell. Fig. 4c is shown. The quantities corresponding to the upper and lower devices are indicated by the indices 1 and 2, respectively. Each gate driver 407, 408 is represented as a voltage source 441, 451, V GG , in series with a gate resistor 442, 452, R g , shown. The gate circuit parameters as well as the capacities of gate-source 452, 462 (C ). gs), Drain-Source 454, 464 (C ds ) and Gate-Drain 453, 463 (C gd ) can, for example, be assumed to be identical for both devices.

[0092] It should be noted that appropriately named elements of Fig. 4 optional corresponding elements of Fig. 1 can correspond to 1 and vice versa; for example, element 4xx corresponds to element xx. Thus, in Fig. Figure 4 shows an example of the cell connections as represented by elements 410 and 411. Thus, corresponding features can have similar or identical characteristics, functions, and details to their counterparts. The signal 412 can be fed to a corresponding measuring device 12, for example, a voltage measuring device.

[0093] The cell can be operated in the de-energized state of the power loop. The gate pulses for the devices are complementary, optionally with a dead time, t. dThe waveforms of the gate-source voltage, magnified to the timescale of the switching process, are in Fig. 5 shown.

[0094] Fig. Figure 5 shows a schematic view of waveforms according to exemplary embodiments of the invention. Fig. Figure 5 shows representative waveforms of the gate-source voltage (v gs ), Drain-Source (v ds ) and GS bus (v f ) both in the initial state and in the stable state (for example, as in Fig. 4). The presence of gate-drain capacitances can couple these gate loop voltages to the power loop, resulting in non-zero drain-source voltages, as also shown in Fig. Figure 5 shows the drain-source voltage for charging the intermediate circuit capacitor C. f up to a voltage V f to be responsible.

[0095] The following are optional details regarding the time domain analysis and the quantification of GIRV according to the following examples: The in Fig. The switching transition shown in Figure 5 can begin with the switch-off command for one device of the cell and end with the switch-on of the other device. Based on this transition, the voltage V can be... f can be quantified. Broadly speaking, the transition can be described as the charging of the device's drain-source capacitances and their subsequent discharge into the GS bus capacitor C. f The circuit can be operated in four stages.

[0096] (i) Stage I (0 ≤ t < t l ): This phase can begin with the OFF command for the upper switch (S1), whose gate voltage v gs,1 falls as in Fig. 5 shown. This phase can continue as long as S1 is switched on, and ends when v gs,1 under V th falls.

[0097] During this phase, the tension, v ds,1 , clamped by the on-resistance of the upper switch. Therefore, power loop parameters, v ds,1 and v ds,2 , not noticeably, that is, significantly, different. The effects of this phase in connection with gate and power loop coupling can, for example, be negligible. The duration t I However, this phase can affect the duration of the other phases.

[0098] (ii) Phase II (0 ≤ t - t I < t II ): Switching off S1 can initiate this phase. The voltage v ds,1 For example, it cannot be clamped because S1 is switched off. Therefore, the continuous drop in gate-source voltage, v, cannot occur. gs,1 , in the power loop sizes, v ds,1 and v ds,2, suppress. The drain-source capacities can be recharged by coupling with the gate loop of S1. Stage II can be used with the dead time (t d ) end and thus the duration of stage II can be determined by t II = t d - t I be specified.

[0099] The gate-source voltage, v gs,1 , at the end of Phase II, with V i denoted. The change in drain-source stresses (v ds,1 and v ds,2 ) during phase II, for example, the value of the voltage v cannot be changed. f depend on the MOSFET parameters, the gate driver parameters, and the duration t II The increase in drain-source stress in Phase II, V II , is in Fig. Figure 5 is shown and can quantify the charging of the drain-source capacities at this stage.

[0100] (iii) Phase III (t I + t II ≤ t < t I + t II + t III): In this phase, S2 is switched ON. The gate-source voltage of S2 can rise in response to the switch-on command. This change in v gs,2 This can, for example, lead to corresponding changes in v ds,1 and v ds,2 This occurs because neither of the two switches is conductive and the gate and power loops are coupled. The voltage rises can have the same polarity as the corresponding rises in Phase II.

[0101] Similar to Phase II, the increase in drain-source voltage in Phase III, V III , regardless of v f be like in Fig. 5 shown. The increases of v ds,1 and v ds,2 Phases II and III can be cumulative.

[0102] (iv) Phase IV (t I +t II +t III ≤ t < T sw / 2): In this phase, the energy stored in the drain-source capacitances in phases II and III can be discharged into the GS bus capacitor.

[0103] Size V III represents the voltage across the drain-source capacitance of the de-energized device before it is switched on. This voltage may depend on the initial voltage in the device, but also on the voltage rises calculated using the relationships derived for phases II and III. The total voltage rise at the end of phase III is given by V X designated and can be independent of the initial voltage in the drain-source capacitance.

[0104] According to some embodiments, it may be necessary, for example, to provide a gate signal to achieve phases II, III, IV, so that optionally only II and IV or only III and IV may be insufficient.

[0105] The charging effects of body diodes and resistor circuits are explained below according to exemplary embodiments.

[0106] Resistors are frequently connected to a GS bus, particularly as a leakage resistor to balance shared capacitors or to couple the GS bus to voltage measurement circuits. These resistors can be a single resistor, R dc , which is connected via the GS bus. A change in voltage at C f , for example twice per switching cycle, can be taken into account for the evaluation of a charge balance equation, which can be used for the evaluation of the circuit.

[0107] Body diodes are an integral part of Si- and SiC-based MOSFETs. The polarity of the coupling voltage leads to a bias voltage of the body diodes and thus to a charging effect, which is quantified by the Shockley relation. This effect can also be used when determining the steady-state voltage VST. fTaking into account loading effects, the integrity information must be determined.

[0108] The following explains a parameter dependency of the GIRV, which can be used to determine the integrity information according to the examples provided.

[0109] The GIRV (V f The GIRV can depend on the parameters of the MOSFET, the gate driver circuit, and the modulation scheme. The influence of each of these parameters on the GIRV can be analyzed for different switching cells, and test parameterization, such as threshold determination, can be performed based on prior knowledge of such influences, for example, in a switching cell-type-specific or even switching cell-specific (e.g., individual) manner.

[0110] Of the device capacities, the gate-drain capacity C can be gd, for example, forming the coupling branch between the gate driver and the power loop. Thus, the variation of C gd have a drastic impact on GIRV. The influence of the gate-source capacitance (C) gs ) and drain-source capacity (C ds ) can be much lower in comparison.

[0111] Since the circuit time constants in phases I, II and III are proportional to the gate resistance R g higher R can be g High R-values ​​slow down these transitions and thus reduce the extent of charge transfer. Therefore, high R-values ​​can... g -Values ​​that decrease GIRV.

[0112] The GIRV can be primarily influenced by the charging of the drain-source capacitances in phases II and III. These two intervals can cause a gate-source voltage change between V. off GG and V thThis includes the difference between the gate-on voltage and the threshold voltage (V). on GG -V th ) have a negligible influence on the GIRV. In contrast, the difference between the gate-off voltage and the threshold voltage (V) can off GG -Vth) significantly influence the GIRV.

[0113] Since the threshold voltage varies between units of a given MOSFET product, quantifying the variation of the GIRV can be relevant for fault detection and thus be considered for evaluating the electrical quantity. The GIRV can exhibit a strong dependence on the switching frequency, f sw, exhibit. Since the GIRV can arise at each switching transition due to a fixed charge transfer, it can increase with the frequency of these transitions, i.e., with the switching frequency. The rate of increase can flatten out at higher GIRV values, which is due, for example, to the nonlinear charging effect of the diodes. Finally, low values ​​of the dead time (t) d ) allow insufficient time for Phase II and thus reduce GIRV.

[0114] The following explains the error detection procedures according to the implementation examples: The previously described charge transfer mechanism from the gate driver to C f In an intact cell, a voltage, V, can be present. f , generated in the GS bus. The mechanism can depend on three different processes, namely the accumulation of charge on the drain-source capacitance of the switched-off device, the transfer of this charge to C fand the storage of charge at C r .

[0115] In a faulty cell, the interruption of one or more of these processes can affect the voltage V f This can significantly influence the differentiation between faulty and intact cells by measuring the voltage V. f enable; the way in which V f The degree to which the error is affected can depend on the type of fault in the cell. In the following analysis, it can be assumed that any fault occurs at the upper switch (S1). A. Short-circuit fault

[0116] It will be on Fig. 6 referred. Fig. Figure 6 presents schematic views of corresponding circuits of a de-energized cell in a fault condition according to exemplary embodiments: (a) Short-circuit fault causing discharge of the GIRV in phase IV. (b) Fault due to open circuit or gate fault, wherein the faulty upper device is replaced by its corresponding capacitance network. Transfer of charge to C f , illustrated by simplified charge flow circuits for phases (c) II, (d) III and (e) IV. Omission of phase II in the event of a fault due to circuit interruption or gate failure can lead to the cancellation of the charges transferred in phases III and IV.

[0117] The faulty device can be described as a resistance R. sc 660 between the drain and source connections can be modeled as in Fig. 6 shown. When the intact device is switched on in phase IV, any voltage can be applied to C. f(for example, capacitor 603, which for example corresponds to capacitor 3 of Fig. 1 or Fig. 403 of Fig. 4 corresponds) into a short circuit. Thus, a cell in which one or two devices are short-circuited can have a negligible voltage at C. f Since even large resistances (e.g., leakage resistances) exert a charging effect on the GIRV, short-circuit resistances several orders of magnitude higher than the device's on-resistance can cancel the GIRV. Thus, the methods according to the exemplary embodiments enable the detection of short-circuit faults, even if these have a significant short-circuit resistance. B. Errors due to circuit interruption and gate errors

[0118] The device cannot switch on if there are faults due to circuit interruption or faults in the device gate or gate driver. In this case, the device can only be represented as a network of corresponding capacitors 670, and these capacitances may differ from those of an intact device. The charge flow during the operation of an intact, de-energized cell is shown for phases II, III, and IV in Fig. 5c, Fig. 5d and Fig. 5e each is shown. The ones in phases II and III on C f transferred charges, each denoted as q II and q III , run in opposite directions and are almost the same size. Thus, they can cancel each other out, and the GIRV can, due to the charge (q), IV ) arise, which in Phase IV on C f is transmitted. If S1 has a circuit breaker, phase II can be taken out of service. The one on Cf The total transferred charge corresponds to (q III -q IV ), which demonstrably cancels itself out in this case. Therefore, no GIRV may arise. C. Error detection strategy and implementation

[0119] The absence of voltage on the de-energized GS bus can indicate a fault in the switching cells connected to this GS bus. Generally, detecting this fault according to the exemplary implementations is achievable without new components in the power converter, and a corresponding strategy is described below.

[0120] The gate driver signals of a switching cell can be activated first. For multiple switching cells connected to a GS bus, for example in an H-bridge configuration, only the gate signals of the cell under test are activated. During testing, source and load disconnect switches can be turned off to keep the GS bus isolated. The coupling voltage measured by the voltage sensor on the GS bus can then be measured. The voltage measured before and after gate signal activation can be compared to eliminate sensor offset. The difference between the two values ​​is compared to a threshold calculated using the simple procedure described earlier. If the difference is below the threshold, a fault alarm can be triggered for the phase section under test.

[0121] The following are some examples of implementation: According to exemplary embodiments, a strategy for detecting faults in transistor circuits, such as MOSFET switching cells, is implemented based on capacitive coupling between the gate and the power loop, for example, between a control path and a load path. The coupling mode can be analyzed, and the coupling voltage, which can be used to distinguish between intact and faulty cells, is quantified, for example, in the form of a threshold for comparison.

[0122] An implementation according to the exemplary embodiments can consist of standard voltage sensors, analog-to-digital converters, and digital control platforms. These embodiments can enable the detection of faults comparable to the deviations resulting from differences between identical devices. The proposed fault detection method according to the exemplary embodiments has been validated in hardware using existing gate drivers and GS-bus voltage sensors and can therefore be implemented in existing hardware setups with little or no architectural modification. The proposed strategy according to the exemplary embodiments is valuable for detecting faulty circuits, such as MOSFET switching cells in currentless converters, using only the gate driver turn-on and the existing GS-bus voltage sensor (for example, a simple resistor divider).

[0123] Thus, the strategy can be implemented according to the exemplary embodiments by integrating the test routine, for example, into the power converter's startup protocol, without requiring any modifications to the existing hardware. Furthermore, the parameters required for fault detection can be estimated using only known circuit and modulation parameters, optionally in conjunction with MOSFET data provided by the manufacturer; no additional device characterization is necessary. Therefore, the methods according to the exemplary embodiments are both simple and widely applicable for detecting faults in power converters before commissioning.

[0124] The following refers to details of the invention relating to the selection of threshold voltages, for example to the selection of threshold voltage 14, in Fig. 1.

[0125] In semiconductor devices 1 and 2 in Fig. 1. These could be, for example, MOSFETs or IGBTs. MOSFETs have an internal body diode whose forward voltage, VDS(on), is determined by the voltage at which they are switched. D , which can be found in the MOSFET's datasheet. IGBTs are typically equipped with an external antiparallel diode connected via this; here too, the forward voltage V can be determined. D This diode's datasheet can be found here.

[0126] The threshold voltage 14 is expressed as -V D / 10 (for example, with a tolerance of + / -10%) is recommended (this can be specified, for example). Since power semiconductor diodes have a forward voltage, V f If the voltage is in the range of 1.5 to 2.0 volts, this means that, for example, a fixed value of minus 0.2 volts can be used for the threshold voltage 14. Thus, such a setting can enable good standard test parameterization.

[0127] An alternative method to the one described above can consist of determining the expected voltage, V. f , in capacitor 3 in Fig. 1 to calculate. Then the threshold voltage 14 can be in Fig. 1 based on V f be defined, for example as V f / 2 (for example, with a tolerance of + / -10%).

[0128] Thus, the threshold voltage can generally be determined according to exemplary embodiments using one or more properties of the transistors, for example a forward voltage of a diode connected to the transistors, or as a fraction of an expected voltage in the capacitor, for example ½ of the expected voltage in the capacitor.

[0129] Details of the invention relating to the choice of the time delay T will be discussed below. d referred, for example, as in Fig. 2 and Fig. 3 shown: The time delay T dcan be calculated based on a time constant τ. The time constant τ can be determined as follows: τ=Cf2fsw(Cgd+Cds)+1Rdc

[0130] This includes: f sw the switching frequency; C f the capacitance of the switching cell capacitor, 3; C gd the gate-drain capacitance of the semiconductor device; C ds the drain-source capacitance of the semiconductor device; R dc the resistance in the switching cell.

[0131] Then the time delay T can be d calculated with an error margin of 10X, that is, T d = 10τ.

[0132] Furthermore, it is noted Fig. 7 referred. Fig. Figure 7 shows a schematic flow diagram of a fault detection strategy according to exemplary implementations. Thus, an electrical quantity, for example v, can be used as an optional feature. f, measured or recorded, 710. On this basis, V0, that is, the value of the voltage in the capacitor before the start of the test, can be determined and, for example, stored as a reference value, see 750. Furthermore, the majority of transistors connected in series can be driven complementarily (for example, after the determination of V0), for example, activated by a start-gate pulse, with the two terminals of the circuit being in a de-energized state, 720. Optionally, the gate driver activation signal can be delayed before evaluation, 740, for example, before it is logically combined with the output signal of the comparator. Furthermore, based on a recording or measurement of the electrical quantity, for example v f , during the provision of the gate driver signals 740 a voltage V fThe voltage is determined at the terminals (and is therefore measured after the start of the test). The difference between the capacitor voltage before the start of the test, V0, and the capacitor voltage measured during the test, V, is then calculated. f , that is (V f -V0), could be the accumulated voltage due to the driver. The difference, or possibly an absolute difference, for example |V r - V0l, can be compared to a threshold δ 760 to obtain the integrity information, for example "fault" or "no fault".

[0133] Thus, exemplary embodiments can include the consideration and optional determination of a reference value, for example V0, in order to determine an accumulated electrical quantity in a load path of the circuit, which is caused by a test pulse supplied to a control path of the circuit.

[0134] Furthermore, it is noted Fig. 8 referred. Fig. Figure 8 shows schematic views of circuits in various states of integrity, along with examples of corresponding signals. That is to say, Fig. Figure 8 shows a device fault detection strategy according to embodiments, experimentally applied to (a) an intact switching cell without fault detection and a switching cell with a MOSFET with (b) short circuit, (c) open circuit and (d) open gate, where faults are detected in these cases.

[0135] In Fig. 8 is the voltage v r The capacitor 403 is indicated as 813 in the respective drawings and can be connected to signal 13 in Fig. 2 and Fig. 3 correspond to, which shows an example of signal 13 in connection with various error modes, as in the context of Fig. 4 explained. As in Fig. The examples shown in section 8 enable the detection of various fault modes of the circuit. Further examples of implementation

[0136] The previously described embodiments primarily concerned the differentiation between intact / fully functional circuits and non-intact / faulty circuits by comparing a voltage generated at the circuit terminals by the complementary drive of the transistors, where the terminals are de-energized or in a closed-circuit state, with a threshold voltage set to a value obtained during the operation of an intact circuit by the complementary drive of the transistors, where the terminals are de-energized or in a closed-circuit state. However, the present invention is not limited to a simple determination of whether a circuit is intact / functional or non-intact / faulty; rather, according to other embodiments, a state of impairment of a circuit is also taken into account.

[0137] As previously described, according to exemplary embodiments, the threshold against which the voltage at the capacitor or at the terminals is compared can also be defined as a fraction of an expected voltage. That is, considering an intact circuit and when the respective transistors are driven complementarily with currentless terminals as described previously, a charge transfer from the transistors to the capacitor results in a specific or expected voltage that can be detected at the terminals. The threshold can be set to a fraction of this expected voltage, for example, 1 / 2 or 4 / 5 of this expected voltage. Thus, for example, by testing various circuits at different degrees of impairment, it is possible to determine up to what degree of impairment a circuit functions reliably.This can be represented by the fraction of the expected voltage, so that by setting the threshold to this fraction of the expected voltage, a distinction can be made between intact / not excessively affected and non-intact / excessively affected circuits.

[0138] If the threshold is set, for example, at 4 / 5 of the expected voltage, the circuit is assumed to function reliably as long as the voltage detected at the terminal is at least 4 / 5 of the expected voltage. Otherwise, the circuit is considered to be so severely impaired that reliable operation can no longer be assumed or expected.

[0139] According to exemplary embodiments, the circuit, for example the circuit in Fig. 1. are considered intact (not impaired beyond a certain degree) or not intact (impaired beyond a certain degree) depending on a comparison of the voltage measured at the terminal with the threshold, which is set at a fraction of the expected voltage at the terminals. With regard to Fig. 2 and Fig. Section 3 now describes the process for determining whether the circuit is intact or not. As in Fig. 2 and Fig. As shown in Figure 3, the activation signal 9 is set to a high level, so that the gate driver signals 5, 6 for the devices / transistors 1, 2 are activated. According to this embodiment, the threshold 14 is set to a fraction of the previously mentioned expected voltage at the terminals of an intact system (when operated by complementary drive of the transistors with no current applied). As shown in Fig. Figure 2 shows that in an intact cell, a negative value of the voltage 13 (the voltage generated by the complementary drive of the transistors with no current applied) is measured, which is below the threshold 14. Thus, the threshold comparison output 16 becomes low. The delay Td in the delayed activation signal 18 can be adjusted or set so that the delayed signal 18 only becomes high when the comparison output 16 becomes low. Therefore, the output 20, which can now be referred to as an impairment indication output 20, remains low and indicates an intact switching cell, that is, a switching cell that is not yet impaired beyond a certain degree.

[0140] On the other hand, as in Fig.Figure 3 shows a negative value of voltage 13 that is above threshold 14, or a non-negative value of voltage 13 measured after the gate driver activation signal has been activated, if the cell has degraded or been impaired beyond a certain level of impairment. Thus, the threshold comparison output 16 remains high, so that when the delayed gate driver activation signal 18 becomes high, the impairment indication output 20 also becomes high, indicating impairment of the circuit beyond a certain degree, for example, impairment of one, some, or all of the circuit elements, especially the active elements, such as transistors 1 and 2 of the circuit.

[0141] The advantage of this embodiment is that, unlike the first embodiment, which only distinguishes between intact (fully functional) and non-intact (non-functional) circuits, it enables the monitoring and maintenance of circuits within an overall system, as long as the degree of impairment does not exceed a certain, predefined level. This avoids the need to replace circuits that are no longer fully functional but still operate reliably given the degree of impairment. Thus, these embodiments also provide a method and a device for monitoring the impairment of circuits, such as isolated-gate semiconductor devices in a power electronics converter, while the converter is de-energized.

[0142] The state of the art includes several approaches for detecting deterioration of circuit elements.

[0143] (1) A first approach relates to a method for detecting deterioration of semiconductor elements by maintaining a voltage in a semiconductor device at a predetermined level by varying the control voltage of the semiconductor device, and if the device is unable to maintain the voltage at a constant level, this is considered to be an impairment of the device.

[0144] This approach has the disadvantage that it offers no way to detect impairment of device parameters that affect the dynamic performance of a device, thus limiting its possibilities. Furthermore, the test requires a special circuit with a variable control voltage, adding complexity and cost. Additionally, the test requires the device to be mounted at the test site, making it impossible to perform the test on-site with existing systems.

[0145] (2) A second approach relates to a diagnostic device and a method for determining a defect in an electrical connection in a power semiconductor device. A voltage in a semiconductor device is measured at different current values ​​and stored as a calibration reference. Subsequently, the voltages in the device are measured at exactly the same currents and compared with the calibrated values, so that a deviation between the measured and the calibrated values ​​can be attributed to a defect in the device.

[0146] This approach has the disadvantage that there is no way to detect the impairment of device parameters that affect dynamic performance, which limits the applicability of this method. Furthermore, current and voltage measurement setups, as well as synchronization mechanisms for these setups, are required, increasing the cost and complexity of the test.

[0147] (3) A third approach concerns the determination of deterioration of a power semiconductor module based on a temperature derived from a value of a temperature-dependent device parameter. This is compared with an actual measured temperature, and a deviation is considered an impairment of the device.

[0148] This approach has the disadvantage that if the device parameter depends on quantities other than temperature, variations in these quantities can interfere with the inference and lead to unreliable results. Furthermore, the approach requires temperature measurement, which incurs additional costs and complexity due to the necessary sensors.

[0149] (4) A fourth approach concerns detecting impairment of semiconductor devices by measuring a range of properties and comparing these with reference or calibration values ​​in order to infer impairment of the device depending on the deviations detected.

[0150] This approach is disadvantageous because it requires a large number of additional sensor circuits, thus increasing the complexity and cost of the measurement system. Furthermore, the method cannot be used on existing systems due to the necessary circuit modifications.

[0151] (5) A fifth approach concerns the detection of impairments caused by aging of power electronics equipment by passing a sinusoidal current through a semiconductor device under test. The resulting temperature rise of the device is recorded. The amplitude of the temperature variation is compared with the reference amplitude to infer impairment of the device.

[0152] This approach has the disadvantage that impairments not directly affecting line loss cannot be detected with this method. Furthermore, additional circuitry and sensors are required for applying the sinusoidal current excitation and measuring the amplitude of the temperature variation, increasing complexity and cost. Additionally, the method requires the device to be set up in a test environment and therefore cannot be performed on-site.

[0153] In contrast to the previously described known approaches, the inventive approach according to the exemplary embodiments is advantageous for determining an impairment of a circuit, since every type of impairment that directly affects the parameters of the device and indirectly affects the measured voltage can be detected, i.e. there is no limitation for detecting an impairment of a specific type, as is present in the previously described prior art approaches (1), (2), (3) and (5).

[0154] Furthermore, the approach according to the invention is non-invasive, as it does not require access to additional signals within the overall system, such as the current converter. The measured voltage used for detection is available from a voltage sensor connected to a current converter, and even if such a sensor is not present, an external sensor can be connected to the converter's terminals, and no access to the circuit or the current converter is required. Thus, the approach according to the invention is less costly and easier to implement, in contrast to the prior art approaches (1) to (5) described above, which require access to or intervention in the gate driver circuit of the semiconductor device as well as additional measurement and testing arrangements.

[0155] Furthermore, embodiments of the approach according to the invention require minimal components, for example, a voltage threshold generator, an AND gate, a time delay block, and a comparator; that is, they only require a single prior measurement, namely the voltage of an intact cell, to determine the voltage threshold during a first calibration. On the other hand, the prior art approaches described above, in particular approaches (2) and (5), require a large number of additional measurements and calibrations.

[0156] According to exemplary embodiments, the inventive approach can be applied to any power converter system that has a large number of modular switching cells and where early detection of impairment, for example during periodic maintenance, is desirable to prevent faults. Examples of such systems are modular high-voltage DC / AC power converters for medium-voltage drives and high-voltage direct current transmissions, solid-state converters and DC energy hubs for smart distribution systems, as well as two-stage voltage source inverter applications, such as those used in grid-connected and solar microinverter applications. Alternative implementation options:

[0157] Although some aspects have been described in connection with a device, it is clear that these aspects also constitute a description of the corresponding method, wherein a block or device corresponds to a method step or a feature of a method step. Similarly, aspects described in connection with a method step also constitute a description of a corresponding block, element, or feature of a corresponding device. Some or all of the method steps may be performed by (or through the use of) a hardware device, such as a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, one or more of the key method steps may be performed by such a device.

[0158] Exemplary embodiments of the invention, in particular functionalities for evaluating the measured entities to obtain integrity information and / or to provide control signals, can be implemented in hardware or software, depending on specific implementation requirements. The implementation can be carried out using a digital storage medium, for example, a floppy disk, DVD, Blu-ray disc, CD, ROM, PROM, EPROM, EEPROM, or flash memory, on which electrically readable control signals are stored. These signals can interact with a programmable computer program to execute the respective method. Therefore, the digital storage medium can be computer-readable.

[0159] Some embodiments of the invention include a data carrier with electronically readable control signals that can work together with a programmable computer system, so that one of the methods described herein is carried out.

[0160] In general, embodiments of the present invention can be implemented as a computer program product comprising program code, wherein the program code is functional for executing one of the methods when the computer program product runs on a computer. The program code can, for example, be stored on a machine-readable medium.

[0161] Other embodiments include the computer program for executing one of the methods described herein, stored on a machine-readable medium.

[0162] That is to say, an embodiment of the method according to the invention is thus a computer program with program code for executing one of the methods described herein when the computer program is running on a computer.

[0163] Another embodiment of the method according to the invention is thus a data carrier (or a digital storage medium or a computer-readable medium) on which the computer program for executing one of the methods described herein is recorded. The data carrier, the digital storage medium, or the recorded medium is typically physical and / or non-volatile.

[0164] Another embodiment of the method according to the invention is therefore a data stream or a sequence of signals for representing the computer program for executing one of the methods described herein. The data stream or sequence of signals can, for example, be configured to be transmitted via a data communication connection, such as the Internet.

[0165] Another embodiment includes a processing means, for example a computer or a programmable logic module, configured or adapted to perform one of the methods described herein.

[0166] Another embodiment includes a computer on which the computer program for executing one of the methods described here is installed.

[0167] Another embodiment of the invention comprises a device or system configured for transmitting (for example, electronically or optically) a computer program for executing one of the methods described herein to a receiver. The receiver can be, for example, a computer, a mobile device, a storage device, or the like. The device or system can, for example, include a file server for transmitting the computer program to a receiver.

[0168] In some embodiments, a programmable logic device (for example, a field-programmable gate array) can be used to perform some or all of the functionalities of the methods described here. In some embodiments, a field-programmable gate array can work in conjunction with a microprocessor to perform one of the methods described here. Generally, the methods are performed by any hardware device.

[0169] The device described here can be implemented using a hardware device, a computer, or a combination of a hardware device and a computer.

[0170] The device described herein, or any components thereof, may be implemented at least partially in hardware and / or software.

[0171] The procedures described here can be carried out using a hardware device, using a computer, or using a combination of a hardware device and a computer.

[0172] The methods or components of the device described herein can be implemented at least partially by hardware and / or software.

[0173] The embodiments described above serve only to illustrate the principles of the present invention. It should be noted that modifications and variations of the arrangements and details described herein are obvious to a person skilled in the art. Therefore, the intention is to limit the scope of the invention through the scope of the pending claims, and not through the specific details presented here to describe and explain the embodiments.

Claims

[1] Method for testing a circuit (200) wherein the circuit has two terminals (10, 11, 410, 411), a capacitor (3, 403, 603) coupled between the two terminals and a plurality of series-connected transistors (1, 2, 401, 402, 431, 432) coupled in parallel with the capacitor between the two terminals, wherein the method comprises the following steps: Complementary control (720) of the majority of series-connected transistors, wherein the two terminals are in a currentless state, Detection (710, 740) of an electrical quantity (13, 412, 413, 813) of the circuit, and Determine (760) using the electrical quantity whether the circuit is intact or not. [2] Method according to claim 1, wherein the detection of the electrical quantity comprises one or more of the following steps: - Detecting a voltage (13, 412, 413, 813) at the capacitor (3, 403, 603), for example by connecting a voltage measuring device (12) to the two terminals (10, 11, 410, 411); - Detecting a voltage (13, 412, 413, 813) at the terminals (10, 11, 410, 411); - Detection of a voltage across one or more individual elements (1, 2, 3) in the circuit (200). [3] Method according to claim 1 or 2, wherein determining whether the circuit (200) is intact or not comprises the following steps: - Comparing (15, 760) a voltage (13, 412, 413, 813) with a threshold voltage (14), and - Determine (760), using comparison, whether the circuit is intact or not. [4] Method according to claim 3, wherein the threshold voltage (14) is determined using one or more properties of the transistors (1, 2, 401, 402, 431, 432), for example a forward voltage of a diode (431, 432) connected to the transistors. [5] Method according to claim 4, wherein If the circuit is intact, the complementary driving (720) of the majority of series-connected transistors, with the two terminals (10, 11, 410, 411) in a currentless state, produces an expected voltage (V f ) at the two terminals (10, 11, 410, 411), and the threshold voltage (14) has a value equal to the expected voltage (V) f ) is, so that by measuring the voltage at the two terminals (10, 11, 410, 411) intact circuits can be distinguished from faulty circuits. [6] Method according to claim 3, wherein the threshold voltage (14) is determined as a fraction of an expected voltage across the capacitor (3, 403, 603), for example 1 / 2 or 4 / 5 of the expected voltage across the capacitor. [7] Method according to claim 6, wherein If the circuit is intact, the complementary driving (720) of the majority of series-connected transistors, with the two terminals (10, 11, 410, 411) in a currentless state, the expected voltage (V f ) at the two terminals (10, 11, 410, 411), and the threshold voltage (14) has a value equal to the fraction of the expected voltage (V) f) is to be able to distinguish between intact circuits that are impaired by less than a certain degree and non-intact circuits that are impaired by the certain degree or by more than the certain degree by measuring the voltage at the two terminals (10, 11, 410, 411). [8] Method according to any one of claims 3 to 7, wherein - the circuit (200) is determined to be not intact or faulty if a comparison (15, 760) of the voltage (13, 412, 413, 813) and the threshold voltage (14) yields a comparison signal (16) with a first logic level, for example a high level, - the circuit (200) is determined to be intact if the comparison (15, 760) of the voltage (13, 412, 413, 813) and the threshold voltage (14) yields the comparison signal (16) with a second logic level, for example a low level. [9] The method according to claim 8, further comprising the following steps: - logical combination (19) of the comparison signal (16) and a gate driver activation signal (9, 18) which causes the control of the transistors (1, 2, 401, 402, 431, 432) and has the first logic level, - if the comparison signal and the gate driver activation signal have different logic levels, indicate (20) that the circuit (200) is intact, and - if the comparison signal and the gate driver activation signal have the same logic levels, indicate (20) that the circuit (200) is not intact or faulty. [10] Method according to one of the preceding claims, wherein the control (720) of the plurality of series-connected transistors (1, 2, 401, 402, 431, 432) comprises the application of complementary gate driver signals (5, 6) to respective control terminals of the series-connected transistors to switch the transistors on and off in a complementary manner. [11] Method according to claim 10, wherein the driving (720) of the plurality of series-connected transistors (1, 2, 401, 402, 431, 432) comprises activating a plurality of gate drivers (7, 8, 407, 408) coupled to the respective transistors using the gate driver activation signal (9). [12] Method according to any of the preceding claims, wherein the plurality of series-connected transistors (1, 2, 401, 402, 431, 432) comprise an Insulated Gate Bipolar Transistor (IGBT) and / or a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). [13] Method according to claim 12, wherein the plurality of series-connected transistors (1, 2, 401, 402, 431, 432) comprises two series-connected IGBTs or two series-connected MOSFETs coupled in parallel with the capacitor (3, 403, 603) between the two terminals (10, 11, 410, 411). [14] Device (100) for testing a circuit (200), wherein the circuit has two terminals (10, 11, 410, 411), a capacitor (3, 403, 603) coupled between the two terminals and a plurality of transistors (1, 2, 401, 402, 431, 432) connected in series and coupled in parallel with the capacitor between the two terminals, wherein the device has the following features: a driver circuit (110) that can be connected to the majority of series-connected transistors to control the majority of series-connected transistors of the circuit in a complementary manner (720), a measuring device (12) for detecting (740) an electrical quantity (13, 412, 413, 813) of the circuit, wherein the two terminals are in a currentless state and the majority of series-connected transistors of the circuit are controlled complementarily, and a signal processing circuit (120) coupled to the measuring device to determine, using the electrical quantity (760), whether the circuit is intact or not. [15] Device according to claim 14, wherein the measuring device (12) is designed to measure a voltage (13, 412, 413, 813) in order to detect the electrical quantity, and where the voltage is at least one of the following: - a voltage (13, 412, 413, 813) at the terminals (10, 11, 410, 411), - a voltage (13, 412, 413, 813) across the capacitor (3, 403, 603), - a voltage applied to one or more individual elements (1, 2, 3) in the circuit (200). [16] Device according to claim 15, wherein - the signal processing circuit (120) has a comparator (15) for comparing (760) the voltage (13, 412, 413, 813) with a threshold voltage (14), - the signal processing circuit (120) is configured to output an initial signal (16, 20) indicating that the circuit (200) is not intact or faulty when the comparator outputs a comparison signal (16) that has an initial logic level, for example, a high level, and - the signal processing circuit (120) is configured to output a second signal (16, 20) indicating that the circuit (200) is intact when the comparator outputs a comparison signal (16) that has a second logical level, for example a low level. [17] Device according to claim 16, wherein If the circuit is intact, the complementary driving (720) of the majority of series-connected transistors, with the two terminals (10, 11, 410, 411) in a currentless state, produces an expected voltage (V f ) at the two terminals (10, 11, 410, 411), and the threshold voltage (14) has a value which - equal to the expected voltage (V f ) is such that by measuring the voltage at the two terminals (10, 11, 410, 411) intact circuits can be distinguished from faulty circuits, or - equal to a fraction of the expected voltage (V f ) is to be able to distinguish between intact circuits that are impaired by less than a certain degree and non-intact circuits that are impaired by the certain degree or by more than the certain degree by measuring the voltage at the two terminals (10, 11, 410, 411). [18] Device according to claim 16 or 17, wherein - the signal processing circuit (120) further comprises a logic gate (19) for logically combining the comparison signal (16) of the comparator (15) and a gate driver activation signal (9, 18) which causes the control of the transistors (1, 2, 401, 402, 431, 432) and has the first logic level, - the logic gate is configured to output the first signal (20) when the comparison signal and the gate driver activation signal have the same logic levels, and - the logic gate is configured to output the second signal (20) when the comparison signal and the gate driver activation signal have different logic levels. [19] Device according to claim 18, wherein the logic gate comprises an AND gate (19). [20] Device according to one of claims 14 to 19, wherein the driver circuit (110) comprises respective gate drivers (7, 8, 407, 408) which can be connected to the transistors (1, 2, 401, 402, 431, 432) to apply complementary gate driver signals (5, 6) to respective control terminals of the transistors connected in series in order to switch the transistors on and off in a complementary manner.

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