SWITCH CONTROL AND REDUCTION OF POWER CONSUMPTION

Abstract

A power converter arrangement discussed herein may be configured to include: a first input effective in receiving a first control signal indicating how to control a main switch; a switch driver circuit arrangement effective in converting the first control signal into a second control signal; and an output effective in outputting the second control signal to the main switch, wherein the second control signal includes a first current supplied to the main switch by a first current source of the switch driver circuit arrangement, the magnitude of which varies based on a voltage magnitude of the second control signal.

Description

[0001] Conventional switch driver circuit arrangements can be configured to receive a primary control signal from a controller and convert it into a secondary control signal that is applied to a respective switch to control its operation.

[0002] One reason for using switch driver circuit arrangements is to isolate the control circuitry from the switch and to properly drive each control input of the switch. For example, the control circuitry may be configured to operate in a first voltage range. The switch may then need to operate in a second voltage range that differs from the first. In certain cases, switches such as GaN (gallium nitride) field-effect transistors require specific drive signals to keep the switch in an ON or OFF state.

[0003] Conventional solutions for driving a given GaN field-effect transistor, such as those using an RC network, can overload the GaN gate of the field-effect transistor, e.g., the RC network, and others can rely solely on the response time of a given driver circuit that senses the GaN power switch Vgs to minimize gate overload.

[0004] The implementation of clean energy (or green technology) is crucial for reducing our impact on the environment. Generally, clean energy encompasses all developing processes and materials aimed at reducing the overall environmental toxicity caused by energy consumption.

[0005] This revelation includes the observation that a desirable aspect of a switch driver circuit is to achieve better power efficiency in controlling individual switches. For example, a certain amount of power is derived simply by turning a switch on and off. Implementing an efficient switch driver circuit arrangement reduces the amount of power consumed when turning a switch on and off.

[0006] The object of the present invention is to provide a device and a method with improved properties.

[0007] This problem is solved by a device according to claim 1 and a method according to claim 18.

[0008] In particular, a power converter arrangement discussed herein may be configured to include: a first input effective in receiving a first control signal indicating how to control a main switch; a switch driver circuit arrangement effective in converting the first control signal into a second control signal; and an output effective in outputting the second control signal to the main switch, wherein the second control signal includes a first current supplied to the main switch from a first current source of the switch driver circuit arrangement, the magnitude of which varies based on a voltage magnitude of the second control signal.

[0009] In one example, the first current source can be, or include, a field-effect transistor that outputs the initial current to a gate node of the main switch. The output of this initial current increases the magnitude of the voltage applied to the gate node of the main switch. This increased voltage causes the gate node of the main switch to either turn itself off or increase its resistance. The increased resistance reduces the magnitude of the initial current supplied to the gate node of the main switch, as discussed further herein.

[0010] The first current source can be a field-effect transistor (FET) or include one that has a source node effective in supplying the first current to a gate node of the main switch. The supply (and control) of the first current from the source node of the FET to the gate node of the main switch can be configured to decrease the magnitude of the first current over time. For example, the magnitude of the first current can be configured to decrease over time in response to an increase in the RDS-on resistance between a drain node and the source node of the FET.The RDS-on resistance between the drain node and the source node of the field-effect transistor increases during operation in response to a decrease in the gate-source voltage between the gate node and the source node of the field-effect transistor, with the decrease occurring in response to an increase in the voltage magnitude of the second control signal (such as applied to a gate node of the main switch) over time.

[0011] It should further be noted that the device discussed herein may be configured to include a second current source effective in generating a second current, the second current source being connected in parallel to the first current source, the second control signal comprising a combination of the first current and the second current; and the second control signal being able to be applied to a gate node of the main switch to control the main switch. The first control signal, such as from a controller or other suitable entity to the main switch, may indicate to activate the main switch for a period of time.Furthermore, the first power source can be configured to: i) supply the first current to the gate node of the main switch for a first segment of the time period; and ii) interrupt the supply of the first current to the gate node of the main switch for a second segment of the time period, the second segment following the first. The second power source can be configured to supply the second current to the gate node of the main switch for both the first and second segments of the time period; and the output of the second control signal to the gate node for the entire time period can be configured to keep the main switch in an ON state for that time period.

[0012] The magnitude of the initial current at one end of the first section of the time period can be configured to keep the main switch in an ON state.

[0013] In other examples discussed herein, the first current source can be a field-effect transistor or include one that is effective in supplying the first current from a source node of the field-effect transistor to a gate node of the main switch. The first current supplied by the field-effect transistor to the gate node of the main switch increases the voltage magnitude of the second control signal supplied to the gate node of the main switch. The field-effect transistor can be an N-type field-effect transistor or another suitable entity.Increasing the voltage magnitude of the second control signal applied to the gate node of the main switch can be configured to reduce a gate-source voltage between a gate node of the field-effect transistor and the source node of the field-effect transistor, with the reduced gate-source voltage effectively reducing the magnitude of the first current supplied by the source node of the field-effect transistor to the main switch.

[0014] The main switch can be implemented and / or manufactured in any suitable manner. For example, the main switch can be made of gallium nitride (GaN). In another example, the main switch discussed herein can be a GaN device or, more specifically, a GaN gate injection transistor (GIT) device.

[0015] Further examples discussed herein include an implementation of the device comprising: a second input effective in receiving feedback that tracks the voltage magnitude of the second control signal (the feedback may be the second control signal itself); a comparator effective in comparing the received feedback (such as the second control signal applied to the gate node of the main switch) to a threshold level; and a signal generator effective in terminating the activation of the first current source supplying the first current to the main switch in response to the detection that the feedback exceeds, is above, or is below the threshold level.

[0016] According to further examples discussed herein, the device can be configured to include a first switch connected between a gate node of the main switch and a source node of the main switch, the first switch being effective in short-circuiting the gate node of the main switch with the source node of the main switch during the start-up of the switch driver circuit arrangement in order to prevent activation of the main switch when the power used to supply power to the switch driver circuit arrangement is below a threshold level.

[0017] It should also be noted that the first current source can be configured in any suitable way. In one example, as discussed earlier, the first current source can be one that includes a first field-effect transistor. The switch driver circuit arrangement can further be configured to include a second field-effect transistor, which is effective in transmitting a control voltage (trimmed voltage) received from a trimmable voltage source to a control input of the first field-effect transistor in order to activate the first field-effect transistor. The magnitude of the control voltage received from the trimmable voltage source can be selected to limit the magnitude of the first current supplied by the first current source to the main switch.The selected current limit (as implemented by the voltage provided by the trimmable voltage source) can be based on the magnitude of the initial current required to drive a gate node of the main switch to activate the main switch to an ON state.

[0018] It should also be noted that, although the examples discussed here are applicable to switch driver applications and respective control of switch circuit arrangements, the concepts disclosed herein can advantageously be applied to any other suitable topologies as well as general power supply control applications.

[0019] In another example, the techniques described here include a method comprising the following steps: receiving, via a first input of the switch driver circuit arrangement, a first control signal indicating how to control a main switch; converting, via the switch driver circuit arrangement, the first control signal into a second control signal; and, via an output of the switch driver circuit arrangement, outputting the second control signal to the main switch, wherein the second control signal includes a first current supplied to the main switch from a first current source of the switch driver circuit arrangement, the magnitude of which varies based on the voltage magnitude of the second control signal.

[0020] The order of the preceding steps has been added for clarity. It should be noted that any of the processing operations discussed here can be carried out in any suitable order.

[0021] Other examples of the present disclosure include software programs and / or respective hardware for carrying out any of the exemplary process steps and operations summarized above and disclosed in detail below.

[0022] It is understood that the system, the procedure, the device, the instructions on computer-readable storage media, etc., as discussed here, can also be implemented strictly as a software program, as firmware, as a hybrid of software, hardware and / or firmware, or as hardware alone, such as within a processor (hardware or software), within an operating system, or within a software application.

[0023] As discussed here, the techniques presented are well-suited for use in the implementation of one or more power converters to supply electricity to a load. However, it should be noted that the examples given are not limited to such applications and that the techniques discussed here are also well-suited for other applications.

[0024] It should also be noted that, although each of the various features, techniques, configurations, etc., may be discussed at different points in this disclosure, it may be intended that each of the concepts can optionally be implemented independently or in combination with one another. Accordingly, the one or more inventions presented here can be implemented and viewed in many different ways.

[0025] It should also be noted that this preliminary discussion of examples does not intentionally list every example and / or every incrementally new aspect of the present disclosure or the claimed invention(s). Instead, this brief description presents only general examples and corresponding novelty elements compared to conventional techniques.

[0026] Preferred embodiments of the present invention are discussed in more detail below with reference to the accompanying drawings, wherein: Fig. 1 is an exemplary diagram of a circuit arrangement comprising a switch driver circuit arrangement as discussed herein. Fig. Figure 2 is an exemplary diagram illustrating a more detailed implementation of a circuit that includes a switch driver and switch, as discussed herein. Fig. 3 is an exemplary timing diagram illustrating states of signals associated with the switching on of a respective main switch, as discussed herein. Fig. 4 is an exemplary timing diagram illustrating states of signals associated with the switching off of a respective main switch, as discussed herein. Fig. 5 is an exemplary timing diagram illustrating states of signals associated with the operation of a main switch, as discussed herein. Fig. 6 is an exemplary timing diagram illustrating states of signals associated with the operation of a main switch, as discussed herein. Fig. 7 is an exemplary method associated with the operation of a switch driver circuit arrangement, as discussed herein.

[0027] The foregoing and other problems, features, and advantages of the invention will become apparent from the following more detailed description of preferred examples herein, as illustrated in the accompanying drawings, in which the same reference numerals in the different views refer to the same parts. The drawings are not necessarily to scale, the emphasis instead being placed on illustrating the examples, principles, concepts, etc.

[0028] As further discussed herein, a device (e.g., a circuit, hardware, etc.) may be configured to include: a first input effective in receiving a first control signal indicating how to control a main switch; a switch driver circuit arrangement effective in converting the first control signal into a second control signal; and an output effective in outputting the second control signal to the main switch, the second control signal comprising a first current supplied to the main switch by a first current source of the switch driver circuit arrangement, the magnitude of the first current varying based on the voltage magnitude of the second control signal.

[0029] In one example, the main switch is a gallium nitride field-effect transistor (e.g., a GaN FET). To maintain the activation of the main switch, as indicated by a received control signal, the switch driver circuitry must continuously drive the gate node of the main switch to keep it in an ON state. It is desirable to prevent so-called gate node overload, e.g., by excessively driving current to the gate node, as this wastes power, especially when the main switch is repeatedly turned on and off at a high rate. For example, there can be a high power cost to turn on any given switch. The switch driver circuitry discussed here provides a more efficient use of power to activate the respective main switch according to the received control signal and keep it in an ON state.

[0030] In particular, as further discussed herein, the switch driver circuit arrangement provides (via the second control signal) the initial current to the gate node of the main switch during a state in which the received control signal indicates that the main switch should be turned on. This initial current can be configured to be sufficiently high at the beginning of the on-time signal and to decrease as the magnitude of the control signal applied to the gate node of the main switch increases. As further discussed herein, the switch driver circuit arrangement can be configured to include a second current source that simultaneously provides a second current to the gate node of the main switch for a duration in which the first control signal indicates that the main switch should be turned on.Thus, initially, both the first and second current sources can be configured to supply current to the gate node of the main switch to activate it to the ON state. Following the initial activation, and after the first segment of each ON time as specified by the control signal, the first current source can be deactivated (the initial current is reduced to essentially zero), and the second current source continues to supply an appropriate current to the gate node of the main switch to keep it in the ON state. In such a case, as discussed herein, the first current source provides a temporary boost to activate the main switch to the ON state but is switched off when no longer needed, since the second current source provides the appropriate current to keep the switch in the ON state.

[0031] Examples herein include optimizing the switching loss to turn on a given main switch (130) by minimizing gate overload of the corresponding main switch gate. Techniques such as those discussed herein may involve implementing one or more trimming operations that essentially balance the dynamic turn-on behavior of different RDSON classes, independent of GaN and C11HV process variations. The turn-on path described herein may be implemented by an NMOS drive switch (e.g., an N-type field-effect transistor 131-1) that exhibits trimmable self-turn-off behavior promptly after initial activation. Conventional solutions, such as those using an RC network, may overload the GaN gate, while others may rely solely on the response time of a driver circuit that senses the GaN power switch Vgs to minimize gate overload.

[0032] Activation of the main switch (130) can be achieved by an NMOS switch (131-1) which switches itself off when the gate voltage Vgate of the GaN switch increases. This self-switch-off threshold can be programmed in production to compensate for GAN and C11HV process variations and can also balance the dynamic behavior for different RDSON classes.

[0033] Thus, the present disclosure can include a switch driver that reduces turn-on switching losses by minimizing gate overload of a respective main switch (130). The turn-on speed (and activation of the main switch) is programmable by an external RDD resistor, and the amount of charge injected into the gate node of the main switch (130) is programmable by trim voltages such as the VDD_HSDRV voltage. This VDD_HSDRV voltage can be trimmed to calibrate the HSNMOS self-turn-off behavior and control the amount of charge injected into the GaN GIT gate, compensating for C11HV and GaN process variations. These calibrations can be achieved for all RDSON classes from 500 mΩ to 55 mΩ.This calibration (trim) can be performed by trimming VDD_HSDRV (117) such that a selected predefined minimum current flows into the gate node of the main switch (130).

[0034] More precisely, Fig. 1. Now an exemplary diagram of a circuit as described herein.

[0035] In this general example, the circuit 100 comprises a switch driver circuit arrangement 110, a trimmable voltage source 120, a monitor 140, and a main switch 130. The switch driver circuit arrangement 110 can be configured to include a power source 131, a current source 132, a switch 135, and a switch 137.

[0036] In general, as discussed further herein, the switch driver circuit arrangement 110 receives the corresponding control signal 105 at input 111. The switch driver circuit arrangement 110 receives the input voltage 121 (also called V9) from the trimmable voltage source 120 at input 117. During operation, the switch driver circuit arrangement 110 converts the received control signal 105 into the control signal 106, which is used to drive the gate node G of the main switch 130.

[0037] The control signal 106 (also called Vgate) controls the main switch 130 between an ON state and an OFF state depending on the magnitude of the voltage associated with the control signal 106, or the magnitude of the corresponding current 107 supplied to the gate node G of the main switch 130.

[0038] In one example, the main switch 130 is a gallium arsenide (GaN) field-effect transistor comprising a gate node G, a drain node D, and a source node S. The main switch 130 may require a minimum amount of current supplied to its gate node G to keep the main switch 130 in an ON state (e.g., where the ON state is a low-impedance path, or Rdson, between the drain node D and the source node S of the main switch 130).

[0039] If sufficient current is supplied to the gate node G of the main switch 130, the voltage at the gate node of the main switch 130 can increase to any suitable voltage, e.g., about 3 volts or another value.

[0040] When no current (e.g., current iGATE = zero) is applied to the gate node of main switch 130 and the voltage associated with control signal 106 is essentially zero, main switch 130 is deactivated (off state). In the off state, there is a high-impedance path between the drain node and the source node of main switch 130.

[0041] Accordingly, the switch driver circuit arrangement 110 discussed herein can be configured to include the following: a first input 111, which is effective in receiving a first control signal 105 (V1) that specifies how the main switch 130 is to be controlled. The switch driver circuit arrangement 110 is configured to convert the first control signal 105 into the control signal 106. The output 119 of the switch driver circuit arrangement 110 outputs the second control signal 106 to the gate node G of the main switch 130. The control signal 106 can be configured to include a first current iC1, which is supplied to the main switch 130 by a first current source 131 of the switch driver circuit arrangement 110. As further discussed herein, the magnitude of the first current iC1 can be configured to vary based on a voltage magnitude of the second control signal 106.

[0042] As further discussed herein, the first current source 131 can be a field-effect transistor or include one that has a source node effective in supplying the first current iC1 to the gate node of the main switch 130. The supply of the first current iC1 from the source node of the current source 131 (e.g., a field-effect transistor) to the gate node of the main switch 130 can be configured to reduce the magnitude of the first current iC1 over time. For example, the magnitude of the first current iC1 can be configured to decrease over time. In one example, the current source 131 (e.g., a field-effect transistor) is a high-side NMOS (HSNMOS) device operating in a saturation mode. The reduction in current iC1 is due to HSNMOS drain-source saturation (IDSAT) reduction.In one example, IDSAT is the measured drain current, with the device 131 biased in the saturation region. As in . Fig. As further shown in Figure 2, the RDS-in resistance between the drain node of the first current source 131 (e.g., field-effect transistor 131-1) and the source node of the current source 131 (e.g., field-effect transistor 131-1) increases in response to a decrease in the gate-source voltage between the gate node and the source node of the field-effect transistor. The decrease in the drain-source voltage (DS) associated with the current source 131 (e.g., field-effect transistor 131-1) can occur in response to an increase in the voltage magnitude of the second control signal 106 over time.

[0043] With renewed reference to Fig. As shown, the circuit 100 discussed herein can be configured to include a second current source 132, which is effective in generating a second current iC2 (holding current for activating the switch 130, which may be trimmable). The second current source 132 can be connected in parallel to the first current source 131.

[0044] The second control signal 106 can be configured to include a combination of the first current iC1 provided by the power source 131 and the second current iC2 provided by the power source 132.

[0045] As previously discussed, the second control signal 106 (e.g., generated via current source 131 and current source 132) can be applied to a gate node G of the main switch 130 to control the ON-OFF states of the main switch 130. The first control signal 105 can indicate that the main switch 130 should be enabled for a duration X, where X is any suitable value. In such a case, the first current source 131 can be configured to: i) supply the first current iC1 to the gate node G of the main switch 130 for a first segment of the duration X, and ii) interrupt the supply of the first current iC1 to the gate node G of the main switch 130 for a second segment of the duration X.

[0046] Additionally, the second current source 132 can be configured to provide the second current iC2 at the gate node of the main switch 130 for both the first and second segments of the duration X. An output of the second control signal 106 for duration X at the gate node G of the main switch 130 can be configured to keep the main switch 130 in an ON state for duration X. A magnitude of the first current iC1 at one end of the first segment of duration X can be configured to keep the main switch 130 in an ON state or to help keep it in an ON state.

[0047] As further shown, the switch driver circuit arrangement 110 can be configured to include the monitoring circuit 140. The monitoring circuit 140 can be configured to monitor a size control signal 106. Following the first segment of the time duration X, the monitoring circuit 140 can be configured to generate the control signal V5 to deactivate the power source 131.

[0048] Fig. 2 is an example diagram illustrating a more detailed implementation of a service provision as described herein.

[0049] In this example, the circuit arrangement 100-1 (e.g., an instantiation of the circuit arrangement 100) includes a switch driver circuit arrangement 110-1 (e.g., an instantiation of the switch driver circuit arrangement 110), a controller 240, and the main switch 130.

[0050] The circuit arrangement 100-1 further comprises the power supply 220, which is capable of generating the voltage Vdd that supplies power to any of the components as discussed herein, e.g., comprising the switch driver circuit arrangement 110-1; the power supply 221, which is capable of generating the voltage VSS_HSDRV (in one example, VSS_HSDRV is a floating ground (VSS) domain for the high-side driver circuit arrangement) used by the switch driver circuit arrangement 110-1; and the power supply 222, which is capable of generating the voltage VDD_LSDRV used to power a circuit arrangement such as the switch driver circuit arrangement 110-1. B. to supply power to a level converter 230, a driver circuit arrangement 235, a driver circuit arrangement 250, etc., which is associated with the switch driver circuit arrangement 110-1.

[0051] As shown, the switch driver circuit arrangement 110-1 includes the level shifter 215, the level shifter 230, the level shifter 260, the comparator 225, the level shifter 260, the level shifter 265, the driver 270, the switch 135, the current source 131 (e.g., comprising capacitor C1, resistor R1 in series with switch 131-1), the current source 132 (providing current iC2), the driver 235, the driver 245, the driver 250, the switch Q2, the switch Q3, the charge pump 255, the switch Q4, the switch 131-1, and the resistor R1.

[0052] During operation, the controller 240 generates the control signal 105 (V1) to control the operation of the main switch 130.

[0053] The controller 240 (e.g. a specific implementation of the controller 140) provides the control signal 105 to both the level converter 215 and the power source 132.

[0054] Setting the control signal 105 to a logic high level indicates that the main switch 130 should be activated in an ON state. For this purpose, the logic high level associated with the control signal 105 causes the current source 132 to supply the corresponding current iC2 to the gate node G of the main switch 130. The logic low level of the control signal 105 causes the current source 132 to discontinue supplying the current iC2 to the gate node G of the main switch 130.

[0055] As further discussed herein, the transition of the control signal 105 from the logic low state to the logic high state also causes a temporary activation of the current source 131 and the corresponding switch 131-1 (e.g., a field-effect transistor) in a manner further discussed herein. The temporary activation of the current source 131, as opposed to a continuous activation of the current source 131 while the control signal 105 is set to a logic high level, contributes to improved efficiency in operating the main switch 130. In other words, the novel process discussed herein reduces the amount of power required to turn the main switch 130 into an ON state.After switch 130 has been appropriately activated to the ON state, the power source that provides the current iC1 is deactivated (switch 131-1 is set to an OFF state, which prevents the flow of the current Ic1).

[0056] As further shown, the level converter 215 converts the received control signal 105 (the voltage V1) into the voltage V2, which is supplied to the level converter 265 (e.g., the driver logic in the high-side area). Based on the voltage V2, the level converter 265 drives the driver 270 to control the operation of the switch 135. The output (V4) of the switch 135 controls the operation of the switch 131-1 and the corresponding current source 131.

[0057] Additionally, the level converter 230 converts the received voltage V2 into the voltage V3, which is supplied to the driver 235 (e.g., the driver logic in the low-side area). Based on the voltage V3, the driver 235 controls the operation of the driver 245 via the signal S1, and the driver 250 controls the signal S2.

[0058] For example, driver 245 generates the control signal V7 based on the signal S1 received from driver 235. This control signal is then supplied to the gate node of switch Q2. Based on the signal S2 received from driver 235, driver 250 generates the control signal V6, which is supplied to the switch assembly Q3. The switch assembly Q3 (one or more transistors, as controlled by driver 250) pulls down the gate node G of switch 130 to the reference potential 199 (reference voltage). Pulling down the gate node G2 (which activates the switch assembly Q3 to an ON state) switches off the reference voltage 199 and then off switch 130.

[0059] Generally, the current source 131 is temporarily activated to switch 130 into an ON state or to activate the transition time of the control signal 105 from a low state to a high state. Switch 135 (on) and switch Q2 (off) allow temporary activation of the current source 131 and the corresponding field-effect transistor 131-1 when the control signal 105 is a logic high level.

[0060] The switching circuit arrangement Q3 can be activated in response to conditions in which the control signal 105 is set to a logic low level. Activation of the switching circuit arrangement Q3 pulls the control signal 106 to a logic low level (e.g., the reference potential 199) and deactivates the switch 130.

[0061] It is further noted that the combination of charge pump 255 and switch Q4 ensures that switch 130 is set to an OFF state when the various power supplies (e.g., Vdd, etc.) are started up, as shown in Fig. 2 is shown. For example, switch Q4 is activated during the start-up conditions, in which the power supply voltages are in Fig. 2 are driven up to the appropriate level and set to an ON state. After the power supplies have reached the appropriate voltage levels, the charge pump 255 provides a control input to the gate node of switch Q4 to deactivate switch Q4 to an OFF state.

[0062] In further examples discussed herein, the first current source 131 can be, or include, a field-effect transistor (switch 131-1) that is effective in controlling / providing the first current iC1 from a source node S of the field-effect transistor 131-1 to a gate node G of the main switch 130. The first current iC1 (when the control signal 105 is set to a logic high level) provided by the field-effect transistor to the gate node G of the main switch 130 increases the voltage magnitude (also called Vgate) of the second control signal 106, which is provided to the gate node G of the main switch 130.

[0063] It is noted that the field-effect transistor 131-1 can be an N-type field-effect transistor. The switch 135 can be a P-type field-effect transistor or another suitable entity.

[0064] Increasing the magnitude of the second control signal 106 (or signal Vgate) applied to the gate node G of the main switch 130 serves to reduce a gate-source voltage between a gate node and the source node of the field-effect transistor (see further timing diagrams). In other words, as discussed herein, switch 131-1 can initially be activated with a voltage V4 (e.g., a substantially fixed voltage) while the magnitude of the control signal 106 is a low voltage. As the current source 131 supplies current iC1 to switch 130, the voltage Vgate (control signal 106) increases, causing a decrease in the magnitude of the gate-source voltage of switch 131-1.The decrease in the gate-source voltage (V4 - Vgate, as shown in timing diagram 310) of switch 131-1 increases a resistance between a drain node D of switch 131-1 and the source node S of switch 131-1, thereby reducing the magnitude of the initial current iC1 supplied by the source S of the field-effect transistor 131-1 (and the corresponding current source 131) to the gate node of the main switch 130. Thus, initially, the current iC1 supplied by the current source 131 is high, as limited by resistance R1, but the magnitude of the current iC1 decreases over time.

[0065] An example of a decrease in the magnitude of the current iCl supplied by the current source 131 is shown in Fig. Figure 6 shows this. For example, shortly before time T10, switch 131-1 is activated to an ON state, resulting in the transmission of current iC1 (starting at a magnitude of Vdd / R1) through switch 131-1 to the gate node G of the main switch 130. Between time T10 and time T15, as the magnitude of the gate voltage Vgate increases, the magnitude of the current iC1 supplied by switch 131-1 to the gate node of the main switch decreases (self-turn-off). Finally, at or around time T15, as discussed further herein, switch 131-1 is deactivated to an OFF state, and the current iC1 is essentially zero.

[0066] With renewed reference to Fig. 2. As previously discussed, the main switch 130 can be implemented and / or manufactured in any suitable way. For example, the main switch 130 can be made of gallium nitride (GaN).

[0067] In another example, to activate switch 132 to an ON state, a certain amount of continuous current is supplied to the gate node G. In one example, iGATE = 1C1 + iC2.

[0068] Further examples discussed herein include an implementation of circuit arrangement 100 or circuit arrangement 100-1 (e.g., a device, hardware, apparatus, etc.) to include: a second input 112 to receive feedback (e.g., a voltage Vgate) that tracks (or indicates) the voltage magnitude of the second control signal 106. In other words, the monitor 140-1 can be configured to receive and monitor the magnitude of the control signal 106 itself, or to monitor a derivative of the control signal 106 that drives the gate node G of the main switch 130. As further discussed below, the purpose of monitoring the control signal 106 is to determine when to fully turn off the switch 131-1.

[0069] In particular, as further shown, the circuit 100 can be configured to include a comparator 225, which is effective in comparing the received feedback (the control signal 106) with a threshold level. A corresponding signal generator is configured to terminate the activation of the first current source 131, which supplies the first current iC1 to the main switch 130, in response to the detection that the feedback (the control signal 106 or Vgate) exceeds (e.g., falls below) a respective threshold level TL1.

[0070] According to further examples discussed herein, the circuit 100-1 can be configured to include a switch Q4 connected between a gate node G of the main switch 130 and a source node S of the main switch 130. As discussed previously, the switch Q4 is configured to short-circuit the gate node G of the main switch 130 to the source node S of the main switch 137 (providing a low-impedance path) during the startup of the switch driver circuit arrangement 100, in order to prevent the main switch 130 from being activated during power supply startup.

[0071] It should be noted that the first current source 131 can be configured in any suitable way. In one example, the first current source 131 is a first field-effect transistor 131-1 or includes one. The switch driver circuit arrangement 110-1 can further be configured to include a second field-effect transistor, which is effective in transmitting a control voltage V4 (trimmed input voltage 117), received from a trimmable voltage source 120, to a control input (e.g., a gate node G) of the first field-effect transistor 131-1 in order to activate the first field-effect transistor 131-1. A magnitude of the control voltage V4, as derived from the input voltage 117 and the corresponding trimmable voltage source 120, can be selected (via a previous trimming process) to limit the magnitude of the first current iC1 supplied by the current source 131 to the main switch 130.

[0072] Additional details are discussed below. It should be noted that the selected current limit (as implemented by the magnitude of the voltage V4 provided by the trimmable voltage source) may be based on the magnitude of the initial current iC1 required to drive a gate node G of the main switch 130 to activate the main switch 130 to an ON state. SPECIAL FEATURES OF CIRCUIT 100-1: - The activation of DV / DT of switch 130 can be programmable via an external RDD resistor. - Minimizing gate overdrive of the main switch 130; field-effect transistor 131-1 can be of N type - All RDSon classes provide similar switching performance; VDD_HSDRV is trimmable. - The HSNMOS switch (131-1) implements a self-turn-off behavior during turn-on when a magnitude of the voltage Vgate increases while the voltage V4 is static. Holding current, such as iC2, can be defined as the minimum current required to provide short-circuit protection for a given Ids current value. For example, holding current iC2 is defined as the minimum constant current required to keep the GaN switch (such as switch 130) in the ON state, which is the Idsat value needed. - All driver sub-circuits associated with the switch driver circuit arrangement 110-1 can be referenced to the VSSP! range, such as reference potential 199, GaN Kelvin source connection; the GaN shutdown power loop is parasitically efficient - The pulse width modulation (the control signal 105) can be received from the VSS! range and can be shifted up to the VDD_HSDRV range and then shifted down to the VDD_LSDRV range; - GaN Vgs (or Vgate) can be monitored to turn off HSNMOS once the target GaN gate voltage is reached. - 24-volt depletion to keep GaN switched off before power-up. The negative charge pump 255 maintains the depletion after power-up.

[0073] Fig. 3 is an exemplary timing diagram illustrating states of signals associated with the switching on of a respective main switch, as discussed herein.

[0074] In this example, the controller 240 generates the transition of the control signal 105 (e.g., V1) from a logic low to a logic high time T1, as shown in the timing diagram 305. This corresponds to a state in which the controller 240 generates a respective control signal 105 to activate the switch 130.

[0075] The transition of the control signal 105 from a logic low to the logic high state at or around time T1 causes the current source 132 to provide the corresponding current iC2 to the gate node of the switch 130, starting around time T8 (see Fig. 5) In other words, as discussed previously, the activation of the power source 132 is based on the control signal 105.

[0076] With renewed reference to Fig. 3 The transition of the control signal 105 to the logically high state causes the level converter 250 to generate the corresponding signal V2 (the timing diagram 306) to a logically high state at or around time T3.

[0077] Thus, signal V2 transitions from low to high of signal V1 at or around time T1, from the low to the high state at time T3. The combination of level shifter 265 and driver 270 receives signal V2 and, in response to the fact that signal V2 is a logic high, the combination of driver circuit 265 and driver 270 activates switch 135 via the output of driver 270 to the gate node G of switch 135. In this case, the activation of switch 135 transmits voltage 117 from the adjustable voltage source 120 (as voltage V4) to the gate node of switch 131-1.

[0078] While switch 135 is in the ON state, the voltage V4 output from the drain node of switch 135 to the gate node of switch 131-1 is essentially equal to the voltage 117 provided by the trimmable voltage source 120. As discussed previously, the control signal 107 controls the magnitude of the voltage 117 output by the trimmable voltage source 120.

[0079] In one example, the magnitude of the gate voltage Vgate applied to the gate node of the main switch 130 can initially be zero before the transition of the control signal 105 from the logic low state to the logic high state. This is because, before time T1, the switch Q3 is activated to an ON state to control the magnitude of the voltage Vgate to the reference potential 199.

[0080] As previously discussed, switch 131-1 and the corresponding current source 131 are activated at approximately time T9. Additionally, the voltage across the gate node G of switch 131-1 is V4. In this case, switch 131-1 is activated to the ON state at or approximately time T9, causing the current iC1 to flow from the voltage source 220 through resistor R1 and switch 131-1 to the gate node G of the main switch 130. Thus, the current source 131 is activated at approximately time T9 to supply the corresponding current iC1 to the gate node G of switch 130, thereby activating switch 130 to an ON state.

[0081] As further shown in timing diagram 306, the transition of voltage V2 to the logic high state at time T3 causes the level shifter 230 to generate voltage V3 (see timing diagram 307), which is supplied to driver 235. In this case, driver 235 and driver 245 generate voltage V7, which is applied to switch Q2. As shown in timing diagram 304, voltage V7 transitions from a logic high to a logic low at time T7 in response to control signal 105 activating switch 130. Voltage V7 also transitions from a logic low to a logic high at approximately time T15. Additionally, voltage V6 transitions from a logic high to a logic low at time T7, as shown in timing diagram 309.

[0082] This deactivation of switch Q2 at or approximately time T7 allows switch 135 to provide the voltage 117 to the gate node of switch 131-1, since the gate node of switch 131-1 is no longer short-circuited to the reference potential 199 via the activated switch Q3 at time T7.

[0083] As further shown in timing diagram 310, the gate-source voltage (V4 - Vgate) associated with switch 131-1 increases at or approximately time T9 based on the activation of switch 131-1 (current source 131, activated by voltage 117 applied to the gate node of switch 131-1 by switch 135) and current source 132. In other words, as previously discussed, the supply of current iC1 and current iC2 between time T7 and time T15 increases the magnitude of the voltage at the gate node G of switch 131-1, which leads to an increase in the magnitude of the RDS-in resistance between the drain node D and the source node S of switch 131-1 (as the gate-source voltage associated with switch 131-1 decreases).

[0084] While both current source 131 and current source 132 are activated to provide current to the gate node of the main switch 130 (e.g., approximately between time T5 and time T15), comparator 225 receives a corresponding feedback signal (e.g., the voltage Vgate applied to the gate node of switch 130) at input 112 of comparator 225. As shown in timing diagram 305, comparator 225 detects that the voltage Vgate exceeds a respective threshold level at or approximately time T12, causing the voltage signal V5 (timing diagram 308) to transition from a logic high to a logic low.Such a transition of voltage V5, from the logic high state to the logic low state, deactivates switch 135 and activates switch Q2 (voltage V7 transitions from a logic low to a logic high state at approximately time T15 to turn on switch Q2). Accordingly, power source 131 and the corresponding switch 131-1 are deactivated at approximately time T15.

[0085] It should be noted that after time T15, as shown in timing diagram 305, although power source 131 and the corresponding current iC1 are switched off, the control signal V1 indicates that switch 130 should remain in the ON state. Although power source 131 and the corresponding switch 131-1 are deactivated at time T15 and the supply current iC1 drops to essentially zero, power source 132 is still activated to supply current iC2 to the gate node of main switch 130. The activation of power source 131 and the supply of the corresponding current iC1 to the gate node between time T9 and time T15 (as a supplement to current iC1) provide a boost to initially turn on main switch 130.

[0086] In one example, it should be noted that the calibration of the trimmable voltage source 120 involves deactivating the current source 132 and the corresponding comparator 225, so that the comparator 225 is unable to deactivate the corresponding signals that control switch 135 and switch 131-1. The control signal 105 is set to the high state, which activates switch 130. Additionally, the power source 299 is activated to apply power, such as a voltage or current, to node RDD. Various settings of power source 120 are tested (such as activating switch 135 using different possible settings of the voltage 117) applied to the source node of switch 135.One of the various possible settings is chosen such that the selected voltage 117 leads to an activation of switch 131-1 to a suitable extent, so that switch 130 is in an ON state.

[0087] As previously discussed, in its active state, switch 135 applies a voltage 117 to the gate node of switch 131-1. Therefore, calibration can involve activating switch 135 to apply the voltage 117 to the gate node of switch 131-1, while power source 299 applies a corresponding current through switch 131-1 to the gate node of main switch 130. The current iDS through switch 130 is measured during calibration tests. The voltage 117 is adjusted (e.g., via control signal 107) so that switch 131-1 delivers a desired current iC1 (e.g., 3 milliamperes or another suitable value) from power source 299 through switch 131-1 to the gate node of switch 130.The appropriate setting of a control signal 107, which provides the desired magnitude of the current iC1, is stored in a buffer of the circuit 100-1 and is then used in normal operation, as shown in the timing diagrams ( . Fig. 3 to Fig. 6) is shown.

[0088] Fig. 4 is an exemplary timing diagram illustrating states of signals associated with the switching off of a respective main switch, as discussed herein.

[0089] At time T21 (e.g., following time T15, as previously discussed), as shown in timing diagram 404, the controller 240 changes the magnitude of the control signal 105 (V1) from a logic high state to a logic low state. This transition of the control signal 105 indicates that the main switch 130 should be switched off.

[0090] In response to the transition of control signal 105 at or approximately time T21, the level shifter 215 causes signal V2 to transition from a logic high to a logic low at or approximately time T23. As further shown in timing diagram 404, the transition of voltage V2 from the logic high to the logic low causes level shifter 230 to cause voltage V3 to transition from a logic high to a logic low. This (falling edge of V3 in timing diagram 407) in turn causes driver 235 and the corresponding driver 250 to change voltage V6 (timing diagram 409) from a logic low to a logic high at time T27, as shown in timing diagram 409, which leads to the activation of switch Q3 at or approximately time T27.The activation of switch Q3 at or approximately time T27 causes the gate voltage Vgate of switch 130 to be pulled down to the reference potential 199. This deactivates the respective main switch 130 at or approximately time T31, as shown in timing diagrams 401 and 402. Accordingly, at or approximately time T31, as shown in timing diagram 401, the current iDS through main switch 130 decreases to essentially 0 amperes or another suitable value. Additionally, at or approximately time T31, because main switch 130 is deactivated to the OFF state, as shown in timing diagram 402, the voltage Vds increases.

[0091] Fig. 5 is an exemplary timing diagram illustrating states of signals associated with the operation of a main switch, as discussed herein.

[0092] As previously discussed, and further shown in timing diagram 505, the transition of control signal 105 from a logic low state to a logic high state causes current source 132 to supply current iC2 from current source 132 to the gate node G of switch 130 at or approximately time T8. As previously discussed, at or approximately time T9, the activation of switch 131-1 causes a respective flow of current iC1 through current source 131 and the corresponding switch 131-1 to the gate node G of switch 130. Accordingly, the total current iGATE supplied by a combination of current sources 131 and 132 peaks immediately after time T9.

[0093] Furthermore, as previously discussed, switch 130 transitions from the OFF state to the ON state at or approximately time T10. Immediately before time T15, the total magnitude of the current iGATE provided by the combination of both activated current sources 131 is approximately 6.5 milliamperes, or some other suitable value. Immediately after time T15, as shown in timing diagram 505, when current source 131 is deactivated at or approximately time T15, current source 132 provides a current iC2 of approximately 3 milliamperes to the gate node of the main switch 130.

[0094] Fig. 6 is an exemplary timing diagram illustrating states of signals associated with the operation of a main switch, as discussed herein.

[0095] As shown in the timing diagram 605, after the power source 131 is deactivated at or about time T15, a quantity of the current iC2 (e.g. holding current) settles at about time T19 to approximately 1.7 milliamperes or another suitable value.

[0096] Fig. 7 is an exemplary method associated with the operation of a switch driver circuit arrangement, as discussed herein.

[0097] In the processing operation 710 of the flowchart 700, the switch driver circuit arrangement 110 receives a first control signal 105 via a first input 111, which specifies how a main switch 130 is to be controlled.

[0098] In processing operation 720, the switch driver circuit arrangement 110-1 converts the control signal 105 (V1) into the control signal 106 (Vgate).

[0099] In processing operation 730, the switch driver circuit arrangement 110 outputs the second control signal 106 and the corresponding current iGATE to the gate G of the main switch 130 via an output 119. As previously discussed, the second control signal 106 can be configured to include a temporary first current iC1, which is supplied to the gate node of the switch 130 by a current source 131 of the switch driver circuit arrangement 110. Furthermore, as previously discussed, the magnitude of the first current iC1 varies based on the voltage magnitude of the second control signal 106. In other words, the initial activation of the current source 131 and the corresponding switch 131-1 causes the current iC1 to flow to the gate node G of the main switch 130.The flow of current iC1 causes the voltage magnitude of the control signal 106 and the voltage at the source node S of switch 131-1 to increase, thereby reducing the gate-source voltage associated with switch 131-1. This reduction in the gate-source voltage associated with switch 131-1 advantageously reduces the magnitude of the current iCl supplied by current source 131 to the gate node of switch 130 during the short time window (time T9 to time T15) in which current source 131 is activated. Finally, the magnitude of the control signal 106 increases above a threshold level, as detected by the comparator 225, causing the power source 131 and the corresponding switch 131-1 to be switched off, while the power source 132 remains in an ON state during the remaining portion of the time period in which the control signal 105 is at a logic high level.Thus, current source 131 provides a temporary boost to the current supplied to the gate node of switch 132 to activate it. Current source 132 provides a sufficient current iC2 to keep switch 130 in the ON state for the duration that the control signal 105 is a logic high level. For example, when switch 131-1 is initially activated at or approximately time T9, the current iC1 is limited by the voltage VDD and the resistance R1. Shortly before time T15, while switch 131-1 is still activated, the current iCl supplied by current source 131 depends on the magnitude of the selected trimmed voltage 117.

[0100] It should be noted again that the techniques presented here are well suited for use in circuit applications, such as those implementing a gate driver circuit arrangement. However, it should be noted that the examples presented here are not limited to use in such applications and that the techniques discussed are also well suited to other applications.

[0101] Based on the description presented here, numerous specific details have been provided to offer a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without these specific details. In other cases, methods, devices, systems, etc., that would be known to a person skilled in the art have not been described in detail in order to avoid obscuring the claimed subject matter. Some sections of the detailed description have been presented in the form of algorithms or symbolic representations of operations on data bits or binary digital signals stored in a computing system memory, such as computer memory.These algorithmic descriptions or representations are examples of techniques used by average professionals in the field of data processing to communicate the content of their work to other professionals. In this context, operations or processing involve the physical manipulation of physical quantities. Typically, though not necessarily, such quantities may take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, or otherwise manipulated. It has sometimes been convenient, mainly for the sake of general usage, to refer to such signals as bits, data, values, elements, symbols, characters, concepts, numbers, figures, or the like. It is understood, however, that all these and similar terms are to be assigned to appropriate physical quantities and are merely convenient designations.Unless expressly stated otherwise, it is understood that, as will be evident from the following discussion, throughout this description discussions which use terms such as "processing", "calculating", "determining" or the like refer to actions or processes of a computing platform, such as a computer or similar electronic computing device, which manipulates or transforms data represented as physical, electronic or magnetic quantities in memory, register or other information storage devices, transmission devices or display devices of the computing platform.

[0102] Although this invention has been shown and described with particular reference to preferred examples thereof, those skilled in the art will understand that various modifications in form and details can be made to it without departing from the spirit and scope of the present application as defined by the appended claims. Such variations are intended to be covered by the scope of this present application. Thus, the foregoing description of examples of the present application is not intended to be limiting. Rather, any limitations of the invention are set forth in the following claims.

Claims

[1] Device having the following features: a first input (111) which is effective in receiving a first control signal (105) which specifies how a main switch (130) is to be controlled; a switch driver circuit arrangement (110) that is effective in converting the first control signal (105) into a second control signal (106); and an output (119) that is effective in outputting the second control signal (106) to the main switch (130), wherein the second control signal (106) comprises a first current (iC1) supplied to the main switch (130) by a first current source (131) of the switch driver circuit arrangement (110), wherein the magnitude of the first current (iC1) varies based on the voltage magnitude of the second control signal (106). [2] Device according to claim 1, wherein the first current source (131) is a field-effect transistor comprising a source node (S) that is effective in outputting the first current (iC1) to a gate node (G) of the main switch (130). [3] Device according to claim 2, wherein the provision of the first current (iC1) from the source node (S) of the field-effect transistor to the gate node (G) of the main switch (130) is effective in reducing the magnitude of the first current (iC1) over time; and wherein the magnitude of the first current (iC1) is effective in decreasing over time, the first current (iC1) being a saturation current. [4] Device according to claim 3, wherein the saturation current decreases over time in response to a decrease in a gate-source voltage between a gate node (G) of the field-effect transistor and the source node (S) of the field-effect transistor, wherein the decrease occurs in response to an increase in the voltage magnitude of the second control signal (106) over time. [5] Device according to any one of claims 1 to 4, which further comprises the following features: a second current source (132) which is effective in generating a second current (iC2), wherein the second current source (132) is connected in parallel to the first current source (131), wherein the second control signal (106) is derived on the basis of a combination of the first current (iC1) and the second current (iC2); and wherein the second control signal (106) is applied to a gate node (G) of the main switch (130) to control the main switch (130). [6] Device according to claim 5, wherein the first control signal (105) indicates to activate the main switch (130) for a duration (X); and wherein the first current source (131) is effective in: i) providing the first current (iC1) to the gate node (G) of the main switch (130) for a first section of the duration (X) and ii) interrupting the provision of the first current (iC1) to the gate node (G) of the main switch (130) for a second section of the duration (X), the second section following the first section. [7] Device according to claim 6, wherein the second current source (132) is effective in providing the second current (iC2) at the gate node (G) of the main switch (130) for both the first part of the time period (X) and the second part of the time period (X); and wherein an output of the second control signal (106) for the time period (X) at the gate node (G) is effective in keeping the main switch (130) in an ON state for the time period (X). [8] Device according to claim 7, wherein a quantity of the first current (iC1) at one end of the first section of the time period (X) is effective in keeping the main switch (130) in an ON state. [9] Device according to any one of claims 1 to 8, wherein the first current source (131) is a field-effect transistor which is effective in providing the first current (iC1) from a source node (S) of the field-effect transistor to a gate node (G) of the main switch (130); and wherein the first current (iC1) provided by the field-effect transistor to the gate node (G) of the main switch (130) increases the voltage magnitude of the second control signal (106) provided to the gate node (G) of the main switch (130). [10] Device according to claim 9, wherein the field-effect transistor is an N-type field-effect transistor. [11] Device according to claim 9 or 10, wherein the increase in the voltage magnitude of the second control signal (106) applied to the gate node (G) of the main switch (130) has the effect of reducing a gate-source voltage between a gate node (G) of the field-effect transistor and the source node (S) of the field-effect transistor, wherein the reduced gate-source voltage has the effect of reducing the magnitude of the first current (iC1) supplied by the source node (S) of the field-effect transistor to the main switch (130). [12] Device according to any one of claims 1 to 11, wherein the main switch (130) is made of gallium nitride (GaN). [13] Device according to any one of claims 1 to 12, which further comprises the following features: a second input (112) which is effective in receiving feedback that tracks the voltage magnitude of the second control signal (106); a comparator (225) which is effective in comparing the received feedback with a threshold level; and a signal generator that is effective in terminating the activation of the first current source (131) which provides the first current (iC1) to the main switch (130) in response to the detection that the feedback is above the threshold level. [14] Device according to any one of claims 1 to 13, which further comprises the following features: a first switch which is connected between a gate node (G) of the main switch (130) and a source node (S) of the main switch (130), wherein the first switch is effective in short-circuiting the gate node (G) of the main switch (130) with the source node (S) of the main switch (130) during the start-up of the switch driver circuit arrangement (110) in order to prevent activation of the main switch (130). [15] Device according to any one of claims 1 to 14, wherein the first current source (131) is a first field-effect transistor; and wherein the switch driver circuit arrangement (110) further comprises a second field-effect transistor which is effective in transmitting a control voltage (V4) received from a voltage source to a gate input of the first field-effect transistor in order to activate the first field-effect transistor. [16] Device according to claim 15, wherein a magnitude of the control voltage (V4) received from the voltage source is selected to limit the magnitude of the first current (iC1) supplied by the first current source (131) to the main switch (130). [17] Device according to claim 16, wherein the limitation is based on the size of the first current (iC1) required to drive a gate node (G) of the main switch (130) to activate the main switch (130) to an ON state. [18] Method comprising the following steps: via a first input (111) of a switch driver circuit arrangement (110), receiving a first control signal (105) that specifies how a main switch (130) is to be controlled; via the switch driver circuit arrangement (110), converting the first control signal (105) into a second control signal (106); and via an output (119) of the switch driver circuit arrangement (110), output of the second control signal (106) to the main switch (130), wherein the second control signal (106) comprises a first current (iC1) supplied to the main switch (130) by a first current source (131) of the switch driver circuit arrangement (110), wherein a magnitude of the first current (iC1) varies based on a voltage magnitude of the second control signal (106). [19] Method according to claim 18, wherein the first current source (131) is a field-effect transistor comprising a source node (S) that is effective in outputting the first current (iC1) to a gate node (G) of the main switch (130); and wherein the output of the second control signal (106) to the main switch (130) comprises providing the first current (iC1) from the source node (S) of the field-effect transistor to the gate node (G) of the main switch (130), wherein the provision of the first current (iC1) reduces the magnitude of the first current (iC1) over time. [20] Method according to claim 18 or 19, wherein the first current source (131) is a first field-effect transistor; and via a second field-effect transistor of the switch driver circuit arrangement (110), transmitting a control voltage (V4) received from a trimmable voltage source (120) to a control input of the first field-effect transistor to activate the first field-effect transistor; and wherein a magnitude of the control voltage (V4) received from the trimmable voltage source (120) is selected to limit the magnitude of the first current (iC1) supplied by the first current source (131) to a gate node (G) of the main switch (130).

Images