Semiconductor element control circuit

Abstract

A semiconductor element driver circuit comprises: a first output terminal to which a first power semiconductor element is connected; a second output terminal to which a second power semiconductor element is connected, having a lower threshold voltage than the first power semiconductor element; a first cutoff semiconductor element that reduces the voltage of the first output terminal when switched on; a second cutoff semiconductor element that reduces the voltage of the second output terminal when switched on; and a cutoff control circuit that switches on the first cutoff semiconductor element and the second cutoff semiconductor element via a cutoff pre-stage circuit.

Description

BACKGROUND Technical area

[0001] The present disclosure relates to a semiconductor element control circuit. Description of the background technology

[0002] A semiconductor element driver circuit that drives two parallel-connected power semiconductor elements has been proposed (for example, published Japanese patent application no. 2018-198505).

[0003] In a semiconductor device containing two parallel-connected power semiconductor elements, it is necessary to reduce conduction loss by improving the characteristics of one power semiconductor element and to reduce costs by miniaturizing the power semiconductor element chip. A configuration that meets these requirements has been proposed in which the threshold voltage of one power semiconductor element is lowered. However, in an inverter device with two power semiconductor elements as a single arm, when a counter-arm connected in series with the same arm performs a switching operation, the voltage between a collector and an emitter (between a drain and a source) of the two power semiconductor elements of the same arm rises sharply.

[0004] As a result, the gate capacitance of the power semiconductor elements of the same arm is charged by a displacement current generated by a time-varying (dV / dt) voltage, and thus a floating gate voltage occurs, in which the gate voltage hardly decreases. Consequently, a problem arises in which a malfunction can occur where a power semiconductor element (especially one with a low threshold voltage) is switched on even when it should be switched off. SUMMARY

[0005] The present disclosure was created with regard to the above problem, and its objective is to provide a technique capable of suppressing a malfunction of a power semiconductor element.

[0006] A semiconductor element drive circuit according to the present disclosure comprises: an input terminal; a first output terminal to which a first power semiconductor element is connected; a second output terminal to which a second power semiconductor element is connected in parallel with the first power semiconductor element and has a lower threshold voltage than the first power semiconductor element; a first output pre-stage circuit that generates a first input correspondence signal based on an input signal of the input terminal; a first output circuit that drives the first power semiconductor element via the first output terminal based on the first input correspondence signal; a first turn-off orA cutoff semiconductor element that reduces the voltage of the first output terminal when switched on; a second output preamplifier circuit that generates a second input correspondence signal based on the input signal; a second output circuit that drives the second power semiconductor element via the second output terminal based on the second input correspondence signal; a second cutoff semiconductor element that reduces the voltage of the second output terminal when switched on; a cutoff preamplifier circuit connected to the first and second cutoff semiconductor elements; and a cutoff control circuit that, via the cutoff preamplifier circuit, switches on the first and second cutoff semiconductor elements if the input signal is at a low level and the voltage of the first output terminal is lower than a predetermined value.

[0007] It is possible to suppress a malfunction of a first power semiconductor element and a second power semiconductor element.

[0008] These and other objectives, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when it is considered in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a circuit diagram illustrating a configuration of a semiconductor element drive circuit according to a first preferred embodiment; Fig. 2 is a timing diagram illustrating the operation of the semiconductor element drive circuit according to the first preferred embodiment; Fig. Figures 3 to 6 are circuit diagrams, each illustrating a configuration example of a cutoff control circuit according to the first preferred embodiment; Fig. Figure 7 is a circuit diagram illustrating a configuration of a semiconductor element drive circuit according to a second preferred embodiment; Fig. 8 is a timing diagram illustrating the operation of the semiconductor element drive circuit according to the second preferred embodiment; Fig. Figure 9 is a circuit diagram illustrating a configuration example of a delay buffer according to the second preferred embodiment; Fig. Figure 10 is a circuit diagram illustrating a configuration of a semiconductor element drive circuit according to a third preferred embodiment; Fig. 11 is a timing diagram illustrating the operation of the semiconductor element drive circuit according to the third preferred embodiment; and Fig. Figure 12 is a circuit diagram illustrating a configuration of a semiconductor element drive circuit according to a fourth preferred embodiment. DESCRIPTION OF PREFERRED EXECUTION FORMS

[0009] Preferred embodiments are described below with reference to the accompanying drawings. Features described in the following preferred embodiments are examples, and not all features are necessarily essential. Furthermore, similar components in a multitude of preferred embodiments are designated by the same or similar reference numerals in the following description, and predominantly different components are described. <Erste bevorzugte Ausführungsform>

[0010] Fig. 1 is a circuit diagram illustrating a configuration of a semiconductor element driver circuit IC according to the first preferred embodiment, and Fig. Figure 2 is a timing diagram illustrating an overview of the operation of the semiconductor element driver circuit IC.

[0011] The semiconductor element control circuit IC from Fig. 1 comprises an input terminal IN, a first output terminal OUT1, a second output terminal OUT2, a first output pre-stage circuit 1, a first output circuit comprising semiconductor elements 2 and 3, a first cutoff semiconductor element 4, a second output pre-stage circuit 5, a second output circuit comprising semiconductor elements 6 and 7, a second cutoff semiconductor element 8, a cutoff pre-stage circuit 9, and a cutoff control circuit 10. The semiconductor element control circuit IC and a first power semiconductor element 31 and a second power semiconductor element 32, which are connected to the semiconductor element control circuit IC, are arranged in a semiconductor device.

[0012] The first output terminal OUT1 is connected to a gate of the first power semiconductor element 31, and the second output terminal OUT2 is connected to a gate of the second power semiconductor element 32. Since the threshold voltage Vth2 of the second power semiconductor element 32 is lower than the threshold voltage Vth1 of the first power semiconductor element 31, the second power semiconductor element 32 is more susceptible to malfunction due to gate voltage floating than the first power semiconductor element 31.

[0013] In the first preferred embodiment, the first power semiconductor element 31 is an insulated gate bipolar transistor (IGBT) made of silicon (Si) and the second power semiconductor element 32 is a metal oxide semiconductor field-effect transistor (MOSFET) made of silicon carbide (SiC).

[0014] However, the first power semiconductor element 31 and the second power semiconductor element 32 are not limited to this, and, for example, at least one of the first power semiconductor element 31 and the second power semiconductor element 32 can be an IGBT or a MOSFET. Note that in the present description, for example, at least one of A, B, C, ... and Z means any combination of one or more elements extracted from the group A, B, C, ... and Z.

[0015] Furthermore, at least one of the first power semiconductor element 31 and the second power semiconductor element 32 can be made of Si or SiC. Instead of this SiC, another wide-bandgap semiconductor such as gallium nitride (GaN), gallium oxide (Ga₂O₃), or diamond can be used. If at least one of the first power semiconductor element 31 and the second power semiconductor element 32 consists of a wide-bandgap semiconductor, it is possible to operate the semiconductor device stably at high temperature and high voltage, increase the switching speed, and miniaturize the semiconductor device.

[0016] The second power semiconductor element 32 is connected in parallel with the first power semiconductor element 31. The first power semiconductor element 31 and the second power semiconductor element 32 can form one arm of an inverter device that drives an inductive load, such as a motor. The inverter device here includes, for example, a half-bridge inverter device, a full-bridge inverter device, a three-phase inverter device, and the like.

[0017] The first power semiconductor element 31 and the second power semiconductor element 32 can, for example, form an upper arm. Furthermore, a collector of the first power semiconductor element 31 and a drain of the second power semiconductor element 32 can be connected to a power supply (not illustrated), and an emitter of the first power semiconductor element 31 and a source of the second power semiconductor element 32 can be connected to a lower arm and an inductive load (not illustrated). The lower arm can comprise two parallel-connected power semiconductor elements similar to the first power semiconductor element 31 and the second power semiconductor element 32.

[0018] The first output preamplifier circuit 1 generates a first input correspondence signal based on an input signal from the input terminal IN. In the first preferred embodiment, the first output preamplifier circuit 1 is a NOT circuit (inverter) and generates the first input correspondence signal by inverting the level of the input signal. That is, the first output preamplifier circuit 1 outputs a first input correspondence signal at a low level if the input signal is at a high level, and outputs a first input correspondence signal at a high level if the first input signal is at a low level. In the first preferred embodiment, the low level corresponds to a reference voltage (GND) connected to the semiconductor device driver circuit IC, and the high level corresponds to a power supply voltage (VCC) connected to the semiconductor device driver circuit IC.

[0019] The first output circuit, comprising semiconductor elements 2 and 3, controls the first power semiconductor element 31 via the first output terminal OUT1 on the basis of the first input correspondence signal from the first output pre-stage circuit 1.

[0020] Once the input signal of the input terminal IN reaches the high level, the semiconductor element 2 of the first output circuit charges the gate capacitance of the first power semiconductor element 31. That is, as in Fig. As illustrated in Figure 2, when the input signal of the input terminal IN reaches the high level, the voltage of the first output terminal OUT1 becomes higher than the threshold voltage Vth1 and the first power semiconductor element 31 is switched on.

[0021] On the other hand, after the input signal of the input terminal IN has reached the low level, the semiconductor element 3 of the first output circuit discharges the gate capacitance of the first power semiconductor element 31. That is, as in Fig. As illustrated in Figure 2, when the input signal of the input terminal IN reaches the low level, the voltage of the first output terminal OUT1 becomes lower than the threshold voltage Vth1 and the first power semiconductor element 31 is switched off.

[0022] Note that in the first preferred embodiment, the semiconductor elements 2 and 3 are a P-type MOSFET (PMOS) and an N-type MOSFET (NMOS), respectively, but are not limited to these.

[0023] When the first cutoff semiconductor element 4 is switched on, it reduces the impedance between the first output terminal OUT1 and ground (GND) to reduce the voltage at the first output terminal OUT1, thereby suppressing any floating of the gate voltage of the first power semiconductor element 31. In the first preferred embodiment, the first cutoff semiconductor element 4 is an NMOS, but this is not limited to NMOS.

[0024] The second output preamplifier circuit 5, the second output circuit comprising semiconductor elements 6 and 7, and the second cutoff semiconductor element 8 are configured similarly to the first output preamplifier circuit 1, the first output circuit comprising semiconductor elements 2 and 3, and the first cutoff semiconductor element 4. That is, the second output preamplifier circuit 5 generates a second input correspondence signal based on the input signal, and the second output circuit drives the second power semiconductor element 32 via the second output terminal OUT2 based on the second input correspondence signal from the second output preamplifier circuit 5.When the second cutoff semiconductor element 8 is turned on, the second cutoff semiconductor element 8 reduces the impedance between the second output terminal OUT2 and ground (GND) in order to reduce the voltage of the second output terminal OUT2, thereby suppressing gate floating of the second power semiconductor element 32.

[0025] If the first power semiconductor element 31 and the second power semiconductor element 32 are not connected to the first output terminal OUT1 and the second output terminal OUT2, respectively, the signal waveforms at the first output terminal OUT1 and the second output terminal OUT2 are square waves similar to the signal waveform at the input terminal IN. If the first power semiconductor element 31 and the second power semiconductor element 32 are connected to the first output terminal OUT1 and the second output terminal OUT2, respectively, they exhibit the waveforms shown in Fig. Figure 2 illustrates that the signal waveforms at the first output terminal OUT1 and the second output terminal OUT2 exhibit smoother changes in rise and fall per unit of time than the square wave signal waveform at the input terminal IN. Note that, for the sake of clarity, the following description may refer to a change in rise per unit of time and a change in fall per unit of time as a rising change and a falling change, respectively.

[0026] The degree to which the rising and falling changes in the signal waveform at the first output terminal OUT1 become smooth or flattened is determined by the on-resistance of the first output circuit and the gate capacitance of the first power semiconductor element 31. Similarly, the degree to which the rising and falling changes in the signal waveform at the second output terminal OUT2 become smooth is determined by the on-resistance of the second output circuit and the gate capacitance of the second power semiconductor element 32.

[0027] In the first preferred embodiment, by adjusting the input resistance and the gate capacitance, the rising change of the signal waveform at the second output terminal OUT2 is smoother than the rising change of the signal waveform at the first output terminal OUT1. Furthermore, by adjusting the input resistance and the gate capacitance, the falling change of the signal waveform at the second output terminal OUT2 is steeper than the falling change of the signal waveform at the first output terminal OUT1. Accordingly, the second power semiconductor element 32 can operate at a low threshold voltage without significantly contributing to the switching process, thus reducing conduction losses.

[0028] Note that in the first preferred embodiment, the second power semiconductor element 32 has a smaller chip area than the first power semiconductor element 31. According to such a configuration, the decay of the signal waveform at the second output terminal OUT2 can be set to a steeper rate than the decay of the signal waveform at the first output terminal OUT1. Therefore, it is possible to easily implement the operation of the second power semiconductor element 32 with a low threshold voltage without significantly contributing to the switching process, which makes it possible to easily reduce line losses.

[0029] Please note that for the sake of clarity in the above description, Fig. 2 does not reflect a floating of the gate voltages of the first output terminal OUT1 and the second output terminal OUT2, a reduction of the gate voltage of the first output terminal OUT1 due to the switching on of the first cutoff semiconductor element 4 and the like.

[0030] The cutoff preamplifier circuit 9 in Fig. 1 is connected to the gates of the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8. The cutoff pre-stage circuit 9 in the first preferred embodiment is a NOT circuit (inverter), inverts the level of a signal from the cutoff control circuit 10 and outputs the inverted signal to the gates of the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8.

[0031] The cutoff control circuit 10 controls the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 via the cutoff pre-stage circuit 9 based on the input signal of the input terminal IN and the voltage of the first output terminal OUT1. The control of the cutoff control circuit 10 is described below with reference to the voltage at a junction VG between the cutoff pre-stage circuit 9 and the gates of the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8.

[0032] In a case where the input signal of the input terminal IN changes from a low level to a high level, the cutoff control circuit 10 outputs a low-level signal from the cutoff preamplifier circuit 9 to the gates of the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8, as in the voltage at junction VG at time t1. Fig. 2. As a result, the cutoff control circuit 10 switches off the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 via the cutoff pre-stage circuit 9.

[0033] On the other hand, in a case where the input signal of the input terminal IN is at a low level and the voltage of the first output terminal OUT1 becomes lower than a predetermined value Vgt, the cutoff control circuit 10 sends a high-level signal from the cutoff preamplifier circuit 9 to the gates of the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8, corresponding to the voltage at the junction VG at time t2. Fig. 2 off. As a result, the cutoff control circuit 10 switches on the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 via the cutoff pre-stage circuit 9.

[0034] In the first preferred embodiment, the time t2 at which the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 are switched on is sufficiently later than the times at which the voltages of the first output terminal OUT1 and the second output terminal OUT2 become equal to or lower than the threshold voltages Vth1 and Vth2. As described above, if the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 are switched on sufficiently later than the switching operation of the first power semiconductor element 31 and the second power semiconductor element 32, it is possible to suppress noise radiated outwards from the semiconductor device.

[0035] Fig. Figures 3 to 6 are circuit diagrams, each illustrating a configuration example of the cutoff control circuit 10.

[0036] As in Fig. As illustrated in Figure 3, the cutoff control circuit can have 10 NOT circuits 41 and 42 and a NAND circuit 43 whose inputs are connected to the NOT circuits 41 and 42. Note that the value of a threshold voltage of the NOT circuit 41, into which a signal from the first output terminal OUT1 is fed, is the value Vgt in Fig. 2. If the input signal of the input terminal IN is at a low level and the voltage of the first output terminal OUT1 is lower than the value Vgt, the cutoff control circuit 10, configured as described above, outputs a signal at a low level, so that the voltage at the junction VG at time t2 is Fig. 2 can be set to the high level.

[0037] As in Fig. As illustrated in Figure 4, the cutoff control circuit 10 can comprise an NOT circuit 44 and an SR-FF circuit 45, in which the NOT circuit 44 is connected to an S terminal and the input signal of the input terminal IN is fed into an R terminal. According to the configuration of Fig. 3. The cutoff control circuit 10 can be implemented with a simple circuit configuration; however, in a case where the gate voltage fluctuates or floats and the voltage of the first output terminal OUT1 becomes equal to or higher than the value Vgt, the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 cannot be turned on. Meanwhile, according to the configuration of Fig. 4, even if the gate voltage is floating and the voltage of the first output terminal OUT1 becomes equal to or higher than the value Vgt, the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 are switched on.

[0038] As in Fig. 5 and Fig. As illustrated in Figure 6, the cutoff control circuit 10 can have a configuration in which the NOT circuits 41 and 44 in the configurations of the Fig. 3 and Fig. Comparators 41a and 44a are replaced by comparators 41a and 44a. According to such a configuration, although the circuit dimensions increase slightly depending on the response speed of the comparators, it is possible to reduce the influence of changes in the supply voltage and temperature, since Vgt serves as the reference voltage for the comparators.

[0039] Note that the configuration of the cutoff control circuit 10 does not apply to the configurations in Fig. The configuration is limited to 3 to 6, and other configurations can be used. A suitable configuration according to an application is applied to the configuration of the cutoff control circuit 10. <Zusammenfassung der ersten bevorzugten Ausführungsform>

[0040] According to the semiconductor element control circuit IC of the first preferred embodiment as described above, the cutoff control circuit 10 switches on the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 if an input signal of the input terminal IN is at a low level and the voltage of the first output terminal OUT1 is lower than the value Vgt. According to such a configuration, it is possible to suppress floating gate voltages in the first power semiconductor element 31 and the second power semiconductor element 32, which makes it possible to suppress malfunctions of the first power semiconductor element 31 and the second power semiconductor element 32.

[0041] Furthermore, in the first preferred embodiment, a cutoff pre-stage circuit 9 and a cutoff control circuit 10 control both the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8. Therefore, it is possible to reduce the circuit dimension compared with a configuration in which both the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 are provided with a cutoff pre-stage circuit and a cutoff control circuit.

[0042] Furthermore, as the value of Vgt decreases, the circuit dimension of the cutoff control circuit 10, which determines whether the voltage of the first output terminal OUT1 is lower than the value of Vgt, generally increases. On the other hand, in the first preferred embodiment, the cutoff control circuit 10 controls the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 based on the input and output on the side of the first output circuit, which controls the first power semiconductor element 31 with the high threshold voltage Vth1.

[0043] Therefore, it is possible to set the value Vgt of the cutoff control circuit 10 higher than the value Vgt of an associated circuit that controls the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 based on the input and output on the side of the second output circuit, which controls the second power semiconductor element 32 with the low threshold voltage Vth2. Consequently, according to the first preferred embodiment, it is possible to reduce the circuit dimension of the cutoff control circuit 10 and, consequently, the circuit dimension of the semiconductor element driver circuit IC.

[0044] Note that in the configuration of the first preferred embodiment, in which the cutoff control circuit 10, which controls both the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8, is arranged, the timing, or the time of switching on the second cutoff semiconductor element 8, may be later than in a configuration in which two cutoff control circuits, one controlling the first cutoff semiconductor element 4 and the other the second cutoff semiconductor element 8, are arranged. However, the delay in timing does not cause any problems, since it is not assumed that the opposite arm will perform a switching operation before the voltage at the first output terminal OUT1 becomes sufficiently low.

[0045] In a case where the size of the semiconductor element 7 of the second output circuit is relatively large, it is also possible to suppress a floating gate voltage of the second power semiconductor element 32. However, in such a case, the problem arises that the current increases during the discharge of the voltage of the second output terminal OUT2, the off-operation of the second power semiconductor element 32 becomes rapid, and thus the noise radiated externally by the semiconductor device increases. On the other hand, according to the first preferred embodiment, it is possible to suppress a floating gate voltage of the second power semiconductor element 32 without increasing the size of the semiconductor element 7 of the second output circuit, which makes it possible to prevent an increase in noise. <Zweite bevorzugte Ausführungsform>

[0046] Fig. 7 is a circuit diagram illustrating a configuration of a semiconductor element driver circuit IC according to the second preferred embodiment, and Fig. Figure 8 is a timing diagram illustrating an overview of the operation of the semiconductor element driver circuit IC.

[0047] The configuration of Fig. 7 is similar to a configuration in which the cutoff control circuit 10 is in the configuration of Fig. 1 is replaced by a delay buffer 16. Note that an input terminal IN, a first output terminal OUT1, a second output terminal OUT2, a first output pre-stage circuit 1, a first output circuit comprising semiconductor elements 2 and 3, a first cutoff semiconductor element 4, a second output pre-stage circuit 5, a second output circuit comprising semiconductor elements 6 and 7, a second cutoff semiconductor element 8, and a cutoff pre-stage circuit 9 are similar to those of the first preferred embodiment.

[0048] The delay buffer 16 is configured to turn on the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 by passing a delay signal, which is a signal whose decay time is delayed relative to the decay time of an input signal, to the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 via the cutoff pre-stage circuit 9.

[0049] In the second preferred embodiment, the delay buffer 16 outputs a low-level signal to the cutoff preamplifier circuit 9 at a time t8 that is delayed by a time td relative to the decay time t7 of an input signal at the input terminal IN. Fig. The voltage at junction VG is delayed until it reaches the high level. Therefore, at time t8, the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 are switched on.

[0050] Note that the delay by the delay buffer 16 is preferably set such that the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 are switched on sufficiently later than the switching operation of a first power semiconductor element 31 and a second power semiconductor element 32. According to such a configuration, it is possible to suppress noise radiated outwards by the semiconductor device.

[0051] In the second preferred embodiment, the delay signal is a signal in which the decay time is delayed relative to the decay time of the input signal, but the rise time is not delayed relative to the rise time of the input signal. Therefore, the delay buffer 16 outputs a high-level signal to the cutoff preamplifier circuit 9 at a rise time t6 of the input signal at input terminal IN. Fig. 8 off, so that the voltage at the VG connection point reaches the low level.

[0052] Fig. Figure 9 is a circuit diagram illustrating a configuration example of the delay buffer 16. As shown in Fig. As illustrated in Figure 9, the delay buffer 16 can comprise a PMOS 51, a PMOS 54, a resistor 52, an NMOS 53, and an NMOS 55. The PMOS 51, resistor 52, and NMOS 53 are connected in series from a power supply voltage (VCC) to a reference voltage (GND) in that order to form a first NOT circuit. The PMOS 54 and NMOS 55 are connected in series from the power supply voltage (VCC) to the reference voltage (GND) in that order to form a second NOT circuit. A junction between resistor 52 and NMOS 53 is connected to the gates of the PMOS 54 and NMOS 55, and the first and second NOT circuits are essentially connected in series.

[0053] The resistor 52 connected to the PMOS 51 delays the rise time of the output signal of the first NOT circuit relative to the fall time of the input signal. The second NOT circuit inverts the output signal of the first NOT circuit. Therefore, the delay buffer 16, configured as described above, can output a low-level signal at time t8, which is delayed by time td relative to the fall time t7 of the input signal at input terminal IN. Fig. 8 is delayed, and is sent to the cutoff preamplifier circuit 9.

[0054] Note that the configuration of delay buffer 16 does not depend on the configuration of Fig. The configuration is limited to 9 and other configurations can be used. A suitable configuration according to an application is applied to the configuration of the delay buffer 16. <Zusammenfassung der zweiten bevorzugten Ausführungsform>

[0055] The semiconductor element driver IC according to the second preferred embodiment as described above is configured to switch on the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 by supplying a delay signal, which is a signal whose decay time is delayed relative to the decay time of an input signal, to the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 via the cutoff pre-stage circuit 9. According to such a configuration, as in the first preferred embodiment, it is possible to suppress a malfunction of the first power semiconductor element 31 and the second power semiconductor element 32.

[0056] Furthermore, in the second preferred embodiment, a cutoff pre-stage circuit 9 and a delay buffer 16 control both the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8. Therefore, it is possible to reduce the circuit dimension compared with a configuration in which both the first cutoff semiconductor element 4 and the second cutoff semiconductor element 8 are provided with a cutoff pre-stage circuit and a delay buffer. <Dritte bevorzugte Ausführungsform>

[0057] Fig. Figure 10 is a circuit diagram illustrating a configuration of a semiconductor element driver circuit IC according to the third preferred embodiment, and Fig. Figure 11 is a timing diagram illustrating an overview of the operation of the semiconductor element driver circuit IC.

[0058] In the configuration of Fig. 10 is the configuration of Fig. 1. A delay buffer 18 is added. Note that an input terminal IN, a first output terminal OUT1, and a second output terminal OUT2 are similar to those of the first preferred embodiment.

[0059] The delay buffer 18 is essentially similar to the delay buffer 16 according to the second preferred embodiment and generates a delay signal, which is a signal whose decay time is delayed relative to a decay time of an input signal of the input terminal IN.

[0060] A first output pre-stage circuit 1 generates a delay correspondence signal based on the delay signal from the delay buffer 18. In the third preferred embodiment, the first output pre-stage circuit 1 is a NOT circuit (inverter) and generates the delay correspondence signal by inverting the level of the delay signal.

[0061] A first output circuit comprising semiconductor elements 2 and 3 is essentially similar to the first output circuit according to the first preferred embodiment and controls a first power semiconductor element 31 via the first output terminal OUT1 on the basis of the delay correspondence signal from the first output pre-stage circuit 1.

[0062] A first cutoff semiconductor element 4 is similar to the first cutoff semiconductor element 4 according to the first preferred embodiment. A second output pre-stage circuit 5 is substantially similar to the second output pre-stage circuit 5 according to the first preferred embodiment and generates an input correspondence signal based on the input signal of the input terminal IN. A second output circuit comprising semiconductor elements 6 and 7 is substantially similar to the second output circuit according to the first preferred embodiment and controls a second power semiconductor element 32 via the second output terminal OUT2 based on the input correspondence signal from the second output pre-stage circuit 5.

[0063] A second cutoff semiconductor element 8 is essentially similar to the second cutoff semiconductor element 8 according to the first preferred embodiment and reduces the voltage of the second output terminal OUT2 when it is switched on. However, in the third preferred embodiment, the second cutoff semiconductor element 8 is switched on based on the delay correspondence signal from the first output pre-stage circuit 1.

[0064] In the third preferred embodiment, the delay buffer 18 outputs at a time t13 that is a time td ahead of a fall-off time t12 of the input signal of the input terminal IN. Fig. With a delay of 11, a low-level signal is sent to the first output preamplifier circuit 1, and thus the voltage at the first output terminal OUT1 begins to drop. Furthermore, at time t13, the voltage at a junction VG2 between the first output preamplifier circuit 1 and the second cutoff semiconductor element 8 reaches a high level, thus switching on the second cutoff semiconductor element 8.

[0065] Note that the delay by the delay buffer 18 is preferably set such that the second cutoff semiconductor element 8 is switched on sufficiently later than the switching operation of the second power semiconductor element 32. According to such a configuration, it is possible to suppress noise radiated externally by the semiconductor device.

[0066] In the third preferred embodiment, the delay signal is a signal in which the decay time is delayed relative to the decay point of the input signal, but the rise time is not delayed relative to a rise point of the input signal. Therefore, the delay buffer 18 outputs a signal at the high level at a rise time t11 of the input signal of the input terminal IN. Fig. 11 to the first output preamplifier circuit 1, so that the voltage at connection point VG2 reaches the low level.

[0067] A 9-inch cutoff preamplifier circuit Fig. 10 is substantially similar to the cutoff pre-stage circuit 9 according to the first preferred embodiment and is connected to a gate of the first cutoff semiconductor element 4. However, in the third preferred embodiment, the cutoff pre-stage circuit 9 is not connected to a gate of the second cutoff semiconductor element 8.

[0068] A cutoff control circuit 10 is essentially similar to the cutoff control circuit 10 according to the first preferred embodiment and switches on the first cutoff semiconductor element 4 via the cutoff pre-stage circuit 9 if the input signal is at a low level and the voltage of the first output terminal OUT1 is lower than a predetermined value Vgt. That is, at a time t14 in Fig. In the third preferred embodiment, the cutoff control circuit 10 switches on the first cutoff semiconductor element 4 via the cutoff pre-stage circuit 9. However, in the third preferred embodiment, the cutoff control circuit 10 does not switch on the second cutoff semiconductor element 8 via the cutoff pre-stage circuit 9. <Zusammenfassung der dritten bevorzugten Ausführungsform>

[0069] According to the semiconductor element control circuit IC of the third preferred embodiment as described above, the cutoff control circuit 10 switches on the first cutoff semiconductor element 4 if the input signal of the input terminal IN is at a low level and the voltage of the first output terminal OUT1 is lower than the value Vgt. Furthermore, the second cutoff semiconductor element 8 is switched on based on the delay correspondence signal from the first output preamplifier circuit 1. According to such a configuration, as in the first preferred embodiment, it is possible to suppress a malfunction of the first power semiconductor element 31 and the second power semiconductor element 32.

[0070] Furthermore, in the third preferred embodiment, the delay buffer 18 and the first output pre-stage circuit 1 control the second cutoff semiconductor element 8. Therefore, it is possible to reduce the circuit dimension compared with a configuration in which the second cutoff semiconductor element 8 is provided with a cutoff pre-stage circuit and a cutoff control circuit. <Vierte bevorzugte Ausführungsform>

[0071] Fig. Figure 12 is a circuit diagram illustrating a configuration of a semiconductor device driver IC according to the fourth preferred embodiment. Note that a timing diagram illustrating an overview of the operation of the semiconductor device driver IC is similar to the timing diagram of Fig. 2 is essentially similar.

[0072] The configuration of Fig. 12 is similar to a configuration in which the configuration of Fig. 1. A diode 21 is added. The diode 21 has a cathode connected to a first output terminal OUT1 and an anode connected to a second output terminal OUT2. Note that the diode can be a Schottky barrier diode (SBD) or a PN junction diode (PND).

[0073] According to the semiconductor element driver circuit IC of the fourth preferred embodiment as described above, the voltage of the second output terminal OUT2 can be set lower than the voltage of the first output terminal OUT1. Consequently, a floating gate voltage of a second power semiconductor element 32 can be suppressed more effectively than a floating gate voltage of a first power semiconductor element 31, making it possible to suppress a malfunction of the second power semiconductor element 32 with a low threshold voltage Vth2.

[0074] Note that, although the example described above involves the diode 21 being configured according to the fourth preferred embodiment as follows: Fig. 1 of the first preferred embodiment, the diode 21 can be applied to the configuration of the second or third preferred embodiment.

[0075] Note that in the present English revelation, 'ein' and 'eine' stand for one or more. Consequently, 'ein', 'eine', 'ein oder mehr' and 'zuhaltdest ein' can be used interchangeably or synonymously.

[0076] Note that the preferred embodiments and modifications can be freely combined, and the preferred embodiments and modifications can be suitably modified or omitted.

[0077] Various aspects of the present revelation are described together in the following appendices. (Appendix 1)

[0078] A semiconductor element control circuit comprising: an input port; a first output terminal to which a first power semiconductor element is connected; a second output terminal to which a second power semiconductor element is connected, which is connected in parallel with the first power semiconductor element and has a lower threshold voltage than the first power semiconductor element; a first output pre-stage circuit that generates a first input correspondence signal based on an input signal from the input terminal; a first output circuit that controls the first power semiconductor element via the first output terminal on the basis of the first input correspondence signal; a first cutoff semiconductor element that reduces the voltage of the first output terminal when it is switched on; a second output preamplifier circuit that generates a second input correspondence signal based on the input signal; a second output circuit that controls the second power semiconductor element via the second output terminal based on the second input correspondence signal; a second cutoff semiconductor element that reduces the voltage of the second output terminal when it is switched on; a cutoff pre-stage circuit connected to the first cutoff semiconductor element and the second cutoff semiconductor element; and a cutoff control circuit which, via the cutoff pre-stage circuit, switches on the first cutoff semiconductor element and the second cutoff semiconductor element if the input signal is at a low level and the voltage of the first output terminal is lower than a predetermined value. (Appendix 2)

[0079] A semiconductor element control circuit comprising: an input port; a first output terminal to which a first power semiconductor element is connected; a second output terminal to which a second power semiconductor element is connected, which is connected in parallel with the first power semiconductor element and has a lower threshold voltage than the first power semiconductor element; a first output pre-stage circuit that generates a first input correspondence signal based on an input signal from the input terminal; a first output circuit which, based on the first input correspondence signal, controls the first power semiconductor element via the first output terminal; a first cutoff semiconductor element that reduces the voltage of the first output terminal when it is switched on; a second output preamplifier circuit that generates a second input correspondence signal based on the input signal; a second output circuit that controls the second power semiconductor element via the second output terminal based on the second input correspondence signal; a second cutoff semiconductor element that reduces the voltage of the second output terminal when it is switched on; a cutoff pre-stage circuit connected to the first cutoff semiconductor element and the second cutoff semiconductor element; and a delay buffer capable of switching on the first cutoff semiconductor element and the second cutoff semiconductor element by supplying a delay signal, which is a signal whose fall-off time is delayed relative to a fall-off time of the input signal, to the first cutoff semiconductor element and the second cutoff semiconductor element via the cutoff pre-stage circuit. (Appendix 3)

[0080] A semiconductor element control circuit comprising: an input port; a first output terminal to which a first power semiconductor element is connected; a second output terminal to which a second power semiconductor element is connected, which is connected in parallel with the first power semiconductor element and has a lower threshold voltage than the first power semiconductor element; a delay buffer that generates a delay signal, which is a signal whose decay time is delayed relative to the decay time of an input signal of the input terminal; a first output pre-stage circuit that generates a delay correspondence signal based on the delay signal; a first output circuit that controls the first power semiconductor element via the first output terminal on the basis of the delay correspondence signal; a first cutoff semiconductor element that reduces the voltage of the first output terminal when it is switched on; a second output preamplifier circuit that generates an input correspondence signal based on the input signal; a second output circuit that controls the second power semiconductor element via the second output terminal based on the input correspondence signal; a second cutoff semiconductor element that is switched on based on the delay correspondence signal and reduces the voltage of the second output terminal when it is switched on; a cutoff pre-stage circuit connected to the first cutoff semiconductor element; and a cutoff control circuit that switches on the first cutoff semiconductor element via the cutoff pre-stage circuit if the input signal is at a low level and the voltage of the first output terminal is lower than a predetermined value. (Appendix 4)

[0081] The semiconductor element control circuit according to one of Appendices 1 to 3, further comprising a diode having a cathode connected to the first output terminal and an anode connected to the second output terminal. (Appendix 5)

[0082] The semiconductor element drive circuit according to one of Appendices 1 to 4, wherein the second power semiconductor element has a smaller chip area than the chip area of ​​the first power semiconductor element. (Appendix 6)

[0083] The semiconductor element drive circuit according to one of Appendices 1 to 5, wherein the first power semiconductor element is an IGBT made of silicon and the second power semiconductor element is a MOSFET made of silicon carbide.

[0084] Although the revelation has been presented and described in detail, the preceding description is illustrative in all aspects and not limiting. It is therefore understood that numerous modifications and variations can be conceived.

Claims

[1] Semiconductor element driver circuit comprising: an input port (IN); a first output terminal (OUT1) to which a first power semiconductor element (31) is connected; a second output terminal (OUT2) to which a second power semiconductor element (32) is connected, which is connected in parallel with the first power semiconductor element (31) and has a lower threshold voltage than the first power semiconductor element (31); a first output pre-stage circuit (1) that generates a first input correspondence signal based on an input signal from the input terminal (IN); a first output circuit (2, 3) that controls the first power semiconductor element (31) via the first output terminal (OUT1) on the basis of the first input correspondence signal; a first cutoff semiconductor element (4) that reduces the voltage of the first output terminal (OUT1) when it is switched on; a second output preamplifier circuit (5) that generates a second input correspondence signal based on the input signal; a second output circuit (6, 7) that controls the second power semiconductor element (32) via the second output terminal (OUT2) on the basis of the second input correspondence signal; a second cutoff semiconductor element (8) that reduces the voltage of the second output terminal (OUT2) when it is switched on; a cutoff pre-stage circuit (9) connected to the first cutoff semiconductor element (4) and the second cutoff semiconductor element (8); and a cutoff control circuit (10) which, via the cutoff pre-stage circuit (9), switches on the first cutoff semiconductor element (4) and the second cutoff semiconductor element (8) if the input signal is at a low level and the voltage of the first output terminal (OUT1) is lower than a predetermined value. [2] Semiconductor element driver circuit comprising: an input port (IN); a first output terminal (OUT1) to which a first power semiconductor element (31) is connected; a second output terminal (OUT2) to which a second power semiconductor element (32) is connected, which is connected in parallel with the first power semiconductor element (31) and has a lower threshold voltage than the first power semiconductor element (31); a first output pre-stage circuit (1) that generates a first input correspondence signal based on an input signal from the input terminal (IN); a first output circuit (2, 3) that controls the first power semiconductor element (31) via the first output terminal (OUT1) on the basis of the first input correspondence signal; a first cutoff semiconductor element (4) that reduces the voltage of the first output terminal (OUT1) when it is switched on; a second output preamplifier circuit (5) that generates a second input correspondence signal based on the input signal; a second output circuit (6, 7) that controls the second power semiconductor element (32) via the second output terminal (OUT2) on the basis of the second input correspondence signal; a second cutoff semiconductor element (8) that reduces the voltage of the second output terminal (OUT2) when it is switched on; a cutoff pre-stage circuit (9) connected to the first cutoff semiconductor element (4) and the second cutoff semiconductor element (8); and a delay buffer (16) that is able to switch on the first cutoff semiconductor element (4) and the second cutoff semiconductor element (8) by supplying a delay signal, which is a signal whose decay time is delayed relative to a decay time of the input signal, to the first cutoff semiconductor element (4) and the second cutoff semiconductor element (8) via the cutoff pre-stage circuit (9). [3] Semiconductor element control circuit comprising: an input port (IN); a first output terminal (OUT1) to which a first power semiconductor element (31) is connected; a second output terminal (OUT2) to which a second power semiconductor element (32) is connected, which is connected in parallel with the first power semiconductor element (31) and has a lower threshold voltage than the first power semiconductor element (31); a delay buffer (18) which generates a delay signal, which is a signal whose decay time is delayed relative to a decay time of an input signal of the input terminal (IN); a first output pre-stage circuit (1) that generates a delay correspondence signal based on the delay signal; a first output circuit (2, 3) that controls the first power semiconductor element (31) via the first output terminal (OUT1) on the basis of the delay correspondence signal; a first cutoff semiconductor element (4) that reduces the voltage of the first output terminal (OUT1) when it is switched on; a second output pre-stage circuit (5) that generates an input correspondence signal based on the input signal; a second output circuit (6, 7) that controls the second power semiconductor element (32) via the second output terminal (OUT2) on the basis of the input correspondence signal; a second cutoff semiconductor element (8) which is switched on based on the delay correspondence signal and reduces a voltage of the second output terminal (OUT2) when it is switched on; a cutoff pre-stage circuit (9) connected to the first cutoff semiconductor element (4); and a cutoff control circuit (10) which switches on the first cutoff semiconductor element (4) via the cutoff pre-stage circuit (9) if the input signal is at a low level and the voltage of the first output terminal (OUT1) is lower than a predetermined value. [4] Semiconductor element control circuit according to one of claims 1 to 3, further comprising a diode (21) having a cathode connected to the first output terminal (OUT1) and an anode connected to the second output terminal (OUT2). [5] Semiconductor element control circuit according to one of claims 1 to 4, wherein the second power semiconductor element (32) has a smaller chip area than a chip area of ​​the first power semiconductor element (31). [6] Semiconductor element control circuit according to one of claims 1 to 5, wherein the first power semiconductor element (31) is a silicon-based IGBT and the second power semiconductor element (32) is a MOSFET consisting of silicon carbide.

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