FAST SERIAL DATA COMMUNICATION

Abstract

A serial communication device alternates between triggering the shift-out of an SDO bit and the shift-in of an SDI bit relative to a first shift clock edge and a second shift clock edge of a shift clock signal SCLK, separated by a first time difference. The serial communication device is further configured to trigger the shift-in of the SDI bit from the shift-out of the SDO bit by a second time difference that is longer than the first time difference.

Description

TECHNICAL AREA OF INVENTION

[0001] The invention relates generally to communication systems, in particular serial data communication. STATE OF THE ART

[0002] In some applications, it can be advantageous to use relatively inexpensive and / or low-power communication systems. An example of such a communication system is a serial communication system, in which bits of data are exchanged sequentially to communicate between different nodes.

[0003] In some examples, signals between nodes of a communication system may be received by a receiving node at a later time than they were sent by a transmitting node due to a propagation delay introduced by a communication path between the respective nodes. In some examples, the speed at which such a serial communication system can operate is limited by the propagation delay imposed on signals exchanged between nodes. SUMMARY

[0004] One of the objectives of the invention described herein is to provide improvements in serial data communication, in particular to enable serial data communication at faster speeds compared to conventional systems. This objective is achieved by the method according to claim 1, the communication device according to claim 14, and the system according to claim 24. Various embodiments and further developments are the subject of the dependent claims.

[0005] For example, a method is described that involves alternating between triggering the outshift of an SDO bit and the inshift of an SDI bit relative to a first shift clock edge, which is separated from a second shift clock edge of a shift clock signal SCLK by a first time difference. The method further involves triggering the inshift of the SDI bit, separate from triggering the outshift of the SDO bit, by a second time difference that is longer than the first time difference.

[0006] In another example, a communication device is described. The communication device is designed to alternate between triggering the shift-out of an SDO bit and triggering the shift-in of an SDI bit relative to a first shift clock edge, which is separated from a second shift clock edge of a shift clock signal SCLK by a first time difference. The communication device is further designed to trigger the shift-in of the SDI bit separately from the shift-out of the SDO bit by a second time difference that is longer than the first time difference.

[0007] Another example describes a system comprising a host node and a peripheral node. The peripheral node is configured to alternate between triggering the outshift of an SDO bit and the inshift of an SDI bit relative to the first and second shift clock edges. Furthermore, the peripheral node is configured to trigger the inshift of the SDI bit separately from the outshift of the SDO bit by a second time difference that is longer than the first. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram representing a host node that is coupled to communicate with a variety of peripheral nodes, according to some embodiments. Fig. Figure 2 is a block diagram that shows an example of a host node that is coupled to communicate with a peripheral node, according to some embodiments. Fig. Figure 3 is a block diagram representing a communication system that includes a host node communicatively coupled to a peripheral node, according to some embodiments. Fig. Figure 4A is a timing diagram showing operations of a peripheral node designed to trigger an in-shift of SDI bits at a second time difference after triggering the out-shift of SDO bits, according to some embodiments. Fig. Figure 4B is a timing diagram representing operations of a peripheral node designed to trigger the pushing in of SDI bits from the pushing out of SDO bits, according to some embodiments, by a second time difference which is twice or nearly twice a first time difference. Fig. 4C is a timing diagram showing operations of a peripheral node designed to trigger an in-shift of SDI bits at a second time difference before triggering the out-shift of SDO bits, according to some embodiments. Fig. 4D is a timing diagram representing operations of a peripheral node designed to trigger the pushing in of SDI bits from the pushing out of SDO bits, according to some embodiments, by a second time difference that is twice or nearly twice a first time difference. Fig. Figure 5A is a timing diagram showing operations of a host node designed to trigger an in-shift of SDI bits at a second time difference before triggering the out-shift of SDO bits, according to some embodiments. Fig. Figure 5B is a timing diagram representing operations of a host node designed to trigger the pushing in of SDI bits from the pushing out of SDO bits, according to some embodiments, separated by a second time difference which is twice or nearly twice a first time difference. Fig. Figure 6A is a timing diagram showing operations of a host node designed to trigger an in-shift of SDI bits at a second time difference after triggering the out-shift of SDO bits, and of a peripheral node designed to trigger an in-shift of SDI bits at a second time difference before triggering the out-shift of SDO bits, according to some embodiments. Fig. Figure 6B is a timing diagram showing operations of a peripheral node designed to trigger an in-shift of SDI bits at a second time difference after triggering the out-shift of SDO bits, and of a host node designed to trigger an in-shift of SDI bits at a second time difference before triggering the out-shift of SDO bits, according to some embodiments. Fig. Figure 7A is a timing diagram showing operations of a host node designed to trigger an in-shift of SDI bits to a second time difference after triggering the out-shift of SDO bits and to trigger an in-shift of SDI bits to a second time difference before triggering the out-shift of SDO bits, according to some embodiments. Fig. Figure 7B is a timing diagram showing operations of a peripheral node designed to trigger an in-shift of SDI bits at a second time difference after triggering the out-shift of SDO bits and to trigger an in-shift of SDI bits at a second time difference before triggering the out-shift of SDO bits, according to some embodiments. Fig. Figure 7C is a timing diagram showing operations of a peripheral node and a host node, both designed to trigger an in-shift of SDI bits at a second time difference after triggering the out-shift of SDO bits, and to trigger an in-shift of SDI bits at a second time difference before triggering the out-shift of SDO bits, according to some embodiments. Fig. 8A and Fig. Figure 8B are timing diagrams showing operations of a peripheral node of a system designed to communicate using a Serial Peripheral Interface (SPI) protocol, according to some embodiments. Fig. 9A and Fig. 9B are timing diagrams showing operations of a communication node of a system designed to communicate using a Serial Peripheral Interface (SPI) protocol, according to some embodiments. Fig. Figure 10 is a flowchart showing an example of a method for operating a serial communication node according to some embodiments. DETAILED DESCRIPTION

[0008] Fig. Figure 1 is a block diagram representing a host node 110 coupled to communicate with a plurality of peripheral nodes 120A-120F, according to some embodiments. The host node 110 may be configured to control communications with the respective peripheral nodes 120A-120F. For example, the host node 110 is a processing component, such as a microcontroller, that acts as a main controller for distributed components of a vehicle system by communicating with the peripheral nodes 120A-120F. As non-limiting examples, the host node 110 may include one or more microprocessors, graphics processing units (GPUs), one or more reduced instruction set processors (RISC processors), or any other processing component configured to control communications with the peripheral nodes 120A-120F.

[0009] As a non-restrictive example, the host node 110 can communicate with the peripheral nodes 120A-120F to control the power supply of a vehicle motor, such as an electric or hybrid powertrain motor, a brake system actuator, a door or brake locking mechanism, window controls, or any other motor or actuator used in a vehicle. In other non-restrictive examples, the host node 110 can communicate with the peripheral nodes 120A-120F to control a vehicle lighting system, for example, to control interior or exterior vehicle lighting systems.

[0010] As in Fig. As shown in Figure 1, the host node 110 is coupled to a shift clock module 107, which is designed to generate a shift clock signal “SCLK” that is sent to each peripheral node 120A-120F and is used to operate the system 100 synchronously. In the Fig. In the embodiment shown in Figure 1, the peripheral nodes 120A-120F are configured as Serial Peripheral Interface (SPI) nodes, each coupled to the host node 110 by four signals: a chip selection signal (CS), a shift clock signal (SCLK), a master-out-slave-in (MOSI) signal, and a master-in-slave-out (MISO) signal, each of which is coupled to analog I / O ports of the host node 110. Although only one transmission line representing each of these signals is shown, in some embodiments each signal can represent multiple signals. For example, the system 100 can be implemented such that each peripheral node is coupled in parallel to multiple MOSI signals and multiple MISO signals. In other embodiments not shown, the peripheral nodes 120A-120F may be coupled by one or more other signals used in various serial data communication topologies.

[0011] To communicate, the host node 110 and the peripheral nodes 120A-120F exchange messages by switching MOSI and MISO bits on and off based on the shift clock signal SCLK. The shift clock signal SCLK includes a first type of signal edge that triggers a shift in of MISO data bits and a second type of signal edge that triggers a shift out of MOSI data bits. For example, the host node 110 can generate a message addressed to one or more peripheral nodes containing multiple MOSI bits and receive a message from the same or a different peripheral node containing the same number of MISO bits. To communicate, the host node 110 generates the shift clock signal SCLK to indicate a switch between shifting a MISO bit in and shifting a MOSI bit out in response to successive edges of the shift clock signal.

[0012] According to the example of Fig. 1. Host node 110 includes several host nodes (HN modules 112A-112C), each representing a different communication topology that can be used to communicatively couple host node 110 with the respective peripheral nodes 120A-120F. The examples of Fig. The numbers 1 and 1 are for illustrative purposes only and are not intended to be restrictive. In some examples, the system may include 100 more (i.e., up to 10 peripheral nodes) or, in some cases, many more peripheral nodes than shown. According to these examples, the host node 110 is coupled to the peripheral nodes according to any one of the following: Fig. To communicate the different topologies shown, individually or in combination.

[0013] As an example, the HN module 112B is coupled with a peripheral node 120D in a peer-to-peer topology. According to this example, the host node 110 and the peripheral node 120D communicate directly via CS, MOSI, MISO, and SCLK signals coupled between the host node 110 and the peripheral node 120D.

[0014] As another example, the HN module 112C is coupled to a pair of peripheral nodes 120E and 120F in a star topology. As shown in Fig. As shown in Figure 1, according to the star topology, the HN module 112C is coupled to several peripheral nodes 120E and 120F via the same SCLK, MOSI, and MISO signals, and each of the several peripheral nodes is selectable via dedicated chip selection signals CS0 and CS1, which are coupled to the respective peripheral nodes 120E and 120F. To communicate in the star topology, the HN module 112C transmits MOSI bits, which are received by the several peripheral nodes 120E and 120F, and the respective chip selection signals indicate which of the peripheral nodes 120E and 120F is the intended receiver of the MOSI bits. In the star topology, a selected peripheral node of peripheral nodes 120E and 120F pushes MISO bits to the host node 110.

[0015] As another example, the HN module 112A is coupled with the peripheral nodes 120A-120C in a series topology. According to the in Fig. In the series topology shown in Figure 1, the host node 110 is coupled to the peripheral nodes 120A and 120C at respective ends of the series topology, with, for example, another peripheral node 120B located between the first peripheral node 120A and the last peripheral node 120C of the series, where the series includes more than two peripheral nodes. For example, as in Fig. As shown in Figure 1, the HN module 112A is coupled to a first peripheral node 120A via a MOSI signal and to the last peripheral node 120C of the series topology via a MISO signal.

[0016] As in Fig. As shown in Figure 1, the HN module 112A includes chip selection CS and SCLK signals that are coupled to each of the peripheral nodes 120A-120C. The HN module 112A is coupled to an input of peripheral node 120A via a MOSI signal. A MISO output of peripheral node 120A is coupled to a MOSI input of peripheral node 120B. The MISO output of peripheral node 120B is coupled to a MOSI input of peripheral node 120C, and the MISO output of peripheral node 120C is coupled to the HN module 112A.

[0017] To communicate using the daisy-chain topology, the HN module 112A can send messages to peripheral nodes 120A-120C via other nodes in the daisy chain. A message sent by the host node 110 can contain one or more data segments (one or more data bits) addressed to each of the respective peripheral nodes 120A-120C. As a non-restrictive example, the HN module 112A can first activate the CS signal, indicating that a message is being transmitted, then push out a data segment for peripheral node 120C, followed by a data segment for peripheral node 120B, followed by a data segment for peripheral node 120A.Peripheral node 120A can receive the message as MOSI bits from HN module 112A, output a data segment followed by the received MOSI bits as MISO bits to peripheral node 120B, and store one or more data segments for peripheral node 120A when the message is complete. Peripheral node 120B can receive the message as MOSI bits from peripheral node 120A, output a data segment followed by the received MOSI bits as MISO bits to peripheral node 120C, and store one or more data segments for peripheral node 120B when the message is complete. Peripheral node 120C can receive the message as MOSI bits from peripheral node 120B and store one or more data segments for peripheral node 120C when the message is complete.Host node 110 can then disable the CS signal to indicate to peripheral nodes 120A-120C that message transmission is complete. According to the daisy-chain topology, peripheral nodes 120A-120C can also send output data segments to host node 110 and / or other peripheral nodes 120A-120C based on the shift clock signal SCLK, which is generated by host node 110 in a similar manner.

[0018] As mentioned above, the example of host node 110 is in Fig. The example of node 110, which is designed to communicate with peripheral nodes 120A-120F using an SPI communication protocol, is provided for illustrative purposes only, and other serial data communication protocols may be used in other examples. Accordingly, in some examples, host node 110 may be described as being designed to push out serial data output (SDO) bits (e.g., MOSI bits) and push in serial data input (SDI) bits (e.g., MISO bits). Likewise, peripheral nodes 120A-120C may be described as being designed to push in SDO bits (e.g., MISO bits) and push in SDI bits (e.g., MOSI bits).

[0019] Fig. Figure 2 is a block diagram illustrating an example of a host node 110 coupled to communicate with a peripheral node 120, according to some embodiments. In the example of Fig. 2. The host node 110 and the peripheral node 120 are coupled according to a Serial-Peripheral Interface (SPI) protocol by a chip selection CS, a shift clock signal SCLK, a master-in-slave-out (MOSI) signal, and a master-out-slave-in (MISO) signal. The host node 110 and the peripheral node 120 can be coupled in a peer-to-peer, star, and / or daisy-chain topology, as in the examples of Fig. 1 shown, or in any other communication topology.

[0020] As in Fig. As shown in Figure 2, the host node 110 includes a baud rate and chip select generation module 113, which is designed to output chip select signals (CS) and shift clock signals (SCLK) to an analog baud rate and chip select receiver module 123 of one or more peripheral nodes 120. The CS signal indicates whether a message is being communicated to the peripheral node 120 and / or other peripheral nodes (not shown) of the system 100. The shift clock signal SCLK is generated by the host node 110 or a component coupled to the host node 110. For example, the shift clock signal SCLK can be coupled to a circuit arrangement that includes a crystal oscillator or one or more other components designed to generate a stable clock reference.

[0021] As in Fig. As shown in Figure 2, the host node 110 includes a transmitter 114 and a transmit buffer 115. To send a message to the peripheral node 120, the host node 110 stores bits of the message in the transmit buffer 115. The transmitter 114 shifts SDO bits (e.g., MOSI bits) to the receiver 126 of the peripheral node 120 based on the shift clock signal SCLK. The receiver 126 receives the SDO bits as SDI bits (e.g., MOSI bits) and stores the SDI bits in the receive buffer 127. In some examples, the transmitter 114 shifts out SDO bits of a message intended for the Fig. The 2 shown peripheral nodes are intended for 120. In some examples, the SDO bits can instead be used for a different peripheral node (in Fig. (2 not shown) is intended to be, for example, sender 114 can send a message with segments of one or more bits for each peripheral node coupled to host node 110, as described above with reference to a daisy-chain topology. Once the message bits are stored in receive buffer 127 when the message is completed, peripheral node 120 can execute one or more instructions contained in the message or use data contained in the message.

[0022] The peripheral node 120 includes a transmitter 124, which is designed to shift SDO bits (e.g., MISO bits) of a message stored in the transmit buffer 125 based on the shift clock signal SCLK. In the example of Fig. 2 The transmitter 124 is designed to push the SDO bits (e.g. generated by the peripheral node 120 or received as SDI bits) to the receiver 116 of the host node 110, which pushes the SDI bits in based on the shift clock signal SCLK and stores them in a receive buffer 117.

[0023] In some examples, the host node 110 and the one or more peripheral nodes 120 can each contain a transmit buffer 115 and a receive buffer 127 with a defined number of K data bits, which are used to shift MOSI data bits in and MISO data bits out, as triggered by the shift clock signal SCLK. According to some such examples, with each period of the shift clock signal SCLK, one MISO data bit is shifted in and one MOSI bit is shifted out. In some examples, the system 100 is designed to transmit a complete message to a number of M peripheral nodes in a series over a number of K*M shift clock periods. As such an example, for a system 100 with three peripheral nodes 120 with receive buffers 127 of 8 bits, a message can be communicated over (K=8 * M=3) = 24 shift clock periods.

[0024] Fig. Figure 3 is a block diagram representing a communication system 100, which includes a host node 110 that is communicatively coupled to a peripheral node 120 in some embodiments. As in Fig. As shown in Figure 3, the respective CS, SCLK, MOSI, and MISO signals of the host node 110 are coupled to I / O stages 118, which are designed to process signals output or received via I / O ports 119. The I / O ports 119 are coupled via transmission lines 130 to one or more I / O ports 129 of the peripheral node 120, which are coupled to one or more I / O stages 128 of the peripheral node 120, which are designed to process signals output or received via the I / O ports 129.The transmission lines 130 may include one or more conductors that couple the I / O ports 119 with the I / O ports 129, for example horizontal conductor tracks and / or vertical vias on or in a printed circuit board (PCB), connectors, cable harnesses, connectors, or other elements such as level converters, transceivers, isolation couplers such as inductive, capacitive or optical couplers, clocked storage elements, filters, I / O ports of other devices or the like that have coupled the I / O ports 119 with the I / O ports 129.

[0025] In some examples, signals communicated between the host node 110 and the peripheral node 120 may not be received at the same time as they are sent. For example, one or more of the I / O stages 118, 128, and / or a parasitic inductance or capacitance of a transmission line 130 coupling the host node 110 to the peripheral node 120 may impose a propagation delay 109 on signals communicated between the host node 110 and the peripheral node 120. As in Fig. As shown in Figure 3, a propagation delay 109A can be imposed on signals from the host node 110 to the one or more peripheral nodes 120, and a propagation delay 109B can be imposed on signals from the one or more peripheral nodes 120 to the host node 110. As shown in Fig. Figure 3 shows a "back-and-forth" propagation delay 109 that includes both delays 109A and 109B.

[0026] According to a non-restrictive example, a host node 110 can trigger the shifting out of an SDO bit (a MOSI bit) on the first shift clock edge of SCLK. Referring to the example of Fig. 3. The SCLK signal can pass through an output buffer 138 of the I / O output stage 118, the I / O port 119, transmission lines 130, the I / O port 129, and an input buffer 139 of the I / O stage 128 before arriving as the SCLK signal at the peripheral node 120. After receiving the shift clock edge (previously generated by the host node 110), the peripheral node 120 shifts out an SDO bit (a MISO bit). The SDO bit passes through an output buffer 138 of I / O stage 128, I / O port 129, transmission line 130, I / O port 119, and an input buffer 139 of input stage 118 before arriving at host node 120 as an SDI bit (a MISO bit). In some examples, the respective propagation delays 109A and 109B, which are described in Fig. As shown in Figure 1, the respective signals are similarly affected, thus imposing a delay of similar duration. In other examples, the respective propagation delays 109A and 109B may be different, i.e., have different durations.

[0027] In some examples, the collective propagation delay 109 imposed on signals communicated between the host node 110 and respective peripheral nodes 120 of the system 100 may be substantially similar, i.e., with a substantially similar delay imposed on signals to and from each respective node. In other examples, signals communicated through different nodes of a communication system 100 are affected by different propagation delays 109. For example, a greater propagation delay 109 may be imposed on signals that must travel over longer transmission lines 130 than on those that travel over shorter transmission lines 130. In some examples, the input and output capacities may differ between devices used in the system 100.In some examples, a peripheral node 120 may be constructed using a different technology than a host node 110, which may result in different propagation delays 109 mediated by one or more of the respective I / O stages 118, 128. In still other examples, a number of parallel inputs / outputs (where the host node 110 is, for example, coupled in parallel by multiple SDI / SDO signals) that couple the respective components of the system 100 may also contribute to one or more propagation delays 109 imposed on signals. In some examples, the nodes 120A-120C of a cascade topology may be affected by different propagation delays 109 depending on their position in the cascade (i.e., the number of nodes between a transmit node and the receive node of a signal).

[0028] According to a conventional communication system, such as those containing a Serial Peripheral Interface (SPI) communication protocol, nodes of the communication system communicate messages by alternately pushing in SDI bits and pushing out SDO bits, which are triggered by transitions, i.e. edges, in the shift clock SCLK, so that the pushing in of the SDI bit is separated from the pushing out of the SDO bit by a time difference that is essentially equal to a difference between the respective edges of the shift clock signal SCLK.In a conventional SPI communication system, the host node and peripheral nodes push SDI bits in and push SDO bits out in response to the same respective edges of the shift clock signal. The host node operates based on the SCLK signal as it is generated, and the one or more peripheral nodes operate based on the time at which the SCLK signal is received from the host node. For example, the host node triggers the outshift of an SDO bit in response to the first edge of the SCLK shift clock signal generated by the host controller, and the peripheral node similarly triggers the outshift of an SDO bit in response to the same first edge of the shift clock signal when it is received from the host node after being affected by the propagation delay 109A. The host node also triggers the inshift of an SDI bit (i.e.,The SDO bit, which was shifted out by the peripheral node in response to the first shift clock edge, is shifted in response to a second edge of the SCLK shift clock signal generated by the host controller. Similarly, the peripheral node triggers the insertion of an SDI bit in response to the same second shift clock edge of the SCLK shift clock signal when the second shift clock edge is received by the host node.

[0029] A propagation delay of 10⁹ in signals communicated between nodes can limit the speed at which a conventional serial communication system can operate. For example, if the propagation delay of 10⁹ has a duration close to or exceeding the time difference between the respective shift clock edges of the shift clock signal SCLK, a conventional host node may trigger an in-shift of an SDI bit (MISO bit) when the SDI bit has not yet changed or is still unstable (i.e., before the host node has received the current SDI bit, which has been shifted out by the peripheral node as an SDO bit). In some cases, this can result in corrupted data being communicated. Therefore, conventional serial communication systems may be designed to operate at frequencies low enough to accommodate the propagation delay of 10⁹.so that the time difference between shift clock edges is longer than the propagation delay 109).

[0030] As a non-restrictive example, a conventional serial data communication system may include a host node and / or peripheral nodes as devices with an input delay to received signals of approximately 5 nanoseconds (ns) and an output delay between 10 ns and 30 ns, depending on characteristics of the one or more input buffers, the one or more output buffers, and a driven load. According to this example, a signal propagation delay between the host node and the peripheral node may be in the range of 25 ns to 40 ns. Accordingly, such a conventional serial communication system may be designed to operate with a shift clock SCLK period of more than 100 nanoseconds, which may correspond to an overall bit rate limit of approximately 10 megahertz (MHz).

[0031] The in Fig. The system 100 shown is uniquely designed to enable high-speed serial data communication by minimizing the impact of propagation delays 109 on the system 100. According to various described examples, the host node 110, one or more peripheral nodes 120, or both are designed to switch between shifting in SDI bits and shifting out SDO bits based on the respective first and second edges of the shift clock signal SCLK, separated by a first time difference, and to trigger the shifting in of the SDI bits separately from the triggering of the shifting out of the SDO bits by a second time difference that is longer than the first time difference.In some examples, the second time difference has a duration chosen to be long enough to account for a propagation delay 109 (sum of 109A and 109B), which is applied as 109A to the shift clock signal SCLK and 109B to the SDO bits. For example, the second time difference can be chosen to account for the propagation delay 109, allowing SDI bits to be reliably shifted (i.e., sampled) at faster speeds (i.e., higher frequencies) of the shift clock signal SCLK. Accordingly, System 100 can be used to support communications for applications operating at relatively high speeds, for example, at shift clock frequencies of about 10 MHz. In some examples, System 100 can operate at speeds in the range of 10 to about 20 MHz.In other examples, the System 100 can be operated at speeds ranging from 10 to about 40 MHz.

[0032] In some examples, the system 100 includes a peripheral node 120 designed to trigger the insertion of SDI bits, separated from the triggering of the insertion of SDO bits by a second time difference longer than the first, as in the examples of Fig. 4A-4D and discussed in detail below. The first time difference corresponds to the time between the first SCLK edge and the following SCLK edge (as generated by host node 110 or as received by peripheral node 120). In other examples, a host node 110 is configured to communicate by triggering the in-shift of SDI bits, which is separated from the out-shift of SDO bits by a second time difference that is longer than the first, as in the examples of Fig. 5A and Fig. 5B and discussed in detail below. In other examples, the host node 110 is configured to trigger the insertion of SDI bits from the insertion of SDO bits by a second time difference, separate from the insertion of SDI bits, which is longer than the first time difference, and the one or more peripheral nodes 120 are also configured to trigger the insertion of SDI bits from the insertion of SDO bits by a second time difference, separate from the insertion of SDO bits, which is also longer than the first time difference, as in the examples of Fig. 6A and Fig. 6B and discussed in detail below. In other examples, the host node 110 and the peripheral node 120 are both designed to trigger the insertion of SDI bits from the insertion of SDO bits separately by a second time difference that is longer than the first, as in the examples of Fig. 6A and Fig. 6B and discussed in detail below. In other examples, a host node 110, a peripheral node 120, or both are designed to trigger both the insertion of SDI bits and the insertion of SDO bits such that the second time difference is longer than the first, as in Fig. 7A-7C described and discussed in more detail below.

[0033] Fig. Figure 4A is a timing diagram representing operations of a peripheral node 120 designed to trigger an in-slide of SDI bits by a second time difference separate from triggering the out-slide of SDO bits, according to some embodiments.

[0034] The example of Fig. Figure 4A shows operations of a host node 110 relative to a shift clock signal SCLK 240A generated by the host node 110, and operations of a peripheral node 120 relative to a shift clock signal SCLK 240B received by a peripheral node 120. Although in Fig. Not shown in 4A, the peripheral node 120 receives the shift clock signal SCLK 240B after being affected by a propagation delay 109A, as shown in Fig. Figure 3 shows how the shift clock signal SCLK 240B is received after it has been sent as the shift clock signal SCLK 240A. Although in Fig. Not shown in 4A, the host node 110 can receive an SDI bit (an SDO bit from the peripheral node 120) after being affected by a propagation delay 109B, as also shown in the example of Fig. 3 shown.

[0035] As in Fig. As shown in Figure 4A, the shift clock signal SCLK 240A, 240B includes a plurality of successive shift clock edges, including first shift clock edges 250A, 250B, which are separated from second shift clock edges 260A, 260B by a first time difference 230. As shown in Figure 4A, the shift clock signal SCLK 240A, 240B comprises a plurality of successive shift clock edges, including first shift clock edges 250A, 250B, which are separated from second shift clock edges 260A, 260B by a first time difference 230. Fig. As shown in Figure 4A, the shift clock signal SCLK 240A is generated by the host node 110 with first shift clock edges 250A, which are separated from the second shift clock edges 260A by a first time difference 230A of the shift clock signal SCLK 240A. As also shown in Fig. As shown in Figure 4A, the shift clock signal SCLK 240B is received by one or more peripheral nodes 120 with first shift clock edges 250B, which are separated from the second shift clock edges 260B by a first time difference 230B of the shift clock signal SCLK 240B. In some examples, where the propagation delay 109A affects the respective first 250B and second edges 260B differently, the first time difference 230A of the generated shift clock signal SCLK 240A may differ from the first time difference 230B of the received shift clock signal SCLK 240B. In other examples, the first time difference 230A may be essentially the same as the first time difference 230B.

[0036] In the example of Fig. 4A are the first shift edges 250A, 250B of a first type (a rising edge) and the second shift edges 260A, 260B of a second type, different from the first type (a falling edge), consecutively, with the second shift edges 260A, 260B immediately following the first shift edges 250A, 250B and the first shift edges 250A, 250B immediately following the second shift edges 260A, 260B. In other examples not shown, the first shift edges 250A, 250B can be falling edges and the second shift edges 260A, 260B can be rising edges.In other examples, the shift clock signal SCLK 240A, 240B can be defined differently, for example, where the first shift clock edges 250A, 250B and the second shift clock edges 260A, 260B are both of the same type (successive rising edges or successive falling edges) and / or are separated from each other by other edges, by the first time difference 230A, 230B.

[0037] According to the example of Fig. In 4A, both the host node 110 and the peripheral node 120 are configured to switch between shifting out SDO bits and shifting in SDI bits based on the respective shift clock edges 250A, 250B and 260A, 260B. As shown by the received shift clock signal SCLK 240A, the host node 110 is configured to operate according to conventional serial communication in response to the shift clock signal SCLK 240A generated by the host node 110, shifting out SDO bits in response to the first shift clock edges 250A and shifting in SDI bits in response to the second shift clock edges 260A, so that the triggering of the SDO bits' shifting out is separated from the triggering of the SDI bits' shifting in by the first time difference 230A.

[0038] The example of Fig. Figure 4A shows an N-1 and an N-2 bit being communicated between host node 110 and peripheral node 120. In some examples, one or more bits (i.e., an N-th or a first bit) may have been communicated previously, either as shown or in response to a CS signal change state.

[0039] As in Fig. As shown in Figure 4A, host node 110 pushes out an SDO bit N-1 in response to the first shift clock edge 250A of the generated shift clock signal SCLK 240A (i.e., upon receiving this and / or essentially at the same time as it) and pushes in an SDI bit N-1 in response to a second shift clock edge 260A. Host node 110 also pushes out an SDO bit N-2 in response to a subsequent first shift clock edge 250A and pushes in an SDI bit N-2 in response to a subsequent second shift clock edge 260A. As in the example of Fig. As shown in Figure 4A, the host node 110 triggers the outshifting of SDO bits at the first time difference 230A separate from the time at which the host node 110 triggers the inshifting of SDI bits.

[0040] According to the example of Fig. 4A The peripheral node 120 is designed to operate differently from the host node 110, such that the peripheral node 120 triggers the shifting of an SDI bit from the time at which the peripheral node 120 triggers the shifting out of an SDO bit by a second time difference 232, which is longer than the first time difference 230B. With reference to the received shift clock signal SCLK 240B, which is in Fig. As shown in Figure 4A, peripheral node 120 does not push the SDI bits in as a direct response to the second shift clock edge 260B. Instead, peripheral node 120 pushes the SDI bits in separately from the triggering of the SDO bits' push-out (and separate from the first shift clock edge 250B) by the second time difference 232, which is longer than the first time difference 230B.

[0041] According to the example of Fig. 4A triggers peripheral node 120 to shift the SDI bits in at a time after the second shift clock edge 260B. For example, as in Fig. As shown in Figure 4A, the peripheral node 120 triggers the insertion of the SDI bits after applying a known delay 272 in response to the second shift clock edges 260B. In some examples, the peripheral node 120 is configured to apply the known delay 272 with a duration selected to accommodate a propagation delay 109A imposed on signals transmitted from the host node 110 to the peripheral node 120, and / or 109B imposed on signals transmitted from the peripheral node 120 to the host node 110, as shown in Figure 4A. Fig. Figure 3 shows. For example, the known delay 272 can be selected such that, if a frequency of the shift clock signal SCLK 240A, 240B is relative to the diagram in Fig. 4A is increased (i.e., the first time difference 230A, 230B is reduced), SDI bits are pushed in from peripheral node 120 at a time when the SDI bits are stable.

[0042] As in Fig. As shown in Figure 4A, peripheral node 120 shifts out an SDO bit N-1 in response to the first shift clock edge 250A. In response to the second shift clock edge 260A, peripheral node 120 applies the known delay 272 and shifts in the SDI bit N-1 after applying the known delay 272. Peripheral node 120 then shifts out another SDO bit N-2 in response to the first shift clock edge 250A and triggers the insertion of an SDI bit N-2 after applying the known delay 272, so that the SDI bit N-2 is inserted separately from the shift out of SDO bit 1 by the second time difference 232.

[0043] Fig. Figure 4B is a timing diagram representing operations of a peripheral node 120 designed to trigger the insertion of SDI bits by a second time difference 234 with a duration substantially equal to or slightly shorter than a full period 290 of the shift clock signal SCLK 240A, 240B, i.e., a difference between two edges of the same type (e.g., successive edges 250A, successive edges 260A), according to some embodiments. As the example of Fig. 4A shows Fig. 4B Operations of a host node 110 relative to a shift clock signal SCLK 240A generated by the host node 110, and operations of a peripheral node 120 relative to a shift clock signal SCLK 240B received by a peripheral node 120.

[0044] In the example of Fig. 4B The host node 110 operates according to traditional serial communication protocols and alternates between shifting SDI bits in and shifting SDO bits out in response to the first and second shift clock edges 250A, 260A, such that the triggering of an SDI bit shift in is separated from the triggering of an SDO bit shift out by the first time difference 230A. The example of Fig. 4B differs from the example from Fig. 4A by the peripheral node 120 triggering the insertion of the SDI bits separately from the triggering of the removal of the SDO bits (and separate from the first shift clock edge 250B) by a second time difference 234, which is longer than the second time difference 232, which is in Fig. 4A is shown.

[0045] In particular, in the example of Fig. 4B the second time difference 234 is selected such that it is essentially equal to or nearly as long as a full period 290 of the shift clock signal SCLK 240A (e.g., essentially twice or nearly twice as long as the first time difference 230A). According to these examples, the peripheral node 120 applies a known delay 274 with a duration essentially equal to the first time difference 230B after the second shift clock edges 260A. As also in Fig. As shown in Figure 4B, where the second time difference 234 is essentially equal to or nearly equal to a full period 290 of the shift clock signal SCLK 240A, the peripheral node 120 can trigger a shift-in of a current SDI bit (e.g., SDI bit N-1) at essentially the same time as, or immediately after, triggering a shift-out of the next SDO bit (e.g., SDI bit N-2) (i.e., aligned with the first shift clock edges 250A). In this way, by applying the known delay 274, the peripheral node 120 extends the shift-in of an SDI data bit to the next first shift clock edge 250A, which can represent a maximum delay that can be applied.

[0046] Fig. Figure 4C is a timing diagram representing operations of a peripheral node 120 designed to trigger the insertion of SDI bits by a second time difference 233 separate from the triggering of the insertion of SDO bits, according to some embodiments. As the example of Fig. 4A shows Fig. 4C Operations of a host node 110 relative to a shift clock signal SCLK 240A generated by the host node 110, and operations of a peripheral node 120 relative to a shift clock signal SCLK 240B received by a peripheral node 120.

[0047] As shown by the generated shift clock signal SCLK 240A, the host node 110 in the example of Fig. 4C is designed to operate according to conventional serial communication protocols, as described above with reference to Fig. 4A described. According to the example of Fig. 4C, the peripheral node 120 is designed to operate differently from the host node 110, such that the peripheral node 120 pushes in SDI bits, which is separated from the push-out of SDO bits by a second time difference 233, which is longer than the first time difference 230. Referring to the received shift clock signal SCLK 240B, which is in Fig. As shown in Figure 4C, peripheral node 120 does not trigger the SDO bit shifting directly in response to the first shift clock edge 250B. Instead, peripheral node 120 triggers the SDO bit shifting separately from the SDI bit shifting (and the first shift clock edge 250B) by the second time difference 233, which is longer than the first time difference 230. Peripheral node 120 can trigger the SDO bit shifting at a predetermined time 282 before the first shift clock edges 250B, for example, after applying a known delay 276 in response to the second shift clock edges 260B or another clock edge (e.g., an edge of a CS signal) before triggering the SDO bit shifting.In some examples, the peripheral node 120 is configured to apply the known delay 276 to accommodate a propagation delay 109A, 109B imposed on signals transmitted between the peripheral node 120 and the host node 110. For example, the known delay 276 can be selected such that if the frequency of the shift clock signal SCLK 240A, 240B is increased (i.e., the first time difference 230A, 230B is reduced), SDI bits are shifted in at a time when the SDI bits are stable.

[0048] As in Fig. As shown in Figure 4C, peripheral node 120 shifts an SDO bit N-1 out at a predetermined time 282 before the shift clock edge 250B. In response to a shift clock edge 260B, peripheral node 120 shifts the SDI bit N-1 in. In response to the shift clock edge 260B, peripheral node 120 applies the known delay 276 and shifts the SDO bit N-2 out after applying the known delay 276. Peripheral node 120 then shifts an SDI bit N-2 in response to the shift clock edge 260B and shifts an SDO bit N-2 out after applying the known delay 276.

[0049] Fig. 4D is a timing diagram representing operations of a peripheral node 120 designed to trigger the insertion of SDI bits separated by a second time difference 235, which is substantially equal to or nearly as long as a full period 290 of the shift clock signal SCLK 240A, 240B, according to some embodiments. As the examples of Fig. 4A-4C shows Fig. 4D operations of a host node 110 relative to a shift clock signal SCLK 240A generated by the host node 110, and operations of a peripheral node 120 relative to a shift clock signal SCLK 240B received by a peripheral node 120.

[0050] In the example of Fig. In 4D, the host node 110 and the peripheral node 120 operate similarly to the one in Fig. Example shown in 4C. The example of Fig. 4D differs from the example from Fig. 4C by the fact that the peripheral node 120 triggers the outshifting of the SDO bit from the inshifting of the SDI bit by a second time difference 235, which is longer than the second time difference 233, which is in Fig. 4C is shown. Following the example of Fig. 4D, the second time difference 235 is essentially equal to or nearly as long as a full period 290 of the shift clock signal SCLK 240B. According to these examples, the peripheral node 120 triggers an in-shift of the SDI bit at a predetermined time 284 before the first shift clock edges 250B, for example by applying a known delay 278 (i.e., a known delay = 0 or slightly greater than 0) after the second shift clock edges 260B, before triggering an out-shift of an SDO bit. As also in Fig. As shown in Figure 4D, where the second time difference 235 is essentially equal to or nearly as long as the shift clock period 290, the peripheral node 120 triggers the shift-out of a current SDO bit (e.g., SDI bit 1) essentially at the same time as, or immediately after, the shift-in of a previous SDI bit (e.g., SDI bit 0) (i.e., aligned with the second shift clock edge 260B). In this way, the peripheral node 120 extends the shift-out of an SDO data bit to a previous second shift clock edge 260B, which can represent a minimum known delay 278 that can be applied.

[0051] Fig. Figure 5A is a timing diagram representing operations of a host node 110 designed to trigger the insertion of SDI bits by a second time difference 233 separate from the triggering of the insertion of SDO bits, according to some embodiments. As the example of Fig. 4A-4D shows Fig. 5A Operations of a host node 110 relative to a shift clock signal SCLK 240A generated by the host node 110, and operations of a peripheral node 120 relative to a shift clock signal SCLK 240B received by a peripheral node 120.

[0052] As shown by the received shift clock signal SCLK 240B, the peripheral node 120 in the example of Fig. 5A is designed to operate according to conventional serial communication, shifting SDO bits out in response to the first shift clock edges at 250B and shifting SDO bits in response to the second shift clock edges at 260B, so that the peripheral node shifts out 120 SDO bits, separated from the shift in SDI bits by the first time difference of 230B. As in Fig. As shown in Figure 5A, peripheral node 120 pushes out an SDO bit N1 in response to the first shift clock edge 250 of the shift clock signal SCLK 240B (i.e., upon receiving this and / or essentially at the same time as it) and pushes in an SDI bit N-1 in response to a second shift clock edge 260B. Subsequently, peripheral node 120 pushes out an SDO bit N-2 in response to a subsequent first shift clock edge 250A and pushes in an SDI bit N in response to a subsequent second shift clock edge 260B.

[0053] According to the example of Fig. 5A, the host node 110 is designed to operate differently from the peripheral node 120, such that the host node 110 shifts SDI bits in, which is separated from the shifting out of SDO bits by a second time difference 233, which is longer than the first time difference 230A. Referring to the generated shift clock signal SCLK 240A, which is in Fig. As shown in Figure 5A, host node 120 does not trigger the SDO bit shift directly in response to the first shift clock edge 250A. Instead, host node 110 triggers the SDO bit shift separately from the SDI bit shift (and the first shift clock edge 250A) by the second time difference 233, which is longer than the first time difference 230A. Host node 110 can trigger the SDO bit shift at a predetermined time 282 before the first shift clock edges 250A, for example, after applying a known delay 276 in response to the second shift clock edges 260A, before the SDO bit shift is triggered. In some examples, the host node 110 is designed to apply a known delay 276 to account for propagation delays 109A, 109B imposed on signals transmitted between the peripheral node 120 and the host node 110.For example, the known delay 276 can be selected such that when a frequency of the shift clock signal SCLK 240A, 240B is increased (i.e., the first time difference 230A, 230B is reduced), SDI bits are shifted in at a time when the SDI bits are stable.

[0054] As in Fig. As shown in Figure 5A, host node 110 shifts an SDO bit N-1 out at a predetermined time 282 before the shift clock edge 250A. In response to a shift clock edge 260A, host node 110 shifts the SDI bit N-1 in. In response to the shift clock edge 260A (or another signal edge, such as a CS signal edge), host node 110 applies the known delay 276 and shifts the SDO bit N-2 out after applying the known delay 276. Host node 110 then shifts an SDI bit N-2 in response to the shift clock edge 260A and shifts an SDO bit N-2 out after applying the known delay 276.

[0055] Fig. Figure 5B is a timing diagram representing operations of a host node 110 designed to trigger the insertion of SDI bits separated by a second time difference 235, which is substantially equal to or nearly as long as a full period 290 of the shift clock signal SCLK 240A, 240B, according to some embodiments. As the example of Fig. 5A shows Fig. 5B Operations of a host node 110 relative to a shift clock signal SCLK 240A generated by the host node 110, and operations of a peripheral node 120 relative to a shift clock signal SCLK 240B received by a peripheral node 120.

[0056] In the example of Fig. 5B The host node 110 and the peripheral node 120 operate similarly to the one in Fig. Example 5A shown. The example of Fig. 5B differs from the example from Fig. 5A by the fact that the host node 110 triggers the outshifting of the SDO bit from the inshifting of the SDI bit by a second time difference 235, which is longer than the second time difference 233, which is in Fig. 5A is shown. Following the example of Fig. 5B, the second time difference 235 is essentially equal to or nearly as long as a full period 290 of the shift clock signal SCLK 240A. According to these examples, the host node 110 triggers an in-shift of the SDI bit at a predetermined time 284 before the first shift clock edges 250B, for example by applying a known delay 278 (i.e., a known delay = 0 or slightly greater than 0) after the first shift clock edges 250B, before triggering an out-shift of an SDO bit. As also in Fig. As shown in Figure 5B, where the second time difference 235 is essentially equal to or nearly as long as the shift clock period 290, the host node 110 triggers the shift-out of a current SDO bit (e.g., SDI bit 1) at essentially the same time as, or shortly after, the shift-in of a previous SDI bit (e.g., SDI bit 0) (i.e., aligned with the second shift clock edge 260A). In this way, the host node 110 extends the shift-out of an SDO data bit to a previous second shift clock edge 260B, which can represent the largest possible minimum known delay that can be applied.

[0057] Fig. Figure 6A is a timing diagram showing a shift clock signal SCLK 240A generated by a host node 110 and a shift clock signal SCLK 240B received by a peripheral node 120, according to some embodiments. As the examples of Fig. 4A-4D and 5A-5B, described above, are the host node 110 and the peripheral node 120 designed to shift SDI bits in and shift SDO bits out based on shift clock signals SCLK 240A, 240B, which include a plurality of successive first shift clock edges 250A, 250B and a plurality of second shift clock edges 260A, 260B, separated by a first time difference 230A, 230B.

[0058] According to the example of Fig. In 6A, both the host node 110 and the peripheral node 120 are designed to operate differently than according to a conventional serial communication protocol. As in Fig. As shown in Figure 6A, the host node 110 triggers an in-shift of SDI bits from the time at which the host node 110 triggers an out-shift of SDO bits by a second time difference 232, which is longer than the first time difference 230A, for example by applying a known delay 272 after the second shift clock edge 260A before the in-shift of the SDI bit, as above with reference to the example of Fig. 4A described. Additionally, as also in Fig. As shown in Figure 6A, the peripheral node 120 triggers the insertion of the SDI bits from the time at which the peripheral node 120 triggers the insertion of the SDO bits, separated by a second time difference 233 which is greater than the first time difference 230B, for example by insertion of the SDO bits at a predetermined time 282 before the first shift clock edges 250B, for example by applying a known delay 276 in response to the second shift clock edges 260B before insertion of the SDO bits.

[0059] According to the example of Fig. 6A, both the host node 110 and the peripheral node 120 are operable to trigger the insertion of SDI bits from the triggering of the insertion of SDO bits by a second time difference 232, 233, both of which are greater than the respective first time differences 230A, 230B. In some examples, the host node 110 and the peripheral node 120 are configured to apply the respective second time differences 232, 233 to account for propagation delays 109A, 109B imposed on signals between the host node 110 and the peripheral node 120, for example, when the sum of the propagation delays 109A, 109B is greater than the first time difference 230A. For example, the known delays 272, 276 can be selected such that when a frequency of the shift clock signal SCLK 240A, 240B is increased (i.e., the first time differences 230A, 230B are reduced), SDI bits are inserted at a time when the SDI bits are stable.

[0060] Fig. Figure 6B is a timing diagram showing a shift clock signal SCLK 240A generated by a host node 110 and a shift clock signal SCLK 240B received by a peripheral node 120, according to some embodiments. As the examples of Fig. 4A-4D, 5A-5B and 6A, which are described above, are the host node 110 and the peripheral node 120 designed to shift SDI bits in and shift SDO bits out based on shift clock signals SCLK 240A, 240B, which include a plurality of successive first shift clock edges 250A, 250B and a plurality of second shift clock edges 260A, 260B, which are separated from each other by a first time difference 230A, 230B.

[0061] According to the example of Fig. In version 6B, both the host node 110 and the peripheral node 120 are designed to operate differently than according to a conventional serial communication protocol. As in Fig. As shown in Figure 6B, peripheral node 120 triggers an in-shift of SDI bits from the time at which peripheral node 120 triggers an out-shift of SDO bits by a second time difference 232, which is longer than the first time difference 230B, for example by applying a known delay 272 after the second shift clock edge 260B before the in-shift of the SDI bit. Additionally, as also shown in Fig. As shown in Figure 6B, the host node 110 triggers the insertion of the SDI bits from the time at which the host node 110 triggers the insertion of the SDO bits by a second time difference 233, which is larger than the first time difference 230A, for example by insertion of the SDO bits at a predetermined time 282 before the first shift clock edges 250A, such as by applying a known delay 276 in response to the second shift clock edges 260A before insertion of the SDO bits.

[0062] According to the example of Fig. 6B, both the host node 110 and the peripheral node 120 can be operated to trigger the insertion of SDI bits from the triggering of the insertion of SDO bits separately by respective second time differences 232, 233, both of which are larger than the respective first time differences 230A, 230B.

[0063] Fig. Figure 7A is a timing diagram showing a shift clock signal SCLK 240A generated by a host node 110 and a shift clock signal SCLK 240B received by a peripheral node 120, according to some embodiments. As the examples of Fig. 4A-4D, 5A-5B and 6A-6B, described above, are the host node 110 and the peripheral node 120 designed to shift SDI bits in and shift SDO bits out based on shift clock signals SCLK 240A, 240B, which include a plurality of successive first shift clock edges 250A, 250B and a plurality of second shift clock edges 260A, 260B, separated by a first time difference 230A, 230B.

[0064] As shown by the received shift clock signal SCLK 240B, the peripheral node 120 in the example of Fig. 5A is designed to operate according to conventional serial communications, pushing SDO bits out in response to the first shift clock edges 250B and pushing SDO bits in in response to the second shift clock edges 260B, so that the peripheral node pushes out 120 SDO bits, separated from the pushing in of the SDI bits by the first time difference 230B.

[0065] According to the example of Fig. 7A, the host node 110, is designed to operate differently than according to a conventional serial communication protocol. According to the example of Fig. 7A, the host node 110 triggers an inward shift of SDI bits from the time at which the host node 110 triggers an outward shift of SDO bits, separated by a second time difference 236, which is longer than the first time difference 230A, by changing when the host node 110 outshifts SDO bits relative to the first shift clock edges 250A and when the host node 110 inshifts the SDI bits relative to the second shift clock edges 260A. For example, as in Fig. As shown in Figure 7A, the host node 110 triggers the insertion of the SDI bits after applying a known delay 272 following the second shift clock edge 260A. Additionally, as also shown in Fig. As shown in Figure 7A, the host node 110 triggers a shift of SDO bits at a predetermined time 282 before the first shift clock edges 250A, for example by applying a known delay 276 after the second shift clock edge 260A (or another signal edge, such as a CS signal edge). In some examples, the host node 110 and the peripheral node 120 are configured to apply their respective second time difference 236 to account for propagation delays 109 imposed on signals between the host node 110 and the peripheral node 120, for example, when the propagation delay 109 is greater than the first time differences 230A, 230B. For example, the known delays 272, 276 can be selected such that when a frequency of the shift clock signal SCLK 240A, 240B is increased (i.e., the first time differences 230A, 230B are reduced), SDI bits are inserted at a time when the SDI bits are stable.

[0066] Fig. Figure 7B is a timing diagram showing a shift clock signal SCLK 240A generated by a host node 110 and a shift clock signal SCLK 240B received by a peripheral node 120, according to some embodiments. As the examples of Fig. 4A-4D, 5A-5B and 6A-6B and 7A, which are described above, are the host node 110 and the peripheral node 120 designed to trigger the in-shift of SDI bits and the out-shift of SDO bits based on shift clock signals SCLK 240A, 240B, which include a plurality of successive first shift clock edges 250A, 250B and a plurality of second shift clock edges 260A, 260B, which are separated from each other by a first time difference 230A, 230B.

[0067] As shown by the generated shift clock signal SCLK 240A, the host node 110 in the example of Fig. 7B is designed to operate according to conventional serial communications, pushing SDO bits out in response to the first shift clock edges 250A and pushing SDO bits in response to the second shift clock edges 260A, so that the host node pushes out 110 SDO bits, which are separated from the pushing in of the SDI bits by the first time difference 230A.

[0068] According to the example of Fig. 7B, the peripheral node 120, is designed to operate differently than according to a conventional serial communication protocol. According to the example of Fig. At 7B, peripheral node 120 triggers an inward shift of SDI bits from the time at which peripheral node 120 triggers an outward shift of SDO bits, separated by a second time difference 238, which is longer than the first time difference 230B, by changing when peripheral node 120 outshifts SDO bits relative to the first shift clock edges 250B and when peripheral node 120 inshifts the SDI bits relative to the second shift clock edges 260B. For example, as in Fig. As shown in Figure 7B, the peripheral node 120 triggers the insertion of the SDI bits after applying a known delay 272 following the second shift clock edge 260B. Additionally, as also shown in Fig. As shown in Figure 7B, the peripheral node 120 triggers a shift of SDO bits at a predetermined time 282 before the first shift clock edges 250B, for example by applying a known delay 276 after the second shift clock edges 260B. In some examples, the host node 110 and the peripheral node 120 are configured to apply their respective second time difference 238 to account for propagation delays 109 imposed on signals between the host node 110 and the peripheral node 120, for example, when the propagation delay 109 is greater than the first time differences 230A, 230B. For example, the known delays 272, 276 can be selected such that when a frequency of the shift clock signal SCLK 240A, 240B is increased (i.e., the first time differences 230A, 230B are reduced), SDI bits are shifted in at a time when the SDI bits are stable.

[0069] Fig. Figure 7C is a timing diagram showing a shift clock signal SCLK 240A generated by a host node 110 and a shift clock signal SCLK 240B received by a peripheral node 120, according to some embodiments. As the examples of Fig. 4A-4D, 5A-5B, 6A-6B, and 7A-7B, as described above, are the host node 110 and the peripheral node 120 designed to trigger the in-shift of SDI bits and the out-shift of SDO bits based on shift clock signals SCLK 240A, 240B, which include a plurality of successive first shift clock edges 250A, 250B and a plurality of second shift clock edges 260A, 260B, separated by a first time difference 230A, 230B.

[0070] According to the example of Fig. In the 7C, both the host node 110 and the peripheral node 120 are designed to operate differently than according to a conventional serial communication protocol. According to the example of Fig. 7C, both the host node 110 and the peripheral node 120 are designed to adapt when they trigger the insertion of SDI bits and the insertion of SDO bits relative to the respective first and second edges 250A-250B, 260A, 260B. According to the example of Fig. 7B, the peripheral node 120 triggers an inward shift of SDI bits from the time at which the peripheral node 120 triggers an outward shift of SDO bits, separated by a second time difference 238, which is longer than the first time difference 230B, by changing when the peripheral node 120 outward shifts SDO bits relative to the first shift clock edges 250B and when the peripheral node 120 inward shifts the SDI bits relative to the second shift clock edges 260B.

[0071] As in Fig. As shown in Figure 7C, the host node 110 triggers an inward shift of SDI bits from the time at which the host node 110 triggers an outward shift of SDO bits by a second time difference 236, which is longer than the first time difference 230A, for example by triggering the inward shift of SDI bits after applying a known delay 272 after the second shift clock edge 260A. Additionally, the host node 110 triggers an outward shift of SDO bits at a predetermined time 282 before the first shift clock edges 250A, for example by applying a known delay 276 after the second shift clock edges 260A.

[0072] As in Fig. As shown in Figure 7C, the peripheral node 120 triggers an in-shift of SDI bits from the time at which the peripheral node 120 triggers an out-shift of SDO bits by a second time difference 238, which is longer than the first time difference 230B, for example by triggering the in-shift of SDI bits after applying a known delay 272 after the second shift clock edge 260A. Additionally, the peripheral node 120 triggers the out-shift of SDO bits at a predetermined time 282 before the first shift clock edges 250B, for example by applying a known delay 276 after the second shift clock edges 260B.In some examples, the host node 110 and the peripheral node 120 are configured to apply their respective second time differences 236, 238 to accommodate propagation delays 109 imposed on signals between the host node 110 and the peripheral node 120, for example, when the propagation delay 109 is greater than the first time differences 230A, 230B. For example, the known delays 272, 276 can be selected such that if the frequency of the shift clock signal SCLK 240A, 240B is increased (i.e., the first time differences 230A, 230B are reduced), SDI bits are shifted in at a time when the SDI bits are stable.

[0073] In some examples, a communication system 100 can be configured such that a host node 110, one or more peripheral nodes 120, or both are configured to push SDI bits in through a second time difference 232, 233, 234, 235, 236, 238, separate from triggering the out-pull of SDO bits. In some examples, the same second time difference 232, 233, 234, 235, 236, 238 is used across the host node 110 and / or one or more respective peripheral nodes 120 to, for example, accommodate a longest total propagation delay 109A plus 109B in communicated signals. In other examples, the host node 110 and / or one or more peripheral nodes 120 can use different second time differences 232, 233, 234, 235, 236, 238 to communicate with different peripheral nodes 120.

[0074] In the examples of Fig. In examples 4A-4D, 5A-5B, 6A-6B, and 7A-7C, the respective delays 272, 274, 276, and 278 applied by peripheral node 120 and / or host node 110 are shown. In some examples, when applied by host node 110, the respective delays 272, 274, 276, and 278 may be substantially similar. In other examples, the respective delays 272, 274, 276, and 278 may differ when applied by host node 110 compared to when applied by peripheral node 120.

[0075] Fig. 8A and Fig. Figure 8B are timing diagrams showing a peripheral node 120 of the system 100, which is designed to communicate using a Serial Peripheral Interface (SPI) protocol, according to some embodiments. The examples of Fig. 8A and Fig. 8B corresponds to the example of Fig. 4A, applied to a peripheral node 120 which is coupled to a host node 110 by chip selection, SCLK, MOSI and MISO signals according to a communication topology as in the example of Fig. Figure 1 shows that if the topology is an ideal star topology, the delay 272 can be extended to a maximum of the first time difference 230, i.e., essentially equal to or nearly equal to a first time period 230A, 230B. In a real-world application with parasitic effects influencing the propagation delays of the SCLK, MISO, and MOSI signals, in some examples not all signals and edges may propagate symmetrically to each other. Accordingly, one signal or edge may propagate faster or slower than another. In particular, in a series topology, asymmetrical propagation delays may occur. Consequently, the known delay 272 can be chosen to be shorter than the first time difference 230B.

[0076] From the perspective of peripheral node 120, the following correspond to the values ​​in Fig. 8A and Fig. The MOSI bits shown in 8B correspond to the SDI bits, which are shown in Fig. 4A and Fig. 4B is referenced. From the perspective of peripheral node 120, the following correspond to those in Fig. The MISO bits shown in 8A correspond to the SDO bits, which are referenced in Fig. 4A and Fig. Reference is made to 4B.

[0077] According to the example of Fig. 8A and Fig. 8B is the peripheral node 120 designed to alternate between shifting MOSI bits in and shifting MISO bits out based on a shift clock signal SCLK 240A which includes a plurality of successive first shift clock edges 250 separated from a plurality of second shift clock edges 260 by a first time difference 230B.

[0078] In the example of Fig. 8A, the peripheral node 120 is configured to operate with a CPHA = 1 setting, according to which the peripheral node 120 begins to communicate by pushing out undefined data when the CS signal becomes active, pushing out a first bit N in response to a first shift clock signal edge 250, and pushing in a first bit N with a second shift clock signal edge 260, continuing to alternate between pushing out and pushing in bits until a final bit 0 is pushed in and out. In the example of Fig. In 8B, the peripheral node 120 operates with the setting CPHA = 0, according to which the peripheral node 120 begins to communicate a message by shifting out bit N in response to the CS signal being activated and traditionally shifting in bit N in response to a first shift clock signal edge 250, and continuing to alternate between shifting out and shifting in bits until a final bit 0 is shifted in and out.

[0079] In the examples of Fig. 8A and Fig. In example 8B, peripheral node 120 is configured to operate with a CPOL setting of 0, whereby the first shift clock edges (250) are rising edges of the shift clock signal SCLK, and the second shift clock edges (260) are falling edges of the shift clock signal SCLK. In other examples, peripheral node 120 is configured to operate with a CPOL setting of 1, whereby the first shift clock edges (250) are falling edges of the shift clock signal SCLK, and the second shift clock edges (260) are rising edges of the shift clock signal SCLK.

[0080] According to the example of Fig. 8A and Fig. 8B is designed to be the peripheral node 120, similar to the example from Fig. 4A to operate and shift MOSI bits (SDI bits) in from the shifting out of MISO bits (SDO bits) by a second time difference 234, which is longer than the first time difference 230B, substantially equal to or slightly less than a full period 290 of the shift clock signal SCLK 240B (e.g., about twice the first time difference 230B). As in Fig. 8A and Fig. As shown in Figure 8B, the peripheral node 120 is designed to trigger a MOSI bit push-in at a different time than a push-in is triggered for a conventional peripheral node 120. To push the MOSI bits in by the second time difference 234 separate from the push-out of MISO bits, as shown, the peripheral node 120 applies a known delay 272 in response to the shift clock edges triggering the MOSI bit push-in (second shift clock edges 260 in Fig. 8A, first shift clock edges in Fig. 8B) with a duration that is essentially the same as or nearly as long as the initial time difference 230B, as in the example of Fig. 4A shows that the MISO bits are shifted out by the second time difference 234, separate from the insertion of the MOSI bits.

[0081] In some examples, delaying the outshift of MISO bits (SDO bits) by the known delay 272 causes the peripheral node 120 to trigger the outshift of a current MISO bit simultaneously with or immediately after the inshift of a previous MOSI bit, e.g., essentially at the same time as, or shortly after, the first shift clock edges 250 (for CPHA=0) or the second shift clock edges 260 (for CPHA=1). For example, as in Fig. 8A and Fig. As shown in Figure 8B, peripheral node 120 pushes out a MISO bit N-1 almost simultaneously with triggering the insertion of a MOSI bit N, pushes out a MISO bit N-2 almost simultaneously with the insertion of a MOSI bit N-1, and so on, until peripheral node 120 pushes out a MISO bit 0 simultaneously with the insertion of a MOSI bit 1, and inserts a MOSI bit 0 at one end of the message.

[0082] Fig. 9A and Fig. Figure 9B are timing diagrams showing a communication node (i.e., a peripheral node 120 or a host node 110) of the system 100, which is designed to communicate using a Serial Peripheral Interface (SPI) protocol, according to some embodiments. The example of Fig. 9A corresponds to the example of Fig. 4C and Fig. 5A. If the communication node is a peripheral node 120, the following apply: Fig. 9A and Fig. The out-shifted bits shown in 9B are MISO / SDO bits, and the in-shifted bits correspond to MOSI / SDI bits, which are shown in Fig. Reference is made to sections 4A-4D. If the communication node is a host node 110, the following applies: Fig. 9A and Fig. The out-shifted bits shown in 9B are MOSI / SDO bits, and the in-shifted bits correspond to MISO / SDI bits, which are shown in Fig. 5A and Fig. Reference is made to 5B.

[0083] According to the example of Fig. 9A and Fig. 9B is the communication node designed to alternate between shifting bits out and shifting bits in based on a shift clock signal SCLK 240A, 240B which includes a plurality of successive first shift clock edges 250 separated from a plurality of second shift clock edges 260 by a first time difference 230.

[0084] In the example of Fig. 9A, the communication node is configured to operate with a CPHA = 1 setting, according to which the communication node begins communicating by shifting out undefined data when the CS signal becomes active, shifting out a first bit N in response to a first shift clock signal edge 250, and shifting in a first bit N with a second shift clock signal edge 260, continuing to alternate between shifting out and in until a final bit 0 is shifted out and in. In the example of Fig. 9B the communication node operates with the setting CPHA = 0, according to which the communication node begins to communicate a message by shifting out bit N in response to the CS signal being activated and traditionally shifting in bit N in response to a first shift clock signal edge 250 and continuing to alternate between shifting out and shifting in bits until a final bit 0 is shifted out and in.

[0085] In one example, peripheral node 120 can trigger the shifting out of an SDO bit before the conventional shift clock edge, such as the second shift clock edge 260 (with CPHA=0, see 9B) or the first shift clock edge 250 (with CPHA=1, see 9A). The earlier shifting out of an SDO bit compared to the conventional shift clock edge can mean that a reference edge occurs earlier than the conventional shift clock edge as a trigger for shifting out an SDO bit. For the first SDO bit (bit N), this trigger can be the activation of the CS signal. For other SDO bits after the first SDO bit N (e.g., bits N-1 to 0 in the examples of Fig. 9A and Fig. 9B) This trigger can be a previous first shift clock edge 250 or a previous second shift clock edge 260. In an ideal example, the shifting out of an SDO bit can be triggered in response to a previous second shift clock edge 260. In some examples, due to asymmetric propagation delays (e.g., due to parasitic effects), a known delay 272, 276 after a previous event (a CS signal edge, a first shift clock edge 250, a second shift clock edge 260) can be applied before an SDO bit is shifted out.

[0086] In the example of Fig. 9A and Fig. In example 9B, the communication node is configured to operate with a CPOL setting of 0, whereby the first shift clock edges are rising edges of the shift clock signal SCLK 240A, 240B, and the second shift clock edges are falling edges of the shift clock signal SCLK 240A, 240B. In other examples, the communication node is configured to operate with a CPOL setting of 1, whereby the first shift clock edges are falling edges of the shift clock signal SCLK 240A, 240B, and the second shift clock edges are rising edges of the shift clock signal SCLK 240A, 240B. In the example of Fig. 9A, Fig. 9B shifts out a first SDI bit N in response to the activation of the CS signal.

[0087] According to the example of Fig. 9A is the communication node designed to function similarly to the examples of Fig. 4C and Fig. 5A to operate and shift SDO bits out of the shift in SDI bits separated by a second time difference 235, which is longer than the first time difference 230A, 230B, and specifically substantially equal to or nearly as long as a full period 290 of the shift clock signal SCLK 240A, 240B (e.g., about twice, almost twice, the first time difference 230 if the SCLK signal is symmetrical) in the example of Fig. 9A. To shift SDO bits out separately from the shifting of SDI bits by a second time difference 235, as shown, the communication node can apply a known delay 276 so that the SDI bits are shifted out by the second time difference 235 separately from the shifting of the SDO bits (at a predetermined time 282 before the first shift clock edges 250).

[0088] As in the example of Fig. 9A and Fig. As shown in Figure 9B, the communication node is designed to shift out a current SDO bit at substantially the same time as shifting in a previous SDI bit, e.g., at substantially the same time as, or slightly before, the first shift clock edges 250 or the second shift clock edges 260. For example, as shown in Fig. 9A and Fig. As shown in Figure 9B, the communication node pushes out an SDO bit N-1 at approximately the same time as it pushes in an SDI bit N-2, pushes out an SDO bit N-2 at approximately the same time as it pushes in an SDI bit N-1, and so on, until the communication node pushes out an SDO bit 0 at approximately the same time as it pushes in an SDI bit 1, and pushes in an SDI bit 0 at one end of the message.

[0089] Fig. Figure 10 is a flowchart showing an example of a method for operating a serial communication node according to some embodiments. As in Fig. As shown in Figure 10, the procedure in step 1001 involves alternating between triggering the outshift of an SDO bit and triggering the inshift of an SDI bit relative to a first shift clock edge 250, 250A, 250B, which is separated from a second shift clock edge 260, 260A, 260B by a first time difference 230A, 230B. As shown in Fig. As shown in Figure 10, the procedure in step 1002 further includes triggering the insertion of the SDI bit separately from triggering the insertion of the SDO bit by a second time difference 232, 233, 234, 235, 236, 238, which is larger than the first time difference 230A, 230B.

[0090] In some examples, the second time difference 232, 233, 234, 235, 236, 238 has a duration chosen to account for a propagation delay 109 that is transferred to the shift clock signal SCLK 240A, 240B. In some examples, the second time difference 234, 235 is substantially equal to or slightly less than a full period 290 of the shift clock signal SCLK 240A, 240B (e.g., substantially equal to twice the first time difference 230 or slightly less than twice the first time difference 230).

[0091] In some examples, the serial communication node is a peripheral node 120, and the method further involves triggering the insertion of the SDI bit at the second time difference 232, 234 after triggering the insertion of the SDO bit. In some examples, the method further involves applying a known delay 272, 274 after the second shift clock edge 260A, 260B before inserting the SDI bit. In some examples, the method further involves inserting a current SDO bit at the same time as, or immediately after, triggering the insertion of a previous SDI bit.

[0092] In other examples, the serial communication node is a peripheral node or a host node, and the procedure further involves triggering the shift-out of the SDO bit at the second time difference 233, 235 before triggering the shift-in of the SDI bit. In some examples, the procedure involves applying a known delay 276, 278 after the second shift clock edge 260A, 260B before shifting out the SDO bit.

[0093] In other examples, the procedure involves: triggering, by a peripheral node 120, the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit; and triggering, by a host node, the insertion of the SDO bit at the second time difference before triggering the insertion of the SDI bit.

[0094] In some examples, the procedure includes: triggering, by a host node 110, the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit; and triggering, by a peripheral node 120, the insertion of the SDO bit at the second time difference before triggering the insertion of the SDI bit.

[0095] In some examples, the procedure includes: triggering, by a peripheral node 120, the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit; and triggering, by the peripheral node 120, the insertion of the SDO bit at the second time difference before triggering the insertion of the SDI bit.

[0096] In some examples, the procedure includes: triggering, by a host node 110, the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit; and triggering, by host node 110, the insertion of the SDO bit at the second time difference before triggering the insertion of the SDI bit. clauses

[0097] Clause 1. A method comprising: alternating between triggering an outshift of an SDO bit and triggering an inshift of an SDI bit relative to a first shift clock edge separated from a second shift clock edge of a shift clock signal SCLK by a first time difference; and triggering the inshift of the SDI bit separately from triggering the outshift of the SDO bit by a second time difference longer than the first time difference.

[0098] Clause 2. The procedure of Clause 1, further comprising: by means of a peripheral node, triggering the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit.

[0099] Clause 3. The procedure of Clause 2, wherein the triggering of the SDI bit shift in at the second time difference after triggering the SDO bit shift out comprises, by the peripheral node, a known delay after the second shift clock edge before triggering the SDI bit shift in.

[0100] Clause 4. The procedure of one of Clauses 1-3, further comprising: triggering the outward shift of the SDO bit to the second time difference before triggering the inward shift of the SDI bit.

[0101] Clause 5. The procedure of Clause 4, wherein triggering the shift out of the SDO bit to the second time difference before triggering the shift in of the SDI bit comprises applying a known delay after the second shift clock edge before triggering the shift out of the SDO bit.

[0102] Clause 6. The method of one of clauses 1-5, wherein the second time difference has a duration selected to account for a propagation delay affecting the shift clock signal SCLK.

[0103] Clause 7. The procedure of one of Clauses 1-6, further comprising: triggering the outshift of a current SDO bit substantially simultaneously or immediately after triggering the inshift of a previous SDI bit.

[0104] Clause 8. The method of one of Clauses 1-7, wherein the second time difference is substantially equal to or slightly less than one full period of the shift clock signal SCLK.

[0105] Clause 9. The method of one of Clauses 1-8, wherein the first shift clock edge and the second shift clock edge are successive edges of the shift clock signal SCLK separated by the first time difference.

[0106] Clause 10. The procedure of one of Clauses 1-9, further comprising: triggering, by a peripheral node, the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit; and triggering, by a host node, the insertion of the SDO bit at the second time difference before triggering the insertion of the SDI bit.

[0107] Clause 11. The procedure of one of Clauses 1-9, further comprising: triggering, by a host node, the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit; and triggering, by a peripheral node, the insertion of the SDO bit at the second time difference before triggering the insertion of the SDI bit.

[0108] Clause 12. The procedure of one of Clauses 1-9, further comprising: triggering, by a peripheral node, the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit; and triggering, by the peripheral node, the insertion of the SDO bit at the second time difference before triggering the insertion of the SDI bit.

[0109] Clause 13. The procedure of one of Clauses 1-9, further comprising: triggering, by a host node, the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit; and triggering, by the host node, the insertion of the SDO bit at the second time difference before triggering the insertion of the SDI bit.

[0110] Clause 14. A communication device designed to: alternate between triggering an outshift of an SDO bit and triggering an inshift of an SDI bit relative to a first shift clock edge separated from a second shift clock edge of a shift clock signal SCLK by a first time difference; and triggering the inshift of the SDI bit separately from triggering the outshift of the SDO bit by a second time difference longer than the first time difference.

[0111] Clause 15. The communication device of Clause 14, wherein the communication device is a peripheral node designed to: trigger the in-shift of the SDI bit at the second time difference after triggering the out-shift of the SDO bit.

[0112] Clause 16. The communication device of Clause 15, wherein the peripheral node is designed to: apply a known delay after the second shift clock edge before triggering the insertion of the SDI bit.

[0113] Clause 17. The communication device of one of Clauses 14-17, wherein the communication device is designed to: trigger the outshift of the SDO bit at the second time difference prior to triggering the inshift of the SDI bit.

[0114] Clause 18. The communication device of Clause 17, wherein the communication device is designed to: apply a known delay after the second shift clock edge before triggering the shift out of the SDO bit.

[0115] Clause 19. The communication device of one of Clauses 14-18, wherein the second time difference has a duration selected to account for a propagation delay.

[0116] Clause 20. The communication device of one of Clauses 14-19, wherein the communication device is designed to: trigger the outshift of a current SDO bit simultaneously or immediately after triggering the inshift of a previous SDI bit.

[0117] Clause 21. The communication device of one of Clauses 14-20, wherein the second time difference is substantially equal to or slightly less than a full period of the SCLK signal.

[0118] Clause 22. The communication device of one of Clauses 14-21, wherein the first shift clock edge and the second shift clock edge are successive edges of the shift clock signal SCLK, separated by the first time difference.

[0119] Clause 23. The communication device of Clause 14, wherein the communication device is further configured to: trigger the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit; and trigger the insertion of the SDO bit at the second time difference before triggering the insertion of the SDI bit.

[0120] Clause 24. A system comprising: a host node; and a peripheral node designed to: alternate between triggering an SDO bit shift-out and an SDI bit shift-in relative to a first shift clock edge separated from a second shift clock edge by a first time difference; and triggering the SDI bit shift-in separately from triggering the SDO bit shift-out by a second time difference longer than the first time difference.

[0121] Clause 25. The system of Clause 23, wherein the host node is designed to: alternate between triggering an SDO bit shift-out and triggering an SDI bit shift-in relative to the first shift clock edge separated from the second shift clock edge by the first time difference; and triggering the SDI bit shift-in, separated by the second time difference from triggering the SDO bit shift-out.

[0122] Clause 26. The system of one of Clauses 24 and 25, wherein the host node and / or the peripheral node is / are designed to: trigger the out-shift of the SDO bit to the second time difference before triggering the in-shift of the SDI bit.

[0123] Clause 27. The system of one of clauses 24-26, wherein the peripheral node is designed to: trigger the in-shift of the SDI bit at the second time difference after triggering the out-shift of the SDO bit.

[0124] Clause 28. The system of one of Clauses 24-27, wherein the peripheral node is designed to trigger the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit, and the host node is designed to trigger the insertion of the SDO bit at the second time difference before triggering the insertion of the SDI bit.

[0125] Clause 29. The system of one of Clauses 24-27, wherein the host node is designed to trigger the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit and to trigger the insertion of the SDO bit at the second time difference before triggering the insertion of the SDI bit.

[0126] Clause 30. The system of one of Clauses 24-27, wherein the peripheral node is designed to trigger the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit and to trigger the insertion of the SDO bit at the second time difference before triggering the insertion of the SDI bit.

[0127] Clause 31. The system of one of Clauses 24-27, wherein the peripheral node and the host node are configured to trigger the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit and to trigger the insertion of the SDO bit at the second time difference before triggering the insertion of the SDI bit.

[0128] While this invention has been described with respect to illustrative embodiments, this description should not be interpreted in a limiting sense. Various modifications and combinations of the illustrated embodiments, as well as other embodiments of the invention, are clear to those skilled in the art with reference to the description. Therefore, the appended claims are intended to cover all such modifications or embodiments.

Claims

[1] Procedure, encompassing: Alternating between triggering an outshift of an SDO bit and triggering an inshift of an SDI bit relative to a first shift clock edge, which is separated from a second shift clock edge of a shift clock signal SCLK by a first time difference; and Triggering the insertion of the SDI bit, separate from triggering the insertion of the SDO bit, by a second time difference that is longer than the first time difference. [2] Method according to claim 1, further comprising: via a peripheral node: triggering the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit. [3] Method according to claim 2, wherein triggering the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit comprises the following: Apply, through the peripheral node, a known delay after the second shift clock edge before triggering the insertion of the SDI bit. [4] Method according to any one of claims 1 to 3, further comprising: Triggering the shift out of the SDO bit to the second time difference before triggering the shift in of the SDI bit. [5] Method according to claim 4, wherein triggering the shift out of the SDO bit to the second time difference before triggering the shift in of the SDI bit comprises applying a known delay after the second shift clock edge before triggering the shift out of the SDO bit. [6] Method according to any one of claims 1 to 5, wherein the second time difference has a duration selected to take into account a propagation delay. [7] Method according to any one of claims 1 to 6, further comprising: Triggering the outshift of a current SDO bit substantially simultaneously or immediately after triggering the inshift of a previous SDI bit. [8] Method according to any one of claims 1 to 7, wherein the second time difference is substantially equal to or slightly less than one full period of the SCLK signal. [9] Method according to any one of claims 1 to 8, wherein the first shift clock edge and the second shift clock edge are successive edges of the shift clock signal SCLK, separated by the first time difference. [10] Method according to any one of claims 1 to 9, further comprising: Triggering, by a peripheral node, of the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit; and Triggering, by a host node, of the SDO bit being pushed out to the second time difference before triggering the SDI bit being pushed in. [11] Method according to any one of claims 1 to 10, further comprising: Triggering, by a host node, of the SDI bit being shifted in at the second time difference after the SDO bit being shifted out; and Triggering, by a peripheral node, the outshifting of the SDO bit to the second time difference before triggering the inshifting of the SDI bit. [12] Method according to any one of claims 1 to 11, further comprising: Triggering, by a peripheral node, of the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit; and Triggering, by the peripheral node, of the outshifting of the SDO bit to the second time difference before triggering the inshifting of the SDI bit. [13] Method according to any one of claims 1 to 12, further comprising: Triggering, by a host node, of the SDI bit being shifted in at the second time difference after the SDO bit being shifted out; and Triggering, by the host node, of the SDO bit being pushed out to the second time difference before triggering the SDI bit being pushed in. [14] Communication device designed to: Alternating between triggering an outshift of an SDO bit and triggering an inshift of an SDI bit relative to a first shift clock edge, which is separated from a second shift clock edge of a shift clock signal SCLK by a first time difference; and Triggering the insertion of the SDI bit, separated from triggering the insertion of the SDO bit by a second time difference that is longer than the first time difference. [15] Communication device according to claim 14, wherein the communication device is a peripheral node designed to: Triggering the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit. [16] Communication device according to claim 15, wherein the peripheral node is designed to: Applying a known delay after the second shift clock edge before triggering the shift of the SDI bit. [17] Communication device according to any one of claims 14 to 16, wherein the communication device is designed to: Triggering the shift out of the SDO bit to the second time difference before triggering the shift in of the SDI bit. [18] Communication device according to claim 17, wherein the communication device is designed to: Applying a known delay after the second shift clock edge before triggering the shift out of the SDO bit. [19] Communication device according to any one of claims 14 to 18, wherein the second time difference has a duration selected to take into account a propagation delay. [20] Communication device according to any one of claims 14 to 19, wherein the communication device is designed to: Triggering the outshift of a current SDO bit simultaneously or immediately after triggering the inshift of a previous SDI bit. [21] Communication device according to any one of claims 14 to 20, wherein the second time difference is substantially equal to or slightly less than a full period of the SCLK signal. [22] Communication device according to one of claims 14 to 21, wherein the first shift clock edge and the second shift clock edge are successive edges of the shift clock signal SCLK, separated by the first time difference. [23] Communication device according to any one of claims 14 to 22, wherein the communication device is further designed to: Triggering the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit; and Triggering the shift out of the SDO bit to the second time difference before triggering the shift in of the SDI bit. [24] System, encompassing: a host node; and a peripheral node designed to: Alternating between triggering an outshift of an SDO bit and triggering an inshift of an SDI bit relative to a first shift clock edge, which is separated from a second shift clock edge by a first time difference; and Triggering the insertion of the SDI bit, separated from triggering the insertion of the SDO bit by a second time difference that is longer than the first time difference. [25] System according to claim 24, wherein the host node is designed to: Alternating between triggering an outshift of an SDO bit and triggering an inshift of an SDI bit relative to the first shift clock edge separated from the second shift clock edge by the first time difference; and Triggering the insertion of an SDI bit, separated from triggering the insertion of an SDO bit by the second time difference. [26] System according to claim 24 or 25, wherein the host node and / or the peripheral node is / are designed to: Triggering the shift out of the SDO bit to the second time difference before triggering the shift in of the SDI bit. [27] System according to any one of claims 24 to 26, wherein the peripheral node is designed to: Triggering the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit. [28] System according to one of claims 24 to 27, wherein the peripheral node is designed to trigger the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit and the host node is designed to trigger the insertion of the SDO bit at the second time difference before triggering the insertion of the SDI bit. [29] System according to one of claims 24 to 28, wherein the host node is designed to trigger the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit and to trigger the insertion of the SDO bit at the second time difference before triggering the insertion of the SDI bit. [30] System according to one of claims 24 to 29, wherein the peripheral node is designed to trigger the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit and to trigger the insertion of the SDO bit at the second time difference before triggering the insertion of the SDI bit. [31] System according to claim 23, wherein the peripheral node and the host node are designed to trigger the insertion of the SDI bit at the second time difference after triggering the insertion of the SDO bit and to trigger the insertion of the SDO bit at the second time difference before triggering the insertion of the SDI bit.

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