Semiconductor device and method for manufacturing a semiconductor device

Abstract

A semiconductor device comprises: a channel-stopper region of a first conductivity type formed on a surface layer of a drift layer in a termination region; a first termination trench formed in the drift layer in the termination region; a plurality of termination electrodes arranged in the first termination trench while surrounded by a first termination insulating film; and a channel-stopper electrode arranged on an upper surface of the drift layer while electrically connected to the channel-stopper region and the termination electrodes, wherein the plurality of termination electrodes comprises a first termination electrode and a second termination electrode.

Description

BACKGROUND OF THE INVENTION Area of ​​the invention

[0001] The technology disclosed in the present description relates to a semiconductor technology. Description of the background technology

[0002] In a semiconductor device, an active region and a termination region surrounding the active region in plan view are arranged, and the extension of a depletion layer extending from a PN junction is controlled by a termination structure arranged in the termination region (see, for example, published Japanese patent application No. 2013-069783).

[0003] In a semiconductor device that handles large currents, such as a power semiconductor device, it is increasingly important to finely control the extent of a depletion layer according to each application. SUMMARY

[0004] The technology disclosed in the present description is a technology for improving the flexibility in controlling a depletion layer.

[0005] A semiconductor device according to a first aspect of the present technology disclosed in the present description is a semiconductor device comprising an active region and a termination region surrounding the active region in plan view, and comprising: a drift layer of a first conductivity type; a channel stopper region of a first conductivity type formed on a surface layer of the drift layer in the termination region and having a higher impurity or defect concentration than that of the drift layer; a first termination trench formed in the drift layer in the termination region; a plurality of termination electrodes arranged in the first termination trench while surrounded by a first termination insulating film;a channel-stopper electrode arranged on an upper surface of the drift layer while electrically connected to the channel-stopper region and at least one of the termination electrodes; a defect region of a second conductivity type formed on the surface layer of the drift layer in the active region; a gate trench formed in the drift layer while adjacent to the defect region; a plurality of gate electrodes arranged in the gate trench while surrounded by a gate insulating film; an interlayer insulating film arranged to cover the gate trench; an electrode on the upper surface arranged to cover the upper surface of the drift layer and the interlayer insulating film;and an electrode on a lower surface, which is arranged on a lower surface of the drift layer at least in the active region, wherein the plurality of termination electrodes in the first termination trench comprises a first termination electrode and a second termination electrode, the plurality of gate electrodes comprises a first gate electrode and a second gate electrode, the first termination electrode and the second termination electrode in the first termination trench are arranged separately from each other, and the first gate electrode and the second gate electrode in the gate trench are arranged separately from each other.

[0006] According to at least the first aspect of the technology disclosed in the present description, a plurality of termination electrodes are arranged in a single termination trench, which can improve the flexibility in controlling a depletion layer.

[0007] However, the objectives, features, aspects and advantages relating to the technology disclosed in the present description will become more apparent from the following detailed description and the accompanying drawings.

[0008] These and other objectives, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when it is considered in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a top view illustrating an example of a configuration of a semiconductor device according to preferred embodiments; Fig. Figure 2 is a perspective view illustrating an example of a part's configuration in an active area in Fig. 1; Fig. 3 is along a line BB in Fig. 2. Sectional view taken to illustrate an example of a configuration; Fig. 4 is along a line CC in Fig. 2. Sectional view taken to illustrate an example of a configuration; Fig. 5 is along a line AA in Fig. 1. Sectional view taken to illustrate an example of a configuration; Fig. 6 is one along line AA in Fig. 1. Sectional view taken to illustrate another example of the configuration; Fig. 7 is along a line DD in Fig. 6. Sectional view taken to illustrate an example of a configuration; Fig. 8 is one along the DD line in Fig. 6. Sectional view taken to illustrate another example of the configuration; Fig. Figures 9 to 16 are views to explain a method for manufacturing a semiconductor device according to the preferred embodiments; Fig. Figures 17 to 23 are views illustrating a method for producing a termination electrode in a termination trench, as shown in Fig. 8, to explain in the semiconductor device according to the preferred embodiments; Fig. 24 and Fig. 25 are each one along line AA in Fig. 1. Sectional view taken to illustrate another example of the configuration in the semiconductor device according to the preferred embodiments; Fig. 26 is one along the DD line in Fig. 6. Sectional view taken to illustrate another example of the configuration; and Fig. 27 and Fig. 28 are each one along line AA in Fig. 1 Sectional view taken to illustrate another example of the configuration in the semiconductor device according to the preferred embodiments. DESCRIPTION OF PREFERRED EXECUTION FORMS

[0009] Preferred embodiments are described below with reference to the accompanying drawings. While detailed features and the like are presented in the following preferred embodiments for the purpose of describing the technology, these are only examples and not all are necessarily essential features for implementing the preferred embodiments in practice.

[0010] Note that the drawings are schematic and, for the sake of clarity, components may be omitted, configurations simplified, or the like. Furthermore, the sizes and relative positions of components illustrated in different drawings are not necessarily depicted accurately and may have been modified. Additionally, hatching may be used in drawings that are not sectional views, such as top views, to facilitate understanding of the preferred embodiments.

[0011] Furthermore, similar components with the same reference numerals are illustrated in the drawings in the following description, and their designations and functions are also similar. Consequently, their detailed descriptions are omitted where appropriate to avoid repetition.

[0012] Furthermore, in the description set out in the present specification or description, when a term is described as "comprising a certain component", "containing a certain component", "having a certain component", or the like, such terms, unless otherwise stated, are not exclusive expressions that exclude the presence of any other component.

[0013] Furthermore, in the description set forth in the present description, ordinal numbers such as "first" and "second", if any, are used for convenience to facilitate an understanding of the contents of the preferred embodiments, and the contents of the preferred embodiments are not limited to the sequence or the like that may be conditioned by these ordinal numbers.

[0014] Furthermore, in the description set forth in the present description, when something is described as "A or B", the description includes a case in which the terms mean only one of A or B, and a case in which the terms mean both A and B, provided there is no contradiction.

[0015] Furthermore, in the description set out in the present description, with regard to the term "positive ... axis direction", "negative ... axis direction" or the like, a direction along an arrow of an illustrated ... axis is a positive direction and a direction opposite to an arrow of an illustrated ... axis is a negative direction.

[0016] Furthermore, in the description set forth in the present description, terms that signify certain positions and directions, such as "upper", "lower", "left", "right", "side", "bottom", "surface" and "back", where applicable, are used for convenience to facilitate an understanding of the contents of the preferred embodiments and are irrelevant to positions and directions in an actual application of the preferred embodiments.

[0017] Furthermore, in the description presented here, when something is described as "an upper surface of..." or "a lower surface of...", the description includes a state in which an additional component is formed on an upper surface or a lower surface of a specific component, in addition to the upper surface or the lower surface of the specific component alone. Specifically, when, for example, "B arranged on an upper surface of A" is described, the description does not preclude the interposition or insertion of another component "C" between A and B. <Erste bevorzugte Ausführungsform>

[0018] In the following, a semiconductor device and a method for manufacturing a semiconductor device according to the present preferred embodiment are described. <Konfiguration einer Halbleitervorrichtung>

[0019] Fig. Figure 1 is a top view illustrating an example of a configuration of a semiconductor device according to the present preferred embodiment. As shown in Fig. As shown in Figure 1 as an example, a semiconductor device 100 comprises an active region 2 and a termination region 4, which is configured to surround the active region 2 in a top view. A gate pad 6 is placed at one end of the active region 2. The gate pad 6 is connected to a gate wire 8, which is configured to surround the active region 2 in a top view.

[0020] Fig. Figure 2 is a perspective view illustrating an example of a configuration of a part in the active area 2 in Fig. 1. In Fig. Figure 1 is an illustration of electrodes formed on an upper surface of the configuration, omitted for convenience.

[0021] As in Fig. As shown in Figure 2 as an example, the semiconductor device 100 is, for instance, a bipolar transistor with an insulated gate (i.e., an IGBT). The semiconductor device 100 comprises, in the active region 2, an n-type drift layer 10, an (n+)-type charge accumulation region 12 formed on an upper surface of the n-type drift layer 10, and a channel-doped region formed on a surface layer of the (n+)-type charge accumulation region 12.: channel doped region) 14 of p-type, a source region 16 of (n+)-type formed on part of a surface layer of the channel doped region 14 of p-type, a defect region 18 of (p+)-type formed on another part of the surface layer of the channel doped region 14 of p-type, a gate trench 20 formed such that it extends from an upper surface of the source region 16 of (n+)-type and an upper surface of the defect region 18 of (p+)-type and reaches the interior of the drift layer 10 of n-type, a gate electrode 24 which, while surrounded by a gate insulating film 22, is placed in the gate trench 20, and an intermediate layer insulating film 26 covering the gate electrode 24, a on a lower surface of the drift layer 10 of n-type a formed collector layer 28 of the (p+) type and a collector electrode 30 formed on a lower surface of the collector layer of the (p+) type.

[0022] The drift layer 10 of n-type consists of, for example, Si, SiC, or the like. The charge accumulation region 12 of (n+)-type exhibits a higher impurity concentration than the impurity concentration of the drift layer 10 of n-type.

[0023] The p-type channel-doped region 14 is formed by ion implantation of impurities such as boron.

[0024] The source region 16 of (n+) type exhibits a higher impurity concentration than the impurity concentration of the drift layer 10 of n type. The impurity region 18 of (p+) type exhibits a higher impurity concentration than the impurity concentration of the channel-doped region 14 of p type. The source region 16 of (n+) type and the impurity region 18 of (p+) type are arranged alternately and each is configured to extend along a Y-axis direction.

[0025] The source region 16 of (n+) type or the defect region 18 of (p+) type, the channel-doped region 14 of p type, and the charge accumulation region 12 of (n+) type are adjacent to or bordering the gate trench 20. The gate trenches 20 are each configured to extend along an X-axis direction and are arranged along the Y-axis direction. However, the direction in which each of the gate trenches 20 extends and the direction in which the gate trenches 20 are arranged are not based on those in the Fig. The case illustrated in Figure 2 is limited, and a positional or locational relationship with a termination trench, which will be described later (in other words, a combination of extension directions), is also not limited to those described in the present preferred embodiment. The gate insulating film 22 is formed on an inner wall and a bottom surface of the gate trench 20 and is configured to surround the gate electrode 24 in the trench 20.

[0026] A plurality of gate electrodes 24 are arranged in a single gate trench 20. The plurality of gate electrodes 24 are arranged separately from one another, and the gate insulating film 22 is arranged between the plurality of gate electrodes 24. Fig. 2 refers to the gate electrode 24 located on one side in a positive Z-axis direction as a gate electrode 24A and to the gate electrode 24 located on one side in a negative Z-axis direction as a gate electrode 24B.

[0027] The arrangement of the plurality of gate electrodes 24 in the gate trench 20 can be an arrangement in which the gate electrodes 24 overlap each other in plan view, as in Fig. Figure 2 illustrates, in other words, an arrangement along the Z-axis direction, or it could be an arrangement along the Y-axis direction or an arrangement along the X-axis direction.

[0028] Fig. 3 is along a line BB in Fig. 2. Sectional view taken to illustrate an example of a configuration. As in Fig. As shown in Figure 3, the semiconductor device 100 in the active region 2 comprises the n-type drift layer 10, the (n+)-type charge accumulation region 12, the p-type channel-doped region 14, the (n+)-type source region 16, the gate trench 20, which is configured to extend from the upper surface of the (n+)-type source region 16 and reach the interior of the n-type drift layer 10, the gate electrodes 24, the interlayer insulating film 26, an emitter electrode 32 covering the interlayer insulating film 26 and the (n+)-type source region 16, the (p+)-type collector layer 28, and the collector electrode 30. Fig. 3 is also the emitter electrode 32, which is in Fig. The omission of point 2 illustrates this.

[0029] Fig. 4 is along a line CC in Fig. 2. Sectional view taken to illustrate an example of a configuration. As in Fig. As shown in Figure 4 by way of example, the semiconductor device 100 in the active region 2 comprises the n-type drift layer 10, the (n+)-type charge accumulation region 12, the p-type channel-doped region 14, the (p+)-type impurity region 18, the gate trench 20, which is configured to extend from the upper surface of the (p+)-type impurity region 18 and reach the interior of the n-type drift layer 10, the gate electrodes 24, the interlayer insulating film 26, the emitter electrode 32, which covers the interlayer insulating film 26 and the (p+)-type impurity region 18, the (p+)-type collector layer 28, and the collector electrode 30. Fig. 4 is the emitter electrode 32, which is in Fig. The omission of point 2 is also illustrated.

[0030] Fig. 5 is along a line AA in Fig. 1. Sectional view taken to illustrate an example of a configuration. In Fig. 5 corresponds along the X-axis direction to an area in which the gate trench 20 is formed, to the active area 2, and an area in the positive X-axis direction with respect to the gate trench 20 corresponds to the closing area 4.

[0031] As in Fig. As illustrated in Figure 5, the semiconductor device 100 comprises a defect region 34 of the (p+) type, which is formed on the surface layer of the drift layer 10 of the n type such that it extends from the active region 2 to the termination region 4, the charge accumulation region 12 of the (n+) type, which is formed on the surface layer of the drift layer 10 of the n type at a position that is further away from the active region 2 than the defect region 34 of the (p+) type, a defect region 36 of the p type, which is formed on a surface layer of the charge accumulation region 12 of the (n+) type, a channel stopper region 38 of the (n+) type, which is formed on a surface layer of the defect region 36 of the p type, a termination trench 40, which is formed such that it extends from an upper surface of the channel stopper region 38 of the (n+) type, and the interior of the drift layer 10 of the n-type is reached, and a terminal electrode 44,which, while surrounded by a termination insulating film 42, is placed in the termination trench 40, a field insulating film 46 formed on the upper surface of the n-type drift layer 10 in the termination region 4, a gate electrode 48 formed such that it is in contact with an upper surface of a gate electrode 24A exposed in the gate trench 20 and extends on an upper surface of the field insulating film 46, a field plate electrode 50 formed on the upper surface of the field insulating film 46 at a position farther from the active region 2 than the gate electrode 48, while separated from the gate electrode 48, a channel stopper electrode 52 formed on the upper surface of the field insulating film 46 at a position farther from the active region 2 than the field plate electrode 50, while separated from the gate electrode 48 the field plate electrode 50 is located separately,The collector layer 28 is of the (p+) type and the collector electrode 30. Note that the defect region 36 is of the p type and the charge accumulation region 12 is of the (n+) type and need not necessarily be arranged.

[0032] The defect area 34 of the (p+) type and the defect area 36 of the p type are formed by ion implantation of defects such as boron.

[0033] The (n+)-type channel stopper region 38 exhibits a higher defect concentration than the (n-type) drift layer 10. The (n+)-type charge accumulation region 12 exhibits a defect concentration that is higher than that of the (n-type) drift layer 10 and lower than that of the (n+)-type channel stopper region 38.

[0034] The termination trench 40 is designed to extend along the Y-axis. The channel stopper region 38 of the (n+) type, the defect region 36 of the p type, and the charge accumulation region 12 of the (n+) type are adjacent to or border the termination trench 40. The termination insulating film 42 is formed on an inner wall and a bottom surface of the termination trench 40 and is designed to surround the termination electrode 44 within the termination trench 40. The termination electrode 44 is exposed near an upper surface of the termination trench 40, but is surrounded by the termination insulating film 42 within the termination trench 40.

[0035] A plurality of termination electrodes 44 are arranged in a single termination trench 40. The plurality of termination electrodes 44 are arranged separately from one another, and the termination insulating film 42 is arranged between the plurality of termination electrodes 44. Fig. Reference is made to the terminal electrode 44 located on one side in the positive Z-axis direction as terminal electrode 44A and to the terminal electrode 44 located on one side in the negative Z-axis direction as terminal electrode 44B.

[0036] When the multiple terminal electrodes 44 are arranged in the terminal trench 40, the arrangement can be such that the terminal electrodes 44 overlap each other in plan view, as shown in Fig. Figure 5 illustrates, in other words, an arrangement along the Z-axis direction, or it could be an arrangement along the Y-axis direction or an arrangement along the X-axis direction.

[0037] As in Fig. As illustrated in Figure 5, a plurality of field plate electrodes 50 can be configured along the X-axis direction, and each of the field plate electrodes 50 can be configured to surround the active region 2 in a top view. Note that the field plate electrode 50 does not necessarily have to be arranged in a specific way.

[0038] The channel stopper electrode 52 is in contact with an upper surface of the termination electrode 44A, which is exposed in the termination trench 40, and is electrically connected to the termination electrode 44A. Furthermore, the channel stopper electrode 52 is in contact with the upper surface of the (n+)-type channel stopper region 38, which is exposed from the field insulating film 46, and is electrically connected to the (n+)-type channel stopper region 38.

[0039] Fig. 6 is one along line AA in Fig. 1. Sectional view taken to illustrate another example of a configuration. In Fig. 6 corresponds along the X-axis direction to an area in which the gate trench 20 is formed, to the active area 2, and an area in the positive X-axis direction with respect to the gate trench 20 corresponds to the closing area 4.

[0040] In the Fig. The 6 illustrated example is in addition to those in Fig. The components illustrated in the 5 diagrams are arranged in a field plate 54. Note that in a case where the field plate 54 is arranged as in the diagram, Fig. Figure 5 illustrates that if the arrangement is not correct, the need for a photomask to form the field plate 54 can be eliminated.

[0041] The field plate 54 is arranged on the upper surface of the n-type drift layer 10 in the termination region 4, its upper and lower surfaces and lateral surfaces being surrounded by a field insulating film 46A. The field insulating film 46A containing the field plate 54 is configured to have a thickness greater than that of the field insulating film 46. As shown in Fig. As illustrated in Figure 6, a multitude of field plates 54 can be formed along the X-axis direction and each of the field plates 54 can be formed such that it surrounds the active area 2 in plan view.

[0042] Furthermore, the field plate 54 can be arranged in a top view at a position between the field plate electrodes 50.

[0043] In the Fig. In the illustrated example 6, a termination electrode 144 located on one side in the positive Z-axis direction in the termination trench 40 further features an extension section 144A, which is arranged such that it extends onto an upper surface of the field insulating film 46A, in other words, onto the upper surface of the n-type drift layer 10. The connection section 144A, like the termination electrode 144, is made of, for example, polysilicon. The channel stopper electrode 52 is in contact with the connection section 144A of the termination electrode 144, which is exposed in the termination trench 40. Note that the connection section 144A can be formed simultaneously with the field plate 54.

[0044] Fig. 7 is along a line DD in Fig. 6. Sectional view taken to illustrate an example of a configuration. As in Fig. As shown in Figure 7, only the terminal electrode 44A can be in contact with the channel stopper electrode 52 to electrically connect the two electrodes. In this case, the terminal electrode 44B is a floating or potential-free electrode.

[0045] Fig. 8 is one along the DD line in Fig. Figure 6 shows a section view to illustrate another example of the configuration. As in Fig. As shown in Figure 8, both the termination electrode 44A and the termination electrode 44B can be in contact with the channel stopper electrode 52 to electrically connect the three electrodes. In this case, the termination electrode 44A, the termination electrode 44B, and the channel stopper electrode 52 are at the same potential. Note that the termination electrode 44B can have multiple points of contact with the channel stopper electrodes 52. Alternatively, in Fig. 8 only the terminal electrode 44B must be transformed or reshaped so that it is electrically connected to the channel stopper electrode 52. <Verfahren zum Herstellen einer Halbleitervorrichtung>

[0046] Fig. Figures 9 to 16 are views illustrating a method for manufacturing a semiconductor device according to the present preferred embodiment.

[0047] In a Fig. In step 9 illustrated, the charge accumulation region 12 of (n+) type, the channel-doped region 14 of p type, the defect region 36 of p type, the channel stopper region 38 of (n+) type and the defect region 34 of (p+) type are individually formed on the surface layer of the drift layer 10 of n type and the field insulating film 46A is formed in a part of the upper surface of the drift layer 10 of n type corresponding to the termination region 4, specifically in a region excluding the upper surface of the channel stopper region 38 of (n+) type.

[0048] The charge accumulation region 12 of the (n+) type and the channel stopper region 38 of the (n+) type are formed by, for example, the implantation of defects such as phosphorus or arsenic into the surface layer of the drift layer 10 of the n type using an ion implantation process and subsequent thermal diffusion of the implanted defects.

[0049] Then, in a Fig. In step 10, for example, a photolithography process and an anisotropic dry etching process are carried out, such that the gate trench 20 is formed at a position adjacent to the charge accumulation region 12 of the (n+) type and the channel-doped region 14 of the p type in the active region 2, and the termination trench 40 is formed in the upper surface of the channel-stopper region 38 of the (n+) type in the termination region 4.

[0050] Then, in a Fig. In Figure 11, an insulating film is formed on the surface (top surface and side surface) of the n-type drift layer 10, including the inside of the gate trench 20 and the inside of the closure trench 40. The insulating film is, for example, a silicon dioxide film. The insulating film in the gate trench 20 corresponds to the gate insulating film 22. The insulating film in the closure trench 40 corresponds to the closure insulating film 42.

[0051] Then, in a Fig. In the illustrated step 12, while a training area is limited using a mask or the like, electrodes are formed in a portion of gate trench 20 and a portion of closure trench 40 by a chemical vapor deposition (CVD) process or the like. The electrodes are, for example, made of polysilicon. The electrode in gate trench 20 corresponds to gate electrode 24B. The electrode in closure trench 40 corresponds to closure electrode 44B. Fig. 12. The electrodes are each formed in approximately a lower half of the gate trench 20 and approximately a lower half of the closure trench 40; however, the electrodes can, for example, be formed only on sides in the positive X-axis direction in the two trenches or only on sides in the positive Y-axis direction in the two trenches. Alternatively, a combination of one electrode on only one side in the positive X-axis direction in one trench and one electrode in approximately a lower half of the other trench, or the like, can be arranged.

[0052] Then, in a Fig. In step 13, insulating films are formed on the upper surfaces of the gate trench 20 and the end trench 40. These insulating films are, for example, silicon dioxide films. The insulating film in the gate trench 20 corresponds to the gate insulating film 22. The insulating film in the end trench 40 corresponds to the end insulating film 42.

[0053] Then, in a Fig. In the step illustrated in Figure 14, while a training area is delimited using a mask or the like, electrodes in the gate trench 20 on the upper surface of the field insulating film 46A in the termination area 4 and in the termination trench 40 are formed by a CVD process or the like. The electrodes are, for example, made of polysilicon. The electrode in the gate trench 20 corresponds to the gate electrode 24A. The electrode in the termination trench 40 corresponds to the termination electrode 144. In this context, the termination electrode 144 has the connecting part area 144A, which is configured to extend over an insulating film on the upper surface of the n-type drift layer 10. The electrode on the upper surface of the field insulating film 46A corresponds to the field plate 54.

[0054] Then, in a Fig. In step 15, insulating films are formed to cover part of the gate electrode 24A and the field plate 54. These insulating films are, for example, silicon oxide films. The insulating film formed to expose part of the gate electrode 24A corresponds to the interlayer insulating film 26. The insulating film covering the field plate 54 is the field insulating film 46A. In this context, the field insulating film 46A is formed by a process for exposing part of the (n+)-type channel stopper region 38.

[0055] Then, in a Fig. In the step illustrated in Figure 16, a metal film is formed over the entire surface using a sputtering process and the like. Furthermore, the metal film is structured using a photolithography process, an anisotropic dry etching process, and the like to form electrodes. These electrodes are, for example, made of aluminum. The electrode located on the upper surface of the gate trench 20 above the interlayer insulating film 26 corresponds to the emitter electrode 32. The electrode located in contact with the exposed part of the gate electrode 24A corresponds to the gate electrode 48. The electrode located on the upper surface of the field insulating film 46 such that it is associated with the field plate 54 corresponds to the field plate electrode 50.The electrode, which is in contact with the connecting part area 144a of the termination electrode 144 and the exposed part of the (n+) type channel stopper area 38, corresponds to the channel stopper electrode 52.

[0056] In addition to the components described above, the (p+)-type collector layer 28 is formed on the lower surface of the n-type drift layer 10, and the collector electrode 30 is further formed on the lower surface of the (p+)-type collector layer 28, thereby enabling the Fig. 6 illustrated semiconductor device is manufactured.

[0057] Fig. Figures 17 to 23 are views explaining a method for producing the termination electrode in the termination trench, illustrated in Fig. 8, in the semiconductor device according to the present preferred embodiment.

[0058] In a Fig. In step 17, the termination trench 40 is formed in the termination area 4 of the drift layer 10 of the n-type and the termination insulating film 42 is formed in the termination trench 40.

[0059] Then, in a Fig. In the illustrated step 18, while a training area is limited using a mask or the like, the termination electrode 44B is trained in a portion of the termination trench 40 by means of a CVD process or the like. For example, for the termination electrode 44B, an electrode is trained a multitude of times, while a training area is modified using different masks, such that the upper surface of the termination electrode 44B has sub-areas of different heights. Fig. 18 is a central sub-area designed in relation to the Y-axis direction such that it is higher than end sub-areas in relation to the Y-axis direction, and the higher sub-area is a sub-area that comes into contact with the channel stopper electrode 52 even after the termination electrode 144 has been formed.

[0060] Then, in a Fig. Figure 19 illustrates the formation of the final insulating film 42 on the upper surface of the termination trench 40. The final insulating film 42 is formed on the upper surface of the termination electrode 44B with sections of varying heights. The insulating film is, for example, a silicon oxide film.

[0061] Then, in a Fig. Figure 20 illustrates how the terminal electrode 144 is formed in the terminal trench 40 using a CVD process or the like. The terminal electrode 144 is formed on partial areas of low height, specifically end regions with respect to the positive and negative Y-axis directions, on the upper surface of the terminal electrode 44B.

[0062] Then, in a Fig. Figure 21 illustrates the formation of the final insulating film 42 on the upper surface of the termination trench 40. The final insulating film 42 is formed on the upper surface of the termination electrode 144 and the exposed surface of the termination electrode 44B. The insulating film is, for example, a silicon oxide film.

[0063] Then, in a Fig. 22 illustrated step the termination insulating film 42 structured such that part of the upper surface of termination electrode 44B and the upper surface of termination electrode 144 are exposed.

[0064] Then, in a Fig. Figure 23 illustrates the formation of the channel stopper electrode 52. The channel stopper electrode 52 is made of aluminum, for example. The channel stopper electrode 52 is in contact with both the terminal electrode 144 and the terminal electrode 44B. <Zweite bevorzugte Ausführungsform>

[0065] A semiconductor device and a method for manufacturing a semiconductor device according to the present preferred embodiment are described. Note that in the following description, components similar to those described in the preferred embodiment described above are illustrated in the drawings with the same reference numerals, and their detailed description is omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0066] Fig. 24 is one along line AA in Fig. Figure 1 shows a sectional view to illustrate a further example of the configuration in the semiconductor device according to the present embodiment. Fig. 24 corresponds along the X-axis direction to an area in which the gate trench 20 is formed, to the active area 2, and corresponds to an area in the positive X-axis direction with respect to the gate trench 20 to the closing area 4.

[0067] In the Fig. The 24 illustrated examples are in addition to those in Fig. The components illustrated in Figure 6 include a termination trench 41, which is designed to extend from the upper surface of the (n+)-type channel stopper area 38 and reach the interior of the n-type drift layer 10, and a termination electrode 45, which is placed in the termination trench 41 while surrounded by the termination insulating film 42.

[0068] The termination trench 41 is designed to extend along the Y-axis. The termination insulating film 42 is formed on an inner wall and a bottom surface of the termination trench 41 and is designed to surround the termination electrode 45 in the termination trench 41.

[0069] A plurality of termination electrodes 45 are arranged in a single termination trench 41. The plurality of termination electrodes 45 are arranged separately from one another, and the termination insulating film 42 is arranged between the plurality of termination electrodes 45. Fig. Reference is made to the terminal electrode 45 located on one side in the positive Z-axis direction as terminal electrode 145 and to the terminal electrode 45 located on one side in the negative Z-axis direction as terminal electrode 45B.

[0070] The arrangement of the multiple termination electrodes 45 in the termination trench 41 can be an arrangement in which the termination electrodes 45 are as in Fig. Figure 24 illustrates in top view that they overlap, in other words an arrangement along the Z-axis direction, or it can be an arrangement along the Y-axis direction or an arrangement along the X-axis direction.

[0071] Furthermore, the in Fig. Figure 24 illustrates that the terminal electrode 144, located on one side in the positive Z-axis direction in the termination trench 40, and the terminal electrode 145, located on one side in the positive Z-axis direction in the termination trench 41, together form a connecting section 144B, which is arranged such that it extends on the upper surface of the field insulating film 46A, in other words, on the upper surface of the n-type drift layer 10. The channel stopper electrode 52 is in contact via the connecting section 144B with the exposed terminal electrode 144 in the termination trench 40 and the exposed terminal electrode 145 in the termination trench 41.Note that the closing electrode 45B may also be electrically connected to the channel stopper electrode 52 in addition to the closing electrode 145 in the closing trench 41, or only the closing electrode 45B may be electrically connected to the channel stopper electrode 52 instead of the closing electrode 145 in the closing trench 41.

[0072] Fig. 25 is one along line AA in Fig. Figure 1 shows a sectional view to illustrate a further example of the configuration in the semiconductor device according to the present preferred embodiment. Fig. 25 corresponds along the X-axis direction to an area in which the gate trench 20 is formed, to the active area 2, and corresponds to an area in the positive X-axis direction with respect to the gate trench 20 to the closing area 4.

[0073] In the Fig. The 25 illustrated examples are in addition to those in Fig. The components illustrated in Figure 6 include a termination trench 41A, which is designed to extend from the upper surface of the (n+)-type channel stopper area 38 and reach the interior of the n-type drift layer 10, and a termination electrode 45A, which is placed in the termination trench 41A while surrounded by the termination insulating film 42.

[0074] The termination trench 41A is located at a position farther from the active area 2 than the termination trench 40. Furthermore, the termination trench 41A is designed to have a greater depth than the termination trench 40. The termination trench 41A extends along the Y-axis. The termination insulating film 42 is formed on an inner wall and a bottom surface of the termination trench 41A and is designed to surround the termination electrode 45A within the termination trench 41A.

[0075] A plurality of termination electrodes 45A is arranged in a single termination trench 41A. The plurality of termination electrodes 45A are arranged separately from one another, and the termination insulating film 42 is arranged between the plurality of termination electrodes 45A. Fig. Reference 25 is made to the terminal electrode 45A located on one side in the positive Z-axis direction as the terminal electrode 145 and to the terminal electrode 45A located on one side in the negative Z-axis direction as the terminal electrode 45C.

[0076] The arrangement of the multiple termination electrodes 45A in the termination trench 41A can be an arrangement in which the termination electrodes 45A are as in Fig. 25 veranschaulicht in Draufsicht einander überlappen, mit anderen Worten eine Anordnung entlang der Z-Achsenrichtung, oder kann es sich um eine Anordnung entlang der Y-Achsenrichtung oder eine Anordnung entlang der X-Achsenrichtung handeln.

[0077] Furthermore, the in Fig. Figure 25 illustrates how the terminal electrode 144, located on one side in the positive Z-axis direction in the terminal trench 40, and the terminal electrode 145, located on one side in the positive Z-axis direction in the terminal trench 41A, together form the connecting section 144B, which is arranged to extend on the upper surface of the field insulating film 46A, in other words, on the surface of the n-type drift layer 10. The channel stopper electrode 52 is in contact via the connecting section 144B with the exposed terminal electrode 144 in the terminal trench 40 and the exposed terminal electrode 145 in the terminal trench 41A. <Dritte bevorzugte Ausführungsform>

[0078] A semiconductor device and a method for manufacturing a semiconductor device according to the present preferred embodiment are described. Note that in this description, components similar to those described in the embodiments described above are illustrated in the drawings with the same reference numerals, and their detailed description is omitted where necessary. <Konfiguration einer Halbleitervorrichtung>

[0079] Fig. 26 is one along the DD line in Fig. Six sectional views are shown to illustrate another example of the configuration. Fig. For convenience, Figure 26 illustrates some of the components included in the section taken along line DD.

[0080] As in Fig. 26 beispielhaft dargestellt ist, ist eine Vielzahl von Abschlusselektroden in einem einzelnen Abschlussgraben 41B angeordnet. Die Vielzahl von Abschlusselektroden ist getrennt voneinander angeordnet, und der Abschluss-Isolierfilm 42 ist zwischen der Vielzahl von Abschlusselektroden angeordnet. In Fig. Reference 26 to the terminal electrode located at a position at an extreme end on one side in the positive Z-axis direction is referred to as terminal electrode 144, reference 26 to the terminal electrode located at a position at an extreme end on one side in the negative Z-axis direction is referred to as terminal electrode 44D, and reference 26 to the terminal electrode located between terminal electrode 144 and terminal electrode 44D is referred to as terminal electrode 44C. Note that, while in Fig. 26 illustrates a case in which three termination electrodes are formed in a single termination trench; the number of termination electrodes formed in a single termination trench does not correspond to that in the case of Fig. 26 is limited and, for example, four or more terminal electrodes can be formed.

[0081] The arrangement of the numerous termination electrodes in termination trench 41B can be an arrangement in which the termination electrodes are as shown in Fig. Figure 26 illustrates overlapping in a top view, in other words an arrangement along the Z-axis direction, or it can be an arrangement along the Y-axis direction, an arrangement along the X-axis direction, an arrangement in a matrix pattern along a multitude of axis directions, and the like.

[0082] All of the multiple termination electrodes in termination trench 41B can be in contact with the channel stopper electrode 52 to electrically connect the four electrodes. In this case, termination electrode 144, termination electrode 44C, termination electrode 44D, and channel stopper electrode 52 are at the same potential. However, at least one termination electrode among the multiple termination electrodes in termination trench 41B cannot be in contact with the channel stopper electrode 52. <Vierte bevorzugte Ausführungsform>

[0083] A semiconductor device and a method for manufacturing a semiconductor device according to the present preferred embodiment are described. Note that in the following description, components similar to those described in the preferred embodiments described above are illustrated in the drawings with the same reference numerals, and their detailed description is omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0084] Fig. 27 is one along line AA in Fig. Figure 1 shows a sectional view to illustrate a further example of the configuration in the semiconductor device according to the present preferred embodiment. Fig. 27 entspricht entlang der X-Achsenrichtung ein Bereich, in dem der Gate-Graben 20 ausgebildet ist, dem aktiven Bereich 2 und entspricht ein Bereich in der positiven X-Achsenrichtung in Bezug auf den Gate-Graben 20 dem Abschlussbereich 4.

[0085] In the Fig. The 27 illustrated example is in addition to those in Fig. The components illustrated in section 6 have a protective film 60 that covers at least the channel stopper electrode 52. Fig. 27 bedeckt der Schutzfilm 60 zusätzlich zu der Kanalstopper-Elektrode 52 einen Teil der Emitterelektrode 32, die Gate-Elektrode 48 und die Feldplattenelektrode 50. Der Schutzfilm 60 besteht aus beispielsweise einem Siliziumnitridfilm, einem Siliziumoxidfilm, Polyimid oder dergleichen. <Fünfte bevorzugte Ausführungsform>

[0086] A semiconductor device and a method for manufacturing a semiconductor device according to the present preferred embodiment are described. Note that in the following description, components similar to those described in the preferred embodiments described above are illustrated in the drawings with the same reference numerals, and their detailed description is omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0087] Fig. 28 is one along line AA in Fig. Figure 1 shows a sectional view to illustrate a further example of the configuration in the semiconductor device according to the present preferred embodiment. Fig. 28 entspricht entlang der X-Achsenrichtung ein Bereich, in dem der Gate-Graben 20 ausgebildet ist, dem aktiven Bereich 2 und entspricht ein Bereich in der positiven X-Achsenrichtung in Bezug auf den Gate-Graben 20 dem Abschlussbereich 4.

[0088] In the Fig. The illustrated example in 28 is instead of the one in Fig. 6 illustrated channel stopper area 38 of (n+) type a channel stopper area 38A of (n+) type formed.

[0089] In Fig. 28. The termination trench 40 in the drift layer 10 of type n is located closer to the active area 2 than one end (outer end) of the channel stopper area 38A of type (n+) on a side opposite the active area 2. In other words, the outer end of the channel stopper area 38A of type (n+) is located farther away from the active area 2 than the termination trench 40.

[0090] In Fig. 28 The channel stopper area 38A of (n+) type is formed on the surface layer of the charge accumulation area 12 of (n+) type in the termination area 4, in other words, on the surface layer of the drift layer 10 of n type. The channel stopper area 38A of (n+) type is located at a position farther from the active area 2 than the connecting part area 144A, where the channel stopper area 38A of (n+) type does not overlap the connecting part area 144A in plan view. Note that in a case where the connecting part area 144B extending over the two termination trenches is as in Fig. 24 and Fig. Figure 25 illustrates that the channel stopper area 38A of the (n+) type is arranged in a position that is further away from the active area 2 than the connecting part area 144B, where the channel stopper area 38A of the (n+) type does not overlap the connecting part area 144B in plan view.

[0091] The (n+)-type channel stopper region 38A exhibits a higher impurity concentration than the impurity concentration of the (n-type) drift layer 10. The channel stopper electrode 52 is in contact with the upper surface of the (n+)-type channel stopper region 38A, which is exposed from the field insulating film 46.

[0092] In this context, a p-type channel stopper area can be arranged instead of the (n+)-type channel stopper area 38A. Note that the p-type channel stopper area is located in a position similar to that of the (n+)-type channel stopper area 38A and has a higher impurity concentration than that of the n-type drift layer 10.

[0093] With the in Fig.In the configuration illustrated in Figure 28, a fault region where the channel stopper region 38A is to be formed can be activated after the termination electrode in the termination region has been formed and, if required, the field plate 54 and the connection section 144A have been formed. In other words, it is possible to increase the flexibility regarding the timing of the formation of the channel stopper region 38A by means of activation. In a case where the channel stopper region 38A is an n-type fault region, the channel stopper region 38A can be activated simultaneously with, for example, the (n+)-type source region 16 or the (n+)-type charge accumulation region 12 in the active region 2.However, in a case where the channel stopper area 38A is a p-type fault area, the channel stopper area 38A can be activated simultaneously with, for example, the (p+)-type fault area 18 or the p-type channel-doped area 14 in the active area 2. <Durch die Vielzahl der oben beschriebenen bevorzugten Ausführungsformen erzeugte Effekte>

[0094] Next, examples of effects produced by the multitude of preferred embodiments described above are described. Note that, although the following description describes effects based on the specific configurations exemplified by the multitude of preferred embodiments described above, these specific configurations can be replaced by other specific configurations exemplified in this description, as long as similar effects are produced. That is to say, for convenience, only one of the corresponding specific configurations is described as representative in some cases, but the representative specific configuration can be replaced by another corresponding specific configuration.

[0095] Furthermore, the exchange can be carried out among a variety of preferred embodiments. That is, a combination of respective configurations, exemplified in various preferred embodiments, can produce similar effects.

[0096] According to the preferred embodiments described above, the semiconductor device comprises the active region 2 and the termination region 4 surrounding the active region 2 in plan view. The semiconductor device includes the drift layer 10 of a first conductivity type (n-type), the channel-stopper region 38 (or channel-stopper region 38A) of the first conductivity type, a first termination trench, a plurality of termination electrodes, the channel-stopper electrode 52, a defect region of a second conductivity type, the gate trench 20, a plurality of gate electrodes, the interlayer insulating film 26, an electrode on a top surface, and an electrode on a bottom surface. In this context, the first termination trench corresponds, for example, to termination trench 40, termination trench 41B, or the like.Furthermore, the defect region of the second conductivity type corresponds, for example, to the channel-doped region 14 of the p-type or the like. The electrode on the upper surface corresponds, for example, to the emitter electrode 32 or the like. The electrode on the lower surface corresponds, for example, to the collector electrode 30 or the like. The channel stopper region 38 is formed on the surface layer of the drift layer 10 in the termination region 4. Furthermore, the channel stopper region 38 has a higher defect concentration than that of the drift layer 10. The termination trench 40 is formed in the drift layer 10 in the termination region 4. The plurality of termination electrodes are arranged in the termination trench 40 and are surrounded by a first termination insulating film. In this context, the first termination insulating film corresponds, for example, to the termination insulating film 42 or the like.The channel stopper electrode 52 is electrically connected to the channel stopper region 38 and at least one termination electrode. Furthermore, the channel stopper electrode 52 is arranged on the upper surface of the drift layer 10. The p-type channel-doped region 14 is formed on the surface layer of the drift layer 10 in the active region 2. The gate trench 20 is formed in the drift layer 10 and is adjacent to the p-type channel-doped region 14. The plurality of gate electrodes are arranged in the gate trench 20 and are surrounded by the gate insulating film 22. The interlayer insulating film 26 is arranged to cover the gate trench 20. The emitter electrode 32 is arranged to cover the upper surface of the drift layer 10 and the interlayer insulating film 26. The collector electrode 30 is arranged on the lower surface of the drift layer 10 at least in the active region 2.The plurality of termination electrodes in termination trench 40 comprises a first termination electrode and a second termination electrode. In this context, the first termination electrode corresponds, for example, to termination electrode 44A, termination electrode 144, or the like. Furthermore, the second termination electrode corresponds, for example, to termination electrode 44B, termination electrode 44D, or the like. The plurality of gate electrodes comprises a first gate electrode and a second gate electrode. In this context, the first gate electrode corresponds, for example, to gate electrode 24A or the like. Furthermore, the second gate electrode corresponds, for example, to gate electrode 24B or the like. Termination electrode 44A and termination electrode 44B are arranged separately from each other in termination trench 40. Gate electrode 24A and gate electrode 24B are arranged separately from each other in gate trench 20.

[0097] This configuration, in which the multiple termination electrodes are arranged in the single termination trench, improves flexibility in controlling a depletion layer. Furthermore, a channel stopper area can be formed with greater flexibility in position. Additionally, if the multiple termination electrodes in the termination trench and the multiple gate electrodes in the gate trench are arranged along the same direction, the termination electrodes and the gate electrodes can be easily fabricated in the same step.

[0098] Note that similar effects can also be produced in a case where another component, as exemplified in the present description, is appropriately added to the components described above, that is to say, in a case where another component, which is not mentioned as one of the components described above but is included in the present description, is appropriately added.

[0099] Furthermore, according to the preferred embodiments described above, the semiconductor device comprises the active region 2 and the termination region 4 surrounding the active region 2 in a top view. The semiconductor device includes the n-type drift layer 10, the channel stopper region 38A, the termination trench 40A, a plurality of termination electrodes, the channel stopper electrode 52, the p-type channel-doped region 14, the gate trench 20, a plurality of gate electrodes, the interlayer insulating film 26, the emitter electrode 32, and the collector electrode 30. The channel stopper region 38A is formed on the surface layer of the drift layer 10 in the termination region 4. Furthermore, the channel stopper region 38A has a higher impurity concentration than that of the drift layer 10. The termination trench 40 is formed in the drift layer 10 in the termination region 4.The plurality of termination electrodes is arranged in the termination trench 40 and surrounded by the termination insulating film 42. The channel stopper electrode 52 is electrically connected to the channel stopper region 38A and at least one termination electrode. The channel stopper electrode 52 is further arranged on the upper surface of the drift layer 10. The p-type channel-doped region 14 is formed on the surface layer of the drift layer 10 in the active region 2. The gate trench 20 is formed in the drift layer 10 and is adjacent to the p-type channel-doped region 14. The plurality of gate electrodes is arranged in the gate trench 20 and surrounded by the gate insulating film 22. The interlayer insulating film 26 is arranged to cover the gate trench 20. The emitter electrode 32 is arranged such that it covers the upper surface of the drift layer 10 and the interlayer insulating film 26.The collector electrode 30 is located on the lower surface of the drift layer 10, at least within the active region 2. The termination trench 40 is located in the drift layer 10 at a position closer to the active region 2 than an outer end of the channel stopper region 38A, i.e., an end on the side opposite the active region 2. The plurality of termination electrodes in the termination trench 40 comprises the termination electrode 144 and the termination electrode 44B. The plurality of gate electrodes comprises the gate electrode 24A and the gate electrode 24B. The termination electrode 44A and the termination electrode 44B are arranged separately from each other in the termination trench 40. The gate electrode 24A and the gate electrode 24B are arranged separately from each other in the gate trench 20.

[0100] With this configuration, in which the multiple termination electrodes are arranged in the single termination trench, flexibility in controlling a depletion layer can be improved. Furthermore, the conductivity type of the channel stopper area is not limited. Additionally, if the multiple termination electrodes in the termination area and the multiple gate electrodes in the gate trench are arranged along the same direction, the termination electrodes and the gate electrodes can be easily fabricated in the same step.

[0101] Note that similar effects can be produced even if a further component, as exemplified in the present description, is appropriately added to the components described above, i.e., even if a further component, which is not mentioned as one of the components described above but is included in the present description, is appropriately added.

[0102] Furthermore, in the preferred embodiments described above, at least a portion of the termination electrode 44A is arranged such that it covers the termination electrode 44B in a top view. At least a portion of the gate electrode 24A is arranged such that it covers the gate electrode 24B in a top view. With this configuration, the plurality of termination electrodes in the termination trench and the plurality of gate electrodes in the gate trench are arranged such that they overlap each other in a top view (in other words, they are arranged along the same direction), and thus the termination electrodes and the gate electrodes can be easily manufactured in the same step.

[0103] According to the preferred embodiments described above, at least one termination electrode connected to the channel stopper electrode 52 further comprises the connection part area 144A (or the connection part area 144B), which is arranged to extend onto the upper surface of the drift layer 10. This configuration increases the contact area between the channel stopper electrode 52 and the termination electrode 144, which stabilizes the connection between the two electrodes and thereby improves the reliability of the semiconductor device.

[0104] Furthermore, according to the preferred embodiments described above, the channel stopper area 38A is arranged at a position further away from the active area 2 than the connecting part area 144A (or the connecting part area 144B), where, in plan view, the channel stopper area 38A does not overlap the connecting part area 144A (or the connecting part area 144B). With this configuration, a fault area in which the channel stopper area 38A is to be formed can be activated after the termination electrode in the termination trench has been formed and, if necessary, the field plate 54 and the connecting part area 144A (or the connecting part area 144B) have also been formed. In other words, it is possible to increase the flexibility in the timing of the formation of the channel stopper area 38A by means of activation.

[0105] According to the preferred embodiments described above, both the termination electrode 44A and the termination electrode 44B are electrically connected to the channel stopper electrode 52. With this configuration, the plurality of termination electrodes placed in the single termination trench are at the same potential and are thus stabilized, which increases the accuracy in controlling a depletion layer.

[0106] According to the preferred embodiments described above, the termination electrode 44B is not electrically connected to the channel stopper electrode 52. This configuration increases the flexibility in controlling a depletion layer by using the termination electrode 44B as a potential-free electrode. Furthermore, it is not necessary to form a contact area to bring the termination electrode 44B and the channel stopper electrode 52 into contact, thus eliminating the need to change the formation area using different masks when forming the termination electrode 44B, resulting in a reduction of the number of masks and steps.

[0107] According to the preferred embodiments described above, the semiconductor device further comprises a second termination trench formed in the drift layer 10 in the termination region 4. In this context, the second termination trench corresponds, for example, to termination trench 41, termination trench 41A, or the like. The plurality of termination electrodes are also arranged in the termination trench 41 and are surrounded by a second termination insulating film. In this context, the second termination insulating film corresponds, for example, to termination insulating film 42 or the like. The channel stopper electrode 52 is arranged on the upper surface of the drift layer 10 and is electrically connected to the channel stopper region 38, at least one termination electrode in termination trench 40, and at least one termination electrode in termination trench 41.The array of termination electrodes in termination trench 41 includes a third termination electrode and a fourth termination electrode. In this context, the third termination electrode corresponds, for example, to termination electrode 145 or the like. The fourth termination electrode corresponds, for example, to termination electrode 45B, termination electrode 45C, or the like. Termination electrode 145 and termination electrode 45B are arranged separately from each other in termination trench 41. This configuration, in which the array of termination electrodes is arranged in each of the arrays of termination trenches, increases the flexibility in controlling a depletion layer.

[0108] According to the preferred embodiments described above, at least a portion of the termination electrode 145 is further arranged such that it overlaps the termination electrode 45B in plan view. With this configuration, in which the plurality of termination electrodes in each of the plurality of termination trenches and the plurality of gate electrodes in the gate trench are arranged such that they overlap each other in plan view (in other words, are arranged along the same direction), the termination electrodes and the gate electrodes can be easily manufactured in the same step.

[0109] According to the preferred embodiments described above, the termination trench 41 is further positioned at a location farther from the active region 2 than the termination trench 40. Furthermore, the termination trench 41 is deeper than the termination trench 40. This configuration facilitates the placement of the termination electrodes along an outer edge of a depletion layer extending from the upper surface of the drift layer 10 from the active region 2 towards the termination region 4. Therefore, depletion of the layer can be effectively suppressed.

[0110] According to the preferred embodiments described above, the plurality of termination electrodes in termination trench 41B further comprises a fifth termination electrode. In this context, the fifth termination electrode corresponds, for example, to termination electrode 44C or the like. Termination electrode 44C is arranged in termination trench 41B separately from termination electrode 144 and termination electrode 44D. With this configuration, in which the three termination electrodes are arranged in the single termination trench, the flexibility in controlling a depletion layer can be increased.

[0111] According to the preferred embodiments described above, the semiconductor device further comprises the protective film 60, which is arranged to cover the channel stopper electrode 52. With this configuration, in which the channel stopper electrode 52 is covered by the protective film 60, the breakdown voltage and the reliability of the semiconductor device can be improved.

[0112] According to the preferred embodiments described above, the semiconductor device further comprises the (n+)-type charge accumulation region 12, which is located below the channel stopper region 38 and adjacent to the termination trench 40. The charge accumulation region 12 has a defect concentration that is higher than that of the drift layer 10 and lower than that of the channel stopper region 38. With this configuration, a depletion layer can be effectively suppressed.

[0113] According to the embodiments described above, in the method for manufacturing a semiconductor device, the p-type channel-doped region 14 is formed on the surface layer of the n-type drift layer 10 in the active region 2. The first-type conductivity channel stopper region 38, with a higher impurity concentration than that of the drift layer 10, is then formed on the surface layer of the drift layer 10 in the termination region 4. Subsequently, the gate trench 20 is formed in the drift layer 10 at a position adjacent to the p-type channel-doped region 14 in the active region 2, and the termination trench 40 is formed in the drift layer 10 in the termination region 4. The gate insulating film 22 and the termination insulating film 42 are then formed in the gate trench 20 and the termination trench 40, respectively.Subsequently, a plurality of gate electrodes surrounded by the gate insulating film 22 and a plurality of termination electrodes surrounded by the termination insulating film 42 are formed in the gate trench 20 and the termination trench 40, respectively. The intermediate insulating film 26 covering the gate trench 20 is then formed. The channel stopper electrode 52, electrically connected to the channel stopper region 38 and at least one termination electrode, is then formed on the upper surface of the drift layer 10. The emitter electrode 22, covering the upper surface of the drift layer 10 and the intermediate insulating film 26, is then formed. The collector electrode 30 is then formed on the lower surface of the drift layer 10, at least in the active region 2. In this context, the plurality of termination electrodes includes the termination electrode 44A and the termination electrode 44B. Furthermore, the multitude of gate electrodes includes the gate electrode 24A and the gate electrode 24B.The terminal electrode 44A and the terminal electrode 44B are furthermore arranged separately from each other in the terminal trench 40. Furthermore, the gate electrode 24A and the gate electrode 24B are arranged separately from each other in the gate trench 20.

[0114] This configuration, in which the multiple termination electrodes are arranged in the single termination trench, improves flexibility in controlling a depletion layer. Furthermore, a channel stopper area can be formed with greater flexibility in position. Additionally, if the multiple termination electrodes in the termination trench and the multiple gate electrodes in the gate trench are arranged along the same direction, the termination electrodes and the gate electrodes can be easily fabricated in the same step.

[0115] Please note that the order in which the respective processes are carried out may be changed unless otherwise specified.

[0116] Furthermore, similar effects can also be produced in a case where another component, as exemplified in the present description, is added to the components described above in a suitable manner, that is to say, also in a case where another component, which is not mentioned as one of the components described above but is included in the present description, is added in a suitable manner.

[0117] Furthermore, according to the preferred embodiments described above, in the method for manufacturing a semiconductor device, the channel-doped region 14 of the p-type is formed on the surface layer of the drift layer 10 of the n-type in the active region 2. The channel-stopper region 38A, with a higher impurity concentration than that of the drift layer 10, is then formed on the surface layer of the drift layer 10 in the termination region 4. The gate trench 20 is then formed in the drift layer 10 at a position adjacent to the channel-doped region 14 of the p-type in the active region 2, and the termination trench 40 is formed in the drift layer 10 in the termination region 4. The gate insulating film 22 and the termination insulating film 42 are then formed in the gate trench 20 and the termination trench 40, respectively.Subsequently, a plurality of gate electrodes surrounded by the gate insulating film 22 and a plurality of termination electrodes surrounded by the termination insulating film 42 are formed in the gate trench 20 and the termination trench 40, respectively. The intermediate insulating film 26 covering the gate trench 20 is then formed. The channel stopper electrode 52, electrically connected to the channel stopper region 38A and at least one termination electrode, is then formed on the upper surface of the drift layer 10. The emitter electrode 32, covering the upper surface of the drift layer 10 and the intermediate insulating film 26, is then formed. The collector electrode 30 is then formed on the lower surface of the drift layer 10, at least in the active region 2.In this context, the termination trench 40 is formed in the drift layer 10 at a position closer to the active region 2 than an outer end of the channel stopper region 38A, that is, an end on a side opposite the active region 2. The plurality of termination electrodes further comprises termination electrode 44A and termination electrode 44B. The plurality of gate electrodes further comprises gate electrode 24A and gate electrode 24B. Termination electrode 44A and termination electrode 44B are also arranged separately from each other in termination trench 40. Gate electrode 24A and gate electrode 24B are also arranged separately from each other in gate trench 20.

[0118] With this configuration, where the multiple termination electrodes are arranged in the single termination trench, flexibility in controlling a depletion layer can be improved. Furthermore, the conductivity type of the channel stopper area is not limited. In addition, if the multiple termination electrodes in the termination trench and the multiple gate electrodes in the gate trench are arranged along the same direction, the termination electrodes and the gate electrodes can be easily fabricated in the same step.

[0119] Please note that the order in which the respective processes are carried out may be changed unless otherwise specified.

[0120] Furthermore, similar effects can be produced even in a case where a further component, as exemplified in the present description, is appropriately added to the components described above, that is to say, even in a case where a further component, which is not mentioned as one of the components described above but is included in the present description, is appropriately added.

[0121] According to the preferred embodiment described above, forming the plurality of termination electrodes further comprises forming at least one termination electrode connected to the channel stopper electrode 52 such that it includes the connection part area 144A (or the connection part area 144B) which is arranged to extend onto the upper surface of the drift layer 10, and comprises forming the channel stopper area 38A at a position farther from the active area 2 than the connection part area 144A (or the connection part area 144B), where the channel stopper area 38A does not overlap the connection part area in plan view. After the plurality of termination electrodes has been formed, areas of the same conductivity type in the active area 2 and the channel stopper area 38A are then activated simultaneously.With this configuration, a fault zone where the channel stopper zone 38A is to be formed can be activated after the termination electrode in the termination trench has been formed and, if necessary, the field plate 54 and the connection section 144A (or the connection section 144B) have also been formed. In other words, it is possible to increase the flexibility in the timing of the formation of the channel stopper zone 38A by means of activation. In a case where the channel stopper zone 38A is an n-type fault zone, the channel stopper zone 38A can be activated simultaneously with, for example, the (n+)-type source zone 16 or the (n+)-type charge accumulation zone 12 in active zone 2.However, in a case where the channel stopper area 38A is a fault area of ​​the p-type, the channel stopper area 38A can be activated simultaneously with, for example, the fault area 18 of the (p+)-type or the channel-doped area 14 of the p-type in the active area 2. <Modifikationen der oben beschriebenen bevorzugten Ausführungsformen>

[0122] In the preferred embodiments described above, properties, materials, dimensions, shapes, relative positions, conditions for implementation and the like of the respective components are described in some cases, but these are in every respect merely examples and not limiting.

[0123] Therefore, countless modifications and equivalents, examples of which have not been described, are conceivable within the scope of the technology disclosed in this description. For example, a case in which at least one component is modified, added, or omitted, and a case in which at least one component is extracted in at least one preferred embodiment and combined with a component in another embodiment are included.

[0124] Furthermore, in at least one preferred embodiment described above, in a case where a material designation or the like is described without specific indications, it is assumed, for example, that the material includes other additives such as an alloy, unless a contradiction arises.

[0125] Furthermore, in a case where, in the preferred embodiments described above, it is stated that “one” component is arranged, it means that “one or more” components may be arranged, provided that no contradiction arises.

[0126] Furthermore, in the preferred embodiments described above, each component is a conceptual unit, and the scope of the technology disclosed in the present description includes a case in which a component comprises a plurality of structures, a case in which a component corresponds to a part of a particular structure, and a case in which a plurality of components are contained in a structure.

[0127] Each component in the preferred embodiments described above further comprises a structure with a different configuration or shape, as long as the same function is fulfilled.

[0128] Reference is further made to the description in the present description for all purposes relating to the present technology, and nothing therein is recognized as prior art.

[0129] Furthermore, in the preferred embodiments described above, the semiconductor substrate is of an n-type, but can also be of a p-type. Moreover, in the preferred embodiments described above, the IGBT was described as an example of the semiconductor device, but it is also conceivable that the example of the semiconductor device could be a metal-oxide-semiconductor field-effect transistor (i.e., MOSFET).

[0130] Note that in a case where the semiconductor device example is a MOSFET, an emitter electrode corresponds to a source electrode and a collector electrode corresponds to a drain electrode.

[0131] In the preferred embodiments described above, it was further described that the first conductivity type is an n-type and the second conductivity type is a p-type; however, they can be reversed, i.e., the first conductivity type can be a p-type and the second conductivity type can be an n-type.

[0132] The following sections describe various aspects of the present revelation together as appendices. (Annex 1)

[0133] A semiconductor device comprising an active region and a termination region surrounding the active region in plan view, comprising: a drift layer of a first conductivity type; a channel stopper region of the first conductivity type, which is formed on a surface layer of the drift layer in the termination region and has a higher impurity concentration than that of the drift layer; a first termination trench that is formed in the drift layer in the termination area; a multitude of termination electrodes which, while surrounded by a first termination insulating film, are arranged in the first termination trench; a channel stopper electrode that is located on an upper surface of the drift layer while being electrically connected to the channel stopper area and at least one of the termination electrodes; a defect area of ​​a second conductivity type, which is formed on the surface layer of the drift layer in the active area; a gate trench formed in the drift layer while adjacent to the fault area; a multitude of gate electrodes arranged in the gate trench while surrounded by a gate insulating film; an intermediate layer insulating film arranged to cover the gate trench; an electrode on an upper surface arranged to cover the upper surface of the drift layer and the interlayer insulating film; and an electrode on a lower surface, which is located on a lower surface of the drift layer at least in the active area, where the multitude of termination electrodes in the first termination trench includes a first termination electrode and a second termination electrode, the multitude of gate electrodes includes a first gate electrode and a second gate electrode, the first terminal electrode and the second terminal electrode are arranged separately from each other in the first terminal trench and The first gate electrode and the second gate electrode are arranged separately from each other in the gate trench. (Annex 2)

[0134] A semiconductor device comprising an active region and a termination region surrounding the active region in plan view, comprising: a drift layer of a first conductivity type; a channel stopper area that is formed on a surface layer of the drift layer in the termination area and has a higher concentration of defects than that of the drift layer; a first termination trench that is formed in the drift layer in the termination area; a multitude of termination electrodes which, while surrounded by a first termination insulating film, are arranged in the first termination trench; a channel stopper electrode that is located on an upper surface of the drift layer while being electrically connected to the channel stopper area and at least one of the termination electrodes; a defect area of ​​a second conductivity type, which is formed on the surface layer of the drift layer in the active area; a gate trench formed in the drift layer while adjacent to the fault area; a multitude of gate electrodes arranged in the gate trench while surrounded by a gate insulating film; an intermediate layer insulating film arranged to cover the gate trench; an electrode on an upper surface arranged to cover the upper surface of the drift layer and the interlayer insulating film; and an electrode on a lower surface, which is formed on a lower surface of the drift layer at least in the active area, where the first termination trench in the drift layer is formed at a position closer to the active area than an outer end of the channel stopper area, the outer end being an end on a side opposite the active area, the multitude of termination electrodes in the first termination trench includes a first termination electrode and a second termination electrode, the multitude of gate electrodes includes a first gate electrode and a second gate electrode, the first terminal electrode and the second terminal electrode are arranged separately from each other in the first terminal trench and The first gate electrode and the second gate electrode are arranged separately from each other in the gate trench. (Annex 3)

[0135] The semiconductor device according to Annex 1 or 2, wherein at least part of the first terminal electrode is arranged in such a way that it overlaps the second terminal electrode in top view, and at least part of the first gate electrode is arranged in such a way that it overlaps the second gate electrode in top view. (Annex 4)

[0136] The semiconductor device according to one of Annexes 1 to 3, wherein the at least one termination electrode connected to the channel stopper electrode further comprises a connecting part area arranged to extend on the upper surface of the drift layer. (Annex 5)

[0137] The semiconductor device according to Annex 4, wherein the channel stopper area is located at a position further away from the active area than the interconnecting part area, where the channel stopper area does not overlap the interconnecting part area in plan view. (Annex 6)

[0138] The semiconductor device according to one of Annexes 1 to 5, wherein both the first termination electrode and the second termination electrode are electrically connected to the channel stopper electrode. (Annex 7)

[0139] The semiconductor device according to one of Annexes 1 to 5, wherein the second termination electrode is not electrically connected to the channel stopper electrode. (Annex 8)

[0140] The semiconductor device according to one of Annexes 1 to 7, further comprising a second termination trench formed in the drift layer in the termination area, where the multitude of termination electrodes are also arranged in the second termination trench, while they are surrounded by a second termination insulating film, the channel stopper electrode is located on the upper surface of the drift layer, while it is electrically connected to the channel stopper area, at least one of the termination electrodes in the first termination trench and at least one of the termination electrodes in the second termination trench, the multitude of terminal electrodes in the second terminal trench includes a third terminal electrode and a fourth terminal electrode and the third terminal electrode and the fourth terminal electrode are arranged separately from each other in the second terminal trench. (Annex 9)

[0141] The semiconductor device according to Annex 8, wherein at least part of the third termination electrode is arranged such that it overlaps the fourth termination electrode in plan view. (Annex 10)

[0142] The semiconductor device according to Annex 8 or 9, wherein the second containment trench is constructed in a position that is further away from the active area than the first containment trench, and the second sealing trench is deeper than the first sealing trench. (Annex 11)

[0143] The semiconductor device according to one of Annexes 1 to 10, wherein the multitude of terminal electrodes in the first terminal trench also includes a fifth terminal electrode and The fifth terminal electrode is arranged separately from the first terminal electrode and the second terminal electrode in the first terminal trench. (Annex 12)

[0144] The semiconductor device according to one of Annexes 1 to 11, further comprising a protective film arranged to cover the channel stopper electrode. (Annex 13)

[0145] The semiconductor device according to one of Annexes 1 to 12, further comprising a charge accumulation region of the first conductivity type, which is arranged below the channel stopper region while adjacent to the first termination trench, the charge accumulation area has a defect concentration that is higher than that of the drift layer and lower than that of the channel stopper area. (Annex 14)

[0146] A method for manufacturing a semiconductor device comprising an active region and a termination region surrounding the active region in a top view: Formation of a defect area of ​​a second conductivity type on a surface layer of a drift layer of a first conductivity type in the active area; Formation of a channel stopper region of the first conductivity type with a higher impurity concentration than that of the drift layer on the surface layer of the drift layer in the termination region; Formation of a gate trench in the drift layer at a position adjacent to the fault area in the active area and formation of a first closure trench in the drift layer in the closure area; Forming a gate insulating film and a first termination insulating film in the gate trench or the first termination trench; Forming a multitude of gate electrodes surrounded by gate insulating film and a multitude of termination electrodes surrounded by first termination insulating film in the gate trench or first termination trench; Forming an intermediate layer insulating film that covers the gate trench; Forming a channel stopper electrode that is electrically connected to the channel stopper area and at least one of the termination electrodes on an upper surface of the drift layer; Forming an electrode on an upper surface that covers the upper surface of the drift layer and the interlayer insulating film; and Forming an electrode on a lower surface of the drift layer, at least in the active area, where the multitude of terminal electrodes includes a first terminal electrode and a second terminal electrode, the multitude of gate electrodes includes a first gate electrode and a second gate electrode, the first terminal electrode and the second terminal electrode are arranged separately from each other in the first terminal trench and The first gate electrode and the second gate electrode are arranged separately from each other in the gate trench. (Annex 15)

[0147] A method for manufacturing a semiconductor device comprising an active region and a termination region surrounding the active region in a top view: Formation of a defect area of ​​a second conductivity type on a surface layer of the drift layer of a first conductivity type in the active area; Formation of a channel stopper area with a higher impurity concentration than that of the drift layer on the surface layer of the drift layer in the termination area; Formation of a gate trench in the drift layer at a position adjacent to the fault area in the active area and formation of a first closure trench in the drift layer in the closure area; Forming a gate insulating film and a first termination insulating film in the gate trench or the first termination trench; Forming a multitude of gate electrodes surrounded by gate insulating film and a multitude of termination electrodes surrounded by first termination insulating film in the gate trench or first termination trench; Forming an intermediate layer insulating film that covers the gate trench; Forming a channel stopper electrode that is electrically connected to the channel stopper area and at least one of the termination electrodes on an upper surface of the drift layer; Forming an electrode on an upper surface that covers the upper surface of the drift layer and the interlayer insulating film; and Forming an electrode on a lower surface of the drift layer, at least in the active area, where the first termination trench in the drift layer is formed at a position closer to the active area than an outer end of the channel stopper area, the outer end being an end on a side opposite the active area, the multitude of terminal electrodes includes a first terminal electrode and a second terminal electrode, the multitude of gate electrodes includes a first gate electrode and a second gate electrode, the first terminal electrode and the second terminal electrode are arranged separately from each other in the first terminal trench and The first gate electrode and the second gate electrode are arranged separately from each other in the gate trench. (Annex 16)

[0148] The method for manufacturing the semiconductor device according to Annex 15, wherein forming the plurality of termination electrodes, forming the terminal electrode connected to the channel stopper electrode, includes at least one termination electrode, such that it has a connecting part area arranged to extend on the upper surface of the drift layer, Forming the channel stopper area includes forming the channel stopper area at a position that is further away from the active area than the connecting part area, wherein the channel stopper area does not overlap the connecting part area in plan view, and

[0149] Areas of the same conductivity type in the active area and the channel stopper area are activated simultaneously after the multitude of termination electrodes has formed.

[0150] Although the revelation has been presented and described in detail, the preceding description is illustrative in all aspects and not limiting. It is therefore understood that numerous modifications and variations can be conceived.

Claims

[1] Semiconductor device comprising an active region (2) and a termination region (4) surrounding the active region (2) in plan view: a drift layer (10) of a first conductivity type; a channel stopper region (38, 38A) of the first conductivity type, which is formed on a surface layer of the drift layer (10) in the termination region (4) and has a higher impurity concentration than that of the drift layer (10); a first termination trench (40, 41B) which is formed in the drift layer (10) in the termination area (4); a plurality of termination electrodes which, while surrounded by a first termination insulating film (42), are arranged in the first termination trench (40, 41B); a channel stopper electrode (52) which is arranged on an upper surface of the drift layer (10) while being electrically connected to the channel stopper area (38, 38A) and at least one of the termination electrodes; a defect area (14) of a second conductivity type, which is formed on the surface layer of the drift layer (10) in the active area (2); a gate trench (20) formed in the drift layer (10) while adjacent to the fault area (14); a plurality of gate electrodes which, while surrounded by a gate insulating film (22), are arranged in the gate trench (20); an intermediate layer insulating film (26) arranged to cover the gate trench (20); an electrode (32) on an upper surface, arranged to cover the upper surface of the drift layer (10) and the interlayer insulating film (26); and an electrode (30) on a lower surface, which is arranged on a lower surface of the drift layer (10) at least in the active region (2), where the multitude of termination electrodes in the first termination trench (40, 41B) includes a first termination electrode (44A, 144) and a second termination electrode (44B, 44D), the multitude of gate electrodes includes a first gate electrode (24A) and a second gate electrode (24B), the first termination electrode (44A, 144) and the second termination electrode (44B, 44D) are arranged separately from each other in the first termination trench (40, 41B) and the first gate electrode (24A) and the second gate electrode (24B) are arranged separately from each other in the gate trench (20). [2] Semiconductor device comprising an active region (2) and a termination region (4) surrounding the active region (2) in plan view: a drift layer (10) of a first conductivity type; a channel stopper area (38A) which is formed on a surface layer of the drift layer (10) in the termination area (4) and has a higher concentration of defects than that of the drift layer (10); a first termination trench (40, 41B) which is formed in the drift layer (10) in the termination area (4); a plurality of termination electrodes which, while surrounded by a first termination insulating film (42), are arranged in the first termination trench (40, 41A); a channel stopper electrode (52) which is arranged on an upper surface of the drift layer (10) while being electrically connected to the channel stopper area (38A) and at least one of the termination electrodes; a defect area (14) of a second conductivity type, which is formed on the surface layer of the drift layer (10) in the active area (2); a gate trench (20) formed in the drift layer (10) while adjacent to the fault area (14); a plurality of gate electrodes which, while surrounded by a gate insulating film (22), are arranged in the gate trench (20); an intermediate layer insulating film (26) arranged to cover the gate trench (20); an electrode (32) on an upper surface, arranged to cover the upper surface of the drift layer (10) and the interlayer insulating film (26); and an electrode (30) on a lower surface, which is formed on a lower surface of the drift layer (10) at least in the active region (2), where the first termination trench (40, 41B) in the drift layer (10) is formed at a position closer to the active area (2) than an outer end of the channel stopper area (38A), the outer end being an end on a side opposite the active area (2), the multitude of termination electrodes in the first termination trench (40, 41B) includes a first termination electrode (44A, 144) and a second termination electrode (44B, 44D), the multitude of gate electrodes includes a first gate electrode (24A) and a second gate electrode (24B), the first termination electrode (44A, 144) and the second termination electrode (44B, 44D) are arranged separately from each other in the first termination trench (40, 41B) and the first gate electrode (24A) and the second gate electrode (24B) are arranged separately from each other in the gate trench (20). [3] Semiconductor device according to claim 1 or 2, wherein at least part of the first terminal electrode (44A, 144) is arranged such that it overlaps the second terminal electrode (44B, 44D) in top view, and at least part of the first gate electrode (24A) is arranged such that it overlaps the second gate electrode (24B) in top view. [4] Semiconductor device according to one of claims 1 to 3, wherein the at least one termination electrode connected to the channel stopper electrode (52) further comprises a connecting part area (144A, 144B) arranged to extend on the upper surface of the drift layer (10). [5] Semiconductor device according to claim 4, wherein the channel stopper area (38A) is arranged at a position that is further away from the active area (2) than the interconnecting part area (144A, 144B), where the channel stopper area (38A) does not overlap the interconnecting part area (144A, 144B) in plan view. [6] Semiconductor device according to any one of claims 1 to 5, wherein both the first termination electrode (44A, 144) and the second termination electrode (44B, 44D) are electrically connected to the channel stopper electrode (52). [7] Semiconductor device according to any one of claims 1 to 5, wherein the second termination electrode (44B, 44D) is not electrically connected to the channel stopper electrode (52). [8] Semiconductor device according to one of claims 1 to 7, further comprising a second termination trench (41, 41A) formed in the drift layer (10) in the termination area (4), where the multitude of termination electrodes are also arranged in the second termination trench (41, 41A), while they are surrounded by a second termination insulating film (42), the channel stopper electrode (52) is arranged on the upper surface of the drift layer (10), while it is electrically connected to the channel stopper area (38, 38A), at least one of the termination electrodes in the first termination trench (40, 41B) and at least one of the termination electrodes in the second termination trench (41, 41A), the multiple termination electrodes in the second termination trench (41, 41A) include a third termination electrode (145) and a fourth termination electrode (45B, 45C) and the third terminal electrode (145) and the fourth terminal electrode (45B, 45C) are arranged separately from each other in the second terminal trench (41, 41A). [9] Semiconductor device according to claim 8, wherein at least part of the third terminal electrode (145) is arranged such that it overlaps the fourth terminal electrode (45B, 45C) in top view. [10] Semiconductor device according to claim 8 or 9, wherein the second termination trench (41, 41A) is formed at a position that is further away from the active area (2) than the first termination trench (40, 41B), and the second termination trench (41, 41A) is deeper than the first termination trench (40, 41B). [11] Semiconductor device according to any one of claims 1 to 10, wherein the multiple terminal electrodes in the first terminal trench (41B) further includes a fifth terminal electrode (44C) and the fifth terminal electrode (44C) is arranged in the first terminal trench (40, 41B) separately from the first terminal electrode (144) and the second terminal electrode (44D). [12] Semiconductor device according to any one of claims 1 to 11, further comprising a protective film (60) arranged to cover the channel stopper electrode (52). [13] Semiconductor device according to any one of claims 1 to 12, further comprising a charge accumulation region (12) of the first conductivity type, which is arranged below the channel stopper region (38, 38A) while being adjacent to the first termination trench (40, 41B), wherein the charge accumulation region (12) has a defect concentration which is higher than that of the drift layer (10) and lower than that of the channel stopper region (38, 38A). [14] Method for manufacturing a semiconductor device comprising an active region (2) and a termination region (4) surrounding the active region (2) in plan view: Formation of a defect area (14) of a second conductivity type on a surface layer of a drift layer (10) of a first conductivity type in the active area (2); Formation of a channel stopper region (38, 38A) of the first conductivity type with a higher impurity concentration than that of the drift layer (10) on the surface layer of the drift layer (10) in the termination region (4); Forming a gate trench (20) in the drift layer (10) at a position adjacent to the fault area (14) in the active area (2) and forming a first closure trench (40, 41B) in the drift layer (10) in the closure area (4); Forming a gate insulating film (22) and a first termination insulating film (42) in the gate trench (20) and the first termination trench (40, 41B), respectively; Forming a plurality of gate electrodes surrounded by the gate insulating film (22) and a plurality of termination electrodes surrounded by the first termination insulating film (42) in the gate trench (20) and the first termination trench (40, 41B), respectively; Forming an intermediate layer insulating film (26) covering the gate trench (20); Forming a channel stopper electrode (52) which is electrically connected to the channel stopper region (38, 38A) and at least one of the termination electrodes on an upper surface of the drift layer (10); Forming an electrode (32) on an upper surface covering the upper surface of the drift layer (10) and the interlayer insulating film (26); and Forming an electrode (30) on a lower surface of the drift layer (10) at least in the active area (2), where the multitude of terminal electrodes includes a first terminal electrode (44A, 144) and a second terminal electrode (44B, 44D), the multitude of gate electrodes includes a first gate electrode (24A) and a second gate electrode (24B), the first termination electrode (44A, 144) and the second termination electrode (44B, 44D) are arranged separately from each other in the first termination trench (40, 41B) and the first gate electrode (24A) and the second gate electrode (24B) are arranged separately from each other in the gate trench (20). [15] Method for manufacturing a semiconductor device comprising an active region (2) and a termination region (4) surrounding the active region (2) in plan view: Formation of a defect area (14) of a second conductivity type on a surface layer of the drift layer (10) of a first conductivity type in the active area (2); Forming a channel stopper area (38A) with a higher impurity concentration than that of the drift layer (10) on the surface layer of the drift layer (10) in the termination area (4); Forming a gate trench (20) in the drift layer (10) at a position adjacent to the fault area (14) in the active area (2) and forming a first closure trench (40, 41B) in the drift layer (10) in the closure area (4); Forming a gate insulating film (22) and a first termination insulating film (42) in the gate trench (20) and the first termination trench (40, 41B), respectively; Forming a plurality of gate electrodes surrounded by the gate insulating film (22) and a plurality of termination electrodes surrounded by the first termination insulating film (42) in the gate trench (20) or the first termination trench (40, 41B); Forming an intermediate layer insulating film (26) covering the gate trench (20); Forming a channel stopper electrode (52) which is electrically connected to the channel stopper area (38A) and at least one of the termination electrodes on an upper surface of the drift layer (10); Forming an electrode (32) on an upper surface covering the upper surface of the drift layer (10) and the interlayer insulating film (26); and Forming an electrode (30) on a lower surface of the drift layer (10) at least in the active area (2), where the first termination trench (40, 41B) in the drift layer (10) is formed at a position closer to the active area (2) than an outer end of the channel stopper area (38A), the outer end being an end on a side opposite the active area (2), the multitude of terminal electrodes includes a first terminal electrode (44A, 144) and a second terminal electrode (44B, 44D), the multitude of gate electrodes includes a first gate electrode (24A) and a second gate electrode (24B), the first termination electrode (44A, 144) and the second termination electrode (44B, 44D) are arranged separately from each other in the first termination trench (40, 41B) and the first gate electrode (24A) and the second gate electrode (24B) are arranged separately from each other in the gate trench (20). [16] Method for manufacturing the semiconductor device according to claim 15, wherein forming the plurality of termination electrodes, forming the terminal electrode connected to the channel stopper electrode (52), comprising at least one termination electrode, such that it has a connecting part area (144A, 144B) which is arranged to extend on the upper surface of the drift layer (10), forming the channel stopper area (38A) comprises forming the channel stopper area (38A) at a position that is further away from the active area (2) than the connecting part area (144A, 144B), wherein the channel stopper area does not overlap the connecting part area in plan view, and Areas of the same conductivity type in the active area (2) and the channel stopper area (38A) are activated simultaneously after the plurality of termination electrodes has formed.

Images