SYSTEM AND METHOD FOR LOSSE-FREE CURRENT SENSORING WITH GAN USING IN-MOTOR DRIVE CIRCUITS

Abstract

A circuit is disclosed. The circuit comprises a first switch with a first source terminal and a first drain terminal, and a second switch with a second source terminal and a second drain terminal, wherein the second drain terminal is connected to the first drain terminal and the second source terminal is connected to the first source terminal. In one aspect, the second switch is configured to generate a first signal corresponding to a current flowing from the first source terminal to the first drain terminal. In another aspect, a detection circuit is configured to receive the first signal and determine the magnitude and polarity of the current flowing from the first source terminal to the first drain terminal, the detection circuit further being configured to transmit a second signal based on the first signal.

Description

REFERENCE TO RELATED REGISTRATIONS

[0001] This application claims priority over U.S. Preliminary Patent Application No. 63 / 683,945 for “System and methods for GaN lossless current sensing used in Motor Drive Circuits”, which was filed on August 16, 2024, and is hereby incorporated in full by reference for all purposes. AREA

[0002] The described embodiments relate generally to power converters and, in particular, the present embodiments relate to systems and methods for lossless current sensing using gallium nitride (GaN) in motor drive circuits. GENERAL STATE OF THE ART

[0003] Electronic devices such as computers, servers, and televisions use one or more power converter circuits to convert one form of electrical energy into another. Some power converter circuits convert a high (or low) DC voltage to a lower (or higher) DC voltage, using a circuit topology called a DC-DC converter. Because many electronic devices are sensitive to the size and efficiency of the power converter circuit, new power converters can provide relatively higher efficiency and smaller size for these devices. SUMMARY

[0004] In some embodiments, a circuit is disclosed. The circuit comprises a first switch with a first source terminal and a first drain terminal; a second switch with a second source terminal and a second drain terminal, wherein the second drain terminal is connected to the first drain terminal and the second source terminal is connected to the first source terminal, the second switch being configured to generate a first signal corresponding to a current flowing from the first source terminal to the first drain terminal; and a detection circuit being configured to receive the first signal and determine the magnitude and polarity of the current flowing from the first source terminal to the first drain terminal, the detection circuit further being configured to send a second signal based on the first signal.

[0005] In some embodiments, the first switch is a gallium nitride (GaN)-based switch.

[0006] In some embodiments, the second switch is a GaN-based switch.

[0007] In some embodiments, the first and second switches are monolithically formed on a single chip.

[0008] In some embodiments, the circuit further comprises a third switch with a third source terminal and a third drain terminal, wherein the third source terminal is connected to the first drain terminal and a first terminal of a load, and the third drain terminal is connected to a current input node.

[0009] In some embodiments, the circuit further comprises a fourth switch with a fourth source terminal and a fourth drain terminal, wherein the fourth drain terminal is connected to the third drain terminal and the fourth source terminal is connected to the third source terminal.

[0010] In some embodiments, the load is a motor.

[0011] In some embodiments, the first switch and the second switch are formed on a gallium nitride (GaN)-based chip and the sensing circuit is formed on a silicon-based chip, the GaN-based chip and the silicon-based chip being jointly housed in a single semiconductor chip.

[0012] In some embodiments, the circuit further includes an overcurrent protection circuit configured to receive the second signal, compare the second signal with a first threshold, and generate a shutdown signal if the second signal exceeds the first threshold.

[0013] In some embodiments, a level-shifting circuit is disclosed. The level-shifting circuit comprises a transmitting circuit; a receiving circuit; and a first level-shifting switch and a second level-shifting switch; wherein the transmitting circuit is formed on a first silicon-based chip, the receiving circuit is formed on a second silicon-based chip, and the first and second level-shifting switches are formed on a gallium nitride (GaN)-based chip.

[0014] In some embodiments, the first and second silicon-based chips and the GaN-based chip are housed together in a single semiconductor package.

[0015] In some embodiments, a source terminal of the first level-shifting switch is connected to a source terminal of the second level-shifting switch and to a power source.

[0016] In some embodiments, the power source is located on the first silicon-based chip.

[0017] In some embodiments, the level conversion circuit also includes a common-mode feedback circuit.

[0018] In some embodiments, during manufacturing, the first and second silicon-based chips are arranged adjacent to each other on a silicon wafer, with the first and second silicon-based chips being received and jointly housed in the unified semiconductor package.

[0019] In some embodiments, a method for operating a circuit is disclosed. The method comprises providing a first switch with a first source terminal and a first drain terminal; providing a second switch with a second source terminal and a second drain terminal, the second drain terminal being connected to the first drain terminal and the second source terminal being connected to the first source terminal; generating a first signal through the second switch corresponding to a current flowing from the first source terminal to the first drain terminal; receiving the first signal through a sensing circuit; determining the magnitude and polarity of the current flowing from the first source terminal to the first drain terminal through the sensing circuit; and transmitting a second signal based on the first signal through the sensing circuit.

[0020] In some embodiments of the disclosed method, the first and second switches are gallium nitride (GaN)-based switches, wherein the first and second switches are monolithically formed on a single chip.

[0021] In some embodiments, the method further comprises providing a third switch with a third source terminal and a third drain terminal, wherein the third source terminal is connected to the first drain terminal and a first terminal of a load, and the third drain terminal is connected to a current input node.

[0022] In some embodiments, the method further comprises providing a fourth switch with a fourth source terminal and a fourth drain terminal, wherein the fourth drain terminal is connected to the third drain terminal and the fourth source terminal is connected to the third source terminal.

[0023] In some embodiments, the method further includes receiving the second signal and comparing the second signal with a first threshold and generating a shutdown signal when the second signal exceeds the first threshold, by means of an overcurrent protection circuit. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 illustrates a simplified scheme of an integrated power device with bidirectional current sensing according to certain embodiments; Fig. Figure 2 illustrates the use of an external resistor to detect the current through a power switch by means of an internal bidirectional current amplifier according to some embodiments; Fig. Figure 3 illustrates a system-level scheme of a power converter with a controller and an integrated power device according to certain embodiments; Fig. Figure 4 illustrates a diagram showing the time-dependent voltages at various nodes within the circuit of Fig. 3 represents; Fig. Figure 5 illustrates a simplified scheme of an integrated power device with bidirectional external current sensing circuitry using the internal current sensing amplifier of the integrated GaN-based chip from Fig. 1 according to some embodiments; Fig. Figure 6 is a simplified flowchart illustrating a procedure for activating the synchronous rectification (SR) function; Fig. 7 and Fig. 8 Illustrate diagrams showing timing diagrams for turning on SR and turning off Sr according to some embodiments; Fig. Figure 9 is a simplified flowchart illustrating a method for prematurely switching off the circuit breaker in SR mode according to some embodiments; and Fig. Figure 10 illustrates a simplified scheme of a level conversion system according to certain embodiments. DETAILED DESCRIPTION

[0024] The circuits, devices, and associated techniques disclosed herein generally relate to power converters. More specifically, the systems, circuits, devices, and associated techniques disclosed herein relate to GaN circuit breakers with lossless current sensing, which are used in half-bridge and full-bridge applications for motor drives. In some embodiments, an integrated power device may include a GaN circuit breaker together with integrated bidirectional lossless current sensing, which may eliminate the need for external current-sensing resistors, thereby increasing system efficiency. The integrated bidirectional lossless current sensing may also enable the integrated power device to autonomously switch on the GaN circuit breaker during third-quadrant conduction, further increasing system efficiency.The integrated power device with bidirectional lossless current sensing enables the detection of the magnitude and direction of a current flowing through the GaN circuit breaker in both positive (i.e., from drain to source) and negative (i.e., from source to drain) directions. The detected current magnitude and direction can be sent to a driver and / or controller circuit, which can then autonomously control the conductivity state of the GaN circuit breaker upon receiving the detected current magnitude and direction.

[0025] In some embodiments, the integrated power device may include sensing and drive circuits housed together with a GaN circuit breaker in a single semiconductor package. The sensing and drive circuits may include a differential amplifier circuit configured to detect the magnitude and the positive and / or negative direction of a current flowing through the GaN circuit breaker. In various embodiments, an external resistor may be used to detect the current flowing through the GaN circuit breaker. Embodiments of the disclosure allow the use of sensing and drive circuits to amplify the voltage across the external sensing resistor.By utilizing the internal sensing circuits, it is possible to use an external resistor that is relatively small compared to the external resistance values ​​used in current approaches. This is because the disclosed circuits and techniques can detect the magnitude and direction of the current flowing through the GaN power switch based on a relatively small voltage generated across the external resistor. In this way, the inverter power loss can be minimized. In some embodiments, for example, the external resistance can be 5 to 10 times smaller than the resistance values ​​used in current approaches.

[0026] Motor drive applications may require relatively accurate current sensing through the circuit breaker. These applications can include, but are not limited to, washing machines, dryers, and hair dryers. The circuits and techniques disclosed herein enable relatively accurate current sensing through a circuit breaker, maintaining the accuracy of the sensed current with a relatively high degree of precision over the lifetime of the device. In some embodiments, a relatively small switch may be coupled to the circuit breaker, the small switch being configured to sensing a current flowing through the circuit breaker. The circuits and techniques disclosed herein mitigate the effects of temporal variations in the ratio of the current in the main breaker to the current in the small switch.For example, the ratio of the current through the main switch to the current through the small switch can vary by up to 7% over time. In motor drive applications, it is advantageous for this ratio to remain relatively constant over time. Embodiments of the disclosure enable relatively accurate current sensing over time. Furthermore, embodiments of the disclosure enable bidirectional sensing of the current through the circuit breaker. Thus, the circuits and techniques disclosed herein enable bidirectional current sensing using the small switch and / or using an external resistor for current sensing.

[0027] In some embodiments, control methods for the autonomous synchronous rectifier (SR) mode allow the circuit breaker to operate as an ideal diode or to have a reverse channel conduction when the current through the breaker is negative (i.e., flowing from source to drain). In motor inverters and other applications where a reverse current can flow through the circuit breaker (also called "freewheeling"), the voltage across the circuit breaker, in combination with the reverse current, can cause relatively high power losses. The circuits and techniques disclosed herein enable the circuit breaker to operate as a synchronous rectifier. In some embodiments, the circuit breaker can be switched on upon detection of a significant reverse current, thereby reducing power losses during current flow from source to drain.Furthermore, the switch can be turned off autonomously and without the use of a controller when approaching zero current (SROFF).

[0028] In various embodiments, methods for the autonomous synchronous rectifier (SR) mode in half-bridge circuits can include shutdown intervention modes. In these embodiments, the circuit breaker can be switched off prematurely in SR mode.

[0029] The circuits and techniques disclosed herein can enable lossless current sensing in multiphase motor driver circuits, for example, in three-phase motor drive circuits. In some embodiments, the sensed current for each phase can be arranged in a wired-OR configuration. In various embodiments, the IC can include positive and negative dV / dt control circuits. In some embodiments, the dV / dt control circuits can include external and / or internal impedance elements coupled to the input pins of the IC. In various embodiments, the driver IC can include gate overdrive circuits. The gate overdrive circuits are disclosed in U.S. Patent Application No. 18 / 733,480, which is hereby incorporated by reference.In various embodiments, the circuits and methods disclosed herein are suitable for driving or controlling GaN-based power switches as well as silicon and / or silicon carbide-based switches.

[0030] In some embodiments, a level-shifting circuit may comprise a silicon-based transmit circuit, GaN-based level-shift switches, and a silicon-based receive circuit. In various embodiments, during the fabrication process, the silicon-based transmit circuit and the silicon-based receive circuit may be deposited from adjacent sites on a silicon wafer to ensure relatively high conformance between the transmit and receive chips. Various inventive embodiments are described herein, including methods, processes, systems, devices, and the like.

[0031] Several illustrative embodiments are now described with reference to the accompanying drawings, which form part of this document. The following description merely presents embodiment(s) and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the following description of the embodiment(s) will provide the person skilled in the art with a helpful description for implementing one or more embodiments. It is understood that various modifications to the function and arrangement of elements may be made without departing from the spirit and scope of this disclosure. Specific details are set forth in the following description for explanatory purposes, in order to enable a comprehensive understanding of certain inventive embodiments.However, it is obvious that various embodiments can be implemented in practice without these specific details. The figures and description are not intended to be restrictive. The word "example" or "exemplary" here means "serving as an example or for illustration." An embodiment or design described herein as "exemplary" or "example" is not necessarily to be understood as preferred or advantageous over other embodiments or designs.

[0032] Fig. Figure 1 shows a schematic of an integrated power device with bidirectional current sensing circuits according to some embodiments. Fig. Figure 1 shows a schematic of an integrated power device 100, which may include a gallium nitride (GaN)-based chip 102, housed together with a silicon-based chip 104 in a single semiconductor package. The GaN-based chip 102 may include one or more GaN-based power switches. The silicon-based chip 104 may include current sensing circuits. In some embodiments, the silicon-based chip may include additional circuitry, such as driver and controller circuitry. The integrated power device may also be referred to as an electronic device.

[0033] In the illustrated embodiment, the GaN-based chip 102 can comprise a GaN power switch 130 with a drain terminal 132, a gate terminal 136, and a source terminal 134. The GaN-based chip 102 can further comprise a GaN switch 122 with a drain terminal 124, a gate terminal 128, and a source terminal 126. The drain terminal 132 can be connected to the drain terminal 124, and the gate terminal 136 can be connected to the gate terminal 128. In some embodiments, the GaN switch 122 can be relatively small. The source terminal 134 can be connected to a ground 106. The source terminal 134 can also be connected to a Kelvin terminal 108. The source terminal 126 can be connected to an output terminal 110.

[0034] The GaN switch 122 can be configured to detect a current flowing through the GaN circuit breaker 130. A current 141 (Isw) can flow from the drain terminal 132 to the source terminal 134 of the GaN switch 130. A current 140 (Isns) can flow from the drain terminal 124 to the source terminal 126 of the GaN switch 122, with Isns being generated based on Isw. In some embodiments, Isns can be proportional to Isw.

[0035] The silicon-based chip 104 can comprise an input terminal 112 and an input terminal 114. The input terminals 112 and 114 can be connected to respective output terminals 110 and 108. In some embodiments, the input terminals 112 and 114 can be connected to the output terminals 110 and 108 by wire connections. The wire connections can be a single wire connection, a plurality of wire connections, or any other technique for establishing an electrical connection can be used. A resistor 116 can be connected between the input terminals 112 and 114. In some embodiments, the resistor 116 can, for example, have a value of 2000 Ω to 6000 Ω, while in other embodiments it can have a value of 4000 Ω.Input terminal 112 can also be connected to a resistor 118, and input terminal 114 can also be connected to a resistor 120. Resistor 118 can be connected to switch 142, and resistor 120 can be connected to switch 144. In some embodiments, resistor 118 can, for example, have a value of 396 Ω, while resistor 120 can, for example, have a value of 400 Ω.

[0036] Switch 142 can be connected to a first input terminal 146 of a current sensing amplifier 150. Switch 144 can be connected to a second input terminal 148 of the current sensing amplifier 150. In some embodiments, the current sensing amplifier 150 can be configured to operate bidirectionally. The current sensing amplifier 150 can have a first output terminal 152 and a second output terminal 154. Switch 156 can be connected between the first output terminal 152 and the first input terminal 146 of the current sensing amplifier 150. Switch 158 can be connected between the second output terminal 154 and the first input terminal 148 of the current sensing amplifier 150.

[0037] An output of the current sensing amplifier 150 can be a current output and can indicate the current flowing in the GaN power switch 130, either bidirectionally or unidirectionally. In some embodiments, the current sensing amplifier 150 can detect the current through the switch 122, enabling improved accuracy and reduced lifetime drift. In various embodiments, the current sensing amplifier 150 can detect a current flowing through an external sensing resistor with improved accuracy and reduced lifetime drift. In some embodiments, overcurrent detection can be performed within the silicon-based chip IC 104. Embodiments of the disclosure allow a user to define their own overcurrent threshold in their microcontroller.

[0038] The output terminals of the current sensing amplifier 150 can be connected to a current mirror circuit 160. In some embodiments, the current mirror 160 can be a 1:1 current mirror, i.e., the magnitude of the current entering the current mirror can be essentially equal to the magnitude of the current exiting the current mirror. The output terminals of the current mirror circuit 160 can be connected to the current mirror and subtraction circuit 162. In various embodiments, the current mirror and subtraction circuit 162 can have a ratio of 1:10, i.e., the magnitude of the current entering the current mirror can be one-tenth the magnitude of the current exiting the current mirror.

[0039] The current mirroring and subtraction circuit 162 can be connected to an overcurrent detection circuit 164, which is configured to generate a positive overcurrent signal (OCP) and a negative overcurrent signal (OCN). The current mirroring and subtraction circuit 162 can be connected to an output pin 174 (labeled CS). A switch 166 and a switch 168 can also be connected to the CS pin. The CS pin can be connected to a resistor divider formed by connecting resistor 170 and resistor 172 in series.

[0040] In some embodiments, the integrated power device 100 can be formed from silicon, GaN, or another suitable semiconductor material. In various embodiments, both the sensing circuits and the switches 130 and 122 can be formed on a silicon substrate. In some embodiments, both the sensing circuits and the switches can be formed on a GaN substrate. In some embodiments, the sensing circuit can be formed on a silicon substrate, while the switches 130 and 122 can be formed on a GaN substrate. In various embodiments, both the sensing circuit and the switches 130 and 122 can be monolithically integrated on a single chip. In some embodiments, the sensing circuits and the switches can be formed on separate, individual chips.In various embodiments, the sensing circuits and the switches 130 and 122 can be integrated in an electronic package, for example, in a quad flat no-lead (QFN) package, a dual flat no-lead (DFN) package, or a ball grid array (BGA) package. In some embodiments, the sensing circuits and the switches can be housed separately in an electronic package.

[0041] The current sensing amplifier 150 can detect a value of Isw by detecting Isns. Isns can generate a voltage across resistor 116. The generated voltage can be detected bidirectionally by the amplifier 150, and corresponding current signals I can be generated. n and I PCurrents can be generated and sent to the current mirror circuit 160. In some embodiments, the current mirror circuit 160 can have a 1:1 ratio. The current mirror circuit 160 can send corresponding signals to the current mirror circuit 162, where the signals can be amplified. The current mirror circuit 162 can be configured to drive the output pin 174 (labeled CS). In various embodiments, overcurrent detection can be performed internally in the integrated power device 100. In some embodiments, users can set their own overcurrent threshold in their microcontroller.

[0042] An output stage of the current sensing amplifier 150 can continuously conduct current such that the output stage always carries a common-mode current. This enables a smooth and seamless transition from negative to positive sensing voltage. In the disclosed bidirectional amplifier architecture, the differential current can flow on one side, depending on the polarity of the sensing voltage. In some embodiments, the resistor 120 can adjust the current in the output stage of the amplifier 150. In various embodiments, the sensing resistor 116 can, for example, have a value of 4 Ω. If, for example, the sensing resistor 116 has a value of 4 Ω and the resistor 120 has a value of 400 Ω, a resistor 118 can have a value of 396 Ω.

[0043] Fig. Figure 2 illustrates the use of an external resistor to detect the current through the power switch by the internal bidirectional current amplifier according to some embodiments. By utilizing the internal detection circuitry of the integrated power device 100, an external resistor can be used that has a relatively small value compared to the external resistor values ​​used in current approaches, since the internal detection circuitry is relatively sensitive. In the embodiment shown, an external resistor 180 can be used to detect a current through the power switch 130. The external resistor 180 can be connected between the source terminal 134 and ground.

[0044] The silicon-based chip 104 can be connected to the external resistor 180 via resistors 182 and 184. In some embodiments, switches 142 and 144 can be controlled by a signal A, and switches 186 and 188 by a signal B. The current sensing amplifier 150 can detect a current flowing through the external sensing resistor 180 with improved accuracy and reduced lifetime drift. The external resistor 180 can have a relatively small value, allowing resistors 182 and 184 to have similar values. Pins 199 (ICSP) and 197 (ICSN) can be floating when the internal current sensing amplifier 150 is to be used. Example calculations for I follow. N and I P :

[0045] If Isw > 0: IP=ISNS×4Ω400Ω+ICMIN=ICM

[0046] If ISW=0: IP=ICMIN=ICM

[0047] If ISW<0: IN=ISNS×4Ω400Ω+ICMIP=ICM

[0048] To determine whether to use internal or external current sensing, the component can drive a current from the ICSP and ICSN pins. If the voltage is greater than approximately 1.5 V, internal current sensing is used. A current value of, for example, 200 µA can be pulsed from the ICSP and ICSN pins for a short time after the component is activated. During this determination period (the decision between internal and external current sensing), the amplifier can use internal current sensing. By default, internal current sensing is used with the internal resistor 116, as this is permanently connected.

[0049] Once the decision has been made whether to use internal (resistor 116) or external current sensing (resistor 180), this decision is buffered to prevent it from changing during operation. This buffer can be cleared when the device is switched off. In some embodiments, the buffered data can only switch the input to the amplifier when gate pin 136 is low. This prevents the amplifier from switching connections while gate pin 136 is high. In other embodiments, current sensing can be performed internally during an initial PWM pulse, and then switched to external current sensing starting with the next PWM pulse. This can only occur if PWM is high when the enable resistor goes high.In some embodiments, for the use of internal current sensing, the ICSP and / or ICSN pin may be floating, or a capacitor or a relatively large resistor may be connected to the ICSP and / or ICSN pin.

[0050] Referring to the current mirror sections of the integrated power device 100, the current output at pin 174 (CS) can be amplified, for example, by a factor of 10 relative to the amplifier's output current (e.g., + / -2.5 mA at Isw = + / -100%). The gain of current mirror circuit 160 and the gain of current mirror circuit 162 can be trimmed to compensate for variations in the ratio of the GaN power switch 130 to the sensing switch 122. Offset trimming can also be performed in current mirror circuits 160 and 162 so that the CS output current is zero when Isw = 0.

[0051] The output stage can also continuously conduct current when Isw = 0 to improve the response speed when the power switch current Isw crosses zero. For a bidirectional output, a user can connect a resistor divider to a reference voltage or a single resistor to a reference voltage. To ensure relatively accurate output current, the CS pin voltage can be kept within a range of, for example, 0.5 V to 3.5 V. For a unidirectional output, a user can connect a resistor from the CS pin to GND (trim bit to configure for unidirectional output). In some embodiments, the CS pin voltage is kept below 3.5 V, for example, to ensure relatively accurate output current. Positive and negative overcurrent detection can be performed internally in the integrated power device 100 and can detect the current in the current mirror circuit.The CS pin can be set to approximately 3.5V (or 5V) for a positive overcurrent and to GND for a negative overcurrent.

[0052] Fig. Figure 3 illustrates a system-level schematic of a power converter with a controller and an integrated power device according to certain embodiments. The circuit 300 may include a controller 304 connected to an integrated power device 302. The integrated power device 302 is similar to the integrated power device 100, except that the integrated power device 302 comprises two integrated power devices. The integrated GaN device 302 may be configured to detect the magnitude and direction of a current flowing through the GaN circuit breaker 308 in the positive (i.e., drain-to-source) or negative (i.e., source-to-drain) direction. In some embodiments, the integrated GaN device 302 may be configured to detect the magnitude and direction of a current flowing through each of the GaN circuit breakers 306 and 308 in the positive (i.e., drain-to-source) direction.from drain to source) or flows in a negative direction (i.e., from source to drain).

[0053] In various embodiments, the GaN circuit breakers can be implemented on a GaN-based chip and the sensing / driver circuits on a silicon-based chip. The GaN-based chip and the silicon-based chip can be housed together in a single semiconductor package. In some embodiments, the GaN circuit breakers and the sensing / driver circuits can be implemented on a single GaN-based chip. In various embodiments, each of the GaN circuit breakers can be coupled with a corresponding sensing circuit.

[0054] For many applications, it can be useful to detect the cyclic current flow through the circuit breaker. Current current detection approaches may involve placing a detection resistor between the circuit breaker source and ground. This method can increase system conduction losses, create hotspots on the printed circuit board, and decrease overall system efficiency. To eliminate this external resistance and the associated hotspots, and to improve system efficiency, the 302 integrated GaN device can employ integrated, relatively accurate, bidirectional, lossless current detection techniques. In some embodiments, current flowing through the internal low-side GaN circuit breaker can be detected internally and then converted into a current at the current detection output pin (CS).An external resistor divider (R1, R2) can be connected to the CS pin and used to adjust the amplitude of the CS pin voltage signal. This allows the CS pin signal to work with different controllers that have varying current sensing input thresholds. In some embodiments, the resistor divider can be placed relatively close to the CS pin to improve robustness and reduce system noise.

[0055] In some embodiments, the resistor divider can be driven by an external voltage, allowing the midpoint voltage to be set to a desired value, for example, to drive a microcontroller's A / D converter at maximum resolution. Positive current through the GaN power FET can cause current to flow out of the CS pin, increasing the voltage at the midpoint of the resistor divider, and negative current through the GaN power FET can cause current to flow into the CS pin, reducing this voltage. The CS pin current can depend on the gain and current of the power transistor. The resistor value can be adjusted to position a voltage range corresponding to a fully positive to fully negative current appropriately within the ADC input voltage range and the maximum voltage at the CS pin.

[0056] Embodiments of the disclosure can determine the entire on-resistance R ON (TOT) significantly reduces the number of steps compared to current approaches. For example, R ON (TOT) for a 300 W high-frequency boost PFC circuit can be reduced from 340 mΩ to 170 mΩ. The savings in power losses from eliminating an external resistor can, for example, lead to an efficiency gain of +0.5% for the overall system and eliminate the RCS PCB hotspot. The following equations show examples for calculating gain and Vcs: Gain=ICS / IDS=1.25mA / 4.5A=0.2778 mA / A VCS=RCS / 2*Gain*IDS+VREF / 2 where RCS=R1=R2 / 2

[0057] Fig. Figure 4 shows a diagram illustrating the time-dependent voltages at various nodes within the circuit of Fig. 3 represents. Fig. 4 indicates the voltage at IN L , INH , V SW and at the CS pin.

[0058] Fig. Figure 5 illustrates a simplified schematic of an integrated power device with a bidirectional external current sensing circuit using an internal current sensing amplifier of the integrated GaN-based chip 102 according to some embodiments. In some embodiments, an external current sensing resistor can be used while the internal amplifier of the integrated power device is still used to increase the voltage across the external sensing resistor. By using the internal current sensing amplifier to increase the voltage across R SNS relatively small R SNS Values ​​are achieved such that the maximum voltage drop is, for example, set to + / -100 mV and the power loss is in R SNS can be minimized. The internal amplifier can increase the voltage at R. SNSThe voltage is measured via two series resistors, R3 and R4, which can be set to the same value. The voltage at CS is derived from: VCS=VREFR1R1+R2+ISW10(RSNS)R3,4R1R2R1+R2

[0059] In various embodiments, the A / D converter of the PWM controller R can SNS directly detect the maximum voltage drop at R SNS However, it can be relatively higher to achieve the resolution used for accurate current sensing. In various embodiments, another option for external current sensing may be to add an external amplifier to increase the R SNS -signal to amplify and enable bidirectional current sensing. This technique is similar to Fig. 2, however, using an external amplifier instead of the internal amplifier. Autonomous synchronous rectification:

[0060] In current designs, a GaN HEMT may lack a body diode, so the voltage across the HEMT in the third quadrant can be, for example, four to five times higher than that of a comparable silicon switch. The resulting conduction losses when the gate remains low can be relatively high, which may lead to GaN being ruled out for use in power converters employing this "freewheeling" approach.

[0061] In some embodiments, control methods for the autonomous synchronous rectifier (SR) mode allow the circuit breaker to operate as an ideal diode or to have a reverse channel when the current through the breaker is negative (i.e., flowing from source to drain). In motor inverters and other applications where a reverse current can flow through the circuit breaker (also called "freewheeling"), the voltage across the circuit breaker, in combination with the reverse current, can cause relatively high power losses. The circuits and techniques disclosed herein allow the circuit breaker to be controlled as a synchronous rectifier when a current channel in the third quadrant is detected. In some embodiments, the circuit breaker can be switched on upon detection of a significant reverse current, thereby reducing power losses during current flow from source to drain.Furthermore, the switch can be turned off autonomously and without the use of a controller when approaching zero current (SROFF).

[0062] In various embodiments, a half-bridge circuit operated with an inductive load in buck mode can utilize autonomous synchronous rectification methods. In such embodiments, a control signal for the low-side switch can be held at zero V, while the high-side control signal can turn the high-side switch on and off to build up current in the load inductance, which is connected to ground by the switching node of the half-bridge. Once the high-side switch is off, the inductor current commutates to the low-side switch, where the low-side switch can begin conducting in the third quadrant. Once the current in the third quadrant of the low-side switch exceeds a predetermined threshold, for example, 700 mA, embodiments of the disclosure allow the integrated power device to autonomously amplify (i.e., turn on) the gate terminal of the low-side switch.The low-side switch gate can be amplified and held at a high level until a high-side control command to "turn on" is received or the current in the half-bridge drops to a predetermined detection threshold. An anti-shoot-through circuit can ensure that the low-side GaN gate is turned off before a "turn on" control command is passed to the high-side gate driver. A similar operating technique can work when the high-side switch is in "boost" mode.

[0063] Fig. Figure 6 illustrates a method for activating the SR functionality according to some embodiments. Fig. Figure 6 illustrates a method 600 for activating the SR functionality, wherein the method includes an arming operation in which the integrated power device can "arm" itself for SR operation when VDS exceeds a first threshold (602). The method also includes a turn-on operation in which, if the integrated power device has previously been "armed" and VDS falls below a second threshold (the SRON voltage, e.g., -1.05 V) for more than a first predetermined time interval, the driver can activate and turn on the power switch (604). The gate can remain on for at least a minimum turn-on duration to ensure that switching noise cannot falsely trigger the turn-off detection circuit. The first predetermined time interval can, for example, be a value of 50 to 100 ns.In some embodiments, the first predetermined time interval can be from 0.1 to 900 ns, while in other embodiments the first predetermined time interval can be from 10 to 200 ns.

[0064] The method further includes switching off, wherein, if the magnitude of the current flowing from the source to the drain falls below a predetermined threshold, the integrated power device can switch off the circuit breaker (606). The method additionally includes re-arming, wherein, if VDS rises above a third threshold (SRARM voltage, e.g., 9.8 V), the integrated power device can be prepared for the next SR cycle (608).

[0065] It should be noted that the in Fig. The specific steps shown in Section 6 represent a particular method for activating the SR functionality according to one embodiment of the disclosure. Alternative embodiments may also perform other sequences of steps. For example, alternative embodiments of the disclosure may perform the steps described above in a different order. Furthermore, the steps shown in Section 6 may be performed in a different order. Fig. The six individual steps depicted comprise several sub-steps, which can be performed in different sequences depending on the step. Furthermore, additional steps can be added or removed depending on the application. A person skilled in the art would recognize many variations, modifications, and alternatives.

[0066] The integrated power device 100 can be configured to have a programmable synchronous rectifier (SR) mode to allow a power switch to operate as an ideal diode and / or to have a reverse channel when the current through the switch is negative (flowing from source to drain), according to some embodiments. When the INL or INH pin is low and the SR enable pin (SREN) is not set, the power switch is off, even when the switching current is negative. When the SREN enable pin is set and INL or INH is low, the power switch turns on when a negative current flows through the switch, acting as an ideal diode and increasing system efficiency.

[0067] Fig. 7 and Fig. Figure 8 illustrates graphs showing timing diagrams for turning on SR and turning off Sr according to some embodiments.

[0068] In some embodiments, the autonomous SR mode may include a method for prematurely switching off the circuit breaker. Fig. Figure 9 is a simplified flowchart illustrating Method 900 for prematurely switching off the circuit breaker in SR mode according to some embodiments. As shown in Fig. As shown in Figure 9, the method 900 may include the integrated power device 100 turning off the low-side gate before sending a high-side level-shift turn-on signal (902) when the low-side operating in SR mode receives a request to turn on the high-side. The method may further include the fact that if the low-side operating in SR mode receives a genuine INL command and if the integrated power device 100 receives an INL signal during SR mode, this signal may take precedence even if the signal goes low before the normal SR turn-off current (904).The procedure further includes the fact that if the high-side operating in SR mode receives a shutdown signal through the level converter, the low-side may not know whether the high-side is operating in SR mode or not, and therefore may continuously send a shutdown pulse to the high-side via the level converter before responding to an INL command (906).

[0069] It should be noted that the in Fig. The specific steps described in Figure 9 represent a particular method for prematurely switching off the circuit breaker in SR mode according to some embodiments. Alternative embodiments may also employ other step sequences. For example, alternative embodiments of the disclosure may perform the steps described above in a different order. Furthermore, the steps described in Figure 9 may be performed in a different manner. Fig. The nine individual steps shown comprise several sub-steps, which can be performed in different sequences depending on the step. Furthermore, additional steps can be added or removed depending on the application. A person skilled in the art would recognize many variations, modifications, and alternatives.

[0070] In some embodiments, SR shutdown may not need to rely solely on current sensing. Instead of sensing that the current falls below a threshold, VSD can be detected and the shutdown triggered when the voltage reaches a relatively small value, for example, a few millivolts.

[0071] In some embodiments, the SR mode can enable accurate detection of negative currents using the internal bidirectional detection method. When current flows in the third quadrant (i.e., from source to drain) and the gate remains low, the ratio of the main power FET to the CS detection FET may differ from when the gate is high. Therefore, when the gate remains low, the gain of the CS output can be relatively inaccurate. The Auto-SR mode can mitigate this problem by ensuring that the gate is turned on and the ratio between the main FET and CS detection FET is correct when the current is negative, even when no PWM signal is present. With current approaches, this problem may not exist with external CS resistors, as the voltage across them is always only Rcs*Idrn.The disclosed Auto-SR method can enable a “lossless” acquisition method in applications where a user does not control the PWM, allowing some users to eliminate the external RCs without changing their firmware and / or control scheme.

[0072] Fig. Figure 10 shows a simplified diagram of a level conversion system according to certain embodiments. As in Fig.As shown in Figure 10, a level-shifting system 1000 can be used in the driver IC, which is used in the integrated power device 100. The level-shifting system 1000 can comprise a transmit circuit 1002, a level-shifting circuit 1004, and a receive circuit 1006. In some embodiments, the transmit circuit 1002 can be referenced to a low-voltage ground, while the receive circuit 1006 can be referenced to a floating voltage. In various embodiments, the transmit circuit 1002 can be made of silicon, the level-shifting switches 1004 of GaN, and the receive circuit 1006 of silicon. The level-shifting switch circuit 1004 can comprise a first switch 1010 and a second switch 1012. The first switch 1010 and the second switch 1012 can be implemented on a GaN-based chip.In some embodiments, the transmitting circuit 1002 can be implemented on a silicon chip, wherein the transmitting circuit chip is separate from the receiving circuit chip. In various embodiments, the transmitting circuit 1002 can be implemented on the same chip as the receiving circuit 1006. In some embodiments, the level-shifting switches 1004 can be high-voltage switches. In various embodiments, the level-shifting switches 1004 can be low-voltage or medium-voltage switches.

[0073] By using the same current source 1008 for the "Receive on" (RX_ON) and "Receive off" (RX_OFF) sections, the network matching can be further improved compared to independent current sources for each level-shift switch 1010 and 1012. This improved matching in the level-shift circuit allows the circuit to operate with relatively high immunity to signal propagation errors. In some embodiments, the current source can be a resistor or a controlled impedance element. In other embodiments, the current source can be located on the GaN chip 1014 or on the silicon chip 1016.

[0074] In some embodiments, the level-shifting system 1000 can comprise a transmit circuit, a receive circuit, and a first and a second level-shifting switch, wherein the first and the second level-shifting switches are made of gallium nitride (GaN). In various embodiments, the transmit circuit and the receive circuit are formed on the same silicon chip. In some embodiments, the transmit circuit is formed on a first chip, the first and the second level-shifting switches are formed on a second chip, and the receive circuit is formed on a third chip, wherein the first chip, the second chip, and the third chip are jointly housed in a single semiconductor package.In various embodiments, the first chip and the third chip are arranged adjacent to each other on a silicon wafer, with the first chip and the third chip being received and arranged together in the unified semiconductor package.

[0075] The level-shifting circuits and techniques disclosed herein enable the formation of level-shifting circuits used in driver ICs for GaN power devices, where the level-shifting circuit operates with relatively high precision, thus saving energy. By selecting chips from the same silicon wafer for the transmit and receive chips, a relatively high level of agreement can be achieved, allowing the level-shifting circuit to operate with relatively high accuracy. In some embodiments, the same chip can be used for both the transmit and receive functions by configuring a downbond (DAP) on the chip that specifies whether the chip is used for the transmit or receive function.

[0076] In some embodiments, the methods disclosed herein can be used to determine the boundary operating conditions of the level conversion system 1000 via the variation of process and temperature fluctuations for the low-side pulse width. In various embodiments, data can be used to determine the slowest dV / dt at which the low-side (LS) information can be successfully transmitted to the high-side (HS) without intervention. For example, if dV / dT is slower than 13 V / ns, it cannot be ensured that the LS pulse width will pass through the level conversion circuit; therefore, according to some embodiments, a common-mode feedback circuit (CMFB) can be used.The CMFB circuit can be advantageous because if the rising edge of dV / dt is such that (1) the magnitude of the resulting common-mode current in the level-shifting FETs (1004) extends the receiving circuit (1006) beyond its dynamic operating range, and (2) the duration of dV / dt is longer than the current pulse sent by the transmitting circuit (1002), the signal from the transmitter may be missed by the receiver without intervention. Therefore, the CMFB circuit can be helpful in mitigating these operating conditions. The CMFB circuit can detect a common-mode current event at the receiver inputs and generate output currents through nodes RX_ON (1020) and RX_OFF (1022) to cancel this current. In this way, the CMFB circuit can bring the receiver inputs back into the correct range to detect a differential signal, i.e., either a current pulse at 1020 (RX_ON) or at 1022 (RX_OFF).Therefore, if the transmitter sends a signal during a dV / dt event that meets the two criteria described above, the signal can still be detected and processed by the receiver.

[0077] In some embodiments, a combination of the circuits and methods disclosed herein can be used to provide bidirectional lossless current sensing and autonomous SR-mode operation for integrated power devices comprising a driver circuit and at least one GaN power switch. Although circuits and methods are described and illustrated herein with respect to several specific configurations for operating GaN power switches, embodiments of the disclosure are suitable for operating silicon-based and / or silicon carbide-based power switches. Furthermore, the circuits and methods described and illustrated herein are suitable for use in AC-DC, DC-DC, ACF, buck, boost, half-bridge, full-bridge, LLC, AHB, class-D, PFC, and motor drive converters.

[0078] The foregoing description describes embodiments of the disclosure with reference to numerous specific details that may vary from implementation to implementation. Accordingly, the description and drawings should be considered illustrative rather than limiting. The sole and exclusive indicator of the scope of the disclosure and the scope of disclosure intended by the applicants is the literal and equivalent scope of the claim set as set out in this application, in the specific form in which it appears, including any subsequent amendments. The specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of the embodiments as disclosed.

[0079] Additionally, spatially relative terms such as "below" or "above" and the like can be used to describe the relationship of one element and / or feature to other elements and / or features, as illustrated in the figures. It is understood that, in addition to the orientation shown in the figures, the spatially relative terms are intended to encompass different orientations of the device in use and / or operation. For example, if the device in the figures is turned upside down, elements described as the "lower" surface may be oriented "above" other elements or features. The device may be oriented differently (e.g., rotated by 90 degrees or in other orientations), and the spatially relative descriptors used here can be interpreted accordingly.

[0080] The terms "and," "or," and "one / or" used here can have different meanings, which depend at least in part on the context in which they are used. When "or" is used to link a list such as A, B, or C, it is generally intended to mean A, B, and C, used here in an inclusive sense, as well as A, B, or C, used here in an exclusive sense. Furthermore, the term "one or more," as used here, can be used to describe each feature, structure, or property in the singular, or it can be used to describe a combination of features, structures, or properties. It should be noted, however, that this is merely an illustrative example, and the subject matter claimed is not limited to this example.Furthermore, when used to link a list such as A, B or C, the term “at least one of” can be interpreted to mean any combination of A, B and / or C, such as A, B, C, AB, AC, BC, AA, AAB, ABC, AABBCCC, etc.

[0081] References in this description to “an example,” “certain examples,” or “exemplary implementation” mean that a particular feature, structure, or property described in connection with the feature and / or example may be included in at least one feature and / or example of the claimed subject matter. Therefore, the appearance of the phrase “in an example,” “an example,” “in certain examples,” “in certain implementations,” or other similar expressions at various points in this description does not necessarily always refer to the same feature, example, and / or limitation. Furthermore, the respective features, structures, or properties may be combined in one or more examples and / or features.

[0082] The preceding detailed description provided numerous specific details to enable a comprehensive understanding of the claimed subject matter. However, the person skilled in the art understands that the claimed subject matter can also be implemented without these specific details. In other cases, methods and devices that would be known to a person skilled in the art were not described in detail in order to avoid obscuring the claimed subject matter. Therefore, it is intended that the claimed subject matter is not limited to the specific disclosed examples, but that it may also encompass all aspects that fall within the scope of the appended claims and their equivalents. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 683,945 f

[0001] US 18 / 733,480

[0029]

Claims

[1] Circuit, comprising: a first switch with a first source terminal and a first drain terminal; a second switch with a second source terminal and a second drain terminal, wherein the second drain terminal is connected to the first drain terminal and the second source terminal is connected to the first source terminal; wherein the second switch is configured to generate a first signal corresponding to a current flowing from the first source terminal to the first drain terminal; and a detection circuit configured to receive the first signal and to determine the strength and polarity of the current flowing from the first source terminal to the first drain terminal, the detection circuit further being configured to send a second signal based on the first signal. [2] Circuit according to claim 1, wherein the first switch is a gallium nitride (GaN)-based switch. [3] Circuit according to claim 2, wherein the second switch is a GaN-based switch. [4] Circuit according to claim 3, wherein the first and the second switch are monolithically formed on a single chip. [5] Circuit according to claim 1, further comprising a third switch with a third source terminal and a third drain terminal, wherein the third source terminal is connected to the first drain terminal and a first terminal of a load and the third drain terminal is connected to a current input node. [6] Circuit according to claim 5, further comprising a fourth switch with a fourth source terminal and a fourth drain terminal, wherein the fourth drain terminal is connected to the third drain terminal and the fourth source terminal is connected to the third source terminal. [7] Circuit according to claim 5, wherein the load is a motor. [8] Circuit according to claim 1, wherein the first switch and the second switch are formed on a gallium nitride (GaN)-based chip and the sensing circuit is formed on a silicon-based chip, and wherein the GaN-based chip and the silicon-based chip are jointly housed in a single semiconductor chip. [9] Circuit according to claim 1, further comprising an overcurrent protection circuit configured to receive the second signal, compare the second signal with a first threshold and generate a shutdown signal when the second signal exceeds the first threshold. [10] Level conversion circuit comprising: a transmitting circuit; a receiving circuit; and a first level-shifting switch and a second level-shifting switch; and wherein the transmitting circuit is formed on a first silicon-based chip, the receiving circuit is formed on a second silicon-based chip, and the first and second level conversion switches are formed on a gallium nitride (GaN)-based chip. [11] Level conversion circuit according to claim 10, wherein the first and second silicon-based chips and the GaN-based chip are housed together in a single semiconductor package. [12] Level conversion circuit according to claim 10, wherein a source terminal of the first level conversion switch is connected to a source terminal of the second level conversion switch and to a current source. [13] Level conversion circuit according to claim 12, wherein the power source is arranged on the first silicon-based chip. [14] Level conversion circuit according to claim 10, further comprising a common-mode feedback circuit. [15] Level conversion circuit according to claim 11, wherein during the manufacturing process the first and the second silicon-based chip are arranged adjacent to each other on a silicon wafer and wherein the first and the second silicon-based chip are received and jointly housed in the unified semiconductor package. [16] Method for operating a circuit, the method comprising: Providing a first switch with a first source terminal and a first drain terminal; Providing a second switch with a second source terminal and a second drain terminal, wherein the second drain terminal is connected to the first drain terminal and the second source terminal is connected to the first source terminal; Generating a first signal through the second switch, corresponding to a current flowing from the first source terminal to the first drain terminal; and Receiving the first signal by a detection circuit; and Determining the magnitude and polarity of the current flowing from the first source terminal to the first drain terminal through the detection circuit; and Sending a second signal based on the first signal through the detection circuit. [17] Method according to claim 16, wherein the first and second switches are gallium nitride (GaN)-based switches and wherein the first and second switches are monolithically formed on a single chip. [18] Method according to claim 16, further comprising providing a third switch with a third source terminal and a third drain terminal, wherein the third source terminal is connected to the first drain terminal and a first terminal of a load and the third drain terminal is connected to a current input node. [19] Method according to claim 18, further comprising providing a fourth switch with a fourth source terminal and a fourth drain terminal, wherein the fourth drain terminal is connected to the third drain terminal and the fourth source terminal is connected to the third source terminal. [20] Method according to claim 16, further comprising receiving the second signal by an overcurrent protection circuit and comparing the second signal with a first threshold value and generating a shutdown signal when the second signal exceeds the first threshold value.

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