METHOD AND DEVICES FOR CONTROLLING AN OFFSET OF A COUNTIF VOLTAGE FOR AN AMPLIFIER CIRCUIT ARRANGEMENT

Abstract

An exemplary setup includes: an amplifier circuit arrangement with a first input, a second input, and an output; a resistor with a first terminal and a second terminal, wherein the first terminal of the resistor is coupled to the output of the amplifier circuit arrangement; a first switch with a first terminal and a second terminal; a second switch with a first terminal and a second terminal; a third switch with a first terminal and a second terminal, wherein the first terminal of the third switch is coupled to the first terminal of the second switch; a fourth switch with a first terminal and a second terminal, wherein the first terminal of the fourth switch is coupled to the first terminal of the first switch; a first transistor with a first terminal and a second terminal;and a second transistor with a first terminal and a second terminal.

Description

TECHNICAL AREA

[0001] This description generally concerns the control of common-mode voltages and more specifically methods and devices for controlling an offset of a common-mode voltage for an amplifier circuit arrangement. BACKGROUND

[0002] Electronic systems employ amplifier circuits for a wide range of operations, such as signal modulation. Such an amplifier circuit generates a modulated output signal by modulating a carrier signal based on an information signal. A load performs operations in response to characteristics of the modulated output signal. In audio systems, an amplifier circuit modulates a carrier signal based on an information signal to produce a modulated output signal, which is a signal with relatively higher power and relatively high noise immunity compared to the information signal. Some amplifier circuits include feedback paths to modulate a relatively less complex signal at an output, relative to the modulated signal.The use of an amplifier circuit arrangement for signal modulation enables electronic systems to generate increasingly complex signals from relatively less complex signals. SUMMARY

[0003] For methods and devices for controlling a common-mode voltage offset for an amplifier circuit arrangement, an exemplary device includes an amplifier circuit arrangement with a first input, a second input, and an output; a resistor with a first terminal and a second terminal, wherein the first terminal of the resistor is coupled to the output of the amplifier circuit arrangement; a first switch with a first terminal and a second terminal; a second switch with a first terminal and a second terminal; a third switch with a first terminal and a second terminal, wherein the first terminal of the third switch is coupled to the first terminal of the second switch; a fourth switch with a first terminal and a second terminal, wherein the first terminal of the fourth switch is coupled to the first terminal of the first switch;a first transistor with a first terminal and a second terminal, wherein the first terminal of the first transistor is coupled to the first input of the amplifier circuit arrangement and the second terminal of the resistor, and wherein the second terminal of the first transistor is coupled to the second terminal of the first switch and the second terminal of the fourth switch; and a second transistor with a first terminal and a second terminal, wherein the first terminal of the second transistor is coupled to the second input of the amplifier circuit arrangement, and the second terminal of the second transistor is coupled to the second terminal of the second switch and the second terminal of the third switch. Further examples are described.

[0004] For methods and devices for controlling a common-mode voltage offset for an amplifier circuit arrangement, an exemplary device includes an amplifier circuit arrangement with a first input and a second input; a first switch with a terminal and a second terminal; a second switch with a first terminal and a second terminal, wherein the first terminal of the second switch is coupled to the first terminal of the first switch; a third switch with a first terminal and a second terminal; a fourth switch with a first terminal and a second terminal, wherein the first terminal of the fourth switch is coupled to the first terminal of the third switch;a first transistor with a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor is coupled to the second terminal of the first switch and the first terminal of the third switch; a second transistor with a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor is coupled to the second terminal of the second switch and the second terminal of the fourth switch;and a control circuit arrangement with a first terminal, a second terminal, and a third terminal, wherein the first terminal of the control circuit arrangement is coupled to the first input of the amplifier circuit arrangement and the second terminal of the first transistor, wherein the second terminal of the control circuit arrangement is coupled to the second input of the amplifier circuit arrangement and the second terminal of the second transistor, and wherein the third terminal of the control circuit arrangement is coupled to the control terminal of the first transistor and the control terminal of the second transistor. Further examples are described.

[0005] For methods and devices for controlling a common-mode voltage offset for an amplifier circuit arrangement, an exemplary device includes an amplifier circuit arrangement having a first input, a second input, and an output; a common-mode control circuit arrangement having a terminal coupled to the output of the amplifier circuit arrangement, wherein the common-mode control circuit arrangement is designed: to generate a first current and a second current in response to a difference between a first input voltage at the first input of the amplifier circuit arrangement and an output voltage at the output of the amplifier circuit arrangement; to control a common-mode voltage of the first input voltage and a second input voltage at the second input of the amplifier circuit arrangement in response to the generation of the first current and the second current;to compensate for a mismatch between the first and second input voltages; and to compensate for a difference between the first and second input voltages. Further examples are described. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram of an exemplary amplifier system, which includes an exemplary amplifier circuit arrangement and an exemplary common-mode control circuit arrangement. Fig. Figure 2 is a block diagram of an exemplary audio system, which includes an exemplary multi-class modulation circuit arrangement and an exemplary common-mode control circuit arrangement. Fig. Figure 3 is a schematic diagram of an example of the common-mode control circuit arrangement of Fig. 1 and Fig. 2, which includes an exemplary mismatch correction circuit arrangement. Fig. Figure 4 is a schematic diagram of an example of the mismatch correction circuit arrangement of Fig. 3. Fig. Figure 5 is a schematic diagram of an example of the mismatch correction circuit arrangement of Fig. 3 and Fig. 4, which includes an exemplary control circuit arrangement. Fig. Figure 6 is a flowchart representing exemplary machine-readable instructions or exemplary operations that can be performed using an exemplary implementation of the mismatch correction circuit arrangement of Fig. 3, Fig. 4 and Fig. 5 or more generally the common-mode control circuit arrangement of Fig. 1, Fig. 2 and Fig. 3 can at least be executed, instantiated and / or performed. Fig. Figure 7 is a schematic diagram of another example of the mismatch correction circuit arrangement of Fig. 3, Fig. 4 and Fig. 5 and another example of the control circuit arrangement of Fig. 5. Fig. 8 is a block diagram of another example of the common-mode control circuit arrangement of Fig. 1, Fig. 2 and Fig. 3, which includes a first exemplary mismatch correction circuit arrangement and a second exemplary mismatch correction circuit arrangement. Fig. Figure 9 is a schematic diagram of an example of the first mismatch correction circuit arrangement of Fig. 8 and an example of the second exemplary mismatch correction circuit arrangement of Fig. 8. Fig. Figure 10 is a flowchart representing exemplary machine-readable instructions or exemplary operations that can be performed using an exemplary implementation of the mismatch correction circuit arrangement of Fig. 7, Fig. 8 and Fig. 9 or more generally the common-mode control circuit arrangement of Fig. 1, Fig. 2, Fig. 3 and Fig. 8 can at least be executed, instantiated and / or performed.

[0006] The drawings are not necessarily to scale. Generally, the same reference symbols in one or more drawings and in this description refer to the same or similar features and / or parts (functionally and / or structurally). Although the drawings show areas with clean lines and boundaries, some or all of these lines and boundaries may be idealized. In reality, the boundaries or lines may be invisible, blended, or irregular. DETAILED DESCRIPTION

[0007] Electronic systems employ amplifier circuits for a wide range of operations, such as signal modulation. Such an amplifier circuit generates a modulated output signal by modulating a carrier signal based on an information signal. A load performs operations in response to characteristics of the modulated output signal. In audio systems, an amplifier circuit modulates a carrier signal based on an information signal to produce a modulated output signal, which is a signal with relatively higher power and relatively high noise immunity compared to the information signal. Some amplifier circuits include feedback paths to modulate a relatively less complex signal at an output, relative to the modulated signal.The use of an amplifier circuit arrangement for signal modulation enables electronic systems to generate increasingly complex signals from relatively less complex signals.

[0008] With advances in electronics, signal modulation techniques are becoming increasingly complex. One method of single-inductor (1L) modulation utilizes a Class AB and a Class D amplifier circuit arrangement to modulate an input signal using a carrier signal. The Class AB and Class D amplifier circuit arrangements receive a sinusoidal signal as the input signal to be modulated with respect to a triangular carrier signal. The Class AB amplifier circuit arrangement modulates the sinusoidal signal to produce a linear output signal. The linear output signal transitions linearly between logic levels, such as a linear transition between a logic high and a logic low state. The Class D amplifier circuit arrangement modulates the sinusoidal input signal by comparing the sinusoidal signal to the triangular carrier signal.The Class D amplifier circuit arrangement generates a digital output signal with a varying duty cycle that represents the sinusoidal input signal. The duty cycle of the digital output signal represents amplitudes of the sinusoidal input signal. Both Class AB and Class D amplifier circuit arrangements also amplify the input signal from an input power domain to an output power domain.

[0009] In some systems, the amplifier circuitry generates the output signal using a 20-volt output supply voltage, while the input signal uses a 5-volt input supply voltage. In such systems, structuring the amplifier circuitry for closed-loop operations increases the accuracy of the output signal. However, the differences between the power domain of the input signal and the power domain of the output signal result in relatively large feedback currents flowing through the current path between the input and output of the amplifier circuitry. Such currents can modify the common-mode voltage of the input signal. In audio systems, when modulating an audio input signal, the amplifier circuitry amplifies changes in the common-mode voltage of the audio input signal, leading to unwanted audio distortion (e.g., audio clipping).

[0010] Some systems prevent such common-mode voltage errors by incorporating a common-mode control circuit to regulate the common-mode voltage at the input of the amplifier circuit. In such systems, the common-mode control circuit includes a current control circuit and an error amplification circuit. The current control circuit monitors voltages at the output of the amplifier circuit to determine a feedback current. The current control circuit represents the current flowing through a current path between an input and an output of the amplifier circuit. The current control circuit acts as a sink for (e.g., draws current from) the feedback current from one or more inputs of the amplifier circuit and one or more outputs of the error amplification circuit.The error amplifier circuit compares a common-mode voltage at one or more inputs of the amplifier circuit to a reference voltage representing a target common-mode voltage. The error amplifier circuit generates currents in response to a detection that the measured common-mode voltage is not equal to the target common-mode voltage. The common-mode control circuit uses the currents from both the current control circuit and the error amplifier circuit to modify the common-mode voltage at the input of the amplifier circuit.

[0011] In operation, the common-mode control circuit modifies both positive and negative input signals at the inputs of the amplifier circuit by the same current. However, component mismatches, such as variations resulting from tolerances, within the common-mode control circuit create asymmetries between a first current modifying the positive input signal and a second current modifying the negative input signal. For example, the first current from the current control circuit and the error amplifier circuit may differ from the second current from both the current control circuit and the error amplifier circuit. In such cases, the first and second currents would ideally be the same, but a component mismatch between the current control circuit and the error amplifier circuit leads to asymmetries between the first and second currents.In amplifier systems, asymmetries between the currents of the positive and negative input signals increase the total harmonic distortion (THD). THD represents distortion due to harmonics with different frequencies in analog signals. Signals with relatively high THD exhibit relatively high voltages at harmonic frequencies. Signals with relatively high THD result in audible distortion. Asymmetries between signals of the differential pair of analog signals increase the THD.

[0012] Relatively large-area components (e.g., components that occupy a relatively large amount of die space) with relatively tighter tolerances compared to relatively smaller-area components reduce asymmetries and the associated THD of a differential pair of analog signals. Alternatively, to reduce package size, designs can be modified to use lower-value components. For example, a five percent tolerance of a ten-ohm resistor (10-Ω resistor) will have a much smaller variation (i.e., ±0.5 ohms) compared to a five percent tolerance of a one-thousand-ohm resistor (i.e., ±50 ohms). However, reducing component values ​​to reduce variation in component values ​​resulting from manufacturing tolerances limits the performance of the amplifier circuit design. For example, variation in component values ​​resulting from tolerances increases the THD.

[0013] Some common-mode control circuits incorporate a chopping circuit to reduce asymmetries between signals in a differential signal pair. The chopping circuit uses a series of switches to toggle between feedback components. Such switching distributes discrepancies between signals in a differential signal pair evenly. For example, the chopping circuit may include a variety of switches coupled to the output of the current control circuit and the error amplifier circuit. In such examples, the switches limit the total harmonic distortion (THD) by switching between components that form a first current path and a second current path. However, switching between current paths that include transistors, such as current mirrors in the current control circuit, introduces voltage fluctuations.The voltage fluctuations of the transistors occur in response to charge injection through parasitic capacitances (also known as Miller capacitances) of the transistors. Such voltage fluctuations can modify the positive and negative input signals because the chopping circuit arrangement allows the voltage fluctuations to propagate to the inputs of the amplifier circuitry. In amplifier systems, such voltage fluctuations at the inputs of the amplifier circuitry can lead to audio distortion and increase the total harmonic distortion (THD).

[0014] The examples described herein include methods and devices for controlling a common-mode voltage offset for an amplifier circuit arrangement using a mismatch correction circuit arrangement. In some of the described examples, a common-mode control circuit arrangement includes a mismatch correction circuit arrangement, which in turn includes a chopping circuit arrangement and isolation components. The chopping circuit arrangement includes a plurality of switches and a clock circuit arrangement. The clock circuit arrangement controls the plurality of switches. A first group of switches supplies a first current from a first current path of the common-mode control circuit arrangement to the positive-side input of the amplifier circuit arrangement for the first segment of a clock cycle.A second set of switches supplies a second current from a second current path of the common-mode control circuit to a negative input of the amplifier circuit for the first part of the clock cycle. The first set of switches supplies the first current from the first current path of the common-mode control circuit to the negative input of the amplifier circuit for the second part of the clock cycle. The second set of switches supplies the second current from the second current path of the common-mode control circuit to the positive input of the amplifier circuit for the second part of the clock cycle. Advantageously, the switches and the clock circuit of the chopping circuit reduce mismatch between components of the common-mode control circuit by averaging the differences between the first and second currents from the common-mode control circuit.

[0015] In some described examples, the isolation circuit arrangement of the mismatch correction circuitry includes a set of transistors and a control circuit. The isolation circuitry isolates signals at the inputs of the amplifier circuitry from the common-mode correction circuitry by setting voltages on the first and second current paths of the common-mode correction circuitry. In some examples, the control circuitry drives a first transistor and a second transistor with a measured common-mode voltage of the positive and negative input signals. The first transistor is coupled between the first input of the amplifier circuitry and the first set of switches in the chopping circuitry. The second transistor is coupled between the second input of the amplifier circuitry and the second set of switches in the chopping circuitry.In such examples, the measured common-mode voltage structures the first and second transistors so that they operate in a saturation mode. In saturation mode, the first and second transistors set the voltages of the common-mode input signals of the first and second current paths of the common-mode regulator assembly equal to the measured common-mode voltage minus the gate-to-source voltage of the transistors. Advantageously, operating the first and second transistors of the mismatch correction circuit using a measured common-mode voltage isolates the first and second inputs of the amplifier assembly from voltage fluctuations of the common-mode regulator assembly. Advantageously, the mismatch correction circuit described herein reduces the THD in response to a reduction in charge injection during common-mode regulation.

[0016] Fig. Figure 1 is a block diagram of an example amplifier system 100. In the example of Fig. The amplifier system 100 comprises an amplifier circuit arrangement 120, a first resistor 130, a second resistor 140, and a common-mode control circuit arrangement 150. The exemplary common-mode control circuit arrangement 150 of Fig. Figure 1 includes an exemplary mismatch correction circuit arrangement 160. The amplifier system 100 has a first input, a second input, a first output, and a second output. The first and second inputs of the amplifier system 100 are configured to be coupled to an analog signal source, such as an audio source or a digital-to-analog converter (DAC). In the example of Fig. The amplifier system 100 is structured to receive positive and negative input signals (INP, INM) at its first and second inputs. The positive and negative input signals are a pair of signals representing an analog signal to be modulated by the amplifier system 100. The first and second outputs of the amplifier system 100 are structured to be coupled to an external circuit arrangement, such as a loudspeaker or a signal processing device. In the example of Fig. 1. The amplifier system 100 generates a positive and a negative output signal (OUTP, OUTM) at the first and second outputs of the amplifier circuit arrangement 100. The positive and negative output signals are a pair of signals that represent a modulated version of the positive and negative input signals.

[0017] The amplifier circuit arrangement 120 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the amplifier circuit arrangement 120 is connected to the resistor 130, the common-mode control circuit arrangement 150, and the first input of the amplifier system 100, which provides the positive input signal (INP). The second terminal of the amplifier circuit arrangement 120 is connected to the resistor 140, the common-mode control circuit arrangement 150, and the second input of the amplifier system 100, which provides the negative input signal (INM). The third terminal of the amplifier circuit arrangement 120 is connected to the resistor 130, the common-mode control circuit arrangement 150, and the first output of the amplifier system 100, which provides the positive output signal (OUTP).The fourth terminal of the amplifier circuit arrangement 120 is coupled to the resistor 140, the common-mode control circuit arrangement 150 and the second output of the amplifier system 100, which provides the negative output signal (OUTM).

[0018] Resistor 130 has a first terminal and a second terminal. The first terminal of resistor 130 is connected to amplifier circuit arrangement 120, common-mode control circuit arrangement 150, and the first input of amplifier system 100, which provides the positive input signal (INP). The second terminal of resistor 130 is connected to amplifier circuit arrangement 120, common-mode control circuit arrangement 150, and the first output of amplifier system 100, which provides the positive output signal (OUTP).

[0019] Resistor 140 has a first terminal and a second terminal. The first terminal of resistor 140 is connected to amplifier circuit arrangement 120, common-mode control circuit arrangement 150, and the second input of amplifier system 100, which provides the negative input signal (INM). The second terminal of resistor 140 is connected to amplifier circuit arrangement 120, common-mode control circuit arrangement 150, and the second output of amplifier system 100, which provides the negative output signal.

[0020] The common-mode control circuit arrangement 150 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the common-mode control circuit arrangement 150 is connected to the amplifier circuit arrangement 120, the resistor 130, and the first input of the amplifier system 100, which provides the positive input signal (INP). The second terminal of the common-mode control circuit arrangement 150 is connected to the amplifier circuit arrangement 120, the resistor 140, and the second input of the amplifier system 100, which provides the negative input signal (INM). The third terminal of the common-mode control circuit arrangement 150 is connected to the amplifier circuit arrangement 120, the resistor 130, and the first output of the amplifier system 100, which provides the positive output signal (OUTP).The fourth terminal of the common-mode control circuit arrangement 150 is coupled to the amplifier circuit arrangement 120, the resistor 140 and the second output of the amplifier system 100, which provides the negative output signal (OUTM).

[0021] In the example of Fig. Figure 1 includes the common-mode control circuit arrangement 150 and the mismatch correction circuit arrangement 160. The mismatch correction circuit arrangement 160 is structured to be coupled to the first and second inputs of the amplifier system 100, which provide the positive and negative input signals (INP, INM). In some examples, the mismatch correction circuit arrangement 160 is also structured to be coupled to the first and second outputs of the amplifier system 100, which provide the positive and negative output signals (OUTP, OUTM). Examples of the mismatch correction circuit arrangement 160 are shown below in conjunction with Fig. 4, Fig. 5, Fig. 7 and Fig. 9 shown and described.

[0022] In exemplary operations, the amplifier circuit arrangement 120 receives the positive and negative input signals from an external signal source. The amplifier circuit arrangement 120 amplifies and / or modulates the positive and negative input signals to generate the positive and negative output signals. In such exemplary operations, resistors 130 and 140 supply feedback currents to the inputs of the amplifier system 100 to increase the accuracy of the positive and negative output signals.

[0023] In exemplary operations, the common-mode control circuit arrangement 150 regulates a common-mode voltage of the positive and negative input signals. In some examples, the common-mode control circuit arrangement 150 generates a first and a second compensation current by mirroring the feedback currents through resistors 130 and 140. The first and second compensation currents are structured to reduce shifts in the common-mode voltage resulting from the feedback currents of resistors 130 and 140. Furthermore, the common-mode control circuit arrangement 150 modifies the first and second compensation currents based on a comparison of the common-mode voltage of the positive and negative signals with a target common-mode voltage. In such exemplary operations, the mismatch correction circuit arrangement 160 includes a circuit arrangement to reduce discrepancies between the first and second feedback currents.Furthermore, the mismatch correction circuit arrangement isolates voltage fluctuations resulting from switching between supplying the first and second feedback currents to the positive and negative input signals.

[0024] Exemplary operations of amplifier system 100 are in connection with Fig. 6 and Fig. 10 below is further illustrated and described. It is also illustrated and described. Fig. 2 An alternative example of amplifier system 100, structured to implement a modulation technique. Alternatively, amplifier system 100 can be modified to implement a different type of signal modulation.

[0025] Fig. Figure 2 is a block diagram of an exemplary audio system 200, which is an exemplary implementation of the amplifier system 100. Fig. 1 is. In the example of Fig. 2 The audio system 200 includes an exemplary audio source 205, an exemplary multi-class modulation circuit arrangement 210, an exemplary filter circuit arrangement 215, an exemplary loudspeaker 220, an exemplary line-out connector 225, and an exemplary common-mode control circuit arrangement 230. The exemplary multi-class modulation circuit arrangement 210 of Fig. 2 includes a first exemplary conditioning circuit arrangement 235, a first exemplary amplifier circuit arrangement 240, a first exemplary resistor 245, a second exemplary resistor 250, a second exemplary conditioning circuit arrangement 255, and a second exemplary amplifier circuit arrangement 260. The exemplary common-mode control circuit arrangement 230 of Fig. 2 includes an exemplary mismatch correction circuit arrangement 265.

[0026] In the example of Fig. The audio system 200 is structured to implement a single-inductor (1L) modulation. Examples of the amplifier circuit arrangement 240, 260, or more generally the multi-class modulation circuit arrangement 210 are shown. Fig. 2 or, more generally, the audio system 200 are further illustrated and described in “METHODS AND APPARATUS TO MODULATE SIGNALS USING MULTI-CLASS MODULATION CIRCUITRY”, US patent application no. 18 / 385,848, which is incorporated in its entirety by reference and transferred to the successor in title of the present application.

[0027] The audio source 205 has a first terminal and a second terminal. The first and second terminals of the audio source 205 are coupled to the multi-class modulation circuit arrangement 210. In the example of Fig. In Figure 2, the audio source 205 is structured as an analog signal source. In some examples, the audio source 205 is a digital-to-analog converter (DAC). In such examples, the audio source 205 is coupled to a digital signal processing circuit arrangement that provides digital audio signals.

[0028] The multi-class modulation circuit arrangement 210 has a first, a second, a third, a fourth, a fifth, and a sixth connection. The first and second connections of the multi-class modulation circuit arrangement 210 are connected to the audio source 205. The third and fourth connections of the multi-class modulation circuit arrangement 210 are connected to the common-mode control circuit arrangement 230. The fifth and sixth connections of the multi-class modulation circuit arrangement 210 are connected to the filter circuit arrangement 215 and the common-mode control circuit arrangement 230.

[0029] The filter circuit arrangement 215 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of the filter circuit arrangement 215 are coupled to the multi-class modulation circuit arrangement 210 and the common-mode control circuit arrangement 230. The third and fourth terminals of the filter circuit arrangement 215 can be coupled to the loudspeaker 220 and / or the line-out terminal 225.

[0030] The loudspeaker 220 has a first and a second connection. The first and second connections of the loudspeaker 220 are connected to the filter circuit arrangement 215 and can be connected to the line-out connection 225. The line-out connection 225 has a first and a second connection. The first and second connections of the line-out connection 225 are connected to the filter circuit arrangement 215 and can be connected to the loudspeaker 220.

[0031] The common-mode control circuit arrangement 230 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of the common-mode control circuit arrangement 230 are coupled to the multi-class modulation circuit arrangement 210. The third and fourth terminals of the common-mode control circuit arrangement 230 are coupled to the multi-class modulation circuit arrangement 210 and the filter circuit arrangement 215. In some examples, the common-mode control circuit arrangement 230 further has a fifth and a sixth terminal. In such examples, the fifth and sixth terminals of the common-mode control circuit arrangement 230 are coupled to supply terminals of the multi-class modulation circuit arrangement 210.

[0032] The signal conditioning circuit assembly 235 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of the signal conditioning circuit assembly 235 are connected to the audio source 205 and the signal conditioning circuit assembly 255. The third terminal of the signal conditioning circuit assembly 235 is connected to the common-mode control circuit assembly 230, the class-D amplifier circuit assembly 240, and the resistor 245. The fourth terminal of the signal conditioning circuit assembly 235 is connected to the common-mode control circuit assembly 230, the class-D amplifier circuit assembly 240, and the resistor 250.

[0033] The class-D amplifier circuit arrangement 240 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the class-D amplifier circuit arrangement 240 is coupled to the common-mode control circuit arrangement 230, the conditioning circuit arrangement 235, and the resistor 245. The second terminal of the class-D amplifier circuit arrangement 240 is coupled to the common-mode control circuit arrangement 230, the conditioning circuit arrangement 235, and the resistor 250. The third terminal of the class-D amplifier circuit arrangement 240 is coupled to the common-mode control circuit arrangement 230, the filter circuit arrangement 215, and the resistor 245. The fourth terminal of the class-D amplifier circuit arrangement 240 is coupled to the common-mode control circuit arrangement 230, the filter circuit arrangement 215, the class-AB amplifier circuit arrangement 260 and the resistor 250.

[0034] Resistor 245 has a first terminal and a second terminal. The first terminal of resistor 245 is coupled to the common-mode control circuit arrangement 230, the conditioning circuit arrangement 235, and the class-D amplifier circuit arrangement 240. The second terminal of resistor 245 is coupled to the common-mode control circuit arrangement 230, the filter circuit arrangement 215, and the class-D amplifier circuit arrangement 240. In some examples, the first resistor 245 is used as a feedback resistor (R1). fb ) designated.

[0035] Resistor 250 has a first terminal and a second terminal. The first terminal of resistor 250 is coupled to the common-mode control circuit arrangement 230, the conditioning circuit arrangement 235, and the class-D amplifier circuit arrangement 240. The second terminal of resistor 250 is coupled to the common-mode control circuit arrangement 230, the filter circuit arrangement 215, the class-D amplifier circuit arrangement 240, and the class-AB amplifier circuit arrangement 260. In some examples, the first resistor 250 is used as a feedback resistor (R). fb ) designated.

[0036] The signal conditioning circuit arrangement 255 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of the signal conditioning circuit arrangement 255 are connected to the audio source 205 and the signal conditioning circuit arrangement 235. The third and fourth terminals of the signal conditioning circuit arrangement 255 are connected to the class AB amplifier circuit arrangement 260.

[0037] The class AB amplifier circuit arrangement 260 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of the class AB amplifier circuit arrangement 260 are coupled to the conditioning circuit arrangement 255. The third and fourth terminals of the class AB amplifier circuit arrangement 260 are coupled to the common-mode control circuit arrangement 230, the filter circuit arrangement 215, the class D amplifier circuit arrangement 240, and the resistor 250.

[0038] In an exemplary operation, the audio source 205 supplies the positive and negative input signals (INP, INM) to the multi-class modulation circuit arrangement 210. In the example of Fig. The positive and negative input signals represent an audio signal which, when delivered to the loudspeaker 220, corresponds to an audible tone. In some examples, the conditioning circuit arrangement 235, 255 filters the positive and negative input signals to reduce noise. The class-D amplifier circuit arrangement 240 receives the positive and negative input signals. The positive input signal of the class-D amplifier circuit arrangement 240 includes contributions from feedback currents from resistor 245 and currents from the common-mode control circuit arrangement 230. The negative input signal of the class-D amplifier circuit arrangement 240 includes contributions from feedback currents from resistor 250 and currents from the common-mode control circuit arrangement 230. The class-D amplifier circuit arrangement 240 modulates the differential pair of amplifier input signals to generate a positive output signal (OUTP).The class AB amplifier circuit arrangement 260 modulates the positive and negative input signals to generate a negative output signal (OUTM). The filter circuit arrangement 215 delivers an amplified audio signal to the loudspeaker 220 and the line-out terminal 225 by filtering the positive and negative output signals.

[0039] In such exemplary operations, resistors 245 and 250 form feedback paths between the inputs of the class-D amplifier circuit arrangement 240 and the outputs of the multi-class modulation circuit arrangement 210. The feedback currents through resistors 245 and 250 are proportional to the differences between the voltages of the positive and negative input signals and the positive and negative output signals. The common-mode control circuit arrangement 230 replicates the feedback currents through resistors 245 and 250. In some examples, the common-mode control circuit arrangement 230 compares the feedback currents to a reactive current representing the feedback currents during idle operations. If the reactive current is greater than the feedback currents, the common-mode control circuit arrangement 230 supplies a current equal to the reactive current minus the feedback currents to the inputs of the class-D amplifier circuit arrangement 240.When the feedback currents are greater than the reactive current, the common-mode control circuit arrangement 230 acts as a sink for a current equal to the feedback currents minus the reactive current from the inputs of the class-D amplifier circuit arrangement 240. Advantageously, the common-mode control circuit arrangement 230 and the mismatch correction circuit arrangement 265 reduce common-mode fluctuations of the inputs of the class-D amplifier circuit arrangement 240 by matching the currents of the positive and negative input signals of the class-D amplifier circuit arrangement 240. Exemplary operations of the common-mode control circuit arrangement 230 and the mismatch correction circuit arrangement 265 are described in conjunction with... Fig. 6 and Fig. 10 illustrated and described below.

[0040] Fig. Figure 3 is a schematic diagram of an exemplary common-mode control circuit arrangement 300, which is an example of the common-mode control circuit arrangement 150, 230 of Fig. 1 and Fig. 2 is. In the example of Fig. Figure 3 includes the common-mode control circuit arrangement 300, a current control circuit arrangement 305, an amplifier circuit arrangement 310, and a mismatch correction circuit arrangement 315. The exemplary current control circuit arrangement 305 of Fig. 3 includes a first exemplary resistor 320, a second exemplary resistor 325, a first exemplary transistor 330, a third exemplary resistor 335, a second exemplary transistor 340, a fourth exemplary resistor 345, a third exemplary transistor 350, and a fourth exemplary resistor 355. The exemplary amplifier circuit arrangement 310 of Fig. 3 includes a first exemplary resistor 360, a second exemplary resistor 365, an exemplary amplifier 370, a third exemplary resistor 375 and a fourth exemplary resistor 380.

[0041] The common-mode control circuit arrangement 300 has a first input, a second input, a first output, and a second output. The first input of the common-mode control circuit arrangement 300 is structured with the amplifier circuit arrangement 120, 240 of Fig. 1 and Fig. 2 to be coupled, which provides the p-side output signal (OUTP). The second input of the common-mode control circuit arrangement 300 is structured, with the amplifier circuit arrangement 120, 260 of Fig. 1 and Fig. The first output of the common-mode control circuit arrangement 300 is coupled to the amplifier circuit arrangement 120, 240, which receives the positive input signal (INP). The second output of the common-mode control circuit arrangement 300 is coupled to the amplifier circuit arrangement 120, 240, which receives the negative input signal (INM).

[0042] The current control circuit arrangement 305 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of the current control circuit arrangement 305 are coupled to the first and second inputs of the common-mode control circuit arrangement 300, which provide the positive and negative output signals (OUTP, OUTM). The second and third terminals of the current control circuit arrangement 305 are coupled to the amplifier circuit arrangement 310 and the mismatch correction circuit arrangement 315.

[0043] The amplifier circuit arrangement 310 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of the amplifier circuit arrangement 310 are coupled to the first and second outputs of the common-mode control circuit arrangement 300, which provide the positive and negative input signals (INP, INM). The third and fourth terminals of the amplifier circuit arrangement 310 are coupled to the current control circuit arrangement 305 and the mismatch correction circuit arrangement 315.

[0044] The mismatch correction circuit arrangement 315 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of the mismatch correction circuit arrangement 315 are coupled to the first and second outputs of the common-mode regulator circuit arrangement 300, which provide the positive and negative input signals (INP, INM). The third and fourth terminals of the mismatch correction circuit arrangement 315 are coupled to the current regulator circuit arrangement 305 and the amplifier circuit arrangement 310. Examples of the mismatch correction circuit arrangement 315 are shown below in conjunction with Fig. 4, Fig. 5 and Fig. 7 further shown and described.

[0045] Resistor 320 has a first terminal and a second terminal. The first terminal of resistor 320 is connected to the second input of the common-mode control circuit arrangement 300, which provides the negative output signal (OUTM). A second terminal of resistor 320 is connected to resistor 325 and transistors 330, 340, and 350.

[0046] Resistor 325 has a first terminal and a second terminal. The first terminal of resistor 325 is connected to the first input of common-mode control circuit 300, which provides the positive output signal (OUTP). A second terminal of resistor 325 is connected to resistor 320 and transistors 330, 340, and 350. In some examples, resistors 320 and 325 have approximately (preferably exactly) the same resistance values. In such examples, resistors 320 and 325 are configured as a common-mode detection circuit that generates a common-mode voltage between the positive and negative output signals at the first and second inputs of common-mode control circuit 300.

[0047] Transistor 330 has a first terminal, a second terminal, and a control terminal. The first and control terminals of transistor 330 are connected to resistors 320 and 325, and transistors 340 and 350, respectively. The second terminal of transistor 330 is connected to resistor 335. Resistor 335 has a first terminal and a second terminal. The first terminal of resistor 335 is connected to transistor 330. The second terminal of resistor 335 is connected to a common terminal that provides a common potential (e.g., ground, AVSS, etc.).

[0048] Transistor 340 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 340 is connected to amplifier circuit 310 and mismatch circuit 315. The second terminal of transistor 340 is connected to resistor 345. The control terminal of transistor 340 is connected to resistors 320 and 325, and transistors 330 and 350. Resistor 345 has a first terminal and a second terminal. The first terminal of resistor 345 is connected to transistor 340. The second terminal of resistor 345 is connected to the common terminal, which provides the common potential.

[0049] Transistor 350 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 350 is connected to amplifier circuit 310 and mismatch correction circuit 315. The second terminal of transistor 350 is connected to resistor 355. The control terminal of transistor 350 is connected to resistors 320 and 325 and transistors 330 and 340. In the example of Fig. In the third section, transistors 330, 340, and 350 are configured as a current mirror circuit arrangement, which uses transistors 340 and 350 to mirror the current through transistor 330. Resistor 355 has a first terminal and a second terminal. The first terminal of resistor 355 is connected to transistor 350. The second terminal of resistor 355 is connected to the common terminal, which provides the common potential.

[0050] In the example of Fig. 3. Transistors 330, 340, and 350 are n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). Alternatively, transistors 330, 340, and 350 can be n-channel field-effect transistors (FETs), n-channel insulated-gate bipolar transistors (IGBTs), n-channel junction field-effect transistors (JFETs), NPN bipolar transistors (BJTs), or, with minor modifications, equivalent p-type devices. Transistors 330, 340, and 350 can be depletion-mode devices, drain-expanded devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the transistors 330, 340, 350 can be implemented in / over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).

[0051] Resistor 360 has a first terminal and a second terminal. The first terminal of resistor 360 is connected to the mismatch correction circuit 315 and the second output of the common-mode control circuit, which provides the negative input signal (INM). The second terminal of resistor 360 is connected to resistor 365 and amplifier 370. Resistor 365 also has a first terminal and a second terminal. The first terminal of resistor 365 is connected to the mismatch correction circuit 315 and the first output of common-mode control circuit 300, which provides the positive input signal (INP). The second terminal of resistor 365 is connected to resistor 360 and amplifier 370. In some examples, resistors 360 and 365 have approximately (preferably exactly) the same resistance values.In such examples, the resistors 360, 365 are structured as a common-mode detection circuit arrangement, which generates a common-mode voltage between the positive and negative input signals at the first and second outputs of the common-mode control circuit arrangement 300.

[0052] Amplifier 370 has a first input, a second input, and an output. The first input of amplifier 370 (also referred to as a non-inverting input) is coupled to resistors 360 and 365. The second input of amplifier 370 (also referred to as an inverting input) is coupled to a reference terminal that provides a reference voltage (Vref). In some examples, the reference voltage is a target common-mode voltage of the positive and negative input signals at the inputs of amplifier circuit arrangement 120 and 240, and the first and second outputs of common-mode regulator circuit arrangement 300. The output of amplifier 370 is coupled to resistors 375 and 380.

[0053] Resistor 375 has a first terminal and a second terminal. The first terminal of resistor 375 is connected to amplifier 370 and resistor 380. The second terminal of resistor 375 is connected to current control circuit 305 and mismatch correction circuit 315. Resistor 380 also has a first terminal and a second terminal. The first terminal of resistor 380 is connected to amplifier 370 and resistor 375. The second terminal of resistor 380 is connected to current control circuit 305 and mismatch correction circuit 315.

[0054] In an exemplary operation, the current control circuit arrangement 305 determines the feedback currents through the resistors 130, 140, 245, 250 of Fig. 1 and Fig. 2 in response to the currents through resistors 320, 325. Transistors 340, 350 reflect the feedback currents in response to a reflection of the current through transistor 330. Transistors 340, 350 contribute current to the positive and negative common-mode signals (CM_INP, CM_INM) at inputs of the mismatch correction circuit arrangement 315 to compensate the positive and negative input signals for the feedback currents.

[0055] In an exemplary operation, the amplifier circuit arrangement 310, in response to a comparison by the amplifier 370, determines a difference between the common-mode voltage of the positive and negative input signals and a target common-mode voltage. Resistors 360 and 365 set the first input of the amplifier 370 to the common-mode voltage of the positive and negative input signals, and the reference terminal, which is coupled to the second input of the amplifier circuit arrangement 370, provides the target common-mode voltage. The amplifier circuit arrangement 370 produces an output proportional to the difference between the measured and the target common-mode voltage. Resistors 375 and 380 contribute current to the positive and negative common-mode signals at the input of the mismatch correction circuit arrangement 315 to compensate for any discrepancy between the measured and the target common-mode voltage.

[0056] In exemplary operations, the mismatch correction circuit arrangement 315 controls the injection of the positive and negative common-mode signals into the inputs of the amplifier circuit arrangement 120, 240, 260 to compensate for common-mode voltage errors. Advantageously, the mismatch correction circuit arrangement 315 sets the voltages of the positive and negative common-mode signals to prevent parasitic capacitances of transistors 340, 350 from generating voltage fluctuations during switching events. Exemplary operations of the common-mode control circuit arrangement 300 are described in conjunction with Fig. 6 below, illustrated and described.

[0057] Fig. Figure 4 is a schematic diagram of an exemplary mismatch correction circuit arrangement 400, which is an example of the mismatch circuit arrangement 160, 265, 315 of Fig. 1, Fig. 2 and Fig. 3 is. In the example of Fig. Figure 4 includes the mismatch correction circuit arrangement 400, comprising a first switch 410, a second switch 420, a third switch 430, a fourth switch 440, a clock circuit arrangement 450, a first transistor 460, a second transistor 470, and a control circuit arrangement 480. The mismatch correction circuit arrangement 400 has a first input, a second input, a third input, a fourth input, a first output, and a second output. The first input of the mismatch correction circuit arrangement 400 is structured with transistor 340. Fig. 3 and the resistor 375 from Fig. 3 or more generally the current control circuit arrangement 305 of Fig. 3 and the amplifier circuit arrangement 310 of Fig. 3 are coupled, providing the negative common-mode signal (CM_INM). The second input of the mismatch correction circuit arrangement 400 is structured, with transistor 350 from Fig. 3 and the resistor 380 from Fig. The third and fourth inputs and the first and second outputs of the mismatch correction circuit arrangement 400 are connected to the amplifier circuit arrangement 120, 240, which provide the positive and negative input signals (INP, INM).

[0058] Switch 410 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 410 is connected to switch 420 and transistor 460. The second terminal of switch 410 is connected to switch 430 and the first input of the mismatch correction circuit 400, which provides the negative common-mode signal (CM_INM). The control terminal of switch 410 is connected to switch 440 and clock circuit 450.

[0059] Switch 420 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 420 is connected to switch 410 and transistor 460. The second terminal of switch 420 is connected to switch 440 and the second input of the mismatch correction circuit 400, which provides the negative common-mode signal (CM_INM). The control terminal of switch 420 is connected to switch 430 and clock circuit 450.

[0060] Switch 430 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 430 is connected to switch 440 and transistor 470. The second terminal of switch 430 is connected to switch 420 and the positive common-mode signal (CM_INP). The control terminal of switch 430 is connected to switch 420 and clock circuit assembly 450.

[0061] Switch 440 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 440 is connected to switch 430 and transistor 470. The second terminal of switch 440 is connected to switch 420 and the first input of the mismatch correction circuit 400, which provides the positive common-mode signal (CM_INP). The control terminal of switch 440 is connected to switch 410 and clock circuit 450.

[0062] The clock circuit arrangement 450 has a first terminal and a second terminal. The first terminal of the clock circuit arrangement 450 is connected to switches 410 and 440. The second terminal of the clock circuit arrangement 450 is connected to switches 420 and 430. In the example of Fig. In section 4, the clock circuit arrangement 450 supplies a first clock signal (PH1) and a second clock signal (PH2) to the switches 410, 420, 430, 440. In such examples, the first clock signal and the second clock signal have different phases and non-overlapping pulses.

[0063] Transistor 460 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 460 is connected to the first output of the mismatch correction circuit assembly 400, which provides the negative input signal (INM). The second terminal of transistor 460 is connected to switches 410 and 420. The control terminal of transistor 460 is connected to transistor 470 and control circuit assembly 480.

[0064] Transistor 470 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 470 is connected to the second output of the mismatch correction circuit assembly 400, which provides the positive input signal (INP). The second terminal of transistor 470 is connected to switches 430 and 440. The control terminal of transistor 470 is connected to transistor 460 and control circuit assembly 480.

[0065] In the example of Fig. 4. Transistors 460 and 470 are n-channel MOSFETs. Alternatively, transistors 460 and 470 can be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or, with minor modifications, equivalent p-type devices. Transistors 460 and 470 can be depletion-mode devices, drain-expanded devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, transistors 460 and 470 can be implemented in / over a silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or gallium arsenide (GaAs) substrate.

[0066] The control circuit assembly 480 has a first terminal, a second terminal, and a third terminal. The first terminal of the control circuit assembly 480 is coupled to the third input terminal of the mismatch correction circuit assembly 400, which provides the positive input signal (INP). The second terminal of the control circuit assembly 480 is coupled to the fourth input terminal of the mismatch correction circuit assembly 400, which provides the negative input signal (INM). The third terminal of the control circuit assembly 480 is coupled to transistors 460 and 470. An example of the control circuit assembly 480 is shown below in conjunction with Fig. 5 further illustrated and described.

[0067] In the example of Fig. In section 4, switches 410, 420, 430, and 440 are illustrated and described as switches. In some examples, switches 410, 420, 430, and 440 may be implemented or illustrated using transistors with control terminals coupled to the clock circuit arrangement 450. Furthermore, switches 410, 420, 430, and 440, and the clock circuit arrangement 450, may be illustrated or referred to as a chopping circuit arrangement. Examples of the mismatch correction circuit arrangement 400 are shown below in conjunction with Fig. 5 and Fig. Figure 7 shows and describes exemplary operations of the mismatch correction circuit arrangement 400 in conjunction with Fig. 6 below, illustrated and described.

[0068] Fig. Figure 5 is a schematic diagram of an exemplary mismatch correction circuit arrangement 500, which is another example of the mismatch circuit arrangement 160, 265, 315 of Fig. 1, Fig. 2 and Fig. 3 is, which includes an exemplary control circuit arrangement 510, which is an example of the control circuit arrangement 480 of Fig. 1 is. In the example of Fig. 5 includes the mismatch correction circuit arrangement 500 and the switches 410, 420, 430, 440 of Fig. 4, the clock circuit arrangement 450 of Fig. 4, the transistors 460, 470 of Fig. 4 and the control circuit arrangement 510. The exemplary control circuit arrangement 510 of Fig. 5 includes a first exemplary resistor 520, a second exemplary resistor 530 and an exemplary buffer circuit arrangement 540.

[0069] The mismatch correction circuit arrangement 500 has a first input, a second input, a third input, a fourth input, a first output, and a second output. The first input of the mismatch correction circuit arrangement 500 is structured, with transistor 340 from Fig. 3 and the resistor 375 from Fig. 3 or more generally the current control circuit arrangement 305 of Fig. 3 and the amplifier circuit arrangement 310 of Fig. 3 are coupled, which supply the negative common-mode signal (CM_INM). The second input of the mismatch correction circuit arrangement 500 is structured, with transistor 350 of Fig. 3 and the resistor 380 from Fig. The third and fourth inputs and the first and second outputs of the mismatch correction circuit arrangement 500 are connected to the amplifier circuit arrangement 120, 240, which provide the positive and negative input signals (INP, INM).

[0070] The control circuit assembly 510 has a first input, a second input, and an output. The first input of the control circuit assembly 510 is coupled to the first input of the mismatch correction circuit assembly 500, which provides the positive input signal. The second input of the control circuit assembly 510 is coupled to the second input of the mismatch correction circuit assembly 500, which provides the negative input signal. The output of the control circuit assembly 510 is coupled to transistors 460 and 470.

[0071] Resistor 520 has a first terminal and a second terminal. The first terminal of resistor 520 is connected to the first input of the control circuit arrangement 510, which provides the positive input signal (INP). The second terminal of resistor 520 is connected to resistor 530 and the buffer circuit arrangement 540.

[0072] Resistor 530 has a first terminal and a second terminal. The first terminal of resistor 530 is connected to the second input of control circuit assembly 510, which provides the negative input signal (INM). The second terminal of resistor 520 is connected to resistor 520 and buffer circuit assembly 540. In some examples, resistors 520 and 530 have approximately (preferably exactly) the same resistance values. In such examples, resistors 520 and 530 are configured as a common-mode detection circuit assembly that generates a common-mode voltage between the positive and negative input signals at the first and second inputs of control circuit assembly 510.

[0073] The buffer circuit arrangement 540 has a first input, a second input, and an output. The first input (also called a non-inverting input) of the buffer circuit arrangement 540 is coupled to resistors 520 and 530. The second input (also called an inverting input) and the output of the buffer circuit arrangement 540 are coupled to transistors 460 and 470. In some examples, the buffer circuit arrangement 540 is illustrated or described as an amplifier. Example operations of the control circuit arrangement 510 are described below. Fig. 5 are in connection with Fig. 6 below, illustrated and described.

[0074] Fig. Figure 6 is a flowchart representing exemplary machine-readable instructions or exemplary operations 600, which are implemented using an exemplary implementation of the mismatch correction circuit arrangement 160, 265, 315, 400, 500 of Fig. 1, Fig. 2, Fig. 3, Fig. 4 and Fig. 5 or more generally the common-mode control circuit arrangement 150, 230, 300 of Fig. 1, Fig. 2 and Fig. 3 must be at least either executed, instantiated, and / or performed. The exemplary operations 600 of Fig. 6 begin at block 605, where the amplifier circuit arrangement 120, 240 of the Fig. 1 and Fig. 2 accepts a first input voltage and a second input voltage as a single input signal. (Block 605). In exemplary operations, an analog signal source, such as the audio source 205 of Fig. 2 or a digital-to-analog converter (DAC), a positive input signal (INP) and a negative input signal (INM) to the amplifier circuit arrangement 120, 240, 260 of Fig. 1 and Fig. 2. In such exemplary operations, the positive and negative input signals are a differential pair of input signals with an amplitude defined by a common-mode voltage. The common-mode voltage is a voltage equidistant from the voltages of the positive and negative input signals. For example, if the positive input signal has a voltage of five volts and the negative input signal has a voltage of negative five volts, then the common-mode voltage is zero volts. In another example, if the positive input signal has a voltage of six volts and the negative input signal has a voltage of negative four volts, then the common-mode voltage is approximately one volt.

[0075] The amplifier circuit arrangement 120, 240 generates a first output voltage based on the input signal (block 610). Furthermore, the amplifier circuit arrangement 120, 260 generates... Fig. 1 and Fig. 2 a second output voltage based on the input signal. (Block 615). In some examples, the positive and negative input signals can represent audio signals, analog data signals, etc. In such examples, the amplifier circuit arrangement 120, 240, 260 amplifies and / or modulates the positive and negative input signals to generate a positive output signal (OUTP) and a negative output signal (OUTM). For example, the multi-class modulation circuit arrangement 210 of Fig. 2 structured to implement a 1L modulation, which generates the positive output signal using class D modulation and the negative output signal using class AB modulation. In such an example, the filter circuit arrangement 215 of Fig. 2. The positive output signal, which, when differentially combined with the negative output signal, produces an amplified audio signal. In exemplary operations, the amplifier circuit arrangement 120, 240, 260 generates a positive and a negative output signal with relatively higher voltages compared to the positive and negative input signals. Advantageously, the amplifier circuit arrangement 120, 240, 260 allows a circuit arrangement with relatively low power to generate relatively higher signals.

[0076] The resistances 130, 245 of Fig. 1 and Fig. 2 generate a first feedback current based on the difference between the first output voltage and the first input voltage (Block 620). In exemplary operations, resistors 130 and 245 form a feedback path between a positive output of the amplifier circuit arrangement 120 and 240 and a positive input of the amplifier circuit arrangement 120 and 240. In such exemplary operations, resistors 130 and 245 modify the current of the positive input signal in response to current being supplied or drawn through resistors 130 and 245. Advantageously, the feedback path formed by resistors 130 and 245 improves the noise immunity and stability of the amplifier circuit arrangement 120 and 240.

[0077] The resistances 140, 250 of Fig. 1 and Fig. 2 generate a second feedback current based on the difference between the second output voltage and the second input voltage (Block 625). In exemplary operations, resistors 140 and 250 form a feedback path between a negative output of amplifier circuit arrangement 120 and 260 and a negative input of amplifier circuit arrangement 120 and 240. In such exemplary operations, resistors 140 and 250 modify the current of the negative input signal in response to current being supplied or drawn through resistors 140 and 250. Advantageously, the feedback path formed by resistors 140 and 250 improves the noise immunity and stability of amplifier circuit arrangement 120 and 260.

[0078] The control circuit arrangement 480, 510 of Fig. 4 and Fig. 5 determines a common-mode voltage of the input signal (block 630). In example operations, resistors 520 and 530 form the Fig. 5 a voltage divider circuit arrangement between the positive and negative input signals. The voltage between resistors 520 and 530 represents a measured common-mode voltage (Vcm). In such exemplary operations, the buffer circuit arrangement 540 controls Fig. 5 the transistors 460, 470 using the measured common-mode voltage by buffering the measured common-mode voltage from the resistors 520, 530.

[0079] The mismatch correction circuit arrangement 160, 265, 315, 400, 500 isolates the first and second input voltages from voltages of the common-mode control circuit arrangement 150, 230, 300 based on the common-mode voltage (Block 635). In exemplary operations, the control circuit arrangement 480, 510 controls Fig. 4 and Fig. 5 the transistors 460, 470 of Fig. 4 and Fig. 5 using the measured common-mode voltage of the positive and negative input signals. Advantageously, transistors 460 and 470 operate in saturation in response to the control circuit arrangement 480 and 510 supplying the measured common-mode voltage at the control terminals of transistors 460 and 470. When operating in saturation, transistors 460 and 470 set the voltages of the positive and negative common-mode signals (Vcmpb and Vcmmb) equal to the common-mode voltage minus the gate-to-source voltage of transistors 460 and 470. In such exemplary operations, transistors 460 and 470 isolate the positive and negative input signals from voltage fluctuations in the positive and negative common-mode signals in response to the control circuit arrangement 480 and 510 using the common-mode voltage to operate in saturation mode.Advantageously, transistors 460, 470 reduce voltage fluctuations at the positive and negative input signals during switching events of switches 410, 420, 430, 440. Fig. 4, which are described in more detail below.

[0080] The switch 440 from Fig. Block 640 (4) compensates the first input voltage for the first feedback current with a first control current. Additionally, switch 410 compensates for... Fig. 4 the second input voltage for the second feedback current with a second control current. (Block 645). In exemplary operations, resistors 320, 325 of Fig. Three feedback currents flow through resistors 130, 140, 245, and 250 in response to their resistances of the same values. In such exemplary operations, transistors 340 and 350 reflect the current through transistor 330, which is a combination of the feedback currents from resistors 320 and 325. Advantageously, the current flowing through transistors 340 and 350 represents the feedback currents through resistors 130, 140, 245, and 250.

[0081] In exemplary operations, resistors 360 and 365 form a voltage divider circuit between the positive and negative input signals. The voltage between resistors 360 and 365 represents a measured common-mode voltage of the positive and negative input signals at an inverting input of amplifier 370. Fig. 3. In such exemplary operations, amplifier 370 compares the measured common-mode voltage with the reference voltage (Vref), which represents a target common-mode voltage. The output of amplifier 370 is proportional to the difference between the measured common-mode voltage and the target common-mode voltage. The output voltage of amplifier 370 sets the current through resistors 375 and 380. Fig. 3 proportional to the difference between the measured common-mode voltage and the target common-mode voltage. Advantageously, currents from transistors 340 and 350 compensate for feedback currents, and currents from resistors 375 and 380 compensate for common-mode mismatch. Advantageously, the currents of the positive and negative common-mode signals (CM_INP and CM_INM) can compensate for common-mode shifts resulting from mismatches and feedback currents.

[0082] In exemplary operations, the clock circuit arrangement 450 of Fig. 4 and Fig. 5. The first and second clock signals (PH1, PH2) are used to control switches 410, 420, 430, and 440. During an initial section, such as the first half of a clock cycle, the clock circuit arrangement 450 structures the first and second clock signals to close switches 410 and 440 and to open switches 420 and 430. When closed, switch 410 supplies currents of the negative common-mode signal to transistor 460, and switch 440 supplies currents of the positive common-mode signal to transistor 470. In such exemplary operations, transistor 460 modifies the current of the negative input signal using currents of the negative common-mode signal, and transistor 470 modifies the current of the positive input signal using currents of the positive common-mode signal.

[0083] The clock circuit arrangement 450 from Fig. Block 4 determines whether half a clock cycle has elapsed (Block 650). During the first section, such as the first half of a clock cycle, clock circuit 450 generates the first and second clock signals to close switches 410 and 440 and open switches 420 and 430. If clock circuit 450 determines that half a clock cycle has not elapsed (e.g., Block 650 returns a result of NO), the controller proceeds by returning to Block 650.

[0084] If the clock circuit arrangement 450 determines that half a clock cycle has passed (e.g., block 650 returns a result of YES), transistors 460 and 470 compensate for this. Fig. 4 the first and second control currents for voltage differences. (Block 655). In exemplary operations, transistors 460, 470 operate in a saturation region in response to the control circuit arrangement 480, 510 supplying the measured common-mode voltage at the control terminals of transistors 460, 470. In saturation, transistors 460, 470 set the positive and negative common-mode signals (CM_INP, CM_INM) equal to the common-mode voltage minus the gate-to-source voltage of transistors 460, 470. In such exemplary operations, transistors 460, 470 reduce voltage fluctuations resulting from parasitic capacitances of transistors 340, 350. Fig. 3 results from the fact that the control circuit arrangement 480, 510 uses the common-mode voltage to operate in saturation mode. Advantageously, the use of transistors 460, 470 to supply voltages of the common-mode input signals on the positive and negative sides compensates for parasitic capacitances of the current regulator circuit arrangement 305 and the amplifier circuit arrangement 310.

[0085] Switch 430 compensates the first input voltage for the first feedback current with the second control current (block 660). Switch 420 also compensates the second input voltage for the second feedback current with the first control current (block 665). In exemplary operation, during the second half of the clock cycle, clock circuitry 450 structures the first and second clock signals to open switches 410 and 440 and to close switches 420 and 430. When closed, switch 430 supplies negative common-mode currents to transistor 470, and switch 420 supplies positive common-mode currents to transistor 460. In such exemplary operations, transistor 460 modifies the current of the negative input signal using currents of the positive common-mode signal, and transistor 470 modifies the current of the positive input signal using currents of the negative common-mode signal.Advantageously, the mismatch circuit arrangement 160, 265, 400, 500 averages out discrepancies (asymmetries) between components of the common-mode control circuit arrangement 150, 230, 300 in response to switching between using the common-mode input signals on the positive and negative sides, in order to balance the positive and negative input signals. Advantageously, switching between the positive and negative common-mode signal input reduces an offset resulting from the common-mode control circuit arrangement 150, 230, 300.

[0086] Clock circuit 450 determines whether another half clock cycle has elapsed (block 670). During the second half of the clock cycle, clock circuit 450 generates the first and second clock signals to open switches 410 and 440 and to close switches 420 and 430. If clock circuit 450 determines that no half clock cycle has elapsed (e.g., block 670 returns a result of NO), the controller proceeds by returning to block 670.

[0087] If the clock circuit arrangement 450 detects that half a clock cycle has elapsed (e.g., block 670 returns a result of YES), transistors 460 and 470 compensate the first and second control currents for voltage differences (block 675). In exemplary operations, transistors 460 and 470 operate in a saturation region in response to the control circuit arrangement 480 and 510 supplying the measured common-mode voltage at the control terminals of transistors 460 and 470. In saturation, transistors 460 and 470 set the positive and negative common-mode signals (CM_INP and CM_INM) equal to the common-mode voltage minus the gate-to-source voltage of transistors 460 and 470.In such exemplary operations, transistors 460 and 470 reduce voltage fluctuations in the positive and negative input signals that arise from parasitic capacitances of transistors 340 and 350 in response to the control circuit arrangement 480 and 510 using the common-mode voltage to operate in saturation mode. Advantageously, the use of transistors 460 and 470 to reduce voltages of the positive and negative common-mode input signals compensates for parasitic capacitances of the current regulator circuit arrangement 305 and the amplifier circuit arrangement 310. Control returns to block 640.

[0088] Exemplary procedures are presented with reference to the [document / section / etc.]. Fig. 6 illustrated flowcharts are described. Many other methods for implementing the mismatch correction circuit arrangement 160, 265, 315, 400, 500 or, more generally, the common-mode control circuit arrangement 150, 230, 300 are described. Fig. 1, Fig. 2 and Fig. However, three options can also be used in this description. For example, the order in which the blocks are executed can be changed, or some of the described blocks can be modified, eliminated, or combined. Similarly, additional operations can be included in the manufacturing process before, between, or after the blocks shown in the illustrated examples.

[0089] Fig. Figure 7 is a schematic diagram of an exemplary mismatch correction circuit arrangement 700, which is another example of the mismatch circuit arrangements 160, 265, 315, 400, 500 of Fig. 1, Fig. 2, Fig. 3, Fig. 4 and Fig. 5 is, and the exemplary control circuit arrangement 710, which is another example of the control circuit arrangement 480, 510 of Fig. 4 and Fig. 5 is. In the example of Fig. 7 includes the mismatch correction circuit arrangement 700, switches 410, 420, 430, 440 of Fig. 4 and Fig. 5, the clock circuit arrangement 450 of Fig. 4 and Fig. 5, transistors 460, 470 of Fig. 4 and Fig. 5 and the control circuit arrangement 710. The exemplary control circuit arrangement 710 of Fig. Figure 7 includes a first exemplary transistor 720 and a second exemplary transistor 730. The mismatch correction circuit arrangement 700 has a first input, a second input, a third input, a fourth input, a first output, and a second output. The first input of the mismatch correction circuit arrangement 700 is structured with transistor 340. Fig. 3 and the resistor 375 from Fig. 3 or more generally the current control circuit arrangement 305 of Fig. 3 and the amplifier circuit arrangement 310 of Fig. 3 are coupled, providing the negative common-mode signal (CM_INM). The second input of the mismatch correction circuit arrangement 700 is structured, with transistor 350 from Fig. 3 and the resistor 380 from Fig. The third and fourth inputs and the first and second outputs of the mismatch correction circuit arrangement 700 are connected to the amplifier circuit arrangement 120, 240, which provide the positive and negative input signals (INP, INM).

[0090] The control circuit arrangement 710 has a first input, a second input, a first output, a second output, a third output, a fourth output, a fifth output, and a sixth output. The first and second inputs of the control circuit arrangement 710 are coupled to the first and second inputs of the mismatch correction circuit arrangement 700, which provide the positive and negative input signals. The first and second outputs of the control circuit arrangement 710 are coupled to the first and second outputs of the mismatch correction circuit arrangement 700, which provide the positive and negative input signals. The third output of the control circuit arrangement 710 is coupled to switches 410 and 420 and transistor 460. The fourth output of the control circuit arrangement 710 is coupled to switches 430 and 440 and transistor 470.The fifth output of the control circuit arrangement 710 is coupled to the control terminal of transistor 460. The sixth output of the control circuit arrangement 710 is coupled to the control terminal of transistor 470.

[0091] Unlike in the example of Fig. 4 and Fig. In section 5, the control circuit arrangement 710 couples the control terminal of transistor 460 to the second input of the mismatch correction circuit arrangement 700, which provides the negative input signal (INM). Furthermore, the control circuit arrangement 710 couples the control terminal of transistor 470 to the first input of the mismatch correction circuit arrangement 700, which provides the positive input signal (INP). In such examples, the voltages of the positive and negative input signals control transistors 460 and 470, respectively.

[0092] Transistor 720 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 720 is connected to the second input of the mismatch correction circuit assembly 700, which provides the negative input signal. The second terminal of transistor 720 is connected to switches 410, 420, and transistor 460. The control terminal of transistor 720 is connected to the first input of the mismatch correction circuit assembly 700, which provides the positive input signal (INP).

[0093] Transistor 730 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 730 is connected to the first input of the mismatch correction circuit assembly 700, which provides the positive input signal (INP). The second terminal of transistor 730 is connected to switches 430, 440, and transistor 470. The control terminal of transistor 730 is connected to the second input terminal of the mismatch correction circuit assembly 700, which provides the negative input signal (INM).

[0094] In the example of Fig. 7. Transistors 460, 470, 720, and 730 are n-channel MOSFETs. Alternatively, transistors 460, 470, 720, and 730 can be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or, with minor modifications, equivalent p-type devices. Transistors 460, 470, 720, and 730 can be depletion-mode devices, drain-expanded devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the transistors 460, 470, 720, 730 can be implemented in / over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).

[0095] In an exemplary operation, transistors 460 and 720 are structured to act as sinks for a current from the negative input signal, and transistors 470 and 730 are structured to act as sinks for a current from the positive input signal. Transistors 460 and 720 detect a common-mode voltage of the positive and negative input signals in response to their control terminals being coupled to these signals. Advantageously, the common-mode voltage of the positive and negative input signals controls transistors 460, 470, 720, and 730 in response to each pair of transistors having different control terminals coupled to the positive and negative input signals. Advantageously, the transistors 460, 470, 720, 730 have the following advantages compared to the use of resistors 520, 530: Fig. 5 and the buffer circuit arrangement 540 of Fig. 5 for controlling the transistors 460, 470, resulting in a faster response time, lower costs, lower energy consumption and a smaller system-on-chip size.

[0096] Fig. Figure 8 is a block diagram of an exemplary common-mode control circuit arrangement 800, which is a further example of the common-mode control circuit arrangement 150, 230 of Fig. 1 and Fig. 2 is. In the example of Fig. Figure 8 includes the common-mode control circuit arrangement 800, a reactive current source circuit arrangement 805, a feedback current source circuit arrangement 810, a current source circuit arrangement 815, a current sink circuit arrangement 820, a common-mode voltage circuit arrangement 825, a first mismatch correction circuit arrangement 830, a second mismatch correction circuit arrangement 835, an input monitoring circuit arrangement 840, and a common-mode voltage control circuit arrangement 845. The feedback current source circuit arrangement 810 of Fig. 8 includes a first exemplary feedback current mirror circuit arrangement 850 and a second exemplary feedback current mirror circuit arrangement 855.

[0097] The common-mode control circuit arrangement 800 has a first input, a second input, a first output, and a second output. The first input of the common-mode control circuit arrangement 800 is structured with the amplifier circuit arrangement 120, 240 of Fig. 1 and Fig. 2 to be coupled, which provides the positive output signal (OUTP). The second input of the common-mode control circuit arrangement 800 is structured, with the amplifier circuit arrangement 120, 260 of Fig. 1 and Fig. The first and second outputs of the common-mode control circuit arrangement 800 are coupled to the amplifier circuit arrangement 120, 240, which receives the positive and negative input signals (INP, INM). In some examples, the common-mode control circuit arrangement 800 further includes an input supply terminal and an output supply terminal coupled to an input supply voltage (AVDD) and an output supply voltage (PVDD), respectively. The input supply voltage represents voltages of the positive and negative input signals. The output supply voltage represents voltages of the positive and negative output signals.

[0098] The reactive power source circuit arrangement 805 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the reactive power source circuit arrangement 805 is connected to the input supply terminal, which provides the input supply voltage (AVDD). The second terminal of the reactive power source circuit arrangement 805 is connected to the output supply terminal, which provides the output supply voltage (PVDD). The third terminal of the reactive power source circuit arrangement 805 is connected to the current source circuit arrangement 815. The fourth terminal of the reactive power source circuit arrangement 805 is connected to the feedback current source circuit arrangement 810 and the current sink circuit arrangement 820.

[0099] The feedback current source circuit arrangement 810 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of the feedback current source circuit arrangement 810 is coupled to the first output of the common-mode control circuit arrangement 800, which provides the positive-side output signal (OUTP). The second terminal of the feedback current source circuit arrangement 810 is coupled to the second output of the common-mode control circuit arrangement 800, which provides the negative-side output signal (OUTM). The third terminal of the feedback current source circuit arrangement 810 is coupled to the current source circuit arrangement 815. The fourth terminal of the feedback current source circuit arrangement 810 is coupled to the reactive current source circuit arrangement 805 and the current sink circuit arrangement 820.The fifth terminal of the feedback current mirror circuit arrangement 810 is coupled to the current sink circuit arrangement 820.

[0100] The current source circuit assembly 815 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of the current source circuit assembly 815 is connected to the input supply terminal, which provides the input supply voltage. The second terminal of the current source circuit assembly 815 is connected to the reactive power source circuit assembly 805. The third terminal of the current source circuit assembly 815 is connected to the current sink circuit assembly 820 and the input monitoring circuit assembly 840. The fourth and fifth terminals of the current source circuit assembly 815 are connected to the mismatch correction circuit assembly 830.

[0101] The current sink circuit arrangement 820 has a first terminal, a second terminal, a third terminal, a fourth terminal, and a fifth terminal. The first terminal of the current sink circuit arrangement 820 is connected to the input supply terminal, which provides the input supply voltage. The second terminal of the current sink circuit arrangement 820 is connected to the reactive power source circuit arrangement 805 and the feedback current source circuit arrangement 810. The third terminal of the current sink circuit arrangement 820 is connected to the current source circuit arrangement 815 and the input monitoring circuit arrangement 840. The fourth and fifth terminals of the current sink circuit arrangement 820 are connected to the mismatch correction circuit arrangement 835.

[0102] The common-mode voltage circuit assembly 825 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the common-mode voltage circuit assembly 825 is coupled to the mismatch correction circuit assembly 830, 835 and the first output of the common-mode control circuit assembly 800, which provides the input signal on the positive side. The second terminal of the common-mode voltage circuit assembly 825 is coupled to the mismatch correction circuit assembly 830, 835 and the second output of the common-mode control circuit assembly 800, which provides the input signal on the negative side. The third and fourth terminals of the common-mode voltage circuit assembly 825 are coupled to the common-mode voltage control circuit assembly 845.In some examples, the common-mode voltage circuit arrangement 825 has any number of terminals that are connected to the common-mode voltage control circuit arrangement 845.

[0103] The mismatch correction circuit arrangement 830 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of the mismatch correction circuit arrangement 830 are coupled to the current source circuit arrangement 815. The third and fourth terminals of the mismatch correction circuit arrangement 830 are coupled to the common-mode voltage circuit arrangement 825, the mismatch correction circuit arrangement 835, the input monitoring circuit arrangement 840, and the first and second outputs of the common-mode control circuit arrangement 800, which provides the positive and negative input signals (INP, INM).

[0104] The mismatch correction circuit arrangement 835 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first and second terminals of the mismatch correction circuit arrangement 835 are coupled to the current sink circuit arrangement 820. The third and fourth terminals of the mismatch correction circuit arrangement 835 are coupled to the common-mode voltage circuit arrangement 825, the mismatch correction circuit arrangement 830, the input monitoring circuit arrangement 840, and the first and second outputs of the common-mode control circuit arrangement 800, which provides the positive and negative input signals (INP, INM).

[0105] The input monitoring circuit arrangement 840 has a first terminal, a second terminal, and a third terminal. The first terminal of the input monitoring circuit arrangement 840 is coupled to the first output of the common-mode control circuit arrangement 800, which provides the positive input signal (INP). The second terminal of the input monitoring circuit arrangement 840 is coupled to the second output of the common-mode control circuit arrangement 800, which provides the negative input signal (INM). The third terminal of the input monitoring circuit arrangement 840 is coupled to the current source circuit arrangement 815 and the current sink circuit arrangement 820.

[0106] The common-mode voltage control circuit arrangement 845 has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the common-mode voltage control circuit arrangement 845 is coupled to the output supply terminal, which provides the output supply voltage. The second and third terminals of the common-mode voltage control circuit arrangement 845 are coupled to the common-mode voltage circuit arrangement 825. The fourth terminal of the common-mode voltage control circuit arrangement 845 is coupled to an analog gain terminal, which provides an indication of the analog gain of the amplifier circuit arrangement 120, 240. In some examples, the common-mode voltage control circuit arrangement 845 is coupled to a bus that provides the analog gain. In other examples, the common-mode voltage control circuit arrangement 845 is coupled to a register that sets the analog gain.

[0107] The feedback current mirror circuit arrangement 850 has a first terminal, a second terminal, and a third terminal. The first terminal of the feedback current mirror circuit arrangement 850 is coupled to the first input of the common-mode control circuit arrangement 800, which provides the output signal on the positive side. The second terminal of the feedback current mirror circuit arrangement 850 is coupled to the second input of the common-mode control circuit arrangement 800, which provides the output signal on the negative side. The third terminal of the feedback current mirror circuit arrangement 850 is coupled to the current source circuit arrangement 815.

[0108] The feedback current mirror circuit arrangement 855 has a first terminal, a second terminal, and a third terminal. The first terminal of the feedback current mirror circuit arrangement 855 is coupled to the first input of the common-mode control circuit arrangement 800, which provides the output signal on the positive side. The second terminal of the feedback current mirror circuit arrangement 855 is coupled to the second input of the common-mode control circuit arrangement 800, which provides the output signal on the negative side. The third terminal of the feedback current mirror circuit arrangement 855 is coupled to the reactive current source circuit arrangement 805 and the current sink circuit arrangement 820.

[0109] Examples of the reactive current source circuit arrangement 805, the feedback current source circuit arrangement 810, the current source circuit arrangement 815, the current sink circuit arrangement 820, the common-mode voltage circuit arrangement 825, the input monitoring circuit arrangement 840, the common-mode voltage control circuit arrangement 845, the feedback current mirror circuit arrangement 850 and the feedback current mirror circuit arrangement 855 are further illustrated and described in “METHODS AND APPARATUS TO REGULATE A COMMON MODE VOLTAGE OF AN AMPLIFIER”, U.S. Patent Application No. 18 / 642,427, which is incorporated in its entirety by reference and has been transferred to the successor in title of the present application.

[0110] Fig. Figure 9 is a schematic diagram of a first mismatch correction circuit arrangement 905, which is an example of the mismatch circuit arrangement 830 of Fig. 8 is, and the second mismatch circuit arrangement 910, which is an example of the mismatch circuit arrangement 835 of Fig. 8 is. The exemplary mismatch correction circuit arrangement 905 of Fig. 9 includes a first exemplary transistor 915, a second exemplary transistor 920, an exemplary control circuit arrangement 930, a first exemplary switch 934, a second exemplary switch 938, a third exemplary switch 942, a fourth exemplary switch 946, and an exemplary clock circuit arrangement 950. The exemplary control circuit arrangement 930 of Fig. Figure 9 includes a first exemplary transistor 954 and a second exemplary transistor 958. The exemplary mismatch correction circuit arrangement 910 of Fig. Figure 9 includes a first exemplary transistor 960, a second exemplary transistor 965, an exemplary control circuit arrangement 970, a first exemplary switch 974, a second exemplary switch 976, a third exemplary switch 980, a fourth exemplary switch 984, and an exemplary clock circuit arrangement 988. The exemplary control circuit arrangement 970 includes a first exemplary transistor 990 and a second exemplary transistor 995.

[0111] The mismatch correction circuit arrangement 905 has a first input, a second input, a third input, a fourth input, a first output, and a second output. The first input of the mismatch correction circuit arrangement 905 is structured with the current source circuit arrangement 815. Fig. The second input of the mismatch correction circuit arrangement 905 is connected to the current source circuit arrangement 815, which provides the positive common-mode signal (CM_INM). The third and fourth inputs and the first and second outputs of the mismatch correction circuit arrangement 905 are connected to the amplifier circuit arrangement 120, 240, which provides the positive and negative input signals (INP, INM).

[0112] The mismatch correction circuit arrangement 910 has a first input, a second input, a third input, a fourth input, a first output, and a second output. The first input of the mismatch correction circuit arrangement 910 is structured with the current sink circuit arrangement 820. Fig. The second input of the mismatch correction circuit arrangement 910 is coupled to the current sink circuit arrangement 820, which provides the positive common-mode signal (CM_INP). The third and fourth inputs and the first and second outputs of the mismatch correction circuit arrangement 910 are coupled to the amplifier circuit arrangement 120, 240, which provides the positive and negative input signals (INP, INM).

[0113] Transistor 915 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 915 is connected to switches 942, 946, and transistor 954. The second terminal of transistor 915 is connected to the second output of the mismatch correction circuit assembly 905, which provides the negative input signal (INM). The control terminal of transistor 915 is connected to the control circuit assembly 930 and the fourth input of the mismatch correction circuit assembly 905, which provides the negative input signal (INM).

[0114] Transistor 920 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 920 is connected to switches 934, 938, and transistor 958. The second terminal of transistor 920 is connected to the first output of the mismatch correction circuit assembly 905, which provides the positive input signal (INP). The control terminal of transistor 920 is connected to the control circuit assembly 930 and the third input of the mismatch correction circuit assembly 905, which provides the positive input signal (INP).

[0115] The control circuit assembly 930 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. The first terminal of the control circuit assembly 930 is connected to transistor 915 and switches 942 and 946. The second terminal of the control circuit assembly 930 is connected to transistor 920 and switches 934 and 938. The third terminal of the control circuit assembly 930 is connected to the control terminal of transistor 915 and the fourth input of the mismatch correction circuit assembly 905, which provides the negative input signal (INM). The fourth terminal of the control circuit assembly 930 is connected to the control terminal of transistor 920 and the third input of the mismatch correction circuit assembly 905, which provides the positive input signal (INP).The fifth terminal of the control circuit assembly 930 is connected to the third input and the first output of the mismatch correction circuit assembly 905, which provides the positive input signal (INP). The sixth terminal of the control circuit assembly 930 is connected to the fourth input and the second output of the mismatch correction circuit assembly 905, which provides the negative input signal (INM).

[0116] Switch 934 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 934 is connected to the first input of the mismatch correction circuit assembly 905, which provides the positive common-mode signal (CM_INP). The second terminal of switch 934 is connected to transistors 920 and 958, and to switch 938. The control terminal of switch 934 is connected to switch 946 and the clock circuit assembly 950.

[0117] Switch 938 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 938 is connected to the second input of the mismatch correction circuit assembly 905, which provides the negative common-mode signal (CM_INM). The second terminal of switch 938 is connected to transistors 920 and 958 and switch 934. The control terminal of switch 938 is connected to switch 942 and clock circuit assembly 950.

[0118] Switch 942 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 942 is connected to the first input of the mismatch correction circuit assembly 905, which provides the positive common-mode signal (CM_INP). The second terminal of switch 942 is connected to transistors 915 and 954 and switch 946. The control terminal of switch 942 is connected to switch 938 and clock circuit assembly 950.

[0119] Switch 946 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 946 is connected to the second input of the mismatch correction circuit assembly 905, which provides the common-mode signal (CM_INM). The second terminal of switch 946 is connected to transistors 915 and 954 and switch 942. The control terminal of switch 946 is connected to switch 934 and clock circuit assembly 950.

[0120] The clock circuit assembly 950 has a first terminal and a second terminal. The first terminal of the clock circuit assembly 950 is connected to switches 934 and 946. The second terminal of the clock circuit assembly 950 is connected to switches 938 and 342. In the example of Fig. In example 9, the clock circuit arrangement 950 supplies a first clock signal (PH1) and a second clock signal (PH2) to the switches 934, 938, 942, 946. In such examples, the first clock signal and the second clock signal have different phases and non-overlapping pulses.

[0121] Transistor 954 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 954 is connected to transistor 915 and switches 942 and 946. The second terminal of transistor 954 is connected to the second output of the mismatch correction circuit assembly 905, which provides the negative input signal (INM). The control terminal of transistor 954 is connected to the third input of the mismatch correction circuit assembly 905, which provides the positive input signal (INP).

[0122] Transistor 958 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 958 is connected to transistor 920 and switches 934 and 938. The second terminal of transistor 958 is connected to the first output of the mismatch correction circuit assembly 905, which provides the positive input signal (INP). The control terminal of transistor 958 is connected to the fourth input of the mismatch correction circuit assembly 905, which provides the negative input signal (INM).

[0123] Transistor 960 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 960 is connected to switches 974, 976, and transistor 990. The second terminal of transistor 960 is connected to the second output of the mismatch correction circuit assembly 910, which provides the negative input signal (INM). The control terminal of transistor 960 is connected to the control circuit assembly 970 and the fourth input of the mismatch correction circuit assembly 910, which provides the negative input signal (INM).

[0124] Transistor 965 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 965 is connected to switches 980, 984, and transistor 995. The second terminal of transistor 965 is connected to the first output of mismatch correction circuit assembly 910, which provides the positive input signal (INP). The control terminal of transistor 965 is connected to control circuit assembly 970 and the third input of mismatch correction circuit assembly 910, which provides the positive input signal (INP).

[0125] The control circuit assembly 970 has a first terminal, a second terminal, a third terminal, a fourth terminal, a fifth terminal, and a sixth terminal. The first terminal of the control circuit assembly 970 is connected to transistor 960 and switches 974 and 976. The second terminal of the control circuit assembly 970 is connected to transistor 965 and switches 980 and 984. The third terminal of the control circuit assembly 970 is connected to the control terminal of transistor 960 and the fourth input of the mismatch correction circuit assembly 910, which provides the negative input signal (INM). The fourth terminal of the control circuit assembly 970 is connected to the control terminal of transistor 965 and the third input of the mismatch correction circuit assembly 910, which provides the positive input signal (INP).The fifth terminal of the control circuit assembly 970 is connected to the third input and the first output of the mismatch correction circuit assembly 910, which provides the positive input signal (INP). The sixth terminal of the control circuit assembly 970 is connected to the fourth input and the second output of the mismatch correction circuit assembly 910, which provides the negative input signal (INM).

[0126] Switch 974 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 974 is connected to the second input of the mismatch correction circuit assembly 910, which provides the negative common-mode signal (CM_INM). The second terminal of switch 974 is connected to transistors 960 and 990 and switch 976. The control terminal of switch 974 is connected to switch 984 and clock circuit assembly 988.

[0127] Switch 976 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 976 is connected to the first input of the mismatch correction circuit assembly 910, which provides the positive common-mode signal (CM_INP). The second terminal of switch 976 is connected to transistors 960 and 990 and switch 974. The control terminal of switch 976 is connected to switch 980 and clock circuit assembly 988.

[0128] Switch 980 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 980 is connected to the second input of the mismatch correction circuit assembly 910, which provides the negative common-mode signal (CM_INM). The second terminal of switch 980 is connected to transistors 965 and 995 and switch 984. The control terminal of switch 980 is connected to switch 976 and clock circuit assembly 988.

[0129] Switch 984 has a first terminal, a second terminal, and a control terminal. The first terminal of switch 984 is connected to the first input of the mismatch correction circuit assembly 910, which provides the positive common-mode signal (CM_INP). The second terminal of switch 984 is connected to transistors 965 and 995 and switch 980. The control terminal of switch 984 is connected to switch 974 and clock circuit assembly 988.

[0130] The clock circuit assembly 988 has a first terminal and a second terminal. The first terminal of the clock circuit assembly 988 is connected to switches 974 and 984. The second terminal of the clock circuit assembly 988 is connected to switches 976 and 980. In the example of Fig. In example 9, the clock circuit arrangement 988 supplies a first clock signal (PH1) and a second clock signal (PH2) to the switches 974, 976, 980, 984. In such examples, the first clock signal and the second clock signal have different phases and non-overlapping pulses.

[0131] Transistor 990 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 990 is connected to transistor 960 and switches 974 and 976. The second terminal of transistor 990 is connected to the second output of the mismatch correction circuit assembly 910, which provides the negative input signal (INM). The control terminal of transistor 990 is connected to the third input of the mismatch correction circuit assembly 910, which provides the positive input signal (INP).

[0132] Transistor 995 has a first terminal, a second terminal, and a control terminal. The first terminal of transistor 995 is connected to transistor 965 and switches 980 and 984. The second terminal of transistor 995 is connected to the first output of the mismatch correction circuit assembly 910, which provides the positive input signal (INP). The control terminal of transistor 995 is connected to the fourth input of the mismatch correction circuit assembly 910, which provides the negative input signal (INM).

[0133] In the example of Fig. In section 9, transistors 960, 965, 990, and 995 are n-channel MOSFETs. Alternatively, transistors 960, 965, 990, and 995 can be n-channel FETs, n-channel IGBTs, n-channel JFETs, NPN BJTs, or, with minor modifications, equivalent p-type devices. In the example of Fig. In section 9, transistors 915, 920, 954, and 958 are p-channel MOSFETs. Alternatively, transistors 915, 920, 954, and 958 can be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or, with minor modifications, equivalent n-type devices. Transistors 915, 920, 954, 958, 960, 965, 990, and 995 can be depletion-mode devices, drain-expanded devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the transistors 915, 920, 954, 958, 960, 965, 990, 995 can be implemented in / over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).

[0134] Fig. Figure 10 is a flowchart representing exemplary machine-readable instructions or exemplary operations 1000, which are performed using an exemplary implementation of the mismatch correction circuit arrangement 160, 265, 700, 830, 835, 905, 910 of Fig. 7, Fig. 8 and Fig. 9 or more generally the common-mode control circuit arrangement 150, 230, 800 of Fig. 1, Fig. 2, Fig. 3 and Fig. 8 can at least be executed, instantiated, and / or performed. The exemplary operations 1000 begin with the operations of blocks 605, 610, 615, 620, and 625 of Fig. 6 above. In such exemplary operations, the amplifier circuit arrangements 120, 240, 260 are structured to generate positive and negative output signals in response to positive and negative input signals. Control then proceeds to block 1010.

[0135] The mismatch correction circuit arrangements 160, 265, 315, 700, 830, 835, 905, 910 of Fig. 1, Fig. 2, Fig. 3, Fig. 7, Fig. 8 and Fig. 9 isolate the first input voltage from the voltages of the common-mode control circuit arrangement based on the input signal. (Block 1010). In exemplary operations, the control circuit arrangement 710, 930, 970 controls Fig. 7 and Fig. 9 the transistors 470, 920, 965 of Fig. 7 and Fig. 9 with the positive-side input signal. Furthermore, the control circuit arrangement 710, 930, 970 controls the transistors 730, 958, 995 of Fig. 7 and Fig. 9 with the negative-side input signal. In such exemplary operations, transistors 470, 730, 920, 958, 965, 995 couple switches 430, 440, 934, 938, 980, 984 from Fig. 7 and Fig. 9 with the input of the amplifier circuit arrangement 120, 240, 260, which receives the positive-side input signals.

[0136] Advantageously, transistors 470, 730, 920, 958, 965, and 995 detect the common-mode voltage of the positive and negative input signals in response to the positive input signal controlling transistors 470, 920, and 965, and the negative input signal controlling transistors 730, 958, and 995. Advantageously, the common-mode voltage of the positive and negative input signals operates transistors 470, 730, 920, 958, 965, and 995 in a saturation mode. When operating in saturation, transistors 470, 730, 920, 958, 965, 995 set the positive and negative common-mode signals (CM_INP, CM_INM) equal to the common-mode voltage minus the gate-to-source voltage of transistors 470, 730, 920, 958, 965, 995.In such exemplary operations, transistors 470, 730, 920, 958, 965, and 995 isolate the side-input signal from voltage fluctuations on the positive and negative common-mode signals in response to the control circuit arrangement 710, 930, and 970 using the common-mode voltage to operate in saturation mode. Advantageously, transistors 470, 730, 920, 958, 965, and 995 reduce voltage fluctuations on the positive input signal during switching events of switches 430, 440, 934, 938, 980, and 984.

[0137] The mismatch correction circuit arrangements 160, 265, 315, 700, 830, 835, 905, 910 isolate the second input voltage from the voltages of the common-mode control circuit arrangement based on the input signal (block 1020). In exemplary operations, the control circuit arrangement 710, 930, 970 controls the transistors 460, 915, 960 of Fig. 7 and Fig. 9 with the negative-side input signal. Furthermore, the control circuit arrangement 710, 930, 970 controls the transistors 720, 954, 990 of Fig. 7 and Fig. 9 with the positive-side input signal. In such exemplary operations, transistors 460, 720, 915, 954, 960, 990 couple switches 410, 420, 942, 946, 974, 976 from Fig. 7 and Fig. 9 with the input of the amplifier circuit arrangement 120, 240, 260, which receives the negative input signal.

[0138] Advantageously, transistors 460, 720, 915, 954, 960, and 990 detect the common-mode voltage of the positive and negative input signals in response to the negative input signal controlling transistors 460, 915, and 960, and the positive input signal controlling transistors 720, 954, and 990. Advantageously, the common-mode voltage of the positive and negative input signals operates transistors 460, 720, 915, 954, 960, and 990 in a saturation mode. When operating in saturation, transistors 460, 720, 915, 954, 960, 990 set the positive and negative common-mode signals (CM_INP, CM_INM) equal to the common-mode voltage minus the gate-to-source voltage of transistors 460, 720, 915, 954, 960, 990.In such exemplary operations, transistors 460, 720, 915, 954, 960, and 990 isolate the negative input signal from voltage fluctuations at the positive and negative common-mode input signals in response to the control circuit arrangement 710, 930, and 970 using the common-mode voltage to operate in saturation mode. Advantageously, transistors 460, 720, 915, 954, 960, and 990 reduce voltage fluctuations at the negative input signal during switching events of switches 410, 420, 942, 946, 974, and 976. The control circuit then proceeds with the operations of blocks 640, 645, 650, 655, 660, 665, and 670. Fig. 6 above.

[0139] Exemplary procedures are presented with reference to the [document / section / etc.]. Fig. The flowchart illustrated in Figure 10 describes many other methods for implementing the mismatch correction circuit arrangement 160, 265, 700, 830, 835, 905, 910 or, more generally, the common-mode control circuit arrangement 150, 230, 800. Fig. 1, Fig. 2 and Fig. However, 8 can also be used in this description. For example, the order in which the blocks are executed can be changed, or some of the described blocks can be modified, eliminated, or combined. Likewise, additional operations can be included in the manufacturing process before, between, or after the blocks shown in the illustrated examples.

[0140] “Containing” and “comprising” (and all forms and tenses thereof) are used here as open terms. Therefore, whenever a claim uses any form of “containing” or “comprising” (e.g., encompasses, includes, encompassing, inclusive, exhibiting, etc.) as a preamble or within any claim statement, additional elements, expressions, etc., may be present without falling outside the scope of the relevant claim or enumeration. When the term “at least,” as used herein, is employed as a transitional term, for example, within a preamble of a claim, it is open in the same way as the terms “comprising” and “containing” are open.The expression "and / or," when used, for example, in a form such as A, B and / or C, denotes any combination or subset of A, B, C, such as (1) only A, (2) only B, (3) only C, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in the context of describing structures, components, elements, objects, and things, the phrase "at least one of A and B" refers to implementations that contain any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, elements, objects, and things, the phrase "at least one of A or B" refers to implementations that contain any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.As used herein in the context of describing the execution or performance of processes, instructions, actions, activities, etc., the phrase "at least one of A and B" refers to implementations that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or performance of processes, instructions, actions, activities, etc., the phrase "at least one of A or B" refers to implementations that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0141] As used herein, singular references (e.g., "a," "an," "one," "first," "second," etc.) do not preclude a plurality. The expression "a" item, as used herein, denotes one or more of that item. The expressions "a," "one or more," and "at least one" are used interchangeably herein. Furthermore, although listed individually, a plurality of means, elements, or actions may be implemented by, for example, the same entity or item. Also, although individual features may be included in different examples or claims, these may potentially be combined, and inclusion in different examples or claims does not mean that a combination of features is at least not possible and / or advantageous.

[0142] As used here, the term "above," unless otherwise specified, describes the relationship of two parts relative to the Earth. A first part is above a second part if the second part has at least one section between the Earth and the first part. Likewise, as used here, a first part is "below" a second part if the first part is closer to the Earth than the second part. As noted above, a first part may be above or below a second part with one or more of: other parts in between, without other parts in between, with the first and second parts in contact with each other, or without the first and second parts being in direct contact.

[0143] As used in this patent, the indication that any part (e.g., a layer, a film, a region, an area, or a plate) is in any way located on another part (e.g., positioned on, situated on, arranged on, or formed on another part, etc.) indicates that the referenced part is either in contact with the other part or that the referenced part lies over the other part with one or more intervening parts.

[0144] As used herein, references to connections (e.g., attached, coupled, joined, and joined) may, at a minimum, include intermediate elements between the elements referenced by the connection reference and / or relative motion between those elements, unless otherwise specified. As such, references to connections do not necessarily imply that two elements are directly connected or in a fixed relationship to one another. As used herein, the statement that any part is in "contact" with another part is defined to mean that there is no intermediate part between the two parts.

[0145] Unless specifically stated otherwise, descriptors such as "first," "second," "third," etc., are used herein without implying or otherwise indicating any significance of priority, physical order, arrangement in a list, or any other order. They are used merely as designations and / or arbitrary names to distinguish elements for the ease of understanding the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element in a claim is referred to by a different descriptor, such as "second" or "third." In such cases, these descriptors are used solely to uniquely identify those elements within the context of discussion (e.g., within a claim) that might otherwise, for example, share the same name.

[0146] As used herein, "approximately" and "about" modify their subjects / values ​​to account for the potential presence of variations that occur in real-world applications. For example, "approximately" and "circa" can modify dimensions that may not be exact due to at least manufacturing tolerances and / or other real-world imperfections. For example, "approximately" and "about" can indicate that such dimensions may be within a tolerance range of + / - 10%, unless otherwise specified herein.

[0147] As used herein, the phrase “in communication”, including variants thereof, encompasses one of or a combination of direct or indirect communication through one or more intermediaries and does not require direct physical (e.g., wired) communication or constant communication, but rather additionally includes selective communication at least in one of periodic intervals, scheduled intervals, non-periodic intervals, or one-off events.

[0148] As used herein, a “programmable circuit arrangement” is defined as comprising at least one of (i) one or more specialized electrical circuits (e.g., an application-specific integrated circuit (ASIC)) structured to perform one or more specific operations and incorporating one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more semiconductor-based general-purpose electrical circuits programmable with instructions to perform one or more specific functions and / or operations, and incorporating one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of a programmable circuit arrangement include programmable microprocessors such as central processing units (CPUs),that can execute first instructions to perform one or more operations or functions; field-programmable gate arrays (FPGAs) that can be programmed with second instructions to at least configure and / or structure the FPGAs to instantiate one or more operations or functions according to the first instructions; graphics processing units (GPUs) that can execute first instructions to perform one or more operations or functions; digital signal processors (DSPs) that can execute first instructions to perform one or more operations or functions; XPUs; network processing units (NPUs); one or more microcontrollers that can execute first instructions to perform one or more operations or functions; or integrated circuits such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented by a heterogeneous computing system.which includes several types of programmable circuit arrangements (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and one or more arbitrary combinations thereof) and orchestration technology (e.g., one or more application programming interfaces (API(s))) that can assign one or more computational tasks to the one or more of the several types of programmable circuit arrangement best suited to perform the one or more computational tasks.

[0149] As used herein, an integrated circuit / circuit assembly is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more components consisting of an ASIC, an FPGA, a chip, a microchip, a programmable logic assembly, a semiconductor substrate coupling multiple circuit elements, a system-on-a-chip (SoC), etc.

[0150] In this description, the term "couple" can encompass connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct communication; or (b) in a second example, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0151] A device that is "designed" to perform a task or function may be configured (e.g., programmed or hardwired) by a manufacturer at a point in time to perform the function and / or be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the design and / or layout of hardware components and / or intermediate connections of the device, or a combination thereof.

[0152] As used herein, the terms "terminal," "node," "intermediate," "pin," and "conduit" are used interchangeably. Unless expressly stated otherwise, these terms are generally used to denote an intermediate connection between, or a termination of, a device element, circuit element, integrated circuit, appliance, other electronics, or semiconductor component.

[0153] In the description and claims, the described "circuit arrangement" may include one or more circuits. A circuit or device described herein as including certain components may instead be designed to be coupled with these components to form the described circuit arrangement or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as one or a combination of resistors, capacitors, or inductors), or one or more sources (such as voltage and / or current sources) may instead only include the semiconductor elements within a single physical device (e.g., a circuit board).a semiconductor die and / or an IC package) and may be designed to be coupled with at least some of the passive elements or sources to form the described structure either at a time of manufacture or after a time of manufacture, for example by at least one end user and / or a third party.

[0154] The circuits described herein are reconfigurable to include the replaced components in order to provide functionality that is at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise specified, are generally representative of any one or more elements coupled in series and / or parallel to provide an impedance amount represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors coupled in parallel between the same nodes.These can be capacitors coupled in series between the same two nodes as the single resistor or capacitor. Although certain elements of the described examples are contained within an integrated circuit and other elements are external to the integrated circuit, in other embodiments additional or fewer features may be integrated into the integrated circuit. Furthermore, some or all of the features illustrated as external to the integrated circuit may be contained within the integrated circuit, and some features illustrated as internal to the integrated circuit may be implemented outside of the integrated circuit.As used herein, the term “integrated circuit” means one or more circuits that are at least one of the following: (i) embedded in / over a semiconductor substrate; (ii) embedded in a single semiconductor package; (iii) embedded in the same module; or (iv) embedded in / on the same printed circuit board.

[0155] Uses of the term "mass" in the foregoing description include a chassis mass and / or an earth mass and / or a floating mass and / or a virtual mass and / or a digital mass and / or a common mass or any other form of ground connection applicable or suitable for the teachings of this description. Unless otherwise specified, "approximately", "about", or "substantially" means a value of + / - 10 percent of the stated value or, if the value is zero, a reasonable range around zero.

[0156] Modifications are possible in the described embodiments, and other embodiments are possible within the scope of the claims. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 385,848

[0026] US 18 / 642,427

[0109]

Claims

[1] Institution, encompassing: an amplifier circuit arrangement with a first input, a second input and an output; a resistor with a first terminal and a second terminal, wherein the first terminal of the resistor is coupled to the output of the amplifier circuit arrangement; a first switch with a first terminal and a second terminal; a second switch with a first terminal and a second terminal; a third switch with a first terminal and a second terminal, wherein the first terminal of the third switch is coupled to the first terminal of the second switch; a fourth switch with a first terminal and a second terminal, wherein the first terminal of the fourth switch is coupled to the first terminal of the first switch; a first transistor having a first terminal and a second terminal, wherein the first terminal of the first transistor is coupled to the first input of the amplifier circuit arrangement and the second terminal of the resistor, and wherein the second terminal of the first transistor is coupled to the second terminal of the first switch and the second terminal of the fourth switch; and a second transistor with a first terminal and a second terminal, wherein the first terminal of the second transistor is coupled to the second input of the amplifier circuit arrangement, the second terminal of the second transistor is coupled to the second terminal of the second switch and the second terminal of the third switch. [2] Device according to claim 1, wherein the amplifier circuit arrangement is a first amplifier circuit arrangement, the resistor is a first resistor and the device further comprises: a second amplifier circuit arrangement with one output; and a second resistor with a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the output of the second amplifier circuit arrangement, the second terminal of the second resistor is coupled to the second input of the first amplifier circuit arrangement and the first terminal of the second transistor. [3] Device according to claim 1, wherein the amplifier circuit arrangement is a first amplifier circuit arrangement, the resistor is a first resistor, the first transistor further comprises a control terminal, the second transistor further comprises a control terminal and the device further comprises: a second resistor with a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the first input of the first amplifier circuit arrangement and the first terminal of the first transistor; a third resistor with a first terminal and a second terminal, wherein the first terminal of the third resistor is coupled to the second input of the first amplifier circuit arrangement and the first terminal of the second transistor; and a second amplifier circuit arrangement with a first input, a second input and an output, wherein the first input of the second amplifier circuit arrangement is coupled to the second terminal of the second resistor and the second terminal of the third resistor, wherein the second input of the second amplifier circuit arrangement is coupled to the control terminal of the first transistor, the control terminal of the second transistor and the output of the second amplifier circuit arrangement. [4] Device according to claim 1, wherein the first transistor further comprises a control terminal, and the second transistor further comprises a control terminal, the control terminal of the first transistor being coupled to the first input of the amplifier circuit arrangement, the second terminal of the resistor and the first terminal of the first transistor, wherein the control terminal of the second transistor is coupled to the second input of the amplifier circuit arrangement and the first terminal of the second transistor. [5] Device according to claim 4, further comprising: a third transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is coupled to the first input of the amplifier circuit arrangement, the second terminal of the resistor, the first terminal of the first transistor and the control terminal of the first transistor, the second terminal of the third transistor is coupled to the second terminal of the first switch, the second terminal of the fourth switch and the second terminal of the first transistor, wherein the control terminal of the third transistor is coupled to the second input of the amplifier circuit arrangement; and a fourth transistor with a first terminal, a second terminal and a control terminal, wherein the first terminal of the fourth transistor is coupled to the second input of the amplifier circuit arrangement, the first terminal of the second transistor and the control terminal of the second transistor, the second terminal of the fourth transistor is coupled to the second terminal of the second switch, the second terminal of the third switch and the second terminal of the second transistor, wherein the control terminal of the fourth transistor is coupled to the first input of the amplifier circuit arrangement. [6] Device according to claim 1, further comprising a current control circuit arrangement with a first input, a second input and a control terminal, wherein the first input of the current control circuit arrangement is coupled to the first terminal of the first switch and the first terminal of the fourth switch, wherein the second input of the current control circuit arrangement is coupled to the first terminal of the second switch and the first terminal of the third switch, and the control terminal of the current control circuit arrangement is coupled to the output of the amplifier circuit arrangement. [7] Device according to claim 6, wherein the first switch, the second switch, the third switch, the fourth switch, the first transistor and the second transistor are a first mismatch correction circuit arrangement, the current control circuit arrangement is a current sink circuit arrangement and the device further comprises: a second mismatch correction circuit arrangement with a first terminal, a second terminal, a third terminal and a fourth terminal; and a current source circuit arrangement with a first output, a second output and a control terminal, wherein the first output of the current source circuit arrangement is coupled to the first input of the amplifier circuit arrangement, the second terminal of the resistor, the first terminal of the first transistor and the first terminal of the second mismatch correction circuit arrangement, wherein the second output of the current source circuit arrangement is coupled to the second input of the amplifier circuit arrangement, the first terminal of the second transistor and the second terminal of the second mismatch correction circuit arrangement. [8] Institution, comprehensive: an amplifier circuit arrangement with a first input and a second input; a first switch with one terminal and a second terminal; a second switch with a first terminal and a second terminal, wherein the first terminal of the second switch is coupled to the first terminal of the first switch; a third switch with a first terminal and a second terminal; a fourth switch with a first terminal and a second terminal, wherein the first terminal of the fourth switch is coupled to the first terminal of the third switch; a first transistor with a first terminal, a second terminal and a control terminal, wherein the first terminal of the first transistor is coupled to the second terminal of the first switch and the first terminal of the third switch; a second transistor with a first terminal, a second terminal and a control terminal, wherein the first terminal of the second transistor is coupled to the second terminal of the second switch and the second terminal of the fourth switch; and a control circuit arrangement with a first terminal, a second terminal and a third terminal, wherein the first terminal of the control circuit arrangement is coupled to the first input of the amplifier circuit arrangement and the second terminal of the first transistor, wherein the second terminal of the control circuit arrangement is coupled to the second input of the amplifier circuit arrangement and the second terminal of the second transistor, and wherein the third terminal of the control circuit arrangement is coupled to the control terminal of the first transistor and the control terminal of the second transistor. [9] Device according to claim 8, wherein the control circuit arrangement comprises: a buffer circuit arrangement with one input and one output, wherein the output of the buffer circuit arrangement is coupled to the control terminal of the first transistor and the control terminal of the second transistor; a first resistor with a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the first input of the amplifier circuit arrangement and the second terminal of the first transistor; and a second resistor with a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the second input of the amplifier circuit arrangement and the second terminal of the second transistor, and the second terminal of the second resistor is coupled to the input of the buffer circuit arrangement and the second terminal of the first resistor. [10] Device according to claim 8, wherein the amplifier circuit arrangement is a first amplifier circuit arrangement and the device further comprises a second amplifier circuit arrangement with a first input, a second input, a first output and a second output, wherein the first input of the second amplifier circuit arrangement is coupled to the first input of the first amplifier circuit arrangement and the second terminal of the first transistor, the second input of the second amplifier circuit arrangement is coupled to the second input of the first amplifier circuit arrangement and the second terminal of the second transistor, the first output of the second amplifier circuit arrangement is coupled to the first terminal of the first switch and the first terminal of the second switch,The second output of the second amplifier circuit arrangement is coupled to the first terminal of the third switch and the first terminal of the fourth switch. [11] Device according to claim 8, wherein the amplifier circuit arrangement further comprises a first output and a second output and the device further comprises: a first resistor with a first terminal and a second terminal, wherein the first terminal of the first resistor is coupled to the first output of the amplifier circuit arrangement; a second resistor with a first terminal and a second terminal, wherein the first terminal of the second resistor is coupled to the second output of the amplifier circuit arrangement; a third transistor with a first terminal and a control terminal; and a fourth transistor with a first terminal and a control terminal, wherein the first terminal of the fourth transistor is coupled to the first terminal of the first switch and the first terminal of the second switch, wherein the control terminal of the fourth transistor is coupled to the second terminal of the first resistor, the second terminal of the second resistor, the first terminal of the third transistor and the control terminal of the third transistor. [12] Device according to claim 8, wherein the control terminal of the first transistor is coupled to the first input of the amplifier circuit arrangement and the second terminal of the first transistor, and wherein the control terminal of the second transistor is coupled to the second input of the amplifier circuit arrangement and the second terminal of the second transistor. [13] Device according to claim 8, wherein the control circuit arrangement comprises: a third transistor having a first terminal, a second terminal and a control terminal, wherein the first terminal of the third transistor is coupled to the first input of the amplifier circuit arrangement, the second terminal of the first transistor and the control terminal of the first transistor, the second terminal of the third transistor is coupled to the second terminal of the first switch, the second terminal of the third switch and the second terminal of the first transistor, and the control terminal of the third transistor is coupled to the second input of the amplifier circuit arrangement; and a fourth transistor with a first terminal, a second terminal and a control terminal, wherein the first terminal of the fourth transistor is coupled to the second input of the amplifier circuit arrangement, the second terminal of the second transistor and the control terminal of the second transistor, the second terminal of the fourth transistor is coupled to the second terminal of the second switch, the second terminal of the fourth switch and the second terminal of the second transistor, wherein the control terminal of the fourth transistor is coupled to the first input of the amplifier circuit arrangement. [14] Device according to claim 8, wherein the amplifier circuit arrangement further comprises an output and the device further comprises a current sink circuit arrangement with a first input, a second input and a control terminal, wherein the first input of the current sink circuit arrangement is coupled to the first terminal of the first switch and the first terminal of the second switch, wherein the second input of the current sink circuit arrangement is coupled to the first terminal of the third switch and the first terminal of the fourth switch, and the control terminal of the current sink circuit arrangement is coupled to the output of the amplifier circuit arrangement. [15] Device according to claim 14, wherein the first switch, the second switch, the third switch, the fourth switch, the first transistor and the second transistor are a first mismatch correction circuit arrangement and the device further comprises: a second mismatch correction circuit arrangement with a first terminal, a second terminal, a third terminal and a fourth terminal; and a current source circuit arrangement with a first output, a second output and a control terminal, wherein the first output of the current source circuit arrangement is coupled to the first input of the amplifier circuit arrangement, the second terminal of the first transistor and the first terminal of the second mismatch correction circuit arrangement, wherein the second output of the current source circuit arrangement is coupled to the second input of the amplifier circuit arrangement, the second terminal of the second transistor and the second terminal of the second mismatch correction circuit arrangement. [16] Institution, comprehensive: an amplifier circuit arrangement with a first input, a second input and an output; a common-mode control circuit arrangement with a connection coupled to the output of the amplifier circuit arrangement, wherein the common-mode control circuit arrangement is designed: to generate a first current and a second current in response to a difference between a first input voltage at the first input of the amplifier circuit arrangement and an output voltage at the output of the amplifier circuit arrangement; to regulate a common-mode voltage of the first input voltage and a second input voltage at the second input of the amplifier circuit arrangement in response to the generation of the first current and the second current; to compensate for a mismatch between the first and second input voltages; and to compensate for the first current and the second current for a difference between the first input voltage and the second input voltage. [17] Device according to claim 16, wherein the common-mode control circuit arrangement is further designed: to act as a sink for the first current from the first input voltage for a first section of a clock cycle; to act as a sink for the second current from the second input voltage for the first part of the clock cycle; to act as a sink for the first current from the second input voltage for a second section of the clock cycle; and to act as a sink for the second current from the first input voltage for the second part of the clock cycle. [18] Device according to claim 16, wherein the common-mode control circuit arrangement is further designed: to determine the common-mode voltage between the first input voltage and the second input voltage; and to control the compensation of the first current and the second current for the difference between the first input voltage and the second input voltage based on the common-mode voltage. [19] Device according to claim 16, wherein the common-mode control circuit arrangement is a current sink circuit arrangement and the device further comprises: a current source circuit arrangement coupled to the amplifier circuit arrangement, wherein the current source circuit arrangement is designed to generate a third current and a fourth current in response to the difference between the output voltage and the first input voltage; and a mismatch circuit arrangement coupled to the amplifier circuit arrangement and the current source circuit arrangement, wherein the mismatch circuit arrangement is designed: to compensate for a mismatch between the third and fourth currents by adjusting the first and second input voltages; and to compensate for the difference between the first input voltage and the second input voltage by using the third current and the fourth current. [20] Device according to claim 19, further comprising: the current sink circuit arrangement is further designed to derive the first current and the second current from the first input voltage and the second input voltage in response to the output voltage being greater than the first input voltage; and The current source circuit arrangement is further designed to supply the third current and the fourth current to the first input voltage and the second input voltage in response to the output voltage being less than the first input voltage.

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