Semiconductor device and method for manufacturing a semiconductor device

Abstract

A semiconductor device according to the present disclosure comprises a first trench electrode and a second trench electrode, wherein the first trench electrode has a two-stage structure comprising a lower electrode provided on a lower side that is a side of a second main electrode, an upper electrode provided on an upper side that is a side of a first main electrode, a first trench insulating layer covering an inner surface of the trench, and a subdivision insulating layer provided between the lower electrode and the upper electrode, wherein the upper electrode has a depression in a portion corresponding to an upper surface of the lower electrode, and a side wall of the depression serves as a pointed portion projecting towards a bottom portion of the trench, wherein the subdivision insulating layer is provided such thatthat it covers the interior of the depression and the pointed part.

Description

Background of the invention; Field of the invention

[0001] The present disclosure relates to a semiconductor device, and in particular to a semiconductor device comprising a trench electrode having a two-stage structure. Description of the state of the art

[0002] In recent years, as in Fig. Section 4 of Japanese patent application disclosure no. 2024-1723 discloses a semiconductor device comprising a two-stage trench electrode with an upper trench electrode on an upper side and a lower trench electrode on a lower side in a thickness direction of a semiconductor substrate and a single-stage trench electrode.

[0003] In Japanese patent application disclosure no. 2024-1723, a source potential, rather than a gate potential, is applied to the lower electrode of the two-stage trench electrode, and the lower electrode functions as a field plate electrode. Furthermore, the source potential is applied to the trench electrode of the single-stage trench electrode.

[0004] In the semiconductor device described above, the trench electrodes of all lower electrodes and the single-stage trench electrode are connected to the source potential, and therefore a problem exists in that a collector-gate capacitance (Cgc) decreases, a ratio (Cgc / Cge) of Cgc to emitter-gate capacitance (Cge) decreases, and a turn-on loss increases in a case where a gate resistance of a semiconductor element is increased and a recovery dv / dt at the time of turn-on is set to a predefined value. Summary

[0005] The present disclosure relates to a semiconductor device, and it is an object of the present disclosure to provide a semiconductor device which has a trench electrode with a two-stage structure and is able to prevent an increase in turn-on loss and improve reliability.

[0006] A semiconductor device according to the present disclosure comprises: a semiconductor substrate having at least a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type on the first semiconductor layer, and a third semiconductor layer of the first conductivity type provided in an upper part of the second semiconductor layer; a first trench electrode and a second trench electrode provided within a trench which penetrates the third semiconductor layer and the second semiconductor layer of the semiconductor substrate in a thickness direction and reaches an interior of the first semiconductor layer; an intermediate insulating layer covering the first trench electrode and the second trench electrode; a first main electrode in contact with the third semiconductor layer; and a second main electrode.which is provided on one side opposite the first main electrode in the thickness direction of the semiconductor substrate, wherein the first trench electrode has a two-stage structure comprising a lower electrode, which is provided on a lower side that is one side of the second main electrode, an upper electrode, which is provided on an upper side that is one side of the first main electrode, a first trench insulating layer covering an inner surface of the trench, and a subdivision insulating layer, which is provided between the lower electrode and the upper electrode, wherein in the upper electrode a portion corresponding to an upper surface of the lower electrode is a depression, and a side wall of the depression is a pointed portion projecting towards a bottom portion of the trench, wherein the subdivision insulating layer is provided such thatthat it covers an interior of the depression and the pointed part, wherein the second electrode has a second trench insulating layer covering an inner surface of the trench, and a trench electrode by means of which the trench covered by the second trench insulating layer is filled, and a sighting element embedded in an upper region of the second trench insulating layer, wherein the upper electrode is connected to a potential of the first main electrode, and wherein the lower electrode and the trench electrode are connected to a gate potential.

[0007] According to the semiconductor device of the present disclosure, it is possible in the semiconductor device, which has a trench electrode with a two-stage structure, to achieve a semiconductor device which is able to prevent an increase in turn-on loss and improve reliability.

[0008] These and other tasks, features, aspects and advantages of the present revelation will become clearer based on the following detailed description of the present revelation in conjunction with the accompanying figures. Brief description of the characters Fig. Figure 1 is a top view which schematically illustrates a configuration of an upper surface of a semiconductor device of a first preferred embodiment according to the present disclosure; Fig. 2 is a top view of a subregion within an active region; Fig. Figure 3 is a cross-sectional view of the subregion within the active region; Fig. Figure 4 is a view illustrating the thickness of a respective part in a two-stage trench electrode and a single-stage trench electrode; Fig. Figures 5 to 18 are cross-sectional views illustrating a manufacturing process of the semiconductor device according to the first preferred embodiments of the present disclosure; Fig. Figure 19 is a cross-sectional view illustrating a configuration of a semiconductor device according to a first modification of the first preferred embodiments according to the present disclosure; Fig. Figure 20 is a top view illustrating a configuration of a semiconductor device according to a second preferred embodiment of the present disclosure; Fig. Figures 21 to 23 are cross-sectional views in an arrow direction of a subregion in an active region; Fig. Figure 24 is a cross-sectional view illustrating a configuration of a semiconductor device of a third embodiment according to the present disclosure; Fig. Figure 25 is a cross-sectional view illustrating a configuration of a semiconductor device of a fourth preferred embodiment according to the present disclosure; Fig. 26 is a top view which schematically illustrates a configuration of an upper surface of a semiconductor device of a fifth preferred embodiment according to the present disclosure; Fig. 27 is a top view of a subregion within an active region; and Fig. Figure 28 is a cross-sectional view of the subregion within the active region. Description of preferred embodiments<Einführung>

[0009] Preferred embodiments according to the present disclosure are described below with reference to the figures. It should be noted that the figures provide schematic illustrations, and the reciprocal relationship of sizes and positions of images illustrated in different figures is not necessarily described precisely and may have been modified appropriately. Furthermore, in the following description, similar components are identified by identical reference numerals, and their names and functions are also similar. Therefore, their detailed description may be omitted.

[0010] Even if the following description uses terms that specify concrete positions or directions, such as "top," "bottom," "side," "bottom," "front," or "back," these terms are used for the sake of simplicity to facilitate understanding of the content of the preferred embodiments and do not refer to the directions when the preferred embodiments are actually implemented. Furthermore, in the following description, "outside" is a direction toward an outer periphery of the semiconductor device, and "inside" is a direction opposite to "outside."

[0011] In the following description, an n-type is generally defined as a “first conductivity type” and a p-type is generally defined as a “second conductivity type” in relation to the conductivity types of defects, but the reverse definition can be used.

[0012] Furthermore, an n denotes - Type, that one impurity concentration is lower than that of the n-type, and an n + Type 1 indicates that a defect concentration is higher than that of type n. Similarly, p indicates that - Type, that an impurity concentration is lower than that of the p-type, and a p + indicates that the impurity concentration is higher than that of the p-type. <Erste bevorzugte Ausführungsform> <vorrichtungskonfiguration>

[0013] Fig. Figure 1 is a top view which schematically illustrates a configuration of an upper surface of an entire insulated-gate bipolar transistor (IGBT) 100 of a first preferred embodiment according to the present disclosure. The Fig. The illustrated IGBT 100 has a rectangular outer shape, and a large portion of this outer shape is an active region AR in which a plurality of the smallest unit structures of the IGBT (IGBT cells), called "unit cells," are arranged and carry a main current. The outer portion of the active region AR is a termination region 5. Within the active region AR, a plurality of trench electrodes (not illustrated) are arranged in parallel at intervals. It should be noted that the plurality of trench electrodes is connected to a gate wiring 3 provided within the active region AR, and the gate wiring 3 is connected to a gate pad 2. A singulation line 4 is provided outside the termination region 5. It should be noted that the shapes and arrangement of the gate wiring 3 and the gate pad 2 do not correspond to those shown in Figure 1. Fig. are limited to 1.

[0014] Fig. Figure 2 illustrates a top view of a subregion 50, which is represented by a dashed line in the active region AR of Fig. 1 is surrounded. Fig. Figure 2 is a partial top view in which an upper structure such as an emitter electrode in the active region AR is omitted.

[0015] As in Fig. As illustrated in Figure 2, in the active region AR, a two-stage trench electrode 30 (first trench electrode), which has a strip shape, and a single-stage trench electrode 40 (second trench electrode) are provided such that their longitudinal directions are parallel to each other. The two-stage trench electrode 30 and the single-stage trench electrode 40 are positioned such that they extend in a direction (left-right direction on the paper) that intersects an extension direction of the gate wiring 3, which is provided in a central part of the active region AR. It should be noted that the extension direction of the two-stage trench electrode 30 and the single-stage trench electrode 40 is not limited to this, and a vertical direction on the paper could be the extension direction.

[0016] Fig. 3 is a cross-sectional view in an arrow direction, which runs along a line AA in Fig. 2 is taken from. As in Fig. As illustrated in section 3, the IGBT 100 has an n - Type Drift layer 9 (first semiconductor layer), which contains a semiconductor substrate. The n - Type Drift layer 9 is a semiconductor layer which, for example, contains arsenic or phosphorus as an n-type defect, and a concentration of the n-type defect corresponds to 1.0 × 10 12 / cm 3 up to 1.0 × 10 15 / cm 3 . In Fig. 3 the semiconductor substrate lies within an area of ​​n + Type source layer 6 up to a p-type collector layer 12. In Fig. 3 will be an upper end of the n + The source layer 6 on the paper is designated as a first principal surface of the semiconductor substrate, and the lower end of the p-type collector layer 12 on the paper is designated as a second principal surface of the semiconductor substrate. The first principal surface of the semiconductor substrate is a principal surface on one side of a front face of the IGBT 100, and the second principal surface of the semiconductor substrate is a principal surface on one side of a back face of the IGBT 100.

[0017] As in Fig. As illustrated in point 3, this is an n + Type 8 charge carrier accumulation layer with a higher concentration of an n-type defect than that of the n - Type Drift layer 9 on the side of the first main surface of the n - Drift layer type 9 provided. The n + Type 8 charge carrier accumulation layer is a semiconductor layer which, for example, contains arsenic or phosphorus as the n-type defect, and a concentration of the n-type defect corresponds to 1.0 × 10 13 / cm 3 up to 1.0 × 10 17 / cm 3 By providing the n + Type 8 charge carrier accumulation layer can reduce current loss when a current flows through the IGBT 100, but the n + Type 8 charge carrier accumulation layer does not need to be provided. The n + Type charge carrier accumulation layer 8 and the n - Type Drift Layer 9 can be collectively referred to as one Drift Layer.

[0018] A p-type base layer 7 (second semiconductor layer) is located on the side of the first main surface of the n + Type charge carrier accumulation layer 8 is provided. The p-type base layer 7 is a semiconductor layer which, for example, contains boron or aluminum as a p-type defect, and a concentration of the p-type defect corresponds to 1.0 × 10 12 / cm 3 up to 1.0 × 10 19 / cm 3 The p-type base layer 7 is in contact with a trench insulation layer 10 (first trench insulation layer) of the two-stage trench electrode 30 and a trench insulation layer 18 (second trench insulation layer) of the single-stage trench electrode 40.

[0019] On the side of the first main surface of the p-type base layer 7 there is an n + Type Source layer 6 (third semiconductor layer) is provided in contact with the trench insulating layers 10 and 18. The n + Type Source layer 6 forms the first main surface of the semiconductor substrate. The n + Type Source layer 6 is a semiconductor layer which, for example, contains arsenic or phosphorus as the n-type defect, and a concentration of the n-type defect corresponds to 1.0 × 10 17 / cm 3 up to 1.0 × 10 20 / cm 3 .

[0020] A + Buffer layer type 11 with a higher concentration of the n-type defect than that of the n - Type Drift Layer 9 is on the side of the second main surface of the n - Drift layer type 9 provided. The n + Type buffer layer 11 is provided to prevent a breakthrough of a depletion layer extending from the p-type base layer 7 to the side of the second main surface when the IGBT 100 is in an off state. The n + Buffer layer type 11 can be formed, for example, by injecting phosphorus (P) or protons (H). + ) or it can be formed by injecting both phosphorus (P) and protons (H). + The concentration of the n-type defect in the n-type buffer layer 11 corresponds to 1.0 × 10 12 / cm 3 up to 1.0 × 10 18 / cm 3 .

[0021] A p + Type collector layer 12 is provided on the side of the second main surface of the n-type buffer layer 11. In other words, the p + Type collector layer 12 between the n - Type Drift layer 9 and the second main surface are provided. The p + Type collector layer 12 is a semiconductor layer which, for example, contains boron or aluminum as the p-type defect, and a concentration of the p-type defect corresponds to 1.0 × 10 16 / cm 3 up to 1.0 × 10 20 / cm 3 .

[0022] The two-stage trench electrode 30 is provided in a trench which is designed such that the p-type base layer 7 is penetrated by the first main surface of the semiconductor substrate and the n - Type Drift layer 9 is achieved. In other words, the two-stage trench electrode 30 contains the trench insulating layer 10 on a bottom part and a side wall of the trench, that is, on an inner surface. A lower electrode 19 is provided below the trench, which is surrounded by the trench insulating layer 10, and an upper electrode 14 is provided above the lower electrode 19. The lower electrode 19 and the upper electrode 14 are insulated by a subdivision insulating layer 20, and the upper electrode 14 is connected to an emitter potential, and the lower electrode 19 is connected to a gate potential.

[0023] In the upper electrode 14, a portion corresponding to the upper side of the lower electrode 19 is a depression, and a side wall of the depression is a pointed portion 15 that projects towards the bottom of the trench. The subdividing insulating layer 20 is provided such that it covers the interior of the depression and the pointed portion 15.

[0024] The single-stage trench electrode 40 is provided in a trench which is designed such that it penetrates the p-type base layer 7 from the first main surface of the semiconductor substrate and the n - Type Drift layer 9 is achieved. In other words, the single-stage trench electrode 40 contains a trench insulation layer 18 on the bottom part and the side wall of the trench, that is, on an inner surface, and contains a trench electrode 17 which extends from the bottom part of the trench to the first main surface, and a sighting element 16, which is formed from a conductor, is embedded in an upper region of the trench insulation layer 18 of the side wall.

[0025] The trench insulation layer 18 of the single-stage trench electrode 40 is in contact with the p-type base layer 7 and the n + Source layer 6. If a gate control voltage is applied to the trench electrode 17, a channel is formed in the p-type base layer 7, which is in contact with the trench insulating layer 18.

[0026] Here, the trench insulating layers 10 and 18 and the subdivision insulating layer 20 are formed, for example, from a silicon oxide layer. The upper electrode 14, the lower electrode 19, the trench electrode 17, and the sight element 16 are formed, for example, from any polysilicon, amorphous silicon, and metal. Furthermore, the trench refers to an opening provided in the semiconductor substrate, but it also refers to a structure formed within the opening.

[0027] As in Fig. As illustrated in Figure 3, an intermediate insulating layer IS is provided on the two-stage trench electrode 30 and the single-stage trench electrode 40, and an emitter electrode 1 (first main electrode) is provided on the first main face of the semiconductor substrate comprising the intermediate insulating layer IS. A collector electrode 13 (second main electrode) is provided on the second main face of the semiconductor substrate opposite the side on which the emitter electrode 1 is provided in a thickness direction.

[0028] The emitter electrode 1 can, for example, be formed using an aluminum alloy such as an aluminum silicon alloy (Al-Si-based alloy), or it can be an electrode containing a multitude of layers of metal layers, in which a plating layer is formed on an electrode which is formed using an aluminum alloy by electroless plating or electrolytic plating.

[0029] Similar to the emitter electrode 1, the collector electrode 13 can be formed using an aluminum alloy or an aluminum alloy and a cladding layer. The collector electrode 13 can have a configuration that differs from that of the emitter electrode 1. The collector electrode 13 is in ohmic contact with the p-type collector layer 12 and is electrically connected to the p-type collector layer 12.

[0030] Fig. Figure 4 is a view illustrating a length in a horizontal direction, that is, a thickness of a respective part in the two-stage trench electrode 30 and the single-stage trench electrode 40. Fig. In section 4, the thickness of the trench insulation layer 10 between the trench sidewall of the two-stage trench electrode 30 and the pointed part 15 is specified at X1, the thickness of the pointed part 15 is specified at X2, and the thickness of the subdivision insulation layer 20 between the pointed part 15 and the lower electrode 19 is specified at X3. Furthermore, the thickness of the trench insulation layer 18 between the trench sidewall of the single-stage trench electrode 40 and the sighting element 16 is specified at X11, the thickness of the sighting element 16 is specified at X12, and the thickness of the trench insulation layer 18 between the sighting element 16 and the trench electrode 17 is specified at X13. A ratio between the thicknesses is given by X1 = X11, X2 = X12, and X3 = X13.

[0031] By handling the thicknesses X1, X2, and X3 of the two-stage trench electrode 30 using the above ratio, the pointed part 15, which has excellent resistance, can be formed, and the reliability of a gate of the IGBT 100 can be improved.

[0032] In other words, when the IGBT 100 is switched off, a negative bias voltage is applied between the gate and the emitter. In this case, holes concentrate near the emitter electrode 1. An electric field due to the negative bias and the holes is present at the emitter electrode 1, and in particular, if the distance between the pointed part 15 formed in the upper electrode 14 and the lower electrode 19 is reduced (i.e., the thickness X3), the electric field concentrates at the pointed part 15. As described above, the electric field intensity concentrated at the pointed part 15 depends on the thickness X3 of the partition insulating layer 20 between the pointed part 15 and the lower electrode 19, thus making it possible to improve the reliability of the IGBT 100 by managing a variation caused by the manufacturing process.

[0033] As described in the manufacturing process described later, the thickness X12 of the visible element 16, which is embedded in the trench insulation layer 18 near the first main surface, can be optically detected by means of a top surface of a wafer during the manufacturing process, and therefore the thickness X3 of the subdivision insulation layer 20 between the pointed part 15 and the lower electrode 19 can be managed by means of the ratio of X2 = X12, and the reliability of the IGBT 100 can be improved.

[0034] In the IGBT 100, the upper electrode 14 is connected to the emitter potential and the lower electrode 19 is connected to the gate potential, thus increasing the ratio of Cgc / Cge and reducing the turn-on loss.

[0035] Furthermore, if the upper electrode 14 is connected to the emitter potential and the lower electrode 19 is connected to the gate potential, the electric field near the pointed part 15 of the upper electrode 14, close to a mesa portion, becomes high during switch-off. However, by adjusting the thickness X12 of the sight element 16, which is embedded in the single-stage trench electrode 40, and the thickness X2 of the subdivision insulating layer 20 between the pointed part 15 and the lower electrode 19, the resistance to damage of the pointed part 15 is improved, and the reliability of the IGBT 100 can be enhanced. <herstellungsverfahren>

[0036] Next, a process for manufacturing the IGBT 100 will be described in relation to the Fig. Sections 5 to 18 describe the manufacturing processes in succession. It should be noted that only one method for manufacturing the two-stage trench electrode 30 and the single-stage trench electrode 40 is described below, and a well-known method for manufacturing each part, different from the two-stage trench electrode 30 and the single-stage trench electrode 40, could be used; therefore, its description has been omitted.

[0037] First, an n-type semiconductor substrate 300 is prepared, and in the process that goes into Fig. As specified in 5, a trench TR is formed in a region of the semiconductor substrate 300 in which the two-stage trench electrode 30 and the single-stage trench electrode 40 are to be formed, which reaches a predefined depth starting from a first main surface 301 of the semiconductor substrate 300 and extends in the depth direction on the paper.

[0038] Next, in the Fig. In the process described in section 6, an insulating layer 303 (first insulating layer) is formed in a region (first region) in which the two-stage trench electrode 30 is to be formed, such that an inner surface of the trench TR is covered, and an insulating layer 304 (second insulating layer) is formed in a region (second region) in which the single-stage trench electrode 40 is to be formed.

[0039] Next, in the Fig. In the process described in Figure 7, a conductor CD is embedded in the trench TR above the insulating layers 303 and 304. The lower electrode 319 is formed in a region where the two-stage trench electrode 30 is to be formed, and a trench electrode 317 is formed in a region where the single-stage trench electrode 40 is to be formed. For example, polysilicon, amorphous silicon, or a metal can be used as the conductor CD.

[0040] Next, as in Fig. 8, the conductor CD, which is formed above the insulating layers 303 and 304 on the first main surface 301, is removed, for example by etching, to expose the upper surfaces of the insulating layers 303 and 304.

[0041] Next, in the Fig. In process 9, a photoresist is applied to the side of the first main surface 301, and structuring is carried out by photolithography or the like to form a resist mask 350.

[0042] Next, in the Fig. 10. The process described above uses the resist mask 350 as the etching mask. The lower electrode 319 is returned to the trench TR, and etching is carried out such that the trench electrode 317 remains.

[0043] Next, as in the one in Fig. The process specified in section 11 removes the resist mask 350, and subsequently, the following occurs in the Fig. 12. In the process described, the insulating layers 303 and 304 were removed by etching, so that the positions of the upper ends of the insulating layers 303 and 304 are lower than the positions of the upper ends of the lower electrode 319 in the trench electrode 317.

[0044] Next, in the Fig. In the process described in Figure 13, an insulating layer 320 (third insulating layer) is formed on the trench sidewall and an upper part of the lower electrode 319 in a region where the two-stage trench electrode 30 is to be formed, and an insulating layer 330 (fourth insulating layer) is formed on the sidewall and an upper part of the trench electrode 317 in a region where the single-stage trench electrode 40 is to be formed. The insulating layers 320 and 330 to be formed exhibit different formation rates per unit time on the trench sidewall, the electrodes, and the withdrawn insulating layers 303 and 304.

[0045] In other words, the withdrawn insulating layers 303 and 304, which are indicated by arrows in Fig. 13 are characterized, the insulating layers 320 and 330 are barely formed, and the insulating layers 320 and 330 are formed on the trench side wall, the upper end of the lower electrode 319, and the upper end of the trench electrode 317, so that a gap GP for embedding the pointed part 315 and the sighting element 316 as in Fig. 14 is specified as being trained.

[0046] Next, in the Fig. 15 specified process of the conductor CD embedded in the trench TR in a state in which the insulating layers 320 and 330 are formed, the upper electrode 314 comprising the pointed part 315 is formed in the region in which the two-stage trench electrode 30 is to be formed, and the sighting element 316 is embedded in the region in which the single-stage trench electrode 40 is to be formed.

[0047] Next, in the Fig. 16. The process of forming the conductor CD above the first main surface 301 is described, and the insulating layers 320 and 330 are reduced to a height of the first main surface 301.

[0048] Next, in the Fig. In the process described in section 17, the single-stage trench electrode 40 is observed from the side of the first main surface 301, a positional relationship between the trench electrode 317, the sighting element 316, and the insulating layer 304 is recorded, and a width and shape of the pointed part 315, which is formed under the upper electrode 314 of the two-stage trench electrode 30, is estimated and handled.

[0049] In a case where the estimated width and shape of the pointed part 315 lie within a design range, an insulating layer 340 is formed on the two-stage trench electrode 30 and the single-stage trench electrode 40 to form an intermediate insulating layer in the Fig. The two-stage trench electrode 30 and the single-stage trench electrode 40 can be obtained by the above processes, and the width and shape of the pointed part 315 of the two-stage trench electrode 30 can be handled using the sighting element 316 of the single-stage trench electrode 40. <Erste Modifikation>

[0050] Fig. Figure 19 is a cross-sectional view illustrating a configuration of an IGBT 101 according to a first modification of the first preferred embodiment, and it is a view corresponding to a cross-sectional view in an arrow direction taken along line AA of subregion 50, which is defined by the dashed line in the active region AR in Fig. 1 is taken from.

[0051] In the IGBT 100 of the first preferred embodiment, which is in Fig. As illustrated in Figure 3, the two-stage trench electrode 30 and the single-stage trench electrode 40 are deployed in the active region AR, but the one in Fig. Figure 19 illustrates IGBT 101, which includes the two-stage electrode 70 in addition to the two-stage trench electrode 30 and the single-stage trench electrode 40.

[0052] The structure of the two-stage trench electrode 70 is essentially identical to that of the two-stage trench electrode 30, with the lower electrode 19 positioned below the trench, which is surrounded by the trench insulating layer 10, and the upper electrode 24 positioned above the lower electrode 19. The lower electrode 19 and the upper electrode 24 are insulated from each other by the subdivision insulating layer 20, and the two-stage trench electrode 70 differs from the two-stage trench electrode 30 only in that the upper electrode 24 is connected to the gate potential.

[0053] In the upper electrode 24, a portion corresponding to the upper side of the lower electrode 19 is a depression, and a side wall of the depression is a pointed portion 25 that projects towards the bottom of the trench. The dividing insulating layer 20 is provided such that it covers the interior of the depression and the pointed portion 25.

[0054] It should be noted that Fig. Figure 19 illustrates an example in which the same number of two-stage trench electrodes 30, the same number of single-stage trench electrodes 40, and the same number of two-stage trench electrodes 70 are provided, but the number is not limited to the same number, and any one of them can be increased, and any one of them can be decreased, like the total number in the active region AR.

[0055] By providing the two-stage trench electrode 70, in which the upper electrode 24 is connected to the gate potential, as in the two-stage trench electrode 30, the number of lower electrodes 19 connected to the emitter potential can be adjusted, and the Cgc / Cge ratio can be adjusted to a desired value. In other words, Cge decreases as the number of electrodes connected to the emitter potential increases, and thus Cge can be adjusted by changing the number of electrodes connected to the emitter potential, and the Cgc / Cge ratio can be adjusted.

[0056] Here, the two-stage trench electrode 30 and the two-stage trench electrode 70 are used to adjust the ratio of Cgc / Cge, and therefore they can each be referred to as a first matching trench electrode and a second matching trench electrode. <Zweite Modifikation>

[0057] In the IGBT 100 of the first preferred embodiment, which is in Fig. As illustrated in Figure 3, the potential of the sight element 16, which is embedded in the upper region of the trench insulation layer 18 of the single-stage trench electrode 40, is not restricted, but the sight element 16 can be connected to either the gate potential or the emitter potential, and it can be a floating potential. This is because the sight element 16 does not function as an electrode and is only used to control the width and shape of the pointed part 15 of the two-stage trench electrode 30. By not restricting the potential of the sight element 16, a degree of freedom in the design is increased. <Zweite bevorzugte Ausführungsform>

[0058] Fig. Figure 20 is a view illustrating a semiconductor device of a second preferred embodiment, and it illustrates a top view of a subregion 60, which is defined by a dashed line in the active region AR of Fig. 1 is surrounded. Fig. Figure 20 is a partial top view in which an upper structure such as an emitter electrode near the gate wiring 3 is omitted, and it is a top view of a wiring connection region.

[0059] The wiring connection region is a region which connects the lower electrode 19 of the two-stage trench electrode 30 to the gate potential, and the lower electrode 19 is exposed at an end part of the two-stage trench electrode 30.

[0060] Fig. 21 is a cross-sectional view, which is drawn along a line BB in Fig. 20 is taken from Fig. 22 is a cross-sectional view taken along a line CC in an arrow direction, and Fig. 23 is a cross-sectional view taken along a line DD in an arrow direction.

[0061] As in the Fig. 21 and Fig. As illustrated in Figure 22, the two-stage trench electrode 30 has a similar structure to that of the single-stage trench electrode 40 at the end part; it is provided in such a way that it extends upwards in an upward direction, so that the lower electrode 19 is in contact with the intermediate insulating layer IS, and it is electrically connected to the gate wiring 3, which is provided on the intermediate insulating layer IS, via a contact hole 62.

[0062] Furthermore, as in Fig. As illustrated in Figure 23, the two-stage trench electrode 30 has a structure of the two-stage trench electrode 30 that differs in one part from the end part, and the upper electrode 14 is in contact with the intermediate insulating layer IS and is electrically connected to an emitter wiring 64 which is provided on the intermediate insulating layer IS, via a contact hole 63.

[0063] As in Fig. As illustrated in Figure 21, a p-type termination trough region 61 is provided on the side of termination region 5, which is located outside the end part of the two-stage trench electrode 30.

[0064] As described above, in the wiring connection region, the end part of the two-stage trench electrode 30 has the same structure as that of the single-stage trench electrode 40, and therefore the width and shape of the pointed part 15 of the two-stage trench electrode 30 can be handled using the sight element 16 of the single-stage trench electrode 40, as shown in Fig. 22 illustrated. <Dritte bevorzugte Ausführungsform>

[0065] Fig. Figure 24 is a view illustrating a semiconductor device of a third preferred embodiment, and it is a cross-sectional view in an arrow direction taken along a line EE of a subregion 80, which is defined by a dashed line in the active region AR in Fig. 1 is surrounded. The subregion 80 is the termination region 5 outside the active region AR, and a single-stage trench electrode 81, which is formed in the termination region, has the same structure as that of the single-stage trench electrode 40, it contains a trench insulating layer 88 on a bottom part and a side wall of the trench, that is, an inner surface, it contains a trench electrode 89, which reaches the first main surface starting from the bottom part of the trench, and a sighting element 82, which is formed from a conductor, embedded in an upper region of the trench insulating layer 88 of the side wall. Therefore, the width and shape of the pointed part 15 of the two-stage trench electrode 30 can be controlled using the sighting element 82.

[0066] It should be noted that a p-type termination trough region 61 is provided outside the single-stage trench electrode 81, and an intermediate insulating layer IS is provided on the p-type termination trough region 61. Although nothing is illustrated in the structure on the region where the single-stage trench electrode 81 is provided, an emitter electrode or an intermediate insulating layer may also be provided here. The width and shape of the pointed part 15 of the two-stage trench electrode 30 are controlled using the sight element 82, and therefore any potential can be applied to the single-stage trench electrode 81, and the single-stage trench electrode may have a floating potential. <Vierte bevorzugte Ausführungsform>

[0067] Fig. Figure 25 is a view illustrating a semiconductor device according to a fourth preferred embodiment, and it is a cross-sectional view taken along a line FF of a subregion 90, which is surrounded by a dashed line in a region in which the singulation line 4 is Fig. 1 is trained. As in Fig. Figure 25 illustrates a single-stage trench electrode 91 formed in subregion 90. The single-stage trench electrode 91 has a structure similar to that of the single-stage trench electrode 40; it contains a trench insulating layer 98 on a bottom part and a side wall of the trench, i.e., on an inner surface, and it contains a trench electrode 99 extending from the bottom part of the trench to the first main surface. A sighting element 92, containing a conductor, is embedded in an upper region of the trench insulating layer 98 of the side wall. Therefore, the width and shape of the pointed part 15 of the two-stage trench electrode 30 can be controlled using the sighting element 92. <Fünfte bevorzugte Ausführungsform>

[0068] Fig. Figure 26 is a top view which schematically illustrates an entire configuration of an upper surface of a backward-conducting IGBT (RC-IGBT) 200 according to the second preferred embodiment of the present disclosure. The RC-IGBT 200 has an IGBT region 250 and a diode region 260 in a semiconductor substrate.

[0069] A multitude of diode regions 260 are arranged side by side in a longitudinal and a transverse direction within the RC-IGBT 200, and the diode regions 260 are surrounded by the IGBT region 250. In other words, the multitude of diode regions 260 are provided in an island configuration within the IGBT region 250. It should be noted that the diode regions 260 are not located on the [unclear] in [unclear] Fig. The number illustrated in 26 is limited.

[0070] The RC-IGBT 200 is similar to the one in Fig. Figure 1 illustrates IGBT 100, the outer side of the active region AR being a termination region 205. Within the active region AR, a plurality of trench electrodes (not illustrated) are arranged in parallel at intervals. The plurality of trench electrodes is connected to a gate wiring 203 provided within the active region AR, and the gate wiring 203 is connected to a gate pad 202. A singulation line 204 is provided outside the termination region 205. It should be noted that the shapes and arrangement of the gate wiring 203 and the gate pad 202 do not correspond to those shown in Figure 1. Fig. 26 are limited.

[0071] A top view of subregion 51, which is defined by a dashed line in the active region AR of Fig. 26 is surrounded by, is in Fig. 27 illustrated. Fig. Figure 27 is a partial top view in which an upper structure such as an emitter electrode in the active region AR is omitted.

[0072] As in Fig. As illustrated in Figure 27, a strip-shaped two-stage trench electrode 230 and a strip-shaped single-stage trench electrode 240 are arranged in parallel in the active region AR. The two-stage trench electrode 230 and the single-stage trench electrode 240 are arranged such that they extend horizontally on the paper parallel to an arrangement direction of the plurality of diode regions 260. It should be noted that the direction of extension of the two-stage trench electrode 230 and the single-stage trench electrode 240 is not limited to this, and a vertical direction on the paper can also be the direction of extension.

[0073] Fig. 28 is a cross-sectional view, which is drawn along a line GG in Fig. 27 is taken in one direction of the arrow. As in Fig. Figure 28 illustrates that the IGBT region 250 of the RC-IGBT 200 exhibits a n - Type Drift layer 209 (first semiconductor layer), which contains a semiconductor substrate. The n - Type Drift Layer 209 is identical to the n - Drift layer 9 of the IGBT 100.

[0074] In Fig. 28 the semiconductor substrate lies in an area of ​​the n + Type source layer 206 up to the p-type collector layer 212. In Fig. 28 will be the upper end of the n + The p-type source layer 206 is referred to on the paper as a first principal surface of the semiconductor substrate, and the lower end of the p-type collector layer 212 on the paper is referred to as a second principal surface of the semiconductor substrate.

[0075] As in Fig. 28 illustrates, is a n + Type charge carrier accumulation layer 208, which has a higher impurity concentration than that of n - Type Drift layer 209 is present, on the side of the first main surface of the n - Drift layer type 209 provided. The n + Type charge carrier accumulation layer 208 is identical to the n + Type 208 charge carrier accumulation layer of the IGBT 100.

[0076] A p-type base layer 207 (second semiconductor layer) is provided on the side of the first main surface of the n+ type charge carrier accumulation layer 208. The p-type base layer 207 is identical to the p-type base layer 207 of the IGBT 100.

[0077] The p-type base layer 207 is in contact with a trench insulation layer 210 (first trench insulation layer) of the two-stage trench electrode 230 and the trench insulation layer 218 (second trench insulation layer) of the single-stage trench electrode 240.

[0078] On the side of the first main surface of the p-type base layer 207 there is an n + Type Source layer 206 (third semiconductor layer) in contact with the trench insulating layer 210. The n + Type Source layer 206 is identical to the n + Type Source layer 6 of the IGBT 100.

[0079] A + Type buffer layer 211 (fourth semiconductor layer), which has a higher concentration of an n-type defect than that of the n - Type Drift Layer 209 is provided on the side of the second main surface of the n-type drift layer 209. The n + Buffer layer type 211 is identical to the n + Buffer layer type 11 of the IGBT 100.

[0080] A p + Type collector layer 212 is provided on the side of the second main surface of the n-type buffer layer 211. The p + Collector layer type 212 is identical to the p + Collector layer type 12 of the IGBT 100.

[0081] In diode region 260 of the RC-IGBT 200, which is in Fig. As illustrated in Figure 28, the same components as those of the IGBT REGION 250 are identified by identical reference symbols, and a redundant description has been omitted.

[0082] As in Fig. As illustrated in Figure 28, in the diode region 260 there is a p-type anode layer 221 (fifth semiconductor layer) instead of the n + Type Source layer 206 provided, and an n + Type cathode layer 222 (sixth semiconductor layer) is used instead of the p + Collector layer type 212 provided.

[0083] The p-type anode layer 221 is a semiconductor layer which, for example, contains boron or aluminum as a p-type defect, and a concentration of the p-type defect corresponds to 1.0 × 10 12 / cm 3 up to 1.0 × 10 19 / cm 3 . The n + Cathode layer type 222 is a semiconductor layer which, for example, contains arsenic or phosphorus as an n-type defect, and a concentration of the n-type defect corresponds to 1.0 × 10 16 / cm 3 up to 1.0 × 10 21 / cm 3 .

[0084] The two-stage trench electrode 230 is provided in a trench which is configured such that the p-type base layer 207 is penetrated by the first main surface of the semiconductor substrate and the n-type drift layer 209 is reached. In other words, the two-stage trench electrode 230 contains the trench insulating layer 210 on a bottom part and a side wall of the trench, that is, on an inner surface. A lower electrode 219 is provided below the trench, which is surrounded by the trench insulating layer 210, and an upper electrode 214 is provided above the lower electrode 219. The lower electrode 219 and the upper electrode 214 are insulated by a subdivision insulating layer 220, and the upper electrode 214 is connected to an emitter potential and the lower electrode 219 is connected to a gate potential.

[0085] In the upper electrode 214, a portion corresponding to the upper side of the lower electrode 219 is a depression, and a side wall of the depression is a pointed portion 215 that projects towards the bottom of the trench. The subdividing insulating layer 220 is provided such that it covers the interior of the depression and the pointed portion 15.

[0086] The single-stage trench electrode 240 is provided in a trench which is configured such that it penetrates the p-type base layer 207 from the first main surface of the semiconductor substrate and reaches the n-type drift layer 209. In other words, the single-stage trench electrode 240 comprises the trench insulating layer 218 on the bottom part and the side wall of the trench, that is, on the inner surface, and includes the trench electrode 217, which extends from the bottom part of the trench to the first main surface, and the sighting element 216, which contains a conductor, is embedded in an upper region of the trench insulating layer 218 of the side wall.

[0087] The two-stage trench electrode 230 and the single-stage trench electrode 240 are identical to the two-stage trench electrode 30 and the single-stage trench electrode 40 of the IGBT 100.

[0088] As in Fig. As illustrated in Figure 28, the interlayer insulating layer IS is provided on the two-stage trench electrode 230 and the single-stage trench electrode 240, and an emitter electrode 201 (first main electrode) is provided on the first main face of the semiconductor substrate, encompassing the interlayer insulating layer IS. A collector electrode 213 (second main electrode), which also functions as a cathode electrode, is provided on the second main face of the semiconductor substrate opposite the side on which the emitter electrode 201 is provided, in a thickness direction.

[0089] The sighting element 216 of the single-stage trench electrode 240 and the pointed part 215 of the two-stage trench electrode 230 are formed by means of the same element, and thus the formation conditions are identical, and by handling a width and a shape of the pointed part 215 of the two-stage trench electrode 230 using the sighting element 216, resistance to damage of the pointed part 215 can be improved, and the reliability of the RC-IGBT 200 can be improved.

[0090] It should be noted that in the present disclosure embodiments can be freely combined, and the embodiments can be appropriately modified or omitted within a scope of the disclosure.

[0091] The present revelation, described above, is collectively described as the Appendices. (Appendix 1)

[0092] comprising a semiconductor device: a semiconductor substrate which exhibits at least the following: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type on top of the first semiconductor layer; and a third semiconductor layer of the first conductivity type, which is provided in an upper part of the second semiconductor layer; a first trench electrode and a second trench electrode which are provided within a trench which penetrates the third semiconductor layer and the second semiconductor layer of the semiconductor substrate in a thickness direction and reaches an interior of the first semiconductor layer; an intermediate insulating layer that covers the first and second trench electrodes; a first main electrode, which is in contact with the third semiconductor layer; and a second main electrode, which is provided on one side opposite the first main electrode in the thickness direction of the semiconductor substrate, wherein the first trench electrode has a two-stage structure which contains: a lower electrode, which is provided on a lower side, which is the side of the second main electrode; an upper electrode which is provided on an upper side which is the side of the first main electrode; a first trench insulation layer, which covers an inner surface of the trench; and a dividing insulating layer which is provided between the lower electrode and the upper electrode, in the upper electrode a part which corresponds to an upper side of the lower electrode is a depression, and a side wall of the depression is a pointed part which protrudes towards a bottom part of the trench, The subdivision insulating layer is provided to cover the interior of the depression and the pointed part. the second trench electrode features: a second trench insulation layer, which covers an inner surface of the trench; a trench electrode with which the trench, which is covered by the second trench insulation layer, is filled; and a visible element which is embedded in an upper region of the second trench insulation layer, the upper electrode is connected to a potential of the first main electrode, and the lower electrode and the trench electrode are connected to a gate potential. (Appendix 2)

[0093] comprising a semiconductor device: comprising a semiconductor substrate: a first region which at least exhibits: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type on top of the first semiconductor layer; a third semiconductor layer of the first conductivity type, which is provided in an upper part of the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type, which is provided in the first semiconductor layer opposite the third semiconductor layer in a thickness direction; a second region which at least has: the first semiconductor layer; the second semiconductor layer; a fifth semiconductor layer of the first conductivity type, which is provided in an upper part of the third semiconductor layer; and a sixth semiconductor layer of the second conductivity type, which is provided in the first semiconductor layer opposite the fifth semiconductor layer in the thickness direction; a first trench electrode which is provided within a first trench which penetrates the third semiconductor layer and the second semiconductor layer in the first region in the thickness direction and reaches an interior of the first semiconductor layer; a second trench electrode, which is provided within a second trench, which penetrates the fifth semiconductor layer and the second semiconductor layer in the second region in the thickness direction and reaches the interior of the first semiconductor layer; an intermediate insulating layer that covers the first and second trench electrodes; a first main electrode, which is in contact with the third semiconductor layer and the fifth semiconductor layer; and a second main electrode, which is provided on one side opposite the first main electrode in the thickness direction of the semiconductor substrate, wherein the first trench electrode has a two-stage structure which contains: a lower electrode, which is provided on a lower side, which is the side of the second main electrode; an upper electrode which is provided on an upper side which is the side of the first main electrode; a first trench insulation layer, which covers an inner surface of the first trench; and a dividing insulating layer which is provided between the lower electrode and the upper electrode, in the upper electrode a part which corresponds to an upper side of the lower electrode is a depression, and a side wall of the depression is a pointed part which protrudes towards the bottom of the trench, The subdivision insulating layer is provided to cover the interior of the depression and the pointed part. the second trench electrode features: a second trench insulation layer, which covers an inner surface of the second trench; a trench electrode with which the trench, which is covered by the second trench insulation layer, is filled; and a visible element which is embedded in an upper region of the second trench insulation layer, the upper electrode is connected to a potential of the first main electrode, and the lower electrode and the trench electrode are connected to a gate potential. (Appendix 3)

[0094] Semiconductor device according to Appendix 1 or 2, wherein in a case where the thickness of the first trench insulation layer between a side wall of the trench of the first trench electrode and the pointed part is specified as X1, the thickness of the pointed part is set to X2, a thickness of the subdivision insulating layer between the pointed part and the lower electrode is set at X3, a thickness of the second trench insulation layer between the side wall of the trench of the second trench electrode and the sighting element on X11 is specified, a thickness of the visual element is set to X12, and a thickness of the second trench insulation layer between the visible element and the trench electrode is specified at X13, a relationship of X1 = X11, X2 = X12, and X3 = X13 is satisfied. (Appendix 4)

[0095] Semiconductor device according to Appendix 3, wherein the first trench electrode has: a first matching trench electrode, in which the upper electrode is connected to a potential of the first main electrode, and the lower electrode is connected to the gate potential; and a second matching trench electrode in which the upper electrode and the lower electrode are connected to the gate potential. (Appendix 5)

[0096] Semiconductor device according to Appendix 3, wherein the viewing element is connected to an arbitrary potential consisting of a first main electrode potential, the gate potential, and a floating potential. (Appendix 6)

[0097] Semiconductor device according to Appendix 4 or 5, wherein the first and second trench electrodes are arranged at intervals from each other such that a longitudinal direction of each of the first and second trench electrodes is parallel in an active region through which a main current flows, the first trench electrode has the same structural part as a structural part of the second electrode at an end part in the longitudinal direction, and the lower electrode is connected to the trench electrode of the structural part and is electrically connected to a gate wiring which is provided along an outer periphery of the active region via the trench electrode. (Appendix 7)

[0098] Semiconductor device according to Appendix 4 or 5, wherein the first and second electrodes are arranged at distances from each other such that a longitudinal direction of each of the first and second trench electrodes lies parallel in an active region through which a main current flows, and the second trench electrode is also located in a termination region outside the active region. (Appendix 8)

[0099] Semiconductor device according to Appendix 4 or 5, wherein the first and second electrodes are arranged at distances from each other such that a longitudinal direction of each of the first and second trench electrodes lies parallel in an active region through which a main current flows, and the second trench electrode is also arranged on a singulation line at an outermost side of the active region. (Appendix 9)

[0100] Semiconductor device according to one of Appendices 1 to 8, wherein the sighting element and the upper electrode are formed from the same conductor. (Appendix 10)

[0101] A method for manufacturing a semiconductor device comprising the steps for: (a) Forming first and second trenches that reach a predefined depth starting from a main surface of the semiconductor substrate; (b) Forming a first insulating layer on an inner surface of the first trench and forming a second insulating layer on an inner surface of the second trench; (c) Embedding a conductor through the first and second insulating layers, forming a lower electrode in the first trench, and forming a trench electrode in the first trench; (d) Removal of the conductor above the first and second insulating layers on the main surface; (e) Selective formation of a resist mask so that the second trench is covered; (f) Performing an etching operation using the resist mask as the etching mask, such that the lower electrode is retracted into the first trench and the trench electrode remains; (g) Removing the first and second insulating layers by etching so that the top ends of the first and second insulating layers are lower than the top ends of the bottom electrode and the trench electrode after removal of the resist mask; (h) Forming a third insulating layer on a side wall of the first trench and a lower part of the lower electrode and forming a fourth insulating layer on a side wall of the second trench and an upper part of the trench electrode; (i) Embedding the conductor in the first and second trenches in a state in which the third and fourth insulating layers are formed, forming an upper electrode which contains a pointed part in the first trench, and embedding a sighting element in the second trench; (j) Removal of the conductor and the third and fourth insulating layers on the main surface; (k) Observing the trench electrode from one side of the main surface; establishing a positional relationship between the trench electrode, the sighting element, and the second insulating layer, and estimating and handling a width and shape of the pointed part of the first trench; and (l) Forming an intermediate insulating layer above the first and second trenches in a case where the estimated width and shape of the pointed part are within a design area.

[0102] While the revelation has been shown and described in detail, the preceding description is illustrative in all aspects and not limiting. It is therefore understood that numerous modifications and variations can be conceived. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2024-1723 [0002, 0003]< / herstellungsverfahren> < / vorrichtungskonfiguration>

Claims

[1] comprising a semiconductor device: • a semiconductor substrate which has at least the following properties: ◯ a first semiconductor layer (9) of a first conductivity type; ◯ a second semiconductor layer (7) of a second conductivity type on the first semiconductor layer; and ◯ a third semiconductor layer (6) of the first conductivity type, which is provided in an upper part of the second semiconductor layer; ◯ a first trench electrode (30) and a second trench electrode (40) which are provided within a trench which penetrates the third semiconductor layer and the second semiconductor layer of the semiconductor substrate in a thickness direction and reaches an interior of the first semiconductor layer; ◯ an intermediate insulating layer (IS) covering the first and second trench electrodes; ◯ a first main electrode (1) which is in contact with the third semiconductor layer; and ◯ a second main electrode (3) which is provided on one side opposite the first main electrode in the thickness direction of the semiconductor substrate, wherein • the first trench electrode has a two-stage structure which contains: ◯ a lower electrode (19) provided on a lower side which is the side of the second main electrode; ◯ an upper electrode (14) which is provided on an upper side which is the side of the first main electrode; ◯ a first trench insulation layer (10) which covers an inner surface of the trench; and ◯ a partition insulating layer (20) which is provided between the lower electrode and the upper electrode, • in the upper electrode a part which corresponds to an upper side of the lower electrode is a depression, and a side wall of the depression is a pointed part (15) which projects towards a bottom part of the trench, • the subdivision insulating layer is provided to cover the interior of the depression and the pointed part, • the second trench electrode has: ◯ a second trench insulation layer (18) which covers an inner surface of the trench; ◯ a trench electrode (17) with which the trench, which is covered by the second trench insulation layer, is filled; and ◯ a visible element (16) which is embedded in an upper region of the second trench insulation layer, • the upper electrode is connected to a potential of the first main electrode, and • the lower electrode and the trench electrode are connected to a gate potential. [2] comprising a semiconductor device: • comprising a semiconductor substrate: ◯ a first region (250) which has at least: ▪ a first semiconductor layer (209) of a first conductivity type; ▪ a second semiconductor layer (207) of a second conductivity type on the first semiconductor layer; ▪ a third semiconductor layer (206) of the first conductivity type, which is provided in an upper part of the second semiconductor layer; and ▪ a fourth semiconductor layer (211) of the second conductivity type, which is provided in the first semiconductor layer opposite the third semiconductor layer in one thickness direction; and ◯ a second region (260) which has at least: ▪ the first semiconductor layer; ▪ the second semiconductor layer; ▪ a fifth semiconductor layer (221) of the first conductivity type, which is provided in an upper part of the third semiconductor layer; and ▪ a sixth semiconductor layer (222) of the second conductivity type, which is provided in the first semiconductor layer opposite the fifth semiconductor layer in the thickness direction; • a first trench electrode (230) which is provided within a first trench which penetrates the third semiconductor layer and the second semiconductor layer in the first region in the thickness direction and reaches an interior of the first semiconductor layer; • a second trench electrode (240) which is provided within a second trench which penetrates the fifth semiconductor layer and the second semiconductor layer in the second region in the thickness direction and reaches the interior of the first semiconductor layer; • an intermediate insulating layer (IS) covering the first and second trench electrodes; • a first main electrode (201) which is in contact with the third semiconductor layer and the fifth semiconductor layer; and • a second main electrode (203) which is provided on a side opposite the first main electrode in the thickness direction of the semiconductor substrate, wherein • the first trench electrode has a two-stage structure which contains: o a lower electrode (219) provided on a lower side which is the side of the second main electrode; o an upper electrode (214) which is provided on an upper side which is the side of the first main electrode; o a first trench insulation layer (210) which covers an inner surface of the first trench; and ◯ a partition insulating layer (220) which is provided between the lower electrode and the upper electrode, ▪ in the upper electrode a part which corresponds to an upper side of the lower electrode is a depression, and a side wall of the depression is a pointed part (215) which projects towards a bottom part of the trench, • the subdivision insulating layer is provided to cover the interior of the depression and the pointed part, • the second trench electrode has: ◯ a second trench insulation layer (218) which covers an inner surface of the second trench; ◯ a trench electrode (217) with which the trench, which is covered by the second trench insulation layer, is filled; and ◯ a visible element (216) which is embedded in an upper region of the second trench insulation layer, • the upper electrode is connected to a potential of the first main electrode, and • the lower electrode and the trench electrode are connected to a gate potential. [3] Semiconductor device according to claim 1 or 2, wherein ▪ in a case where the thickness of the first trench insulation layer between a side wall of the trench of the first trench electrode and the pointed part is specified at X1, • the thickness of the pointed part is set to X2, • the thickness of the subdivision insulating layer between the pointed part and the lower electrode is set at X3, • a thickness of the second trench insulation layer between the side wall of the trench of the second trench electrode and the sighting element on X11 is specified, • the thickness of the visible element is set to X12, and • the thickness of the second trench insulation layer between the visible element and the trench electrode is specified at X13, • a relationship of X1 = X11, X2 = X12, and X3 = X13 is satisfied. [4] Semiconductor device according to claim 3, wherein • the first trench electrode has: a first matching trench electrode (30) in which the upper electrode is connected to a potential of the first main electrode, and the lower electrode is connected to the gate potential; and a second matching trench electrode (70) in which the upper electrode and the lower electrode are connected to the gate potential. [5] Semiconductor device according to claim 3, wherein the viewing element is connected to any potential of the first main electrode, the gate potential, and a floating potential. [6] Semiconductor device according to claim 4 or 5, wherein • the first and second trench electrodes are arranged at intervals from each other such that a longitudinal direction of each of the first and second trench electrodes lies parallel in an active region (AR) through which a main current flows, • the first trench electrode has the same structural part as a structural part of the second electrode at an end part in the longitudinal direction, and • the lower electrode is connected to the trench electrode of the structural part and is electrically connected to a gate wiring (3) which is provided along an outer periphery of the active region, via the trench electrode. [7] Semiconductor device according to claim 4 or 5, wherein • the first and second electrodes are arranged at distances from each other such that a longitudinal direction of each of the first and second trench electrodes lies parallel in an active region (AR) through which a main current flows, and • the second trench electrode is also located in a termination region (5) outside the active region. [8] Semiconductor device according to claim 4 or 5, wherein • the first and second electrodes are arranged at distances from each other such that a longitudinal direction of each of the first and second trench electrodes lies parallel in an active region (AR) through which a main current flows, and • the second trench electrode is also arranged on a singulation line (4) at an outermost side of the active region. [9] Semiconductor device according to any one of claims 1 to 8, wherein the viewing element and the upper electrode are formed from the same conductor. [10] A method for manufacturing a semiconductor device comprising the steps of: (a) Forming first and second trenches (TR) which reach a predefined depth starting from a main surface (301) of a semiconductor substrate (300); (b) Forming a first insulating layer (303) on an inner surface of the first trench and forming a second insulating layer (304) on an inner surface of the second trench; (c) Embedding a conductor (CD) through the first and second insulating layers, forming a lower electrode (319) in the first trench, and forming a trench electrode (317) in the first trench; (d) Removal of the conductor above the first and second insulating layers on the main surface; (e) selectively forming a resist mask (350) so that it covers the second trench; (f) Performing an etching operation using the resist mask as the etching mask, such that the lower electrode is retracted into the first trench and the trench electrode remains; (g) Removing the first and second insulating layers by etching so that the top ends of the first and second insulating layers are lower than the top ends of the bottom electrode and the trench electrode after removal of the resist mask; (h) Forming a third insulating layer (320) on a side wall of the first trench and an upper part of the lower electrode and forming a fourth insulating layer (330) on a side wall of the second trench and an upper part of the trench electrode; (i) Embedding the conductor in the first and second trenches in a state in which the third and fourth insulating layers are formed, forming an upper electrode (314) having a pointed part (315) in the first trench, and embedding a sighting element (316) in the second trench; (j) Removal of the conductor and the third and fourth insulating layers on the main surface; (k) Observing the trench electrode from one side of the main surface; establishing a positional relationship between the trench electrode, the sighting element, and the second insulating layer, and estimating and handling a width and shape of the pointed part of the first trench; and (I) Forming an intermediate insulating layer (340) above the first and second trenches in a case where the estimated width and shape of the pointed part are within a design area.

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