STORAGE DEVICE AND METHOD FOR OPERATING THE SAME

Abstract

A storage device can comprise a peripheral circuit and a control circuit. The peripheral circuit performs a programming operation on memory cells, checks the memory cells based on a target voltage and a pre-target voltage, and applies bit-line voltages to bit lines. The control circuit manages the peripheral circuit to determine that the memory cells are initially programmed cells, adjacent programmed cells, and fully programmed cells, and adjusts the timing of when to apply the bit-line voltages to the bit lines connected to the initially programmed cells, the adjacent programmed cells, and the fully programmed cells.When performing these operations, the control circuit manages the peripheral circuit to adjust the timing of a voltage to be applied to a bit line connected to the adjacent programmed cells, depending on a number of at least one of the initially programmed cells, the adjacent programmed cells, or the fully programmed cells.

Description

BACKGROUND 1. Technical field

[0001] Various embodiments of the present disclosure relate to a storage device and a method for operating the storage device, in particular a storage device and a method for operating the storage device that perform a programming operation. 2. State of the art

[0002] A storage device can comprise a memory cell array in which data is stored and peripheral circuitry that performs a programming, read, or erase operation. The memory cell array can comprise memory blocks. Each memory block can contain a multitude of memory cells. Because memory cells have different electrical properties, the times at which the memory cells are programmed can vary.

[0003] The peripheral circuitry may include a control circuit that controls the operation of the storage device in response to a command transmitted by an external controller, as well as circuits that perform a programming operation, an erasing operation, or a read operation according to the control of the control circuit.

[0004] When a programming operation is performed on a selected memory block, the threshold voltage distributions of the memory cells contained within that block can broaden due to differences in their programming speeds. For example, when a programming voltage is applied to a selected word line, the threshold voltages of memory cells connected to that word line can increase as a result of the programming voltage. This increase occurs because the programming process injects electrons into the floating gates of the memory cells. This creates a buildup of negative charges in the floating gates, requiring higher voltages to turn on the memory cell transistors, thus increasing the cell threshold voltages.

[0005] The programming speed of memory cells can be directly proportional to their threshold voltages. For example, the threshold voltages of memory cells with a relatively high programming speed may rise more rapidly than those of memory cells with a relatively low programming speed. This can broaden the threshold voltage distribution. Due to these broadened threshold voltage distributions, the number of error bits occurring during a read operation can increase, thus degrading the reliability of the storage device. SUMMARY

[0006] Various embodiments of the present disclosure relate to a storage device and a method for operating the storage device which can improve the threshold voltage distributions of memory cells.

[0007] An embodiment of the present disclosure can provide a storage device. The storage device can comprise one or more memory cells, a peripheral circuit configured to perform a programming operation on the memory cells, to check the memory cells based on a target voltage and a pre-target voltage that is lower than the target voltage, and to apply voltages to bit lines connected to the memory cells, and a control circuit coupled to the peripheral circuit and configured to determine, depending on the result of a check performed on the memory cells, memory cells as initially programmed cells, adjacent programmed cells, or fully programmed cells, and to set time points.to adjust, to which bit line voltages are to be applied to bit lines connected to the initially programmed cells, the adjacent programmed cells and the fully programmed cells, wherein adjusting the timing of the bit line voltages comprises controlling the peripheral circuit to adjust a timing of at least one bit line voltage to be applied to a bit line connected to one of the adjacent programmed cells, among the bit line voltages depending on a number of at least one of the initially programmed cells, the adjacent programmed cells or the fully programmed cells.

[0008] An embodiment of the present disclosure may provide a method for operating a storage device. The method may include classifying memory cells as initially programmed cells, adjacent programmed cells, or fully programmed cells depending on the result of a check performed on the memory cells during a programming operation; applying a programming enable voltage to a first bit line corresponding to the initially programmed cells; optionally applying a second programming lock voltage and the programming enable voltage to a second bit line corresponding to the adjacent programmed cells; applying a first programming lock voltage to a third bit line corresponding to the fully programmed cells; applying a programming voltage to a word line connected to the memory cells; and adjusting a time.during which the second programming lock voltage is applied to the second bit line, depending on the number of initially programmed cells and adjacent programmed cells. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows a diagram representing a storage device according to an embodiment of the present disclosure. Fig. Figure 2 shows a diagram illustrating the arrangement of a memory cell arrangement and a peripheral circuit according to an embodiment of the present disclosure. Fig. Figure 3 shows a perspective view representing a memory block according to an embodiment of the present disclosure. Fig. Figure 4 shows a circuit diagram representing a memory block according to an embodiment of the present disclosure. Fig. Figure 5 shows a diagram illustrating the states of memory cells as a function of threshold voltages according to an embodiment of the present disclosure. Fig. Figure 6 shows a diagram illustrating voltages applied to a selected memory block during a programming operation according to an embodiment of the present disclosure. Fig. Figure 7 shows a flowchart representing a programming operation according to a first embodiment of the present disclosure. Fig. Figure 8 shows a diagram illustrating a testing operation according to an embodiment of the present disclosure. The Fig. Figures 9A to 9D show diagrams illustrating programming operations according to a first embodiment of the present disclosure. Fig. Figure 10 shows a flowchart representing a programming operation according to a second embodiment of the present disclosure. Fig. Figures 11A to 11C and 12A to 12C show diagrams illustrating programming operations according to a second embodiment of the present disclosure. Fig. Figures 13A to 13D show diagrams illustrating the threshold voltages of memory cells that are successively increased during a programming operation, according to the present disclosure. Fig. Figure 14 shows a diagram representing a memory card system to which a storage device according to an embodiment of the present disclosure is applied. Fig. Figure 15 shows a diagram representing a solid-state drive (SSD) to which a storage device according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0009] Specific structural or functional descriptions disclosed herein serve as examples to describe embodiments according to the concept of this disclosure. The embodiments according to the concept of this disclosure should not be considered limited to those described below and may be modified in various ways and replaced by other equivalent embodiments.

[0010] Although the terms "first" and "second" are used below to describe different elements, these elements should not be restricted by these terms. The terms are used to distinguish one element from another.

[0011] Fig. Figure 1 shows a diagram representing a storage device 100 according to an embodiment of the present disclosure.

[0012] With reference to Fig. 1 The storage device 100 can comprise a memory cell arrangement 110 in which data is stored and a peripheral circuit 180 that performs a programming operation, a read operation or an erase operation on the memory cell arrangement 110.

[0013] The memory cell arrangement 110 can comprise a first to j-th memory block BLK1 to BLKj in which data is stored. Each of the first to j-th memory blocks BLK1 to BLKj can comprise a plurality of memory cells, which can be implemented in a two-dimensional (2D) structure, where the memory cells are arranged horizontally on a substrate, or in a three-dimensional (3D) structure, where the memory cells are stacked vertically on a substrate. Each of the first to j-th memory blocks BLK1 to BLKj according to the present embodiment can be formed in a 3D structure. Drain select lines DSL, word lines WL, source select lines SSL, and a source line SL can be connected to each of the first to j-th memory blocks BLK1 to BLKj.

[0014] The peripheral circuit 180 can include a voltage generator 120, a line decoder 130, a side buffer group 140, a column decoder 150, an input and output (input / output) circuit 160 and a control circuit 170.

[0015] The voltage generator 120 can generate and output the operating voltages Vop required for various operations in response to an OPCD operation code. For example, the voltage generator 120 can generate and output a programming voltage, a verification or test voltage, a read voltage, a pass voltage, an erase voltage, a compensation voltage, etc. The voltage generator 120 can adjust or set the respective levels, output times, or blocking times of the operating voltages Vop in response to the OPCD operation code.

[0016] The line decoder 130 can select a memory block from the first to j-th memory blocks BLK1 to BLKj, which are included in the memory cell arrangement 110, according to a line address RADD and transfer the operating voltages Vop to the selected memory block.

[0017] The page buffer group 140 can be connected to the memory cell array 110 via bit lines BL. For example, the page buffer group 140 can comprise a plurality of page buffers, each connected to the bit lines BL. The page buffers can operate concurrently in response to page buffer control signals PBSIG and temporarily store data during a programming or read operation. For this operation, each of the page buffers can comprise a plurality of latches in which data is temporarily stored. The number of latches can vary depending on a program procedure. For example, the page buffers can be configured differently depending on the number of bits that can be stored in a memory cell, and they can be configured differently depending on the number of test voltages used in a test operation.

[0018] The column decoder 150 can transfer data DATA between the input / output circuit 160 and the page buffer group 140 according to a column address CADD.

[0019] The input / output circuit 160 can be connected to a controller via input / output (I / O) lines. The input / output circuit 160 can receive or output a command (CMD), an address (ADD), and data (DATA) via the input / output (I / O) lines from an external device, such as a controller or memory controller. For example, the input / output circuit 160 can transmit the command (CMD) and address (ADD) received via the input / output (I / O) lines to the controller circuit 170 and transmit the data (DATA) received via the input / output (I / O) lines to the column decoder 150. The input / output circuit 160 can output the data (DATA) received from the column decoder 150 to the external device via the input / output (I / O) lines.

[0020] The control circuit 170 can output the operation code OPCD, the row address RADD, the page buffer control signals PBSIG, and the column address CADD in response to the command CMD and the address ADD. For example, the control circuit 170 can include software that performs a programming operation, a read operation, or an erase operation in response to the command CMD and the address ADD, and hardware that outputs the operation code OPCD, the row address RADD, the page buffer control signals PBSIG, and the column address CADD according to the software control.

[0021] The control circuit 170 can be configured to perform a programming operation according to either a single-level cell (SLC) or a multi-level cell (MLC) scheme. The SLC scheme is used to program one bit of data into a memory cell. When the programming operation is performed according to the SLC scheme, each memory cell can enter either an erase state or a programming state. The multi-level scheme is used to program two or more data bits into a memory cell. For example, the two or more data bits can be programmed into a memory cell based on different electrical charge levels in a floating gate. When the programming operation is performed according to the multi-level scheme, each memory cell can enter either an erase state or one of a variety of programming states.For example, if 3 data bits are programmed into a memory cell, the memory cell can enter the erase state or one of seven different programming states.

[0022] Because memory cells have different electrical properties, their programming speeds can also differ. For example, a memory cell with a relatively high programming speed becomes a fast cell, and a memory cell with a relatively low programming speed becomes a slow cell. During a programming operation, the threshold voltage of the fast cell may rise more rapidly than that of the slow cell. Thus, even if the same programming voltage is applied to both the fast and slow cells, their threshold voltages may differ and rise at different rates. For example, fast cells generally have higher threshold voltages than slow cells. As the difference between the threshold voltages increases, the width of the threshold voltage distributions of the memory cells also increases.

[0023] Based on the results of the memory cell check, the control circuit 170, according to the present embodiment, can determine whether the memory cells are initially programmed cells, adjacent programmed cells, or fully programmed cells. The control circuit 170 can control the peripheral circuit 180 to control or regulate voltages applied to the bit lines connected to the initially programmed cells, adjacent programmed cells, or fully programmed cells, and to adjust the duration of the voltage application to the bit lines depending on the number of initially programmed cells and the number of adjacent programmed cells.

[0024] To reduce the width of the threshold voltage distributions, the control circuit 170 according to the present embodiment can determine the states of memory cells during a programming operation on the selected memory block and control the side buffer group 140 in such a way that the voltages to be applied to the bit lines are adjusted on the basis of the result of the determination.

[0025] To reduce the width of the threshold voltage distributions, the control circuit 170, according to the present embodiment, can control the side buffer group 140 such that the voltages applied to the bit lines are adjusted during a programming operation on the selected memory block, depending on the number of incomplete cells that failed the check operation or the number of cells that passed the check operation. For example, the control circuit 170 can compare a preset reference number of cells with the number of incomplete cells and adjust the voltages applied to the bit lines based on the result of the comparison. The preset reference number can be a value stored in the control circuit and can be changed according to the storage device.

[0026] Fig. Figure 2 shows a diagram illustrating the arrangement of the memory cell arrangement 110 and the peripheral circuit 180 according to one embodiment.

[0027] With reference to Fig. 2. The peripheral circuit 180 can be arranged on a substrate, and the memory cell arrangement 110 can be arranged above the peripheral circuit 180. The memory cell arrangement 110 can comprise a first to j-th memory block BLK1 to BLKj. Bit lines BL can be arranged on the first to j-th memory block BLK1 to BLKj, and a source line SL can be arranged below the first to j-th memory block BLK1 to BLKj. In contrast to the one in Fig. In the structure shown in Figure 2, the bit lines BL can be arranged under the first to j-th memory blocks BLK1 to BLKj, and the source line SL can be arranged on the first to j-th memory blocks BLK1 to BLKj.

[0028] The multitude of bit lines BL can be arranged such that they are spaced apart along an X-direction and can extend along a Y-direction. The first to j-th memory blocks BLK1 to BLKj can be arranged such that they are spaced apart along the Y-direction. The source line SL can be connected to the first to j-th memory blocks BLK1 to BLKj. The first to j-th memory blocks BLK1 to BLKj can be implemented in the same way. An arbitrary memory block is described in detail below.

[0029] Fig. Figure 3 shows a perspective view representing a memory block BLK, which may be representative of, for example, the first to j-th memory block BLK1 to BLKj.

[0030] With reference to Fig. Figure 3 shows a portion of the memory block BLK. A source selector line SSL, first to nth word lines WL1 to WLn, and a drain selector line DSL contained within the memory block BLK can be stacked such that they are spaced apart along a Z-direction. The source selector line SSL, the first to nth word lines WL1 to WLn, and the drain selector line DSL can be formed from the same conductive material. For example, each of the source selector line SSL, the first to nth word lines WL1 to WLn, and the drain selector line DSL can be made of a metallic material such as tungsten (W), molybdenum (Mo), cobalt (Co), or nickel (Ni), or a semiconductor material such as silicon (Si) or polysilicon (Poly-Si), but the material is not limited to these.

[0031] Cell connectors (CPL) can traverse the source select line (SSL), the first to nth word lines (WL1 to WLn), and the drain select line (DSL). Each cell connector (CPL) can comprise a core column (CP), a channel layer (CH), a tunnel insulation layer (TX), a charge trap layer (CTL), and a barrier layer (BX) coupled between one of the bit lines (BL) and the select line (SL). The core column (CP) can be cylindrical, rectangular, or polygonal and can be made of an insulating material or a layer of conductive material. The channel layer (CH) can surround the surface of the core column (CP) and can be made of polysilicon. The tunnel insulation layer (TX) can surround the surface of the channel layer (CH) and can be made of an oxide layer. The charge trap layer (CTL) can surround the surface of the tunnel insulation layer (TX) and can be made of a nitride layer.The barrier layer BX can surround the surface of the charge-trapping layer CTL and may be formed from an oxide layer.

[0032] Fig. Figure 4 shows a circuit diagram representing a memory block BLK, which is used for the in Fig. The two memory blocks shown may be representative.

[0033] With reference to Fig. 4. The memory block BLK (e.g., BLKj) can comprise cell strings ST, which are arranged between the source line SL and the respective first to i-th bit lines BL1 to BLi. The cell strings ST can be arranged such that they are spaced apart along the X and Y directions and can extend along a Z direction. The first to i-th bit lines BL1 to BLi can be arranged such that they are spaced apart along the X direction, and each of the first to i-th bit lines BL1 to BLi can extend along the Y direction. Each of the cell strings ST can comprise a source selector transistor SST, the first to sixteenth memory cells MC1 to MC16, and a drain selector transistor DST. The first to sixteenth memory cells MC1 to MC16 can be connected between the source selector transistor SST and the drain selector transistor DST.The number of source selection transistors SST, first to sixteenth memory cells M1 to M16 and drain selection transistors DST that are in . Fig. The information shown in section 4 may vary depending on the storage device.

[0034] Gates of source selector transistors (SST) in different cell strings (ST) can be connected to a single source selector line (SSL). Gates of the first through sixteenth memory cells (MC1 through MC16) can each be connected to a single word line (WL1 through WL16), and gates of drain selector transistors (DST) can be connected to a single drain selector line (DSL). The source selector line (SSL) can be connected to the source selector transistors (SST) arranged along the X and Y directions. Alternatively, the memory block can contain multiple source selector lines (SSL). For example, one source selector line (SSL) can be connected to the source selector transistors (SST) arranged along the X direction, and another source selector line (SSL) can be connected to the source selector transistors (SST) arranged along the Y direction. The different source selector lines (SSL) can be isolated from one another.

[0035] Each of the first through sixteenth word lines WL1 to WL16 can be connected to the memory cells arranged along the X and Y directions. For example, the first memory cells MC1 arranged along the X and Y directions can be connected to the first word line WL1, and the second memory cells MC2 arranged along the X and Y directions can be connected to the second word line WL2. The drain selector line DSL can be connected to the drain selector transistors DST arranged along the X direction. Different drain selector lines DSL can be connected to the drain selector transistors DST arranged along the Y direction.

[0036] A group of memory cells connected to the same word line can be a page (PG). In the example shown, the group of memory cells MC6 connected to word line WL6 can correspond to a page PG. Thus, each memory block BLK can contain a plurality of pages, the number of which corresponds to the number of word lines allocated to memory block BLK. A programming or read operation can be performed on a page-by-page (PG) basis. For example, a group of memory cells connected to a selected word line among the memory cells in cell strings ST, which are connected to a drain select line DSL chosen from the drain select lines DSL, can be a selected page. The selected page can be a page that contains program target memory cells during a programming operation.This means that the selected page can be determined by the drain selection line DSL and the corresponding word line.

[0037] Since the programming operation on the memory block BLK is performed on a page-by-page basis, a word line associated with the selected page can be designated as a selected word line Sel_WL, and word lines associated with the remaining pages can be designated as unselected word lines Unsel_WL. For example, if the eleventh word line WL11 is the selected word line Sel_WL, then the first through tenth word lines WL1 through WL10 and the twelfth through sixteenth word lines WL12 through WL16 can be the unselected word lines Unsel_WL within the memory block BLKj.

[0038] Fig. Figure 5 shows a diagram illustrating the states of memory cells as a function of threshold voltages according to an embodiment of the present disclosure. In the diagram of Fig. 5 denotes the horizontal axis as voltages and the vertical axis as the number of memory cells (e.g. the number of cells).

[0039] With reference to Fig. 5. During a programming operation, a selected memory cell can be one of three types: an initially programmed cell MCi, an adjacent programmed cell MCa, and a fully programmed cell MCc. The type of memory cell can depend on the magnitude of its threshold voltage. For example, a fully programmed cell MCc can be a cell with a threshold voltage raised to a target voltage Vt or higher. An adjacent programmed cell MCa can be a cell with a threshold voltage lower than the target voltage Vt and higher than a pre-target voltage Vp. An initially programmed cell MCi can be a cell with a threshold voltage lower than the pre-target voltage Vp.

[0040] The target voltage Vt can be a reference voltage to determine whether each memory cell has been programmed to a target program state. The pre-target voltage Vp can be set to a voltage lower than the target voltage Vt.

[0041] During a programming operation in the multi-level cell scheme, the memory cells are programmed to different states, and thus a variety of target voltages Vt can be set. Once a variety of target voltages Vt are set, a variety of pre-target voltages Vp, corresponding to each of the target voltages Vt, can be set. When the pre-target voltages Vp are set, they can be configured to be lower than the target voltages Vt and higher than the highest threshold voltage in a threshold voltage distribution for a state below the corresponding target voltages Vt.

[0042] In the present embodiment, the states of the memory cells can correspond to the previously mentioned types of memory cells, wherein the states of the memory cells can be classified according to the threshold voltages of the memory cells, for example, as initially programmed cells MCi, adjacent programmed cells MCa, or fully programmed cells MCc. Each adjacent programmed cell MCa can be a memory cell with a threshold voltage that is lower than a target voltage Vt, but is increased during a programming operation to approach the target voltage Vt. Therefore, in the present embodiment, the voltage of the bit line corresponding to an adjacent programmed cell MCa is adjusted.

[0043] Fig. Figure 6 shows a diagram representing the voltages applied to a selected memory block during a programming operation according to the present disclosure.

[0044] With reference to Fig. 6. During a programming operation on a memory block BLK, a programming voltage Vpgm can be applied to a selected word line Sel_WL, and a pass voltage Vpass can be applied to unselected word lines Unsel_WL. The programming voltage Vpgm has a level greater than 0 V to raise the threshold voltages of selected memory cells and can be incrementally increased during the execution of the programming operation. The pass voltage Vpass can be a voltage for forming a channel in a string and can be set to a level at which memory cells connected to the unselected word lines Unsel_WL can be turned on.

[0045] A ground voltage (GND) can be applied to a source line (SL), and a turn-on voltage (Von) can be applied to a source selector line (SSL) and a drain selector line (DSL). The turn-on voltage (Von) can be set to a level at which source selectors and drain selectors can be switched on.

[0046] A voltage selected from a programming enable voltage Val, a first programming lock voltage 1Vin and a second programming lock voltage 2Vin can be applied to each of the first to fourth bit lines BL1 to BL4 depending on the states of the memory cells.

[0047] In the Fig. In the example shown, a sixth word line WL6 is a selected word line Sel_WL, a memory cell corresponding to a first bit line BL1 is a memory cell connected to the selected word line Sel_WL, an initially programmed cell MCi is a memory cell corresponding to a second bit line BL2, an adjacent programmed cell MCa is a memory cell corresponding to a third bit line BL3, a fully programmed cell MCc is a memory cell corresponding to a fourth bit line BL4, and an unselected cell Unsel_MC is a memory cell corresponding to a fourth bit line BL4.

[0048] Since the voltage difference between the threshold voltage of the initially programmed cell MCi and a target voltage is greater than the voltage difference between the threshold voltage of the adjacent programmed cell MCa and the target voltage, the programming enable voltage Val (i.e., the lowest voltage among those applied to the bit lines) can be applied to the first bit line BL1, which corresponds to the initially programmed cell MCi. The first programming lock voltage 1Vin (i.e., the highest voltage among those applied to the bit lines during the programming operation) can be applied to the third bit line BL3, which corresponds to the fully programmed cell MCc, and to the fourth bit line BL4, which corresponds to the unselected memory cell Unsel_MC. The programming lock voltage 1Vin can be a voltage that prevents memory cells (e.g.,The programming lock voltage prevents fully programmed cells (and unselected memory cells) from being programmed during the programming operation performed on the selected memory block. The programming lock voltage can also prevent the threshold voltages of these memory cells from rising during the programming operation.

[0049] At least one of the programming enable voltage Val and the second programming lock voltage 2Vin can be selectively applied to the second bit line BL2, which is connected to a string containing the adjacent programmed cell MCa. For example, the programming enable voltage Val and the second programming lock voltage 2Vin can each be applied to the second bit line BL2 for specified times. For example, after the programming enable voltage Val has been applied to the second bit line BL2 for a specified time, the second programming lock voltage 2Vin can be applied to the second bit line BL2 for a subsequent specified time. Alternatively, after the second programming lock voltage 2Vin has been applied to the second bit line BL2 for a specified time, the programming enable voltage Val can be applied to the second bit line BL2 for a subsequent specified time.The time during which the programming enable voltage Val is applied to the second bit line BL2, and the time during which the second programming lock voltage 2Vin is applied to the second bit line BL2, can be changed.

[0050] During the programming operation, the programming speed of the adjacent programmed cell MCa can be adjusted by modifying the times during which the programming enable voltage Val and the second programming lock voltage 2Vin are applied to the second bit line BL2, which is connected to a string containing the adjacent programmed cell MCa. Since the rate at which the threshold voltage of the adjacent programmed cell MCa rises can be adjusted, the width of the threshold voltage distribution of the memory cells can be reduced.

[0051] Fig. Figure 7 shows a flowchart representing a programming operation according to a first embodiment of the present disclosure. The programming operation can be described by reference to Fig. 5 and Fig. 6 will be explained.

[0052] With reference to Fig. In S71, when a programming operation begins on a selected memory block, a programming enable voltage Val and an initial programming lock voltage 1Vin can be optionally applied to bit lines connected to the selected memory block, and a programming voltage Vpgm can be applied to a selected word line Sel_WL among the word lines connected to the selected memory block. The selected word line Sel_WL can be a word line connected to a selected page.

[0053] The program enable voltage Val can be a voltage used to decrease the channel voltages of strings that include memory cells and can be applied to selected bit lines. The first program lock voltage 1Vin can be a voltage used to increase the channel voltages of strings that include unselected memory cells and can be applied to unselected bit lines. The selected bit lines can be connected to selected strings that include the selected memory cells, and the unselected bit lines can be connected to unselected strings that include the unselected memory cells.

[0054] In S71, a pass voltage Vpass can be applied to unselected word lines among those connected to the selected memory block. The pass voltage Vpass can be used to create channels in the unselected strings by activating the unselected memory cells.

[0055] After the programming voltage has been applied to the selected word line Sel_WL for a specific time, a test operation can be performed on the selected memory cells in S72. During the test operation, a target test voltage using a pre-test voltage and a target test operation using a target test voltage can be performed sequentially. The pre-test voltage can be applied to the selected word line Sel_WL to detect memory cells with threshold voltages greater than a pre-target voltage Vp. The target test voltage can be applied to the selected word line Sel_WL to detect memory cells with threshold voltages higher than the target voltage Vt. The pre-target voltage and the target voltage can be used as a basis for classifying the states of memory cells coupled to the selected word line Sel_WL and are described above with reference to Fig. 5 has been described. Therefore, a detailed description of the pre-target voltage and the target voltage is omitted. After the pre-test operation has been performed using the pre-test voltage in S72, the target test operation can be performed using the target test voltage. A detailed test operation will be described later with reference to Fig. 8 described.

[0056] If both the pre-check operation and the target check operation in S72 were successful or passed, the programming operation performed on the selected page is terminated.

[0057] If the target check operation fails regardless of the result of the pre-check operation in S72, an operation to determine the states of the memory cell included in the selected page can be performed in S73.

[0058] In S73, the states of the memory cells can be determined based on the result of the check operation performed in S72. For example, the states of the memory cells can be determined depending on the results of the pre-check operation and the target check operation, which are performed sequentially in S72.

[0059] Depending on the result of the pre-test operation, memory cells with threshold voltages below the pre-target voltage and memory cells with threshold voltages above the pre-target voltage can be detected. Depending on the result of the target test operation, memory cells with threshold voltages below the target voltage and memory cells with threshold voltages above the target voltage can be detected.

[0060] Memory cells with threshold voltages below the pre-target voltage can be classified as initially programmed cells (MCi). Memory cells with threshold voltages above and below the target voltage can be classified as adjacent programmed cells (MCa). Memory cells with threshold voltages above the target voltage can be classified as fully programmed cells (MCc).

[0061] The memory cells identified as initial programmed cells MCi can be programmed according to the procedure described in S74. The memory cells identified as adjacent programmed cells MCa can be programmed according to the procedure described in S75. The memory cells identified as fully programmed cells MCc and the unselected memory cells Unsel_MC can be prevented from being programmed in S76. If the states of the memory cells are determined in S73, S74, S75, and S76 can be performed simultaneously.

[0062] In S74, the programming voltage Vpgm can be reset to a voltage increased by one step voltage, and this reset programming voltage can be applied to the selected word line. For example, a programming voltage can be used that is greater by one step voltage than the programming voltage used in a previous program loop. The step voltage can be a voltage difference by which the programming voltage is increased in an incremental step pulse programming (ISPP) scheme and can be preset in the memory device. The programming enable voltage Val can be applied to bit lines (e.g., BL1) of memory cells designated as initially programmed cells MCi, while the programming voltage Vpgm is applied to the selected word line.

[0063] In S75, the programming voltage Vpgm can be reset to a voltage increased by one step voltage, and this reset programming voltage can be applied to the selected word line. The programming enable voltage Val and the second programming lock voltage 2Vin can be selectively applied (e.g., sequentially) to bit lines (e.g., BL2) of the memory cells identified as adjacent programmed cells MCa, depending on the timing of the programming voltage application to the selected word line. For example, the programming enable voltage Val and the second programming lock voltage 2Vin can be applied at different times to adjust the rate at which the threshold voltages of the adjacent programmed cells MCa are increased.

[0064] In S76, the programming voltage Vpgm can be reset to a voltage increased by one step voltage, and the reset programming voltage can be applied to the selected word line. The first programming lock voltage 1Vin can be applied to bit lines (e.g., BL3) of memory cells designated as fully programmed cells MCc and unselected memory cells Unsel_MC, while the programming voltage Vpgm is applied to the selected word line Sel_WL.

[0065] In S74, the threshold voltages of the initially programmed memory cells MCi can be increased quickly (at a first rate) due to the programming enable voltage Val applied to the bit lines.

[0066] In S75, the threshold voltages of adjacent programmed memory cells MCa can be increased more slowly (e.g., at a second rate lower than the first) than in S74, due to the programming enable voltage Val and the second programming disable voltage 2Vin, which are selectively applied to the bit lines. That is, since the programming enable voltage Val is applied for a shorter time than the time it is applied to the first bit line BL1, the rate at which the threshold voltage of the adjacent programmed cell MCa increases can be slower than the rate at which the threshold voltage of the initially programmed cell MCi increases. Consequently, the rate at which the threshold voltages of the adjacent programmed memory cells MCa are increased can be adjusted.

[0067] In S76, the memory cells are in the state where programming is complete or are unselected memory cells. Therefore, the threshold voltages of the memory cells are not increased by the first programming lock voltage applied to the bit lines. The voltages applied to the respective lines in S74, S75, and S76 will be discussed later with reference to the Fig. Sections 9A to 9D are described in detail.

[0068] After the programming voltage has been applied to the selected word line in S74, S75, and S76 for a specific time, a check operation can be performed on the selected memory cells in S77. The check operation in S77 can be performed in the same way as the check operation performed in S72. If a target check operation performed in S77 fails, S73 can be repeated. If the target check operation performed in S77 was successful, the programming operation on the selected page can be terminated.

[0069] Fig. Figure 8 shows a diagram illustrating the test operation according to an embodiment of the present disclosure. The test operation can be used to classify memory cells coupled to a selected word line based on voltages generated in response to an applied pre-charge voltage.

[0070] With reference to Fig. 8 will be a detailed procedure of the one described in S72 to S77. Fig. The seven test operations are shown. The test operation can be performed during a period from a first time point T1 to a fourth time point T4. During the execution of the test operation, a ground voltage (i.e., 0 V) ​​can be applied to the source line SL, a pass voltage Vpass can be applied to the unselected word lines Unsel_WL, and a turn-on voltage Von can be applied to the drain and source selection lines DSL and SSL.

[0071] At the first time point T1, a pre-charge voltage Vpre can be applied to all bit lines BL#. The pre-charge voltage Vpre can be a positive voltage greater than 0 V and can be used to check voltage or current changes on the bit lines BL# as a function of the memory cell states.

[0072] At the second time point T2, when the pre-charge voltage Vpre rises to a setpoint, a pre-test voltage Vpv is applied to a selected word line Sel_WL. The pre-test voltage Vpv has a level lower than that of a target test voltage Vtv. For example, the pre-test voltage Vpv is used to detect initially programmed cells MCi, and the target test voltage Vtv is used to distinguish adjacent programmed cells MCa from fully programmed cells MCc. The ground voltage can be applied to the source line SL while the test operation is being performed.

[0073] The voltages of the bit lines connected to memory cells whose threshold voltages are below the pre-target voltage (e.g., Vp in Fig. 5) can be lower than the pre-charge voltage Vpre, while the pre-test voltage Vpv is applied to the selected word line Sel_WL (T2-T3). During the period T2-T3, the memory cells connected to the bit lines, whose voltages are reduced, can be recognized as initially programmed cells MCi.

[0074] At the third time point T3, the target test voltage Vtv can be applied to the selected word line Sel_WL. The voltages of bit lines connected to memory cells whose threshold voltages are below the target voltage (e.g., Vt in) Fig. 5) can become smaller than the pre-charge voltage Vpre while the target test voltage Vtv is applied to the selected word line Sel_WL (T3-T4). During the period T3-T4, the memory cells connected to the bit lines whose voltages are reduced can be classified as adjacent programmed cells. The rate at which the voltages of the adjacent programmed cells MCa decrease from the pre-charge voltage Vpre can differ from the rate (e.g., exhibit a steeper slope) at which the voltages of the initially programmed cells MCi decrease from the pre-charge voltage Vpre. During the period T3-T4, the memory cells connected to the bit lines held at the pre-charge voltage Vpre can be classified as fully programmed cells MCc.

[0075] As described above, during the inspection operation, the pre-inspection operation can be performed during the period from the second time point T2 to the third time point T3, and the target inspection operation can be performed during the period from the third time point T3 to the fourth time point T4. Data acquired or sampled in the pre-inspection operation and data acquired or sampled in the target inspection operation can be stored in buffers located in a page buffer group (e.g., 140 in Fig. 1) are included. The voltages to be applied to the bit lines in a subsequent programming loop can be determined depending on the acquired data stored in page buffer group 140.

[0076] The check operation on the selected page can pass or fail depending on the result of the target check operation. For example, the preliminary check operation can be performed to distinguish the initially programmed cells MCi, and the target check operation can be performed to distinguish the adjacent programmed cells MCa and the fully programmed cells MCc, and to determine whether the selected page has successfully passed the check operation. Determining whether the check operation has been successfully passed or failed can be identical to determining whether the programming operation performed on the selected page is complete or incomplete.

[0077] The Fig. Figures 9A to 9D show diagrams illustrating programming operations according to a first embodiment of the present disclosure.

[0078] With reference to the Fig. 6, Fig. 7 and Fig. 9A are memory cells corresponding to the first to third bit lines BL1 to BL3, selected memory cells, and a memory cell corresponding to a fourth bit line BL4 is a non-selected memory cell (see e.g. Fig. 6).

[0079] At a first point in time T1', when a program loop for a selected page begins, a first programming voltage 1Vpgm can be applied to the selected word line Sel_WL, a programming enable voltage Val can be applied to the first to third bit lines BL1 to BL3, and a first programming block voltage 1Vin can be applied to the fourth bit line BL4. A pass voltage Vpass can be applied to unselected word lines Unsel_MC, a ground voltage can be applied to a source line, and a turn-on voltage can be applied to drain and source selection lines.

[0080] Since the memory cells connected to the first to third bit lines BL1 to BL3 are the selected memory cells MCi, MCa and MCc, the threshold voltages of the selected memory cells can be increased due to the first programming voltage 1Vpgm.

[0081] After the first programming voltage 1Vpgm has been applied for a period from the first time T1' to a second time T2', a test operation can be performed on the memory cells included in the selected page. The test operation can correspond to the test operation described with reference to Fig. As explained in section 8, the check operation can classify the memory cells included in the selected page (or determine their different states). The result of the check operation is, as explained above with reference to... Fig. As described in section 6, a memory cell connected to the first bit line BL1 is an initially programmed cell MCi, a memory cell connected to the second bit line BL2 is an adjacent programmed cell MCa, and a memory cell connected to the third bit line BL3 is a fully programmed cell MCc.

[0082] Depending on the result of the check operation, at a third time point T3', when the next program loop begins, the programming enable voltage Val can be applied to the first bit line BL1, the second programming block voltage 2Vin can be applied to the second bit line BL2, and the first programming block voltage 1Vin can be applied to the third bit line BL3 and the fourth bit line BL4. The programming enable voltage Val applied to the initially programmed cell MCi can be applied for a different time (e.g., a longer time) than the time at which the programming enable signal Val is applied to the adjacent programmed cell MCa. This results in the threshold voltages of the initially programmed cell MCi and the adjacent programmed cell MCa rising at different rates.

[0083] Since the memory cell connected to the first bit line BL1 is the initially programmed cell MCi, the programming enable voltage Val can be applied to the first bit line BL1 to quickly raise the threshold voltage of the initially programmed cell MCi. The programming enable voltage Val can be the lowest voltage among those applied to the bit lines during the programming operation.

[0084] Since the memory cell connected to the second bit line BL2 is the adjacent programmed cell MCa, the second programming lock voltage 2Vin can be applied to the second bit line BL2 to raise the threshold voltage of the adjacent programmed cell MCa more slowly than that of the initially programmed cell MCi. This is because the second programming lock voltage 2Vin is applied to the adjacent programmed cell MCa at least for a portion of the time.

[0085] For example, in Fig. As shown in 9A, the second programming lock voltage 2Vin can be set to a voltage that is greater than the programming enable voltage Val and less than or equal to the first programming lock voltage 1Vin. Furthermore, in the example of Fig. 9A The second programming lock voltage 2Vin is applied before the programming enable voltage Val and can be applied for a longer time than the programming enable voltage Val. Because the programming enable voltage Val is applied to the second bit line BL2 for a shorter time than the time it is applied to the first bit line BL1, the rate at which the threshold voltage of the adjacent programmed cell MCa rises can be slower than the rate at which the threshold voltage of the initially programmed cell MCi rises.

[0086] Since the memory cell connected to the third bit line BL3 is the fully programmed cell MCc, and the memory cell connected to the fourth bit line BL4 is the unselected memory cell Unsel_MC, the first programming lock voltage 1Vin can be applied to the third and fourth bit lines BL3 and BL4, respectively, to prevent the threshold voltages of the fully programmed cell MCc and the unselected memory cell Unsel_MC from increasing further. The first programming lock voltage 1Vin can be the highest voltage among those set to be applied to the bit lines during the programming operation.

[0087] A second programming voltage of 2Vpgm can be applied to the selected word line Sel_WL. This second programming voltage can be set to a voltage one step higher than the first programming voltage of 1Vpgm. The second programming voltage can be configured to be applied to the selected word line Sel_WL for a period from the third time point T3' to the fifth time point T5'.

[0088] The first programming lock voltage 1Vin can also be applied to the third and fourth bit lines BL3 and BL4 during the period from the third time T3' to the fifth time T5'.

[0089] As in Fig. As shown in Figure 9A, the second programming lock voltage 2Vin can be applied to the second bit line BL2 for a period shorter than the period during which the second programming voltage 2Vpgm or the first programming lock voltage 1Vin is applied. For example, the second programming lock voltage 2Vin can be applied to the second bit line BL2 for a period from the third time point T3' to the fourth time point T4'. The period from the third to the fourth time point T3'-T4' can be shorter than the period from the third to the fifth time point T3'-T5', during which the second programming voltage 2Vpgm is applied to the selected word line Sel_WL. During a period from the fourth to the fifth time point T4'-T5', the programming enable voltage Val can be applied to the second bit line BL2.

[0090] In contrast to the one referring to Fig. In the embodiment described in 9A, if the second programming lock voltage 2Vin is applied to the second bit line BL2 during the same period T3'-T5' as the first programming lock voltage 1Vin, the time during which the threshold voltage of the adjacent programmed cell MCa is increased is extended, which may result in the time required for the programming operation being excessively extended.

[0091] In the case of the reference to Fig. In the embodiment described in 9A, if the second programming lock voltage 2Vin is applied to the second bit line BL2 during the period from the third to the fourth time T3'-T4' and the programming enable voltage Val is applied to the second bit line BL2 during the period from the fourth to the fifth time T4'-T5', the time during which the threshold voltage of the adjacent programmed cell MCa is increased can be adjusted, thereby reducing the time required for the programming operation.

[0092] In the reference to Fig. In the embodiment described in 9A, the time during which the second programming lock voltage 2Vin is applied to the second bit line BL2 is longer than the time during which the programming enable voltage Val is applied to the second bit line BL2. However, the times during which the second programming lock voltage 2Vin and the programming enable voltage Val are applied to the second bit line BL2 can be modified in different embodiments. Various embodiments for adjusting the second programming lock voltage 2Vin can be described as follows.

[0093] With reference to Fig. 9B, the second programming lock voltage 2Vin can be applied to the second bit line BL2 during a period from the third to the fourth time point T3'-T4". The fourth time point T4" is before the fourth time point T4', which is referred to above. Fig. 9A was described. During the period from the fourth to the fifth time point T4"-T5', the programming enable voltage Val can be applied to the second bit line BL2. The period from the third to the fourth time point T3'-T4" can be shorter than the period from the fourth to the fifth time point T4"-T5'. Thus, in the case described above with reference to Fig. In the embodiment described in 9B, the time during which the programming enable voltage Val is applied to the second bit line BL2 is longer than the time during which the second programming lock voltage 2Vin is applied to it. As a result, the time required for the programming operation may be longer compared to that described above with reference to Fig. The embodiment described in 9A can be shortened. Since a method for applying voltages to the remaining lines is used, except for the time during which the second programming lock voltage 2Vin and the programming enable voltage Val are applied to the second bit line BL2, as described above with reference to Fig. Since the embodiment described in 9A is identical, a repeated description is omitted.

[0094] With reference to Fig. In 9C, during a period from the third to the fifth time point T3'-T5', the programming enable voltage Val is first applied to the second bit line BL2, and then the second programming lock voltage 2Vin can be applied to it. For example, the programming enable voltage Val is applied to the second bit line BL2 during the period from the third to the fourth time point T3'-T4', and the second programming lock voltage 2Vin can be applied to the second bit line BL2 during a period from the fourth to the fifth time point T4'-T5'. In this embodiment, the time (T3'-T4') during which the programming enable voltage is applied to the second bit line BL2 is longer than the time during which the second programming lock voltage 2Vin is applied to the second bit line BL2, i.e., the time T3'-T4' is greater than the time T4'-T5'.Therefore, the threshold voltage of the adjacent programmed cell MCa can be increased relatively quickly during the period from the third to the fourth time point T3'-T4', and the threshold voltage of the adjacent programmed cell MCa can be increased relatively slowly during the period from the fourth to the fifth time point T4'-T5'. Since the procedure for applying voltages to the remaining lines, except for the time when the programming enable voltage Val and the second programming lock voltage 2Vin are applied to the second bit line BL2, is the same as described above with reference to... Fig. Since the embodiment described in 9A is identical, a repeated description is omitted.

[0095] With reference to Fig. 9D, the programming enable voltage Val can be applied to the second bit line BL2 during a period from the third to the fourth time point T3'-T4", and the second programming block voltage 2Vin can be applied to the second bit line BL2 during a period from the fourth to the fifth time point T4"-T5'. In this case, the time (T4"-T5') during which the second programming enable voltage 2Vin is applied to the second bit line BL2 is longer than the time (T3'-T4") during which the programming enable voltage Val is applied. Therefore, the threshold voltage of the adjacent programmed cell MCa can be increased relatively quickly during the period from the third to the fourth time point T3'-T4", and the threshold voltage of the adjacent programmed cell MCa can be increased relatively slowly during the period from the fourth to the fifth time point T4"-T5'.Since the procedure for applying voltages to the remaining lines, with the exception of the time during which the programming enable voltage Val and the second programming lock voltage 2Vin are applied to the second bit line BL2, is the same as described above with reference to . Fig. Since the embodiment described in 9A is identical, a repeated description is omitted.

[0096] Fig. Figure 10 shows a flowchart representing a programming operation according to a second embodiment of the present disclosure.

[0097] With reference to Fig. 10, when a programming operation starts on a selected memory block, a programming enable voltage Val can be applied to selected bit lines connected to the selected memory block in S101, and an initial programming lock voltage 1Vin can be applied to unselected bit lines.

[0098] A pass voltage Vpass can be applied to unselected word lines among word lines connected to the selected memory block in S102, and a programming voltage Vpgm can be applied to the selected word line in S103. The selected word line Sel_WL can be a word line connected to a selected page among the pages contained in the selected memory block.

[0099] After the programming voltage Vpgm has been applied to the selected word line Sel_WL for a specific time, a check operation can be performed in S104 on memory cells included in the selected page. The check operation can be performed using a function described above. Fig. The procedures described in section 8 are carried out. As above with reference to Fig. As described in section 8, a pre-check operation and a target check operation can be performed during the check operation. Based on the check operation in S104, each of the memory cells included in the selected page can therefore be classified as an initially programmed cell, an adjacent programmed cell, or a fully programmed cell.

[0100] During the test operation performed in S104, the number of incomplete cells Nf, detected from the result of the target test operation, is compared in S105 with a reference number Nr. The number of incomplete cells can be the sum of the number of initially programmed cells MCi and the number of adjacent programmed cells MCa. For example, the control circuit (e.g., 170 in Fig. 1) Calculate the number of incomplete cells Nf by summing the number of initially programmed cells MCi and the number of adjacent programmed cells MCa based on data acquired during the check operation and stored in the page buffer group (e.g., 140 in Fig. 1) be saved.

[0101] The control circuit 170 can compare the number of incomplete cells Nf with the pre-stored reference number Nr. The reference number Nr can be set differently depending on the storage device. According to one embodiment, instead of the number of incomplete cells Nf, the number of fully programmed cells can be counted, whereby the reference number corresponding to the number of passed cells can differ from the reference number Nr corresponding to the number of incomplete cells. The embodiments described below describe a method for comparing the number of incomplete cells Nf with the reference number Nr.

[0102] If S105 determines that the number of incomplete cells Nf is less than the reference number Nr (Nf <Nr), wird in S106 die Programmierfreigabespannung Val an mit den anfänglich programmierten Zellen MCi verbundenen Bitleitungen angelegt, die Programmierfreigabespannung Val und eine zweite Programmiersperrspannung 2Vin werden nacheinander an mit den benachbarten, programmierten Zellen MCa verbundenen Bitleitungen angelegt, die erste Programmiersperrspannung 1Vin wird an mit vollständig programmierten Zellen verbundenen Bitleitungen angelegt, die Durchgangsspannung wird an nicht ausgewählte Wortleitungen Unsel_ML angelegt, und die Programmierspannung Vpgm wird an eine ausgewählte Wortleitung Sel_WL angelegt. Die an die ausgewählte Wortleitung angelegte Programmierspannung Vpgm kann mit zunehmender Anzahl von Programmschleifen um eine Schrittspannung erhöht werden.

[0103] The programming enable voltage Val and the second programming lock voltage 2Vin, applied to the bit lines connected to the adjacent programmed cells MCa, can be applied sequentially while the programming voltage Vpgm is applied to the selected word line. The order in which the programming enable voltage Val and the second programming lock voltage 2Vin are applied to the bit lines connected to the adjacent programmed cells MCa, and the times at which the voltages are applied, can be changed. Here, the time during which the second programming lock voltage 2Vin is applied to and maintained on the bit lines connected to the adjacent programmed cells MCa is assumed to be a first control time CT1.

[0104] If S105 determines that the number of incomplete cells Nf is greater than the reference number Nr (Nf > Nr), then in S107 the programming enable voltage Val is applied to the bit lines connected to the initially programmed cells MCi. The programming enable voltage Val and a second programming lock voltage 2Vin are applied sequentially in a predefined order to the bit lines connected to the adjacent programmed cells MCa. The first programming lock voltage 1Vin is applied to the bit lines connected to the fully programmed cells MCc. The pass voltage is applied to unselected word lines Unsel_WL, and the programming voltage Vpgm is applied to a selected specific word line. The programming voltage applied to the selected word line Sel_WL can be increased by a step voltage with an increasing number of program loops.

[0105] If S105 determines that the number of incomplete cells Nf equals the reference number Nr, it can be specified that S106 or S107 is performed. In one embodiment, the time during which the second programming lock voltage 2Vin is applied to and maintained on the bit lines connected to the adjacent programmed cells MCa is a second control time CT2, which is shorter than the first control time in S107.

[0106] After step S106 or S107 has been performed, the test operation on the selected memory cells in step S104 can be performed again. Steps S104 to S107 can be repeated until the test operation performed in step S104 is successful.

[0107] Fig. Figures 11A to 11C and 12A to 12C show diagrams illustrating programming operations according to a second embodiment of the present disclosure.

[0108] Fig. 11A and Fig. 12A represent different embodiments of S106 from Fig. 10 correspond to Fig. 11B and Fig. 12B represent different embodiments of S107 from Fig. 10 correspond, and Fig. 11C and Fig. 12C represent further embodiments that S107 from Fig. 10 corresponds. That is, if S106 is from Fig. 10 is set up in such a way that it is like in the in Fig. If the embodiment shown in 11A is carried out, S107 can be extracted Fig. 10 are carried out, as described in the Fig. The embodiment shown in 11B is illustrated. In other embodiments, if S106 is made of Fig. 10 is set up in such a way that, as in the case of the in Fig. The embodiment shown in 12A is carried out, S107 from Fig. 10 are carried out, as in the case of the in Fig. The embodiment shown in 12B is illustrated. Fig. 11C and Fig. 12C represent embodiments in which the voltages to be applied to bit lines are adapted compared to step S106.

[0109] With reference to the Fig. 6, Fig. 10 and Fig. 11A In one embodiment, memory cells corresponding to the first to third bit lines BL1 to BL3 are selected memory cells, and a memory cell corresponding to the fourth bit line BL4 is a non-selected memory cell. Furthermore, in another embodiment, memory cells (e.g., MCi, MCa, and MCc) corresponding to the first to third bit lines BL1 to BL3 are selected memory cells, and a memory cell Unsel_MC corresponding to the fourth bit line BL4 is a non-selected memory cell (see, for example, Fig. 6).

[0110] At a first time point T1', when a program loop for a selected page begins, an initial programming voltage of 1Vpgm can be applied to the selected word line Sel_WL, a programming enable voltage Val can be applied to the first to third bit lines BL1 to BL3, and an initial programming block voltage of 1Vin can be applied to the fourth bit line BL4. A pass voltage can be applied to unselected word lines, a ground voltage can be applied to a source line, and a turn-on voltage can be applied to drain select lines as well as source select lines. Since the memory cells connected to the first to third bit lines BL1 to BL3 are the selected memory cells, the threshold voltages of the selected memory cells can be increased due to the initial programming voltage of 1Vpgm.

[0111] After the first programming voltage 1Vpgm has been applied during a period from the first to the second time T1' - T2', a test operation can be performed on memory cells included in the selected page to classify the types of memory cells coupled to the first to third bit lines BL1 to BL3.

[0112] The testing operation can be performed using one of the methods described above. Fig. The procedures described in section 8 are carried out. The result of the testing operation is as described above with reference to section 8. Fig. 6 described, assuming that a memory cell connected to the first bit line BL1 is an initially programmed cell MCi, a memory cell connected to the second bit line BL2 is an adjacent programmed cell MCa, and a memory cell connected to the third bit line BL3 is a fully programmed cell MCc.

[0113] Depending on the result of the check operation, at a third time point T3', when the next program loop begins, the programming enable voltage Val can be applied to the first bit line BL1, the second programming lock voltage 2Vin can be applied to the second bit line BL2, and the first programming lock voltage 1Vin can be applied to the third bit line BL3 and the fourth bit line BL4. The programming enable voltage Val, the second programming lock voltage 2Vin, and the first programming lock voltage 1Vin can be applied during a time when a second programming voltage 2Vpgm is applied to the selected word line Sel_WL.

[0114] Since the memory cell connected to the first bit line BL1 is the initially programmed cell MCi, the programming enable voltage Val can be applied to the first bit line BL1 to quickly raise the threshold voltage of the initially programmed cell MCi. The programming enable voltage Val can be the lowest voltage among those set to be applied to the bit lines during the programming operation.

[0115] Since the memory cell connected to the second bit line BL2 is the adjacent programmed cell MCa, the second programming lock voltage 2Vin can be applied to the second bit line BL2 to increase the threshold voltage of the adjacent programmed cell MCa more slowly than that of the initially programmed cell MCi. Thus, the threshold voltage of the initially programmed cell MCi can be increased at a first rate, and the threshold voltage of the adjacent programmed cell MCa can be increased at a second rate that is lower than the first rate. The second programming lock voltage 2Vin can be set to a voltage that is higher than the programming enable voltage Val and lower than or equal to the first programming lock voltage 1Vin.

[0116] Since the memory cell connected to the third bit line BL3 is the fully programmed cell MCc, and the memory cell connected to the fourth bit line BL4 is the unselected memory cell Unsel_MC, the first programming lock voltage 1Vin can be applied to the third and fourth bit lines BL3 and BL4, respectively, to prevent the threshold voltages of the fully programmed cell MCc and the unselected memory cell Unsel_MC from increasing further. The first programming lock voltage 1Vin can be the highest voltage among those set to be applied to the bit lines during the programming operation.

[0117] A second programming voltage of 2Vpgm can be applied to the selected word line Sel_WL. This second programming voltage can be set to a voltage one step higher than the first programming voltage of 1Vpgm. The second programming voltage can be configured to be applied to the selected word line Sel_WL for a period from the third time point T3' to the fifth time point T5'.

[0118] The first programming lock voltage 1Vin can also be applied to the third and fourth bit lines BL3 and BL4 during the period from the third time T3' to the fifth time T5', e.g. during the same period in which the second programming voltage 2Vpgm is applied.

[0119] The second programming lock voltage, 2Vin, can be applied to the second bit line, BL2, for a time shorter than the time during which the second programming voltage, 2Vpgm, or the first programming lock voltage, 1Vin, is applied. (See above, referring to...) Fig. In operation S106, as described in section 10, the second programming lock voltage 2Vin can be applied to the second bit line BL2 during a first control time CT1. This means that if the number of incomplete cells Nf detected in the check operation is less than the reference number Nr, the time during which the second programming lock voltage 2Vin is applied to the second bit line BL2 can be defined as the first control time CT1. The number of incomplete cells can be the sum of the number of initially programmed cells MCi and the number of adjacent programmed cells MCa coupled to the selected word line Sel_WL. Therefore, the fact that the number of incomplete cells Nf is less than the reference number Nr can indicate that the number of fully programmed cells is greater.In other words, the fact that the number of incomplete cells Nf is less than the reference number Nr can mean that the number of cells whose threshold voltages are to be increased is less than the number of fully programmed cells. The control circuit (e.g., 170 in . Fig. 1) can the side buffer group (e.g. 140 in Fig. 1) such that the second programming lock voltage 2Vin is applied to the second bit line BL2 for a time longer than the programming enable voltage Val applied to the second bit line BL2.

[0120] The first control time CT1 can be the period from the third time point T3' to the fourth time point T4'. Since the fourth time point T4' is earlier than the fifth time point T5', the first control time CT1 can be shorter than the period from the third time point T3' to the fifth time point T5'. The first control time CT1 can be changed between the third time point T3' and the fifth time point T5'. During a period from the fourth to the fifth time point T4'-T5', the programming enable voltage Val can be applied to the second bit line BL2 to raise the threshold voltage of the adjacent, programmed cell MCa with the slower rate.

[0121] With reference to the Fig. 6, Fig. 10 and Fig. In one embodiment, 11B memory cells corresponding to a first to third bit line BL1 to BL3 are selected memory cells, and a memory cell corresponding to a fourth bit line BL4 is a non-selected memory cell.

[0122] At a first time point T1', when a program loop for a selected page begins, an initial programming voltage of 1Vpgm can be applied to the selected word line Sel_WL, a programming enable voltage Val can be applied to the first to third bit lines BL1 to BL3, and an initial programming block voltage of 1Vin can be applied to the fourth bit line BL4. A pass voltage can be applied to unselected word lines, a ground voltage can be applied to a source line, and a turn-on voltage can be applied to a drain select line as well as a source select line. Since the memory cells connected to the first to third bit lines BL1 to BL3 are the selected memory cells, the threshold voltages of the selected memory cells can be increased due to the initial programming voltage of 1Vpgm.

[0123] After the first programming voltage 1Vpgm has been applied for a period from the first to the second time point T1' - T2', a test operation can be performed on the memory cells included in the selected page. The test operation can be performed using a method described above. Fig. The procedures described in section 8 are performed to classify the memory cells coupled with the selected word line Sel_WL as initially programmed cells MCi, adjacent programmed cells MCa, and fully programmed cells MCc.

[0124] As a result of the testing operation, as above with reference to Fig. As described in section 6, a memory cell connected to the first bit line BL1 is an initially programmed cell MCi, a memory cell connected to the second bit line BL2 is an adjacent programmed cell MCa, and a memory cell connected to the third bit line BL3 is a fully programmed cell MCc.

[0125] Depending on the result of the test operation, at a third time T3', when the next program loop begins, the programming enable voltage Val can be applied to the first bit line BL1, the second programming block voltage 2Vin can be applied to the second bit line BL2, and the first programming block voltage 1Vin can be applied to the third bit line BL3 and the fourth bit line BL4.

[0126] Since the memory cell connected to the first bit line BL1 is an initially programmed cell MCi, the programming enable voltage Val can be applied to the first bit line BL1 to quickly raise the threshold voltage of the initially programmed cell MCi. The programming enable voltage Val can be the lowest voltage among those set to be applied to the bit lines during the programming operation.

[0127] Since the memory cell connected to the second bit line BL2 is an adjacent programmed cell MCa, the second programming lock voltage 2Vin can be applied to the second bit line BL2 to raise the threshold voltage of the adjacent programmed cell MCa more slowly than that of the initially programmed cell MCi. The second programming lock voltage 2Vin can be set to a voltage that is higher than the programming enable voltage Val and lower than or equal to the first programming lock voltage 1Vin.

[0128] Since the memory cell connected to the third bit line BL3 is a fully programmed cell MCc, and the memory cell connected to the fourth bit line BL4 is an unselected memory cell Unsel_MC, the first programming lock voltage 1Vin can be applied to the third and fourth bit lines BL3 and BL4 to prevent the threshold voltages of the fully programmed cell MCc and the unselected memory cell Unsel_MC from increasing further. The first programming lock voltage 1Vin can be the highest voltage among those set to be applied to the bit lines during the programming operation.

[0129] A second programming voltage of 2Vpgm can be applied to the selected word line Sel_WL. This second programming voltage can be set to a voltage one step higher than the first programming voltage of 1Vpgm. The second programming voltage can be configured to be applied to the selected word line Sel_WL for a period from the third time point T3' to the fifth time point T5'.

[0130] The first programming lock voltage 1Vin can also be applied to the third and fourth bit lines BL3 and BL4 during the period from the third time T3' to the fifth time T5'.

[0131] The second programming lock voltage, 2Vin, can be applied to the second bit line, BL2, for a time shorter than the time during which the second programming voltage, 2Vpgm, or the first programming lock voltage, 1Vin, is applied. (See above, referring to...) Fig. The operation described in S107 can set the second programming lock voltage 2Vin during a second control time CT2, which is shorter than the first control time CT1. Fig. 11A, applied to the second bit line BL2. That is, if the number of incomplete cells Nf detected in the test operation is greater than the reference number Nr, the time during which the second programming lock voltage 2Vin is applied to the second bit line BL2 can be defined as the second control time CT2.

[0132] This means that the fact that the number of incomplete cells Nf is greater than the reference number Nr can mean that the number of passed cells is smaller; that is, the fact that the number of incomplete cells Nf is greater than the reference number Nr can mean that the number of cells whose threshold voltages are to be increased is larger. Therefore, the control circuit (e.g., 170 in Fig. 1) the side buffer group (e.g. 140 in Fig. 1) Control such that the second programming lock voltage 2Vin is applied to the second bit line BL2 for a shorter time than the programming enable voltage Val. Because the programming enable voltage Val is applied to the second bit line BL2 for a shorter time than the time it is applied to the first bit line BL1, the rate at which the threshold voltage of the adjacent programmed cell MCa rises can be slower than the rate at which the threshold voltage of the initially programmed cell MCi rises.

[0133] The second control time CT2 can be the period from the third time point T3' to the fourth time point T4". Since the fourth time point T4" is earlier than the fifth time point T5', the second control time CT2 can be shorter than the period from the third time point T3' to the fifth time point T5'. The second control time CT2 can be changed between the third time point T3' and the fifth time point T5'. During a period from the fourth to the fifth time point T4"-T5', the programming enable voltage Val can be applied to the second bit line BL2.

[0134] With reference to the Fig. 6, Fig. 10 and Fig. 11C, as above with reference to Fig. As described in Section 11B, if the number of incomplete cells Nf is greater than a reference number Nr, the time during which the second programming lock voltage is applied to the second bit line BL2 can be shortened to the period from the third time T3' to the fourth time T4", which corresponds to the second control time CT2. In this embodiment, the level of the second programming lock voltage 2Vin applied to the second bit line BL2 can be adjusted to a lower level 2Vin'. Thus, in this embodiment, both the time and the level of the second programming lock voltage applied to the second bit line BL2 can be adjusted simultaneously. For example, the second programming lock voltage 2Vin', which is applied with reference to Fig. 11C describes a level that is lower than the second programming lock voltage 2Vin, which is described with reference to Fig. 11B is described, and is greater than 0 V (and the programming enable voltage Val), and can be applied to the second bit line BL2 between the third time T3' and the fourth time T4".

[0135] With reference to the Fig. 6, Fig. 10 and Fig. In one embodiment, memory cells corresponding to the first to third bit lines BL1 to BL3 are selected, and a memory cell corresponding to the fourth bit line BL4 is unselected. Furthermore, in another embodiment, memory cells corresponding to the first to third bit lines BL1 to BL3 are selected, and a memory cell corresponding to the fourth bit line BL4 is unselected. In this embodiment, the programming enable voltage Val is applied to the second bit line BL2 before the second programming lock voltage 2Vin is applied to the second bit line BL2.

[0136] At a first point in time T1', when a program loop for a selected page begins, a first programming voltage 1Vpgm can be applied to the selected word line Sel_WL, a programming enable voltage Val can be applied to the first to third bit lines BL1 to BL3, and a first programming block voltage 1Vin can be applied to the fourth bit line BL4. A pass voltage can be applied to unselected word lines, a ground voltage can be applied to a source line, and a turn-on voltage can be applied to a drain and a source selection line.

[0137] Since the memory cells connected to the first to third bit lines BL1 to BL3 are the selected memory cells, the threshold voltages of the selected memory cells can be increased due to the first programming voltage 1Vpgm.

[0138] After the first programming voltage 1Vpgm has been applied for a period from the first to the second time point T1' - T2', a test operation can be performed on the memory cells included in the selected page. The test operation can be performed using a method described above. Fig. The procedure described in section 8 is performed to classify the memory cells coupled to the selected word line Sel_WL as initially programmed cells MCi, adjacent programmed cells MCa, and fully programmed cells MCc. That is, as a result of the check operation, as described above with reference to Fig. 6 described, assuming that a memory cell connected to the first bit line BL1 is an initially programmed cell MCi, a memory cell connected to the second bit line BL2 is an adjacent programmed cell MCa, and a memory cell connected to the third bit line BL3 is a fully programmed cell MCc.

[0139] Depending on the result of the test operation, at a third time T3', when the next program loop begins, the programming enable voltage Val can be applied to the first bit line BL1, the programming enable voltage Val can be applied to the second bit line BL2, and the first programming block voltage 1Vin can be applied to the third bit line BL3 and the fourth bit line BL4.

[0140] The memory cell connected to the first bit line BL1 is an initially programmed cell MCi, and thus the programming enable voltage Val can be applied to the first bit line BL1 to rapidly increase the threshold voltage of the initially programmed cell MCi during a period from the third to the fifth time point T3'-T5'. The programming enable voltage Val can be the lowest voltage among those set to be applied to the bit lines during the programming operation.

[0141] Since the memory cell connected to the second bit line BL2 is an adjacent programmed cell MCa, in this embodiment the programming enable voltage Val is first applied to the second bit line BL2, and then the second programming lock voltage 2Vin is applied to it to raise the threshold voltage of the adjacent programmed cell MCa more slowly than that of the initially programmed cell MCi. The threshold voltage of the adjacent programmed cell MCa rises more slowly than the threshold voltage of the initially programmed cell MCi because the time the programming enable voltage Val is applied to the second bit line BL2 is shorter than the time the programming enable voltage Val is applied to the first bit line BL1. The second programming lock voltage 2Vin can be set to a voltage greater than the programming enable voltage Val and less than or equal to the first programming lock voltage 1Vin.

[0142] Since the memory cell connected to the third bit line BL3 is the fully programmed cell MCc, and the memory cell connected to the fourth bit line BL4 is the unselected memory cell Unsel_MC, the first programming lock voltage 1Vin can be applied to the third and fourth bit lines BL3 and BL4, respectively, to prevent the threshold voltages of the fully programmed cell MCc and the unselected memory cell Unsel_MC from increasing further. The first programming lock voltage 1Vin can be the highest voltage among those set to be applied to the bit lines during the programming operation.

[0143] A second programming voltage of 2Vpgm can be applied to the selected word line Sel_WL. This second programming voltage can be set to a voltage one step higher than the first programming voltage of 1Vpgm. The second programming voltage can be configured to be applied to the selected word line Sel_WL for a period from the third time point T3' to the fifth time point T5'.

[0144] The first programming lock voltage 1Vin can also be applied to the third and fourth bit lines BL3 and BL4 during the period from the third time T3' to the fifth time T5'.

[0145] The second programming lock voltage, 2Vin, can be applied to the second bit line, BL2, for a time shorter than the time during which the second programming voltage, 2Vpgm, or the first programming lock voltage, 1Vin, is applied. (See above, referring to...) Fig. In the operation described in section 10, the second programming lock voltage 2Vin can be applied to the second bit line BL2 during a first control time CT1 in S106. That is, if the number of incomplete cells Nf detected in the test operation is less than the reference number Nr, the time during which the second programming lock voltage 2Vin is applied to the second bit line BL2 can be defined as the first control time CT1. In other words, the fact that the number of incomplete cells Nf is less than the reference number Nr can mean that the number of fully programmed cells is greater. Conversely, the fact that the number of incomplete cells Nf is less than the reference number Nr can mean that the number of cells whose threshold voltages are to be increased is smaller. Therefore, the control circuit (e.g., section 170 in S106) can be configured to use a different programming lock voltage. Fig. 1) the side buffer group (e.g. 140 in Fig. 1) such that the second programming lock voltage 2Vin is applied to the second bit line BL2 for a time longer than the programming enable voltage Val.

[0146] The first timing CT1 can be a period from the fourth time point T4" to the fifth time point T5'. Since the fourth time point T4" is earlier than the fifth time point T5', the first timing CT1 can be shorter than the period from the third time point T3' to the fifth time point T5'. The first timing CT1 can be changed between the third time point T3' and the fifth time point T5'.

[0147] With reference to the Fig. 6, Fig. 10 and Fig. In section 12B, it is assumed that memory cells corresponding to the first to third bit lines BL1 to BL3 are selected memory cells, and that a memory cell corresponding to the fourth bit line BL4 is an unselected memory cell. It is also assumed that memory cells corresponding to the first to third bit lines BL1 to BL3 are selected memory cells and that a memory cell corresponding to the fourth bit line BL4 is an unselected memory cell.

[0148] At a first point in time T1', when a program loop for a selected page begins, a first programming voltage 1Vpgm can be applied to the selected word line Sel_WL, a programming enable voltage Val can be applied to the first to third bit lines BL1 to BL3, and a first programming block voltage 1Vin can be applied to the fourth bit line BL4. A pass voltage can be applied to unselected word lines, a ground voltage can be applied to a source line, and a turn-on voltage can be applied to a drain and a source selection line.

[0149] Since the memory cells connected to the first to third bit lines BL1 to BL3 are the selected memory cells, the threshold voltages of the selected memory cells can be increased due to the first programming voltage 1Vpgm.

[0150] After the first programming voltage 1Vpgm has been applied for a period from the first to the second time point T1' - T2', a test operation can be performed on the memory cells included in the selected page. The test operation can be performed using a method described above. Fig. The procedures described in section 8 are performed to classify the selected memory cells as initially programmed cells MCi, adjacent programmed cells MCa, and fully programmed cells MCc. As a result of the verification operation, as described above with reference to Fig. 6 described, a memory cell connected to the first bit line BL1 is an initially programmed cell MCi, a memory cell connected to the second bit line BL2 is an adjacent programmed cell MCa, and a memory cell connected to the third bit line BL3 is a fully programmed cell MCc.

[0151] Depending on the result of the test operation, at a third time T3', when the next program loop begins, the programming enable voltage Val can be applied to the first bit line BL1, the programming enable voltage Val can be applied to the second bit line BL2, and the first programming block voltage 1Vin can be applied to the third bit line BL3 and the fourth bit line BL4.

[0152] Since the memory cell connected to the first bit line BL1 is an initially programmed cell MCi, the programming enable voltage Val can be applied to the first bit line BL1 to quickly raise the threshold voltage of the initially programmed cell MCi. The programming enable voltage Val can be the lowest voltage among those set to be applied to the bit lines during the programming operation.

[0153] Since the memory cell connected to the second bit line BL2 is the adjacent programmed cell MCa, the programming enable voltage Val is first applied to the second bit line BL2, and then the second programming lock voltage 2Vin is applied to it to raise the threshold voltage of the adjacent programmed cell MCa more slowly than that of the initially programmed cell MCi. The slower rise in the threshold voltage results from the fact that the programming enable voltage Val is applied to the second bit line BL2 for a shorter time than the time it is applied to the first bit line BL1. The second programming lock voltage 2Vin can be set to a voltage greater than the programming enable voltage Val and less than or equal to the first programming lock voltage 1Vin.

[0154] Since the memory cell connected to the third bit line BL3 is the fully programmed cell MCc, and the memory cell connected to the fourth bit line BL4 is the unselected memory cell Unsel_MC, the first programming lock voltage 1Vin can be applied to the third and fourth bit lines BL3 and BL4, respectively, to prevent the threshold voltages of the fully programmed cell MCc and the unselected memory cell Unsel_MC from increasing further. The first programming lock voltage 1Vin can be the highest voltage among those set to be applied to the bit lines during the programming operation.

[0155] A second programming voltage of 2Vpgm can be applied to the selected word line Sel_WL. This second programming voltage can be set to a voltage one step higher than the first programming voltage of 1Vpgm. The second programming voltage can be configured to be applied to the selected word line Sel_WL for a period from the third time point T3' to the fifth time point T5'.

[0156] The first programming lock voltage 1Vin can also be applied to the third and fourth bit lines BL3 and BL4 during the period from the third time T3' to the fifth time T5'.

[0157] The second programming lock voltage, 2Vin, can be applied to the second bit line, BL2, for a time shorter than the time during which the second programming voltage, 2Vpgm, or the first programming lock voltage, 1Vin, is applied. (See above, referring to...) Fig. The operation described in S107 can set the second programming lock voltage 2Vin during a second control time CT2, which is shorter than the first control time CT1. Fig. 12A, applied to the second bit line BL2. That is, if the number of incomplete cells Nf detected in the test operation is greater than the reference number Nr, the time during which the second programming lock voltage 2Vin is applied to the second bit line BL2 can be defined as the second control time CT2. That is, the fact that the number of incomplete cells Nf is greater than the reference number Nr can mean that the number of fully programmed cells is smaller; that is, the fact that the number of incomplete cells Nf is greater than the reference number Nr can mean that the number of cells whose threshold voltages are to be increased is greater. Therefore, the control circuit (e.g., 170 in Fig. 1) the side buffer group (e.g. 140 in Fig. 1) such that the second programming lock voltage 2Vin is applied to the second bit line BL2 for a time that is shorter than that of the programming enable voltage Val.

[0158] The second timing interval CT2 can be a period from the fourth time point T4' to the fifth time point T5'. Since the fourth time point T4' is earlier than the fifth time point T5', the second timing interval CT2 can be shorter than the period from the third time point T3' to the fifth time point T5'. The second timing interval CT2 can be changed between the third time point T3' and the fifth time point T5'.

[0159] With reference to the Fig. 6, Fig. 10 and Fig. 12C, as above with reference to Fig. As described in Section 12B, if the number of incomplete cells Nf is greater than a reference number Nr, the time during which the second programming lock voltage is applied to the second bit line BL2 can be shortened to the period from the fourth time point T4' to the fourth time point T5', which corresponds to the second control time CT2. In this embodiment, the level of the second programming lock voltage 2Vin applied to the second bit line BL2 can be adjusted to a lower level 2Vin'. Thus, in this embodiment, both the time and the level of the second programming lock voltage applied to the second bit line BL2 can be adjusted simultaneously. For example, the second programming lock voltage 2Vin', which is applied with reference to Section 12B, can be adjusted to a lower level 2Vin'. Fig. 12C describes a level that is lower than the second programming lock voltage 2Vin, which is described with reference to Fig. 12B is described, and is greater than 0 V (and the programming enable voltage Val), and can be applied to the second bit line BL2 between the fourth time T4' and the fourth time T5'.

[0160] Fig. Figures 13A to 13D show diagrams representing the threshold voltages of memory cells that are successively increased during a programming operation according to an embodiment of the present disclosure.

[0161] With reference to Fig. 13A The programming operation is performed on memory cells in an erase state, so the threshold voltages of memory cells in an initial phase of the programming operation may be lower than a pre-target voltage Vp. During a above reference to Fig. In the five described check operations, a preliminary check operation and a target check operation can be performed. Whether the programming operation performed on a selected page passes or fails can be determined depending on the result of the target check operation. As described in Fig. As shown in Figure 13A, the threshold voltages of the memory cells in the initial phase of the programming operation may be lower than a target voltage Vt, so the result of the test operation may be negative.

[0162] Since the check is negative, a voltage can be set to be applied to bit lines connected to memory cells selected for the next program loop. As in Fig. As shown in Figure 13A, if the threshold voltages of the selected memory cells are less than the pre-target voltage Vp, the programming enable voltage can be applied to the bit lines connected to the selected memory cells.

[0163] With reference to Fig. 13B The selected page can include, when the threshold voltages of memory cells are increased by the programming voltage, memory cells with threshold voltages greater than the target voltage Vt, memory cells with threshold voltages between the pre-target voltage Vp and the target voltage Vt, and memory cells with threshold voltages less than the pre-target voltage Vp. The reason that memory cells programmed with the same programming voltage have different threshold voltages is that the electrical properties of the memory cells differ from one another. That is, since the memory cells can be programmed at different speeds, the programmed memory cells cannot have the same threshold voltage. Therefore, the threshold voltages of memory cells corresponding to the same program state can be distributed within a range set to the same program state. As in Fig. As shown in Figure 13B, the number of incomplete cells Nf can be greater than the reference number Nr if the number of memory cells that failed the check operation is greater than the number of memory cells that passed the check operation.

[0164] In this case, in the next program loop, the programming enable voltage can be applied to bit lines of initially programmed cells that have threshold voltages below the pre-target voltage Vp, the second programming lock voltage and the programming enable voltage can be applied at different times to bit lines of adjacent programmed cells that have threshold voltages between the pre-target voltage Vp and the target voltage Vt, and the first programming lock voltage can be applied to bit lines of fully programmed cells that have threshold voltages higher than the target voltage Vt.

[0165] As in Fig. As shown in 13B, if the number of incomplete cells Nf is greater than the reference number Nr, the second programming lock voltage can be applied during a second time (e.g., CT2 in Fig. 11B or Fig. 12B) are applied to the bit lines.

[0166] With reference to Fig. 13C, if the threshold voltages of the memory cells are further increased due to the programming voltage, the number of memory cells that have passed the test operation may become greater than the number of memory cells that have failed the test operation, and thus the number of incomplete cells Nf may be less than the reference number Nr.

[0167] In this case, in the next program loop, the programming enable voltage Val can be applied to bit lines of initially programmed cells MCi with threshold voltages below the pre-target voltage Vp, the second programming lock voltage 2Vin and the programming enable voltage Val can be applied at different times to bit lines of adjacent programmed cells with threshold voltages between the pre-target voltage Vp and the target voltage Vt, and the first programming lock voltage 1Vin can be applied to bit lines of fully programmed cells MCc with threshold voltages greater than the target voltage Vt.

[0168] As in Fig. As shown in 13C, if the number of incomplete cells Nf is less than the reference number Nr, the second programming lock voltage 2Vin can be applied during a first period (e.g., CT1 in Fig. 11A or Fig. 12A) are applied to the bit lines.

[0169] With reference to Fig. 13D can, if the threshold voltages of selected memory cells included in the selected page become greater than the target voltage Vt, the test operation is passed and the programming operation on the selected page is terminated.

[0170] Fig. Figure 14 shows a diagram representing a memory card system 3000 to which a storage device 100 according to an embodiment of the present disclosure is applied.

[0171] With reference to Fig. 14 The memory card system 3000 comprises a controller 3100, a storage device 3200 and a connector 3300.

[0172] The controller 3100 is connected to the storage device 3200. The controller 3100 can access the storage device 3200. For example, the controller 3100 can control a programming operation, a read operation, or an erase operation of the storage device 3200, or control background operations of the storage device 3200. The controller 3100 can provide an interface between the storage device 3200 and a host. The controller 3100 can execute firmware to control the storage device 3200. For example, the controller 3100 can include components such as random access memory (RAM), a processor, a host interface, a memory interface, and error correction circuitry.

[0173] The 3100 controller can communicate with an external device via the 3300 connector. The 3100 controller can communicate with an external device (e.g., a host) based on a specific communication standard. In one embodiment, the 3100 controller can communicate with the external device using at least one of several communication standards, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnection (PCI), PCI Express (PCIe or PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and Nonvolatile Memory Express (NVMe).In one embodiment, the connector 3300 can be defined by at least one of the different communication standards described above.

[0174] The 3200 storage device can include memory cells and can be used in the same way as the one in Fig. The storage device 100 shown in Figure 1 is set up and operating. For example, the storage device can comprise 3200 memory cells, a peripheral circuit that programs the memory cells, and a control circuit that controls the peripheral circuit in response to a command. During a programming operation, the peripheral circuit can perform a test operation on the selected memory cells using a target voltage and a pre-target voltage that is lower than the target voltage. The control circuit can control the peripheral circuit such that it adjusts the voltages applied to the bit lines connected to the memory cells depending on the result of the test operation, e.g., based on a classification of the memory cells as initially programmed cells MCi, adjacent programmed cells MCa, and fully programmed cells MCc.The control circuit can control the peripheral circuitry in such a way that it adjusts the times during which corresponding voltages (e.g. Val, 2Vin and 1Vin) are applied to the bit lines, depending on the number of incomplete cells (e.g. number of initially programmed cells MCi and / or number of adjacent programmed cells MCa that were detected during the test operation, as described above).

[0175] The 3100 controller and the 3200 storage device can be integrated into a single semiconductor device to form a memory card. For example, the 3100 controller and the 3200 storage device can be integrated into a single semiconductor device and then form a memory card such as a PC card (Personal Computer Memory Card International Association: PCMCIA), a CompactFlash card (CF), a SmartMedia card (SM or SMC), a Memory Stick, a multimedia card (MMC, RS-MMC, MMCmicro or eMMC), a Secure Digital card (SD, miniSD, microSD or SDHC), a Universal Flash Storage (UFS) or the like.

[0176] Fig. Figure 15 shows a diagram representing a solid-state drive (SSD) system 4000 to which the storage device 100 is applied according to an embodiment of the present disclosure.

[0177] With reference to Fig. The SSD system 4000 comprises a host 4100 and an SSD 4200. The SSD 4200 can exchange signals with the host 4100 via a signal connector 4001 and be powered via a power connector 4002. The SSD 4200 can include a controller 4210, a variety of storage devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0178] The controller 4210 can control the plurality of storage devices 4221 to 422n in response to signals received from the host 4100. In one embodiment, the signals can be based on the interfaces of the host 4100 and the SSD 4200. For example, the signals can be defined by at least one of the following interfaces: Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnection (PCI), PCI-Express (PCIe or PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Memory (UFS), WiFi, Bluetooth, and Nonvolatile Memory Express (NVMe).

[0179] Each of the multiple storage devices 4221 to 422n can comprise cells in which data can be stored. Each of the multiple storage devices 4221 to 422n can be used in the same way as those in Fig.A storage device 100 as depicted in Figure 1 may be set up. For example, each of the plurality of storage devices may comprise 4221 to 422n memory cells, a peripheral circuit that programs the memory cells, and a control circuit that controls the peripheral circuit in response to a command. During a programming operation, the peripheral circuit may perform a test operation on the selected memory cells using a target voltage and a pre-target voltage that is lower than the target voltage. The control circuit may control the peripheral circuit such that it adjusts the voltages to be applied to the bit lines connected to the memory cells depending on the result of the test operation. The control circuit may control the peripheral circuit such that it determines the times during which the corresponding voltages (e.g.,Val, 2Vin, 1Vin) are applied to the bit lines, depending on the number of incomplete cells (e.g., the number of initially programmed cells MCi and / or the number of adjacent programmed cells MCa) detected during the test operation, as previously described.

[0180] The auxiliary power supply 4230 can be connected to the host 4100 via the power connector 4002. The auxiliary power supply 4230 can be powered and charged by the host 4100. The auxiliary power supply 4230 can supply voltage to the SSD 4200 if the power supply from the host 4100 is not functioning reliably. In one embodiment, the auxiliary power supply 4230 is located inside the SSD 4200 or outside of the SSD 4200. For example, the auxiliary power supply 4230 can be located on a mainboard and supply auxiliary power to the SSD 4200.

[0181] The 4240 buffer memory acts as a buffer for the 4200 SSD. For example, the 4240 buffer memory can temporarily store data received from the 4100 host, or data received from the multitude of storage devices 4221 to 422n, or it can temporarily store metadata (e.g., mapping tables) of the storage devices 4221 to 422n. The 4240 buffer memory can include volatile memory such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM, or non-volatile memory such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0182] According to the present disclosure, the distributions of the threshold voltages of memory cells during a programming operation can be improved, and thus the reliability of a storage device can be increased.

[0183] Although the embodiments of the present disclosure have been presented and described with reference to specific embodiments and drawings, the disclosed embodiments are not to be understood as limiting. Furthermore, it is pointed out that the embodiments can be achieved in various ways by substitution, alteration, and modification, as will be clear to a person skilled in the art in view of the present disclosure, without departing from the fundamental idea and / or scope of the present disclosure and the following claims. Moreover, the embodiments can be combined to form additional embodiments.

Images