POWER SHEMULATOR PACKAGES AND ASSOCIATED METHODS

Abstract

Implementations of a substrate may include: a semiconductor material; a rewiring layer coupled to a first largest planar surface of the semiconductor material; and a hollow via extending from a second largest planar surface of the semiconductor material completely through one thickness of the semiconductor material, with the hollow via being directly coupled to the rewiring layer.

Description

BACKGROUND 1. Technical field

[0001] Aspects of this document relate generally to semiconductor packages. More specific implementations include power semiconductor packages. 2. State of the art

[0002] Semiconductor packages have been developed to provide mechanical support and protection for one or more semiconductor dies enclosed within the package. Other semiconductor packages prevent damage to the semiconductor die from electrostatic discharge. Still other semiconductor packages help prevent damage to an enclosed semiconductor die from shock, vibration, or moisture. SUMMARY

[0003] Implementations of a substrate may include: a semiconductor material; a rewiring layer coupled to a first largest planar surface of the semiconductor material; and a hollow via extending from a second largest planar surface of the semiconductor material completely through one thickness of the semiconductor material, with the hollow via being directly coupled to the rewiring layer.

[0004] Implementations of a substrate can include one, all, or any of the following: The rewiring layer can include at least one thick copper layer. The rewiring layer can include at least one dielectric layer and at least one layer of a solderable metal or a sinterable metal.

[0005] The semiconductor material can be thinned starting from an initial thickness.

[0006] The semiconductor material can be silicon carbide.

[0007] The semiconductor material can be silicon.

[0008] The substrate can enclose an oxide layer between the rewiring layer and the semiconductor material.

[0009] The substrate can enclose an oxide layer on the second largest planar surface of the semiconductor material.

[0010] The substrate can enclose a back metal layer coupled to the second largest planar surface of the semiconductor material.

[0011] Implementations of a method for embedding a semiconductor die may include: providing a silicon substrate including a first oxide layer on it; forming at least one opening in the first oxide layer; etching a cavity into the silicon substrate at the at least one opening in the first oxide layer; forming a second oxide layer in the cavity; forming a thick copper layer on top of the first oxide layer and on top of the second oxide layer; and structuring the thick copper layer.The process may include: sintering at least one semiconductor die onto the thick copper layer in the cavity; filling a gap between the at least one semiconductor die and the thick copper layer in the cavity with a polyimide; forming a layer of photosensitive polymer over the at least one semiconductor die, the thick copper layer, and the first oxide layer; and structuring the photosensitive polymer layer to form a plurality of openings within it. The process may include: forming a first copper layer within the plurality of openings; and forming a second copper layer over the photosensitive polymer layer and the first copper layer.

[0012] Implementations of a method for embedding a semiconductor die may include one, all, or any of the following: The formation of the first copper layer and the formation of the second copper layer can occur simultaneously.

[0013] The process can include the formation of a nucleation layer on the second oxide layer before the formation of the thick copper layer.

[0014] The process can include baking the polyimide.

[0015] The process can include coupling a rewiring layer or another semiconductor die to the second copper layer.

[0016] Implementations of a method for embedding a semiconductor die may include: providing a silicon substrate including an oxide layer on it; forming a thick copper layer on the oxide layer; structuring the thick copper layer; depositing a first photosensitive polyimide over the thick copper layer; and structuring the first polyimide to form an opening in it. The method may include one of sintering or soldering a semiconductor die in the opening; forming a first copper layer on the first photosensitive polyimide and the semiconductor die; and depositing a second photosensitive polyimide over the first copper layer.The process may include structuring the second photosensitive polyimide; forming a second copper layer on the second photosensitive polyimide; and coupling a rewiring layer or another semiconductor die to the second copper layer.

[0017] Implementations of a method for embedding a semiconductor die may include one, all, or any of the following: The process can include the formation of a nucleation layer on the oxide layer prior to the formation of the thick copper layer.

[0018] The process can include filling a space around the semiconductor die with a polyimide before the first copper layer is formed.

[0019] The formation of the first copper layer can also include the simultaneous formation of vias and conductor tracks.

[0020] The formation of the first copper layer can furthermore include first forming vias and then forming conductor tracks.

[0021] The formation of the second copper layer may further include: simultaneously forming vias and conductor tracks; or first forming vias and then forming conductor tracks.

[0022] The foregoing and other aspects, features and advantages will be evident to professionals from the DESCRIPTION and DRAWINGS as well as from the CLAIMS. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following describes implementations in conjunction with the accompanying drawings, where identical reference symbols denote similar elements and where: Fig. 1 is a cross-sectional view of an implementation of a silicon substrate; Fig. 2 a cross-sectional view of the silicon substrate of Fig. 1 with a rewiring layer formed on it; Fig. 3 a cross-sectional view of the silicon substrate of Fig. 1 with a rewiring layer formed on it and a back metal layer; Fig. 4 a perspective view of a silicon substrate mounted on a frame, a set of silicon substrates packed for shipment in a shipping package, and a cross-sectional view of a set of silicon substrates arranged in the shipping package; Fig. 5 is a cross-sectional view of an implementation of a silicon substrate; Fig. 6 a cross-sectional view of the silicon substrate of Fig. 5 after the formation of a rewiring layer on it; Fig. 7 a cross-sectional view of the silicon substrate of Fig. 6 after the formation of hollow vias; Fig. Figure 8 shows a cross-sectional view of an implementation of a silicon substrate; Fig. 9 a cross-sectional view of the silicon substrate of Fig. 8 after the formation of cavities in it and the formation of a thick copper layer on it; Fig. 10 a cross-sectional view of the silicon substrate of Fig. 9 after coupling the semiconductor die into the cavities and its sintering; Fig. 11 a cross-sectional view of the silicon substrate of Fig. 10 after structuring a photosensitive polymer layer on it; Fig. 12 a cross-sectional view of the silicon substrate of Fig. 11 after the formation of a second copper layer on it; Fig. 13 is a cross-sectional view of an implementation of a silicon substrate; Fig. 14 a cross-sectional view of the silicon substrate of Fig. 13 after the formation of a structured thick copper layer on it; Fig. 15 a cross-sectional view of the silicon substrate of Fig. 14 after the formation of a structured photosensitive polyimide layer on it; Fig. 16 a cross-sectional view of the silicon substrate of Fig. 15 after the sintering of the semiconductor die onto the structured thick copper layer located on it; Fig. 17 a cross-sectional view of the silicon substrate of Fig. 16 after the formation of intermediate compounds next to the semiconductor die; and Fig. 18 a cross-sectional view of the silicon substrate of Fig. 17 after the formation of a second structured photosensitive polyimide layer and a second copper layer on it. DESCRIPTION

[0024] This disclosure, its aspects, and implementations are not limited to the specific components, assembly procedures, or process elements disclosed herein. Many other components, assembly procedures, and / or process elements known in the prior art that are compatible with the intended power semiconductor packages are apparent from this disclosure for use with specific implementations. Accordingly, for example, although specific implementations are disclosed, these implementations and implementing components may include any shapes, sizes, designs, types, models, versions, dimensions, concentrations, materials, quantities, process elements, process steps, and / or the like from the prior art for these power semiconductor packages, as well as implementing components and processes, that are compatible with the intended mode of operation and the intended processes.

[0025] Power semiconductor packages often enclose a substrate on which one or more semiconductor dies are mounted. The substrate includes conductive traces that carry electrical signals and a dielectric or other electrically non-conductive / insulating layer(s) that help to electrically isolate the layer and its traces from other package components or from a printed circuit board or other mainboard to which the power semiconductor package is attached. An example of a substrate is a direct-bonded copper (DBC) substrate, which may contain a layer of copper bonded to an electrically insulating layer, or two layers of copper bonded on each of the largest flat sides of an electrically insulating layer.One of the challenges with many substrate types is that the coefficient of thermal expansion differs between the material of the electrically insulating layer and the material of one or more semiconductor dies bonded to the substrate. Furthermore, the need for good thermal performance to cool the one or more semiconductor dies during operation (especially if the dies are power semiconductors) can also limit the types of electrically insulating materials that can be used. Finally, the material cost of the electrically insulating material may be so high that the material's higher thermal performance outweighs the overall cost. For example, aluminum oxide (Al₂O₃) is relatively inexpensive and has a thermal conductivity of 25 W / m*K.Aluminum nitride (AlN), on the other hand, is expensive and has a much higher thermal conductivity of 170 W / m*K. Silicon nitride substrates (Si3N4 substrates) are also expensive but have a thermal conductivity of 90 W / m*K. HPS substrates (aluminum oxide with ZrO2 doping) are more expensive than aluminum oxide itself and, at 25 W / m*K, have a similar thermal conductivity to aluminum oxide, but offer better reliability. Direct-bonded copper substrates, which use electrically insulating layers made of one of the aforementioned materials, exhibit high current carrying capacity, high breakdown voltage, and high thermal conductivity relative to other insulators, but are relatively expensive.

[0026] This document discloses the use of silicon in combination with an oxide layer or another electrically insulating layer as the material for an electrically insulating layer in a substrate. Silicon is readily available and therefore inexpensive, given its existing use as a primary substrate for various semiconductor dies at scale. Silicon has a higher thermal conductivity than aluminum oxide (120 W / m*K) and exhibits essentially the same coefficient of thermal expansion as a semiconductor die using silicon as its substrate material. Furthermore, the coefficient of thermal expansion of silicon is close to that of a semiconductor die using silicon carbide as its substrate material. Provided the oxide layer / layer of other electrically insulating material is sufficiently thick, the silicon material can also provide reasonably high breakdown voltages.Further advantages of using silicon include the ability to embed dies using various existing silicon fabrication processes, as well as the wide selection of different solderable or sinterable metals available for use in forming electrically conductive layers on the front or back of the silicon layer. While the various implementations disclosed herein relate to the use of silicon as a substrate, these implementations could also be used as interposers in various package designs, with silicon interposers being used in combination with other substrate types to help build the three-dimensional structure of a semiconductor package.

[0027] Referring to Fig. Figure 1 illustrates an implementation of a silicon substrate 2 with an oxide layer 4 (SiO2 in this implementation) on top of it. The silicon substrate 2 can be a full-thickness substrate, meaning that its thickness is typically dependent on the substrate's dimensions. For example, a silicon substrate with a diameter of 300 mm would have a thickness between approximately 775 micrometers and approximately 925 micrometers, this thickness being determined by the need to prevent excessive sagging or warping of the substrate during normal semiconductor processing operations. However, in various implementations, the silicon substrate can be a thinned substrate, meaning that its thickness is less than would normally be expected for its size. The thickness of the oxide layer can be substantial to help ensure that the desired breakdown voltage for the silicon substrate is achieved.In various implementations, the oxide layer thickness can range from approximately 0.1 micrometers to approximately 5 micrometers. For low-voltage applications in the double-digit volt range, oxide layers near the lower end of this thickness range can be used, while for very high-voltage applications above 2000 V, oxide layer thicknesses at the upper end of the range can be employed. While the use of an oxide layer is illustrated here, other dielectric materials could be used in various implementations to achieve the desired breakdown voltage, such as, as a non-limiting example, spin-on glass, low-k dielectrics, nitrides, boron phosphosilicate glass (BPSG), organic dielectrics, polyimides, benzocyclobutene, combinations of Si3N4 and SiO2, metal oxides, tantalum oxide, hafnium oxide, aluminum oxide, or any other dielectric material.

[0028] Referring to Fig. 2 is the silicon substrate 2 of Fig. Figure 1 illustrates the formation of a rewiring layer 6 on top of the oxide layer 4. The process of forming the rewiring layer initially involves the formation of thick copper traces 8 on the oxide layer 4. These thick copper traces can be between approximately 12 micrometers and approximately 35 micrometers thick in various implementations. The process of forming the thick copper traces 8 includes, in various process implementations, the application of a copper adhesion layer to the oxide layer 4, which, as a non-limiting example, may include one or more layers of tantalum, titanium, titanium nitride, titanium tungsten, chromium, any combination thereof, or other materials designed to facilitate the adhesion of the thick copper traces 8 to the oxide layer 4 material.The bonding layer can be formed using sputtering, chemical vapor deposition, or electroless deposition in various process implementations. A copper seed layer is applied to the copper bonding layer in various process implementations; this seed layer can be formed using sputtering, electroless deposition, or electroplating.

[0029] Once the copper seed layer is formed, the surface is ready for the formation of the thick copper layer, from which the thick copper traces will be created. The thick copper layer can be formed using an electroplating, lamination, sputtering, or vapor deposition process. However, in some implementations where a seed layer is not used, a copper foil can be applied / bonded / glued / sintered / soldered onto the bonding layer if the copper foil is of the required thickness. After the thick copper layer is formed, a patterned layer is created on the thick copper layer using a lithographic process, screen printing, stenciling, dispensing, or another process to form a trace pattern on the thick copper layer. The thick copper layer is then etched to form the thick copper traces (patterned trace layer).In other process implementations, the use of a structured layer can be omitted, and instead the thick copper traces 8 can be formed using milling, lasers, or waterjet cutting. When using lasers, a protective layer can be placed over the thick copper layer to help protect the resulting thick copper traces 8 from the slag generated during the laser process. Subsequently, the protective layer is removed by a washing process to remove the slag and expose the thick copper traces 8.

[0030] While the use of thick copper has been illustrated so far, aluminum could also be used to form the thick conductor tracks. The aluminum could also be formed using any of the previously described processes compatible with depositing aluminum onto the corresponding surfaces of the oxide layer or conductor tracks. The corresponding removal process for the aluminum can include any of the previously described methods compatible with removing aluminum.

[0031] After the formation of the thick copper conductor tracks 8, a dielectric material 10 is applied over the thick copper conductor tracks 8. A wide variety of materials can be used, including, as a non-limiting example, spin-on glass, BPSG, polyimide, photodefinable polyimides, photodefinable polymers, low-k dielectrics, silicon dioxide, silicon oxynitride, any combination thereof, or any other type of dielectric material capable of covering the thick copper conductor tracks 8 and forming a substantially flat surface. Depending on the material used, the processes employed to form the dielectric material may include lamination, spray coating, curtain coating, or centrifugal coating.In some process implementations, a planarization process can be used on the dielectric material 10 to planarize the surface after the application / formation of the dielectric material 10. After the application / formation of the dielectric material 10, a set of openings 12, 14 is formed in the dielectric material 10. If the dielectric material 10 is a photodefinable polymer, a lithography process can be used to directly create the openings 12, 14. If the dielectric material is not photodefinable, in some implementations a structured layer is formed on the dielectric material 10 and an etching process is used to create the openings 12, 14. In still other process implementations, a laser or waterjet cutting process can be used to form / mill the openings 12, 14 in the dielectric material 10.

[0032] After the formation of the openings 12, 14, an electrically conductive material is used to fill them, forming a second set of conductor tracks 16 with corresponding vias 18. In some implementations, the electrically conductive material can be copper, and a Damascus (planar) process can be used to form the vias 18 and the second set of conductor tracks 16 simultaneously. In other implementations, the vias 18 can be formed first, followed by the conductor tracks, using a structuring process similar to that used to form the thick copper conductor tracks 8 using a non-planar process. Other metals, including gold, silver, aluminum, gold alloys, silver alloys, aluminum alloys, copper, copper alloys, or any combination thereof, could be used in various implementations.In various implementations, additional layers of conductor tracks and vias could also be formed to create a interconnect stack that generates the rewiring layer, which is composed of layers of electrically conductive and electrically non-conductive materials. The resulting layer allows the movement of electrical signals from the thick copper layers 8 to the second set of conductor tracks 16 and vice versa, depending on how the substrate is electrically connected to one or more semiconductor dies. In various implementations, a metal cap containing cobalt or another metal / metal stack can be used, designed to prevent the diffusion of copper into organic dielectric materials. The resulting substrate 26 is in . Fig. 2 illustrated.

[0033] Fig. Figure 3 illustrates the silicon substrate 2 after the formation of a further oxide layer 20 and a back metal layer 22 on it. In this implementation, the silicon substrate 2 was thinned using grinding, lapping, or another thinning process, and the oxide layer 20 was formed within it. The material of this oxide layer 20 can be any dielectric material disclosed in this document that is compatible with the back metal material. The back metal layer 22 can include one or more metal layers and, in various implementations, can include an adhesive layer. In some implementations, if the back metal layer 22 is electroplated, a nucleation layer may also be present.

[0034] The resulting substrates / interposers 24, 26 are now ready for use in various semiconductor package types, which, as a non-limiting example, can include power modules, integrated power modules, leaded packages, leadless packages, inverters, power conversion equipment, or any other semiconductor package type that uses a substrate or interposer. These packages can be cooled on one or both sides. In various semiconductor package implementations, a heat sink can also be coupled to the back metal layer 22. Furthermore, the substrates 24, 26 can be used in wafer-scale packaging operations, where they are isolated with one or more semiconductor dies to which they have been connected.Substrates 24 and 26 can also be used in chip-scale packaging processes, where they are pre-separated into smaller sections to which semiconductor dies are then attached. If substrates 24 and 26 are already pre-separated to the desired size, they can be used in a chip-scale packaging process without further separation.

[0035] All substrates formed at the substrate / panel / wafer level 24, 26 can be stored and transported to a subsequent location for further processing. Referring to Fig. 4. A substrate 28 in the form of a silicon wafer was mounted on a frame 30 using a cutting belt 32. Now that the substrate 28 is mounted on the frame 30, a specific number of substrates can be packed into the shipping container 34. The drawing on the right side of Fig. Figure 4 shows a cross-sectional view of the contents of the shipping package 34, which contains a stack of 25 frames with 26 spacers between the frames to prevent contact between the cutting tape and the top of each substrate, with six foam spacers 36 at the top and bottom ensuring that the frames do not move. When shipping substrate implementations such as those disclosed herein to other locations for additional semiconductor packaging operations, a wide variety of shipping techniques, shipping packages, and other transportation systems can be used.

[0036] Referring to Fig. Figure 5 illustrates another implementation of a silicon substrate 38 with an oxide layer 40 on it. Fig. Figure 6 illustrates the silicon substrate 38 after the formation of a rewiring layer 42 on it, which uses thick copper conductor tracks 44 and a second set of conductor tracks 46, similar to those used in the substrate implementations in Fig. Figures 1 to 3 illustrate this. At this point, the substrate 38 is ready for further processing. The processing begins by thinning the substrate 38 material to a desired thickness using a thinning process disclosed herein. After thinning, an oxide layer 48 (or another dielectric material disclosed herein) is grown / formed on a second largest planar surface 50 of the substrate 38, which faces a first largest planar surface 52 on which the rewiring layer 42 was formed. The oxide layer 48 is then patterned using a patterning layer formed on the oxide layer 48 using a lithography process or another patterning process disclosed herein, and the oxide layer 48 is etched to expose the silicon substrate 38 material. In the Fig. In the implementation illustrated in Figure 7, a second structured layer is formed, outlining the positions of the silicon vias 54 before etching. As illustrated, the silicon vias 54 are etched with slanted sidewalls, creating a larger opening on the second-largest flat side 50 of the silicon substrate 38 and a narrower opening where the silicon vias 54 meet the thick copper traces 44. This slanted sidewall etching can be achieved by appropriate adjustments to the etching chemistry and chamber conditions, and the thick copper traces 44 serve as an etch stop for the silicon vias 54.

[0037] After etching the silicon, a copper bonding layer is applied, containing any of the materials previously disclosed in this document. In some implementations, a copper barrier layer may also be formed in the silicon vias 54 and the exposed silicon. The copper barrier layer may include nickel or nickel vanadium in various implementations. In some process implementations, a seed layer is subsequently applied over the barrier layer. In other process implementations, a thick copper layer 56 is then electroplated into the silicon vias 54 and over other exposed areas of the silicon to form conductor tracks 58. The thickness of the thick copper layer 56 may be any thickness previously disclosed in this document. As in Fig. As illustrated in Figure 7, the resulting silicon vias 54 are hollow because the ends of the vias are not sealed. This ability to keep the silicon vias 54 hollow can protect them from damage during operation, especially from high temperature / current cycles, which have been observed to cause copper pumping, leading to cracks in the copper within the solid silicon vias. The ability for the resulting substrate 60 to allow electrical connections to both sides of the substrate 60 through the silicon vias 54 can make this substrate design particularly useful as an interposer in a semiconductor package design.The electrical connections can be any of a wide variety of electrical connector types, including, but not limited to, wire connections, bond wires, clips, wires, flexible connectors, or any other type of electrical connector. The electrically conductive materials used for the electrical connectors can be of a wide variety of materials, including, but not limited to, gold, gold alloys, silver, silver alloys, aluminum, aluminum alloys, copper, copper alloys, nickel, nickel alloys, any combination thereof, or any other electrically conductive material or alloy type. Since there are 38 thick copper conductor tracks on both sides of the silicon substrate, this substrate can be an effective replacement for a direct-bonded copper substrate in various implementations.In various implementations, the silicon vias 54 can be connected via a fan-out wiring formed by the conductor tracks 58. This would allow various active and / or passive components to be coupled / connected to both sides of the substrate 60, although from a processing point of view this would take place after the semiconductor packages / substrate have been separated into sections of package size.

[0038] The various other substrate implementations disclosed herein can be formed using different methods for forming substrates / interposers. Referring to Fig. Figure 8 illustrates a silicon substrate 62 enclosing an oxide layer 64 formed thereon. Although an oxide layer 64 is illustrated, any of the other dielectric / non-electrically conductive materials disclosed herein could also be used in various substrate implementations. Referring to Fig. Figure 9 illustrates the silicon substrate 62 after the formation of cavities 66 into the thickness / material of the silicon substrate 62. In various process implementations, the cavities 66 are formed by first forming a structured layer over the oxide layer 64 and then etching the oxide to expose the surface of the silicon substrate. Subsequently, the structured layer is removed, and the oxide layer 64 is used as the structured layer during an etching process to remove the silicon and form the cavities 66. As illustrated, the etching process of the cavities 66 forms inclined edges, indicating that the etching is isotropic rather than anisotropic. Various etching processes, including wet or dry etching, can be used to etch the cavities 66 and achieve the desired cavity shape.The use of inclined sidewalls facilitates the achievement of a more uniform formation of subsequent layers. Although the use of etching has been disclosed, in some process implementations the cavities 66 could be formed by laser or milling processes that could simultaneously cut through both the oxide and the silicon, thus avoiding the need to use the formation of a structured layer.

[0039] After the formation of the cavities 66, a further oxide layer 68 is formed over the exposed silicon in the cavities 66. This oxide layer 68 can be formed using any of the methods disclosed herein and can, in particular, be formed as a conformal layer. In other implementations, however, the use of the oxide layer 68 may not be employed, but instead a barrier layer and / or nucleation layer may be applied to the exposed silicon. Once the two oxide layers 64, 66 are in place, a structured layer of a desired height is then formed to facilitate the formation of a thick copper layer 70 in the cavities together with copper conductor sections 72. In the Fig. In the implementation illustrated in Figure 9, a seed layer and / or a barrier layer, like any layer previously disclosed in this document, is applied over the exposed oxide layers 64, 66, and then an electroplating process is used to form a thick copper layer 72 and corresponding copper conductor sections 72, like any layer disclosed herein. In other implementations, any of the other disclosed methods for forming a thick copper layer may also be used. After the formation of the thick copper layer 70 and all corresponding copper conductor sections 72, the structured layer is then removed. Using the principles disclosed in this document, a wide variety of thick copper structures can be formed that extend into, out of, and on the surface of the oxide layers 64, 66, forming conductors.

[0040] While in the Fig. While the use of copper is disclosed in the illustrated process implementation in Section 9, other process implementations may utilize any other metal or metal alloy disclosed herein, employing any of the corresponding methods for forming that metal. In some process implementations, multiple metal layers of different or the same type may also be used.

[0041] Referring to Fig. Figure 10 illustrates the silicon substrate 62 after joining semiconductor dies 74. In this implementation, the semiconductor die 74 is placed in cavities 66 on the thick copper layer 72 and then sintered either directly or using a sintering material compatible with forming a bond between the surface of the semiconductor die 74 and the thick copper layer 70. In other method implementations, the semiconductor die 74 can be soldered to the thick copper layer 70 by applying a solder material either to the semiconductor die 74 or the thick copper layer 70, or to both, and then heating the silicon substrate 62 to melt the solder and form the desired bond.Depending on the material(s) of the semiconductor die 74 and the desired processing conditions and the desired connection, a wide variety of solder materials can be used, including, as a non-limiting example, lead-tin solder, lead-silver-tin solder, tin-silver solder, tin-copper solder, tin, any combination thereof, or any other solder material compatible with one or more arbitrary metal layers on the semiconductor die and the thick copper layer or other metal layer at the bottom of the cavities 66.In implementations where a solder is used, a solder adhesion layer can first be formed over the thick copper layer 70. This layer can be, as a non-limiting example, titanium, titanium tungsten, tantalum, titanium nitride, chromium, any combination thereof, or any other metal or material that facilitates adhesion between the specific solder and the specific type of metal to which the solder is attached. Other materials / bonding systems could also be used to attach the semiconductor die to the thick copper layer 70, including, as a non-limiting example, a die attachment film, adhesive, die attachment bonding agent, a friction fit, a mechanical fit, or any other system / method for attaching a semiconductor die in a cavity.

[0042] Fig. Figure 10 illustrates how, after joining the semiconductor die 74 to the thick metal layer 70, the edge gaps around the semiconductor die 74 and the thick metal layer 70 in the cavities 66 were filled with a filler material. In this implementation, the filler material can be a polyimide material 76, applied using an inkjet printing process, a needle dispensing process, or other precision dispensing methods, followed by a baking process to cure the polyimide material 76 in the edge gaps. In other implementations, other materials can be used to fill the edge gaps, including, as a non-limiting example, polymers, resins, molding compounds, or other electrically insulating materials that can be cured using the appropriate curing process.

[0043] Referring to Fig. Figure 11 illustrates the silicon substrate 62 after spin coating of a photosensitive polymer layer 78 over the semiconductor die 74, the oxide layers 64, 68, the thick copper layer 70, and the copper conductor sections 72, followed by exposure and development to form openings 80 over the desired sections of the semiconductor die 74 and / or the copper conductor sections 72. In this implementation, a curing process is used to complete the curing of the photosensitive polymer layer 78, so that it is prepared to remain in place during subsequent operations. While in the process implementation of Fig. 11 where the use of centrifugal coating of the photosensitive polymer is illustrated, any other method disclosed herein for forming a polymer layer could be used which is compatible with the specific polymer / resin material used to form the polymer layer.

[0044] Fig. Figure 12 illustrates the silicon substrate 62 of Fig. 11 after the formation of copper conductor tracks 82 and vias 84 in the openings 80 of the photosensitive polymer layer 78. The formation of the copper conductor tracks 82 and vias 84 can be achieved by first using a sputtering process to form a seed layer over the photosensitive polymer layer 78, followed by electroplating. In this process, the vias and conductor tracks can be formed simultaneously in a damascene (planar) manner. After electroplating, a lithography process can be used to form a structured layer over the copper conductor tracks 82, and then an etching process can be used to complete the formation of the copper conductor tracks 82. However, in other process implementations, a planarization step can be used before the lithography process to produce smoother copper conductor tracks.When other metals are used, the corresponding deposition, via-filling, and trace formation processes for these metals can be employed. In various implementations, the vias can initially be formed using metals that are different from or the same as the traces, depending on the process used. At this point, the resulting substrate 86 is ready for use in further semiconductor processing operations. For example, one or more additional rewiring layers could be formed over the copper traces 82 (second copper layer) to form an interconnect stack. One or more additional semiconductor dies could also be coupled to the copper traces 82 and exposed by a molding compound or further embedded in additional rewiring layers.In various semiconductor packages, several substrates 86 could be enclosed in stacked or otherwise connected configurations within multichip modules. Finally, the substrate 86 could be thinned and / or a backing metal added, using any processing method disclosed for each operation revealed in this document.

[0045] Referring to Fig. Figure 13 illustrates an implementation of a silicon substrate 88 with an oxide layer 90 on it. While this implementation illustrates the use of an oxide layer, any of the previously disclosed dielectric materials could be used. In this implementation, a structured layer of thick copper conductors 92 is then formed over the oxide layer 90. This structured layer begins with the deposition of an adhesion and / or nucleation layer, followed by the electroplating / formation of a thick copper layer using one of the layer types and formation / deposition methods disclosed in this document for the various layers.Subsequently, a structured layer is formed over the thick copper layer, and then an etching / removal process such as any described herein is performed to remove the thick copper layer in the exposed areas to form the thick copper traces 92. If etching is not used, a milling / laser process could also be used to form the thick copper traces. If a laser process is used, a protective layer can be formed over the thick copper layer to retain any slag present on it, which can then be removed by washing or another cleaning process. The resulting structure is shown in . Fig. Figure 14 illustrates where thick copper conductor tracks 92 are illustrated and sections of the oxide layer 90 are exposed.

[0046] Referring to Fig. Figure 15 illustrates the silicon substrate 88 after vacuum lamination of a photosensitive polyimide layer (PSPI layer) 94 over the thick copper conductor tracks 92 and the oxide layer 90. Since the polyimide is photodefinable, after the layer has been conformally formed over the surface of the silicon substrate 88, exposure and development of the reacted PSPI material is carried out to create openings 96. Fig. Figure 16 illustrates the silicon substrate 88 after the semiconductor die 98 has been joined into the openings 96 onto the thick copper conductor tracks 92. The joining can be carried out using any die joining method disclosed herein, including sintering and soldering.

[0047] Referring to Fig. Figure 17 illustrates the silicon substrate 88 after a precision filling process of the gap between the openings 96 and the semiconductor die 98 using any filling material and process disclosed herein. Subsequently, a baking / curing process is used to stabilize the filling material. Then, vias 100 and copper traces (second copper layer) 102 are formed to create electrical connections with the thick copper traces 92. The vias 100 and the copper traces 102 can be formed using any copper layer formation process disclosed herein. For the vias 100 and / or traces 102, metals / electrically conductive materials other than copper can be used in various implementations, employing deposition and formation processes compatible with these metals.

[0048] Fig.Figure 18 illustrates the silicon substrate 88 after the application of another layer of photodefinable polyimide / photodefinable polymer over the vias 100 and conductor tracks 102 using any method disclosed herein, and the formation of a second set of vias 104 and a third set of copper conductor tracks 106 on / in it. Additional electrically conductive and non-electrically conductive layers could be formed to provide additional electrical conduction to another semiconductor die coupled to the conductor tracks 102. In this way, the semiconductor dies 98 are embedded in the resulting substrate 108. The substrate 108 can then be used in packaging operations to form all previously disclosed semiconductor package types, including multichip modules. The substrate 108 can also be thinned and / or backed with a metal backing.If the substrates 86 and 108 have metallic / electrically conductive layers on both sides, they can be effectively used for mounting active and / or passive components on both sides of the substrates after any necessary singulation.

[0049] In this document, the semiconductor die that can be used can be one of a wide variety, including, as a non-limiting example, power semiconductor dies, diodes, metal-oxide field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), hybrid devices, rectifiers, random-access memory, high electron mobility transistors, image sensors, wide-bandgap semiconductor devices (WBGs), hybrid devices, or any other type of semiconductor die / device. For the semiconductor die that is packaged with the semiconductor package designs disclosed in this document, a wide variety of semiconductor substrate types can be used, including, as a non-limiting example, silicon, silicon carbide, gallium arsenide, gallium nitride, silicon on insulator, ruby, sapphire, or any other type of semiconductor material.A wide variety of semiconductor package configurations can be formed using the principles disclosed herein.

[0050] The various semiconductor packages, which incorporate the different substrate implementations disclosed herein, can be cooled from one side or from both sides of the packages (dual-sided cooling). Furthermore, the semiconductor die embedding methods disclosed herein can be used to embed multiple semiconductor dies in multiple layers of the same substrate or in combinations of multiple substrates.

[0051] It is understood without further ado that where the foregoing description relates to particular implementations of semiconductor packages and implementing components, subcomponents, methods and sub-methods, a number of modifications may be made without deviating from their essence, and that these implementations, implementing components, subcomponents, methods and sub-methods may also be applied to other semiconductor packages.

Claims

[1] Substrate, comprising: a semiconductor material; a rewiring layer coupled to a first largest planar surface of the semiconductor material; and a hollow via extending from a second largest planar surface of the semiconductor material completely through one thickness of the semiconductor material, with the hollow via being directly coupled to the rewiring layer. [2] Substrate according to claim 1, wherein the rewiring layer comprises at least one thick copper layer. [3] Substrate according to claim 1, wherein the rewiring layer comprises at least one dielectric layer and at least one layer of a solderable metal or a sinterable metal. [4] Substrate according to claim 1, wherein the semiconductor material is thinned from an initial thickness. [5] Substrate according to claim 1, wherein the semiconductor material is silicon carbide. [6] Substrate according to claim 1, wherein the semiconductor material is silicon. [7] Substrate according to claim 6, further comprising an oxide layer between the rewiring layer and the semiconductor material. [8] Substrate according to claim 6, further comprising an oxide layer on the second largest planar surface of the semiconductor material. [9] Substrate according to claim 1, further comprising a back metal layer coupled to the second largest planar surface of the semiconductor material. [10] Method for embedding a semiconductor die, the method comprising: Providing a silicon substrate that includes a first oxide layer on it; Forming at least one opening in the first oxide layer; Etching a cavity into the silicon substrate at the at least one opening in the first oxide layer; Formation of a second oxide layer in the cavity; Formation of a thick copper layer on the first oxide layer and on the second oxide layer; Structuring the thick copper layer; Sintering of at least one semiconductor die onto the thick copper layer in the cavity; Filling a gap between the at least one semiconductor die and the thick copper layer in the cavity with a polyimide; Forming a layer of photosensitive polymer over the at least one semiconductor die, the thick copper layer and the first oxide layer; Structuring the layer of photosensitive polymer to form a multitude of openings within it; Forming an initial copper layer in the multitude of openings; and Forming a second copper layer over the layer of photosensitive polymer and the first copper layer. [11] Method according to claim 10, wherein the formation of the first copper layer and the formation of the second copper layer take place simultaneously. [12] Method according to claim 10, further comprising forming a nucleation layer on the second oxide layer prior to forming the thick copper layer. [13] Method according to claim 10, further comprising baking the polyimide. [14] Method according to claim 10, further comprising coupling a rewiring layer or another semiconductor die with the second copper layer. [15] Method for embedding a semiconductor die, the method comprising: Providing a silicon substrate comprising an oxide layer on it; Formation of a thick copper layer on the oxide layer; Structuring the thick copper layer; Applying a first photosensitive polyimide over the thick copper layer; Structuring the first photosensitive polyimide to form an opening in it; either sintering or soldering a semiconductor die into the opening; Forming a first copper layer on the first photosensitive polyimide and the semiconductor die; Applying a second photosensitive polyimide layer over the first copper layer; Structuring the second photosensitive polyimide; Forming a second copper layer on the second photosensitive polyimide; and Coupling a rewiring layer or another semiconductor die to the second copper layer. [16] Method according to claim 15, further comprising forming a nucleation layer on the oxide layer prior to forming the thick copper layer. [17] Method according to claim 15, further comprising filling a space around the semiconductor die with a polyimide prior to forming the first copper layer. [18] Method according to claim 15, wherein the formation of the first copper layer further comprises the simultaneous formation of vias and conductor tracks. [19] Method according to claim 15, wherein the formation of the first copper layer further comprises the formation of vias and then the formation of conductor tracks. [20] The method of claim 15, wherein the formation of the second copper layer further comprises one of: simultaneous formation of vias and conductor tracks; or First, the vias are formed, and then the conductor tracks are formed.

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