Semiconductor packaging with embedded device and redistribution layer

Abstract

A semiconductor package can enclose a semiconductor die mounted on a first substrate, having at least one first contact on a first side and at least one second contact on a second side opposite the first side. An insulator, such as a dielectric, can encapsulate the semiconductor die. A second substrate with the semiconductor die sandwiched between them can be mounted on the first substrate. Both the first and second substrates can have a cavity formed within them, and the semiconductor die can be located in one or both cavities. Vias through the first substrate, the dielectric, and / or the second substrate can be used to connect to the semiconductor die, thereby enabling the formation of a redistribution layer.Instead of the semiconductor die and the associated contacts, magnetic elements and the associated windings can also be used.

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims the benefit and priority of the preliminary US application No. 63 / 715.912, filed on November 4, 2024, and the preliminary US application No. 63 / 736.415, filed on December 19, 2024, and the simultaneously filed non-preliminary US application xx / xxx.xxx entitled “Semiconductor Module with Power Bridge for Integrated Die Interconnection”, which are hereby incorporated in their entirety by reference. TECHNICAL AREA

[0002] This description refers to the packaging of semiconductor devices. STATE OF THE ART

[0003] Conventional packaging techniques for semiconductor devices exhibit a number of shortcomings. Such shortcomings are particularly problematic in the context of packaging semiconductor power devices, as these devices typically have multiple requirements that must be met simultaneously by a single packaging technique.

[0004] For example, semiconductor power devices often require operation at high voltage and high temperature, necessitating high-voltage insulation and high thermal conductivity for heat transfer to one or more heat sinks for safety reasons. The packaging of power devices is often intended to be inexpensive and small, further exacerbating the challenges of meeting voltage / temperature requirements.

[0005] In one specific example, it is desirable to provide semiconductor modules for electric vehicle traction inverters with low on-resistance across many parallel devices, along with low circuit parasitics, while maintaining the aforementioned requirements for low cost, small size, and voltage / thermal management. In another specific example, artificial intelligence (AI) data centers have high energy demands, but current packaging techniques suffer from problems such as the complexity associated with multi-chip packaging in a small footprint (exacerbated by the use of flip-chip technology), the poor thermal conductivity of the encapsulation materials used, and the undesirably large packaging volume caused by the inclusion of bond wires.

[0006] Newer approaches attempt to address the aforementioned and related challenges, such as embedding printed circuit boards (PCBs). However, these approaches can be expensive and complex, and still do not satisfactorily resolve the existing challenges. For example, embedding PCBs typically requires expensive laser drilling for vias, while simultaneously providing inadequate cooling. SUMMARY

[0007] According to a general aspect, a semiconductor package includes a substrate, a semiconductor die arranged on the substrate and having at least one first contact on a first side and at least one second contact on a second side opposite the first side, a dielectric encapsulation material encapsulating the semiconductor die and having vias formed therein, and a redistribution layer formed on the dielectric encapsulation material and connected to the first contact and the second contact via the vias.

[0008] According to another general aspect, a method for manufacturing a semiconductor package includes providing a semiconductor die on a substrate, wherein the semiconductor die has at least one first contact on a first side and at least one second contact on a second side opposite the first side, encapsulating the semiconductor die with a dielectric encapsulation material, forming vias in the dielectric encapsulation material, and forming a redistribution layer on the dielectric encapsulation material, which is connected to the first contact and the second contact via the vias.

[0009] According to another general aspect, a semiconductor package includes a first substrate, a semiconductor die arranged on the first substrate, a second substrate with a cavity formed therein, wherein the cavity defines a first section of the second substrate with a first depth and a second section of the second substrate with a second depth greater than the first depth, and wherein the second substrate is attached to the first substrate by the second section of the second substrate, and wherein the semiconductor die is arranged within the cavity, a via formed by the first section of the second substrate, and a contact arranged on the second substrate and electrically connected to the semiconductor die via the via.

[0010] According to another general aspect, a method for fabricating a semiconductor package includes placing a semiconductor die on a first substrate, forming a cavity in a second substrate, wherein the cavity defines a first section of the second substrate with a first depth and a second section of the second substrate with a second depth greater than the first depth, attaching the second substrate to the first substrate by means of the second section of the second substrate, wherein the semiconductor die is arranged within the cavity, forming a via through the first section of the second substrate, and placing a contact on the second substrate that is electrically connected to the semiconductor die via the via.

[0011] According to another general aspect, a semiconductor package includes a substrate with a cavity formed therein, a magnetic element arranged in the cavity, a metallic winding arranged on the substrate and surrounding the magnetic element, a dielectric encapsulation material which encapsulates the magnetic element and the metallic winding, and a contact which is electrically connected to the metallic winding via a via formed in the dielectric encapsulation material.

[0012] According to another general aspect, a method for manufacturing a semiconductor package includes forming a cavity in a substrate, arranging a magnetic element in the cavity, providing a metallic winding on the substrate and around the magnetic element, encapsulating the magnetic element and the metallic winding with a dielectric encapsulation material, forming a via in the dielectric encapsulation material, and electrically connecting a contact to the metallic winding via the via.

[0013] According to another general aspect, a semiconductor package includes a first substrate, a metal layer arranged on the first substrate, metal pillars arranged on the metal layer and forming a cavity, a semiconductor die arranged in the cavity with a first surface on the metal layer, an encapsulation material encapsulating the semiconductor die, including a second surface of the same opposite the first surface, and at least one section of the metal pillars, a second substrate formed on the encapsulation material and the metal pillars, and a redistribution layer formed on the second substrate and connected to the first surface of the semiconductor die, the second surface of the semiconductor die, and at least one of the metal pillars via vias formed through the second substrate.

[0014] According to another general aspect, a method for manufacturing a semiconductor package includes forming a metal layer on a first substrate, arranging metal pillars on the metal layer to define a cavity, arranging a semiconductor die in the cavity, wherein a first surface is arranged on the metal layer, encapsulating the semiconductor die with an encapsulation material, including a second surface of the same facing the first surface and at least one section of the metal pillars, forming a second substrate on the encapsulation material and the metal pillars, forming vias through the second substrate, and forming a redistribution layer on the second substrate, which is connected to the first surface of the semiconductor die, the second surface of the semiconductor die, and at least one of the metal pillars via the vias.

[0015] The details of one or more implementations are set out in the accompanying drawings and the description below. Other features will become apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows a cross-sectional view of a semiconductor module according to exemplary embodiments. Fig. 2A is a cross-sectional view of an exemplary processing stage for the formation of the semiconductor module from Fig. 1. Fig. 2B is a cross-sectional view of an exemplary processing stage for the formation of a semiconductor module, which is the semiconductor module made of Fig. 1 resembles. Fig. 2C is a cross-sectional view of an exemplary processing stage for the formation of the semiconductor module from Fig. 2B. Fig. 2D is a cross-sectional view of another exemplary processing stage for the formation of the semiconductor module from Fig. 2B. Fig. 2E is a cross-sectional view of an exemplary processing stage for the formation of the semiconductor module from Fig. 2D, illustrating additional optional contacts. Fig. 2F is a cross-sectional view of a final processing stage for the semiconductor module made of Fig. 2B. Fig. Figure 3 is a cross-sectional view of a semiconductor module with a cavity according to exemplary embodiments. Fig. 4 a cross-sectional view of an exemplary embodiment with a second substrate. Fig. 5A is a cross-sectional view of a first processing stage for forming the exemplary embodiment from Fig. 4. Fig. 5B is a cross-sectional view of a second processing stage for forming the exemplary embodiment from Fig. 4. Fig. Figure 6 is a cross-sectional view of an exemplary embodiment with stacked devices. Fig. Figure 7 is a cross-sectional view of an exemplary embodiment with stacked modules. Fig. Figure 8 is a cross-sectional view of an exemplary embodiment of a semiconductor module with rear-side contacting. Fig. Figure 9 is an exemplary embodiment illustrating the simple connection of a semiconductor module constructed using the described techniques to allow adaptation of the footprint to existing packages. Fig. Figure 10 is a cross-sectional view of an exemplary embodiment with nested modules. Fig. Figure 11 illustrates a first exemplary use case for the exemplary embodiment from Fig. 10. Fig. Figure 12 illustrates a first exemplary use case for the exemplary embodiment from Fig. 9. Fig. Figure 13 is a circuit diagram illustrating the operation of a module according to exemplary embodiments, which operates as a solid-state relay. Fig. Figure 14 is a top view of a section of a wafer used to manufacture modules, each containing four semiconductor dies. Fig. Figure 15 is a top view of the entire wafer made of Fig. 14. Fig. Figure 16 is an exemplary implementation demonstrating dual thermal and electrical connectivity. Fig. Figure 17 is an alternative exemplary implementation demonstrating dual thermal and electrical connectivity. Fig. Figure 18 illustrates an exemplary embodiment with multiple cavities. Fig. Figure 19 illustrates an exemplary embodiment with an arrangement of several modules made of Fig. 18, which are deployed together. Fig. Figure 20A is an isometric view of an exemplary embodiment with a cooling block. Fig. 20B is a cross-sectional view of the exemplary embodiment from Fig. 20A. Fig. Figure 21 is a 3D exploded view of an exemplary assembled package for the embodiments from Fig. 18 to Fig. 20B. Fig. Figure 22 illustrates an exemplary single-metal layer routing for multiple dies. Fig. Figure 23 is a cross-sectional view of an exemplary double cavity design. Fig. Figure 24 is a cross-sectional view of an alternative exemplary double cavity design. Fig. Figure 25 is a cross-sectional view of an exemplary single-cavity design on metal. Fig. Figure 26 is a cross-sectional view of an exemplary double-cavity design with silicon bonded to diamond. Fig. Figure 27 is a cross-sectional view of an exemplary double-cavity design with a drain-side redistribution layer. Fig. Figure 28 is a cross-sectional view of an alternative exemplary double cavity design with a drain-side redistribution layer. Fig. Figure 29 is a cross-sectional view of an exemplary double-cavity design, wherein one cavity is formed using a metal substrate and a substrate frame. Fig. Figure 30 is a cross-sectional view of an exemplary double substrate single cavity design. Fig. Figure 31 is a cross-sectional view of an exemplary double-cavity design with a redistribution layer formed between substrates. Fig. Figure 32 is a cross-sectional view of an exemplary double-cavity design with integrated passive devices. Fig. Figure 33 is a cross-sectional view of an exemplary double-cavity design with integrated active circuit arrangement. Fig. Figure 34 is a cross-sectional view of an exemplary double-cavity design with integrated MEMs technology. Fig. Figure 35 is a cross-sectional view of an exemplary double-cavity design with integrated MEMS tubes for liquid cooling. Fig. Figure 36 is a cross-sectional view of an alternative exemplary double cavity design with integrated MEMs technology and / or active circuit arrangement. Fig. Figure 37 is a cross-sectional view of an exemplary double-cavity / double-die design. Fig. Figure 38 is a top view of an exemplary embodiment, which is made using various of the exemplary embodiments from Fig. 37 and / or Fig. 39 to Fig. 50 can be constructed. Fig. Figure 39 is a cross-sectional view of an exemplary dual-die embodiment, which has a substrate with a cavity on metal to provide a common drain connection. Fig. Figure 40 illustrates an example gate / source routing. Fig. Figure 41 illustrates an exemplary gate / source / drain routing for the example from Fig. 40. Fig. Figure 42 is a cross-sectional view of an exemplary double-cavity / double-die design with a single redistribution layer. Fig. Figure 43 is a cross-sectional view of an exemplary stacked module with multiple double-cavity / double-die modules. Fig. Figure 44 is a cross-sectional view of an exemplary stacked module in a half-bridge configuration. Fig. Figure 45 is a cross-sectional view of an alternative exemplary stacked module in a half-bridge configuration. Fig. Figure 46 is a cross-sectional view of a second alternative exemplary stacked module in a half-bridge configuration. Fig. Figure 47 is a cross-sectional view of an implementation of the example from Fig. 46 with busbars. Fig. Figure 48 is a top view of the exemplary embodiment from Fig. 47. Fig. Figure 49 is a cross-sectional view of another exemplary stacked module in a half-bridge configuration. Fig. Figure 50 is a circuit diagram for a stacked module in a half-bridge configuration. Fig. Figure 51 is a cross-sectional view of a dual-cavity form factor packaged with a printed circuit board and a heat sink. Fig. Figure 52 is a cross-sectional view of a single-cavity design with alternative gate routing and a bonded interface. Fig. Figure 53 is a cross-sectional view of a single-cavity design with alternative gate and source routing for accommodating a heat sink. Fig. Figure 54 is a cross-sectional view of a single-cavity design with alternative gate routing. Fig. Figure 55 is a cross-sectional view of a single-cavity design with an embedded magnetic element. Fig. 56 is a top view of the example from Fig. 55. Fig. 57A illustrates a first exemplary embodiment of the examples from Fig. 55 and Fig. 56. Fig. 57B illustrates a second exemplary embodiment of the examples from Fig. 55 and Fig. 56. Fig. 58 illustrates a third exemplary embodiment of the examples from Fig. 55 and Fig. 56. Fig. Figure 59 is a cross-sectional view of an alternative single-cavity design. Fig. Figure 60 is an exemplary top view of the embodiment from Fig. 59. Fig. 61A illustrates initial exemplary processes for forming a lower arrangement from Fig. 59. Fig. 61B illustrates a second exemplary process for forming a lower arrangement from Fig. 59. Fig. 61C illustrates a third exemplary process for forming a lower arrangement from Fig. 59. Fig. Figure 61D illustrates the fourth exemplary process for forming a bottom array from Fig. 59. Fig. 61E illustrates the fifth exemplary process for forming a bottom arrangement from Fig. 59. Fig. Figure 61F illustrates the sixth exemplary process for forming a bottom arrangement from Fig. 59. Fig. 61G illustrates the seventh exemplary process for forming a lower arrangement from Fig. 59. Fig. 62A illustrates initial exemplary processes for forming an upper arrangement from Fig. 59. Fig. 62B illustrates a second exemplary process for forming an upper arrangement from Fig. 59. Fig. 62C illustrates a third exemplary process for forming an upper arrangement from Fig. 59. Fig. 62D illustrates the fourth exemplary process for forming a top array from Fig. 59. Fig. 63A illustrates initial exemplary processes for forming an alternative embodiment with metal columns. Fig. 63B illustrates a second exemplary process for forming an alternative embodiment with metal columns. Fig. Section 63C illustrates a third exemplary process for forming an alternative embodiment with metal columns. Fig. 63D illustrates the fourth exemplary process for forming an alternative embodiment with metal columns. Fig. Figure 63E illustrates the fifth exemplary process for forming an alternative embodiment using metal columns. Fig. 63F illustrates the sixth exemplary process for forming an alternative embodiment with metal columns. Fig. 63G illustrates the seventh exemplary process for forming an alternative embodiment using metal columns. Fig. Section 63H illustrates eight exemplary processes for forming an alternative embodiment using metal columns. Fig. 63I illustrates ninth exemplary processes for forming an alternative embodiment with metal columns. Fig. 63J illustrates ten exemplary processes for forming an alternative embodiment with metal columns. Fig. Figure 64 is a cross-sectional view of an exemplary embodiment with heat sinks formed in vias. Fig. Figure 65 illustrates an exemplary process flow for forming cavities that can be used in various embodiments. Fig. Figure 66 is a first flowchart illustrating exemplary embodiments. Fig. Figure 67 is a second flowchart illustrating exemplary embodiments. Fig. Figure 68 is a third flowchart illustrating exemplary embodiments. Fig. Figure 69 is a fourth flowchart illustrating exemplary embodiments. DETAILED DESCRIPTION

[0016] The described packaging techniques for power semiconductors enable improvements regarding the aforementioned and other shortcomings of conventional techniques. For example, the described techniques provide improved thermal properties (including bidirectional cooling), improved package parasitics, and simplified bidirectional electrical / thermal access. The described techniques provide more compact and reliable packages and, among other advantages, enable the use of simplified manufacturing techniques that still allow a high degree of flexibility in the design of a variety of semiconductor modules.

[0017] In the exemplary techniques described, at least one semiconductor die is placed on a substrate and encapsulated or embedded in an insulator, such as a dielectric layer or an air cavity. A second substrate can be positioned on top of the first, with the semiconductor die and the insulator located between the first and second substrates. Vias through the second substrate and / or through the dielectric layer can be used to provide a redistribution layer (RDL) that provides electrical access to and control of the semiconductor die.

[0018] By using these and similar structures, many different embodiments can be constructed using many different manufacturing processes. For example, one or more semiconductor dies can be arranged in one or more cavities. If, for instance, a second substrate is used to surround or encapsulate a semiconductor die positioned on or in a first substrate, one or more cavities can be formed either in the first substrate, in the second substrate, or in both.

[0019] A residual distribution layer (RDL) can be provided for the semiconductor die(s) on a single plane or layer within the resulting module. For example, if the semiconductor die encloses a transistor, the transistor's source, gate, and drain contacts can be redistributed onto a single metallization layer. If, for example, a second substrate is enclosed, the RDL can be provided on a layer of the module located on a surface of the second substrate facing the first substrate. In other examples, the RDL can be provided on a layer of the module located between the first and second substrates. In still other examples, contacts for the semiconductor die can be distributed on opposite sides of the module.

[0020] Exemplary embodiments can have electrical connectivity on an upper and / or lower surface and can have thermal conductivity on an upper and / or lower surface of the semiconductor module. For example, the semiconductor module can have electrical connectivity on an upper surface and thermal conductivity on a lower surface.

[0021] Mechanical devices can be manufactured and integrated with the semiconductor die within the semiconductor module. For example, a device can be integrated with microelectromechanical systems (MEMS). MEMS devices can be integrated, for instance, to provide a fast, galvanically isolated electromechanical solid-state relay that can be used, for example, as a circuit breaker, offering the advantages of both electromechanical and solid-state circuit breakers.

[0022] In other examples, magnetic elements can be enclosed instead of or in addition to semiconductor devices. Metal layers or traces can be used to provide windings around the magnetic element(s), enabling the construction of transformers and other inductive devices.

[0023] Many different fabrication techniques can be used. For example, if standard dielectric and / or semiconductor materials are used, standard fabrication techniques can be integrated to enable the construction of the described devices in a fast, cost-effective, and reliable manner. For instance, if a second substrate includes silicon, common etching techniques can be used to provide silicon through-silicon vias (TSVs) for use in constructing an RDL. In contrast, as mentioned above, conventional embedded packaging techniques that use organic materials or other encapsulating agents may require more expensive drilling techniques, such as laser drilling, to provide electrical connections.

[0024] In some embodiments, when silicon is used for a first and a second substrate, wafer-to-wafer bonding can be used, followed by singulation of individual semiconductor modules. In other embodiments, semiconductor devices can be arranged on wafer plates, followed by singulation / separation, and then the addition of a second substrate can be provided.

[0025] In this way, the second substrate and / or the dielectric layer and enclosed vias used to form a residual dielectric layer (RDL) can partially or completely replace wire bonds or other conventional interconnection techniques. Furthermore, since the second substrate can be provided using silicon or variations thereof (e.g., silicon carbide (SiC)), active or passive devices can be embedded within the second substrate, increasing the flexibility of available module design options while further reducing the module size. Thus, the described techniques can be used to complement or replace conventional semiconductor packages, including for high-power semiconductor devices and modules.

[0026] Fig. Figure 1 is a cross-sectional view of a semiconductor module 100 according to exemplary embodiments. In the example from Fig. Figure 1 illustrates a semiconductor die 102 as a transistor with a gate pad 104, a source pad 110, and a drain pad 116. For example, the semiconductor die 102 can represent a silicon- or gallium nitride-based transistor, which may feature low on-resistance, reduced parasitics, fast and efficient switching behavior, and other advantages described herein, including improved capability for operation in high-current, high-power, and high-temperature environments. In other embodiments, the semiconductor die 102 can incorporate an insulated-gate bipolar transistor (IGBT), silicon carbide (SiC) diodes, or thyristors. Furthermore, these and other devices, and various combinations thereof, can benefit from the reliability and flexibility provided by the encapsulation and electrical routing techniques described below.

[0027] For example, the gate pad 104 is illustrated with a gate connection or gate contact 108 formed using a gate via 106. Similarly, the source pad 110 is illustrated with a source connection or source contact 114 formed using source vias 112. The drain pad 116 is arranged on a metal layer 118 that extends beyond the semiconductor die 102 and the vias 120 to provide electrical contact with a drain connection or drain contact 122. Fig. 1. Any suitable metal, e.g. copper, can be used to form the various electrical contacts and / or layers.

[0028] Accordingly, the gate contact 108, the source contact 114, and the drain contact 122 can be enclosed in a metallization layer that provides an RDL 124, enabling the type of flexible, reliable connections between the semiconductor die 102 and other components within a larger semiconductor module mentioned above, as illustrated and further described in various embodiments provided below. In other words, the RDL 124 establishes a simple and reliable contact with the semiconductor die 102, as shown, for example, in the Fig. 9 and Fig. 12 shown.

[0029] Furthermore, in Fig. 1. A dielectric 126 provides an encapsulation of the semiconductor die 102. The encapsulation dielectric 126 can be provided using any suitable non-conductive dielectric material, including, for example, silicon dioxide, silicon nitride, silicon oxynitride, or polyimide (PSP), to name a few. Such materials are widely used in semiconductor processing because of their ability to provide insulation, for example, in providing separation between metallization layers. Fig. In contrast, the dielectric 126 provides complete encapsulation of the semiconductor die 102 by extending around the semiconductor die 102 and the vias 106, 112, 120, as well as around the metal layer 118. In particular, a dielectric layer 128 ensures the separation between the encapsulated semiconductor die 102 and a substrate 130.

[0030] The substrate 130 can be provided using any suitable material, including a semiconductor material such as silicon or other suitable materials, including, for example, metal, ceramic, or glass. A heat sink 132 can be attached to the substrate 130. As just mentioned, the dielectric layer 128 in Fig. 1 provides electrical insulation between the semiconductor die 102 and the substrate 130, thus enabling the use of the heat sink 132. In other implementations, e.g., as in the examples of the Fig. As shown in Figures 2B to 2F, the metal layer 118 can be formed directly on the substrate 130, i.e., it can be electrically isolated from the substrate 130.

[0031] The use of substrate 130 and encapsulation dielectric 126 enables the use of otherwise standard techniques for the fabrication or processing of the semiconductor module 100, as described below with regard to the Fig. 2A to 2F are illustrated and described in more detail. The dielectric 126 is capable of being used as an encapsulation material, due in part to the superior thermal management techniques described herein, including the potential for top and / or bottom cooling, with bottom cooling being achieved in Fig. 1 is illustrated by the use of the dielectric layer 128 and the heat sink 132.

[0032] Fig. 2A is a cross-sectional view of an exemplary processing stage for the formation of the semiconductor module from Fig. 1. In Fig. 2A, a substrate 202 can represent any suitable substrate, such as a silicon substrate. For example, a 300 mm silicon wafer can be used, as in relation to the Fig. 14 and Fig. 15 described in more detail.

[0033] Subsequently, a dielectric layer 204 can be deposited onto the silicon wafer using any suitable deposition technique. The dielectric layer 204 corresponds to the dielectric layer 128 from Fig. 1 and provides electrical insulation between the substrate 202 and a metal layer 206, wherein the metal layer 206 is made of metal layer 118 Fig. 1 corresponds to.

[0034] The metal layer 206 with the desired thickness and structure can be deposited on the entire silicon wafer. That is to say, Fig. Figure 2A illustrates the metal layer 204 on a reticulum of a wafer, wherein the metal layer 204 can be copied a desired number of times across the entire wafer to create multiple instances of the semiconductor module 100. Fig. 1 to obtain for one wafer.

[0035] In the Fig. In 2B to 2F, the dielectric layer 204 is omitted, thus enabling electrical connectivity to the substrate 202. That is, as in Fig. As shown in Figure 2B, the metal layer 206 is formed directly on the substrate 202. A semiconductor die 208 is then attached to the metal layer 206 (e.g., soldered or sintered). This means that multiple instances of the semiconductor die 208 can be placed on the entire wafer for each semiconductor module to be formed.

[0036] Then a dielectric layer 210, which is made of dielectric layer 126 Fig. 1 corresponds to the entire wafer, including the substrate 202 and the metal layer 206. Fig. 2B, deposited. Standard processing techniques can be used to achieve any desired structuring of the dielectric layer 210 across the entire wafer and to obtain a substantially flat surface of the dielectric layer 210. Accordingly, as with respect to Fig. 1 described and illustrated and how in Fig. 2B shows the semiconductor die 208 completely encapsulated or embedded by the dielectric layer 210.

[0037] In Fig. 2C, vias 212 are formed, e.g. etched, to establish contact with the semiconductor die 208. Then in Fig. 2D, and in accordance with the example from Fig. 1. Metal is deposited or otherwise provided within the vias 212 to provide a gate contact 214, a source contact 216, and a drain contact 218. As also with regard to Fig. As described in Figure 1, contacts 214, 216, 218 provide an RDL 220 which enables a flexible, reliable and uncomplicated connection with the semiconductor die 208.

[0038] Fig. 2E is a cross-sectional view of an exemplary processing stage for the formation of the semiconductor module from Fig. Figure 2D illustrates additional exemplary optional contacts 222, 224, 226, which are formed in vias in a dielectric layer 227 and provide an electrical connection through it. That is, the contacts 222, 224, 226 represent metal contacts that provide a gate contact 222, a source contact 224, and a drain contact 226, which together provide a second RDL 228. The second RDL 228 thus enables additional connection options for the semiconductor die 208. More generally, any number of such RDL layers can be provided as required to enable the desired connections to the semiconductor die 208.

[0039] Fig. 2F is a cross-sectional view of a final processing stage for the semiconductor module made of Fig. 2B. In Fig. 2F will be the substrate 202 made from Fig. 2E is subjected to a grinding process or another type of thinning to obtain a thinned substrate 230. Subsequently, a back-side metal 232 can be added to, for example, provide another connection for the semiconductor die 208 (e.g., to a drain connection thereto). Subsequently, singulation or another separation process can be performed to obtain individual or groups of semiconductor modules. The resulting exemplary embodiment from Fig. 2F can therefore be considered similar to the one from Fig. 1 and Fig. 2A can be viewed, however without the electrical insulation provided by the dielectric layer 128. Fig. 1 or the dielectric layer 204 made of Fig. 2A is provided.

[0040] The exemplary embodiments from Fig. 1 and 2A to 2F, together with various other exemplary embodiments described below, offer several advantages. For example, the use of a sufficiently high-quality dielectric as the encapsulation material ensures high-voltage insulation while maintaining good thermal conductivity and, in particular, provides superior thermal performance compared to conventional substrates such as Active Metal Brazing (AMB) or Direct Bond Copper (DBC) substrates.

[0041] The described techniques enable the creation of vias using etching techniques (instead of drilling methods, e.g., laser drilling), making via formation cost-effective and allowing for very good depth control. Furthermore, these techniques accelerate the time from order to delivery of the modules. For example, design can be performed using standard semiconductor manufacturing and testing techniques (and automation), without requiring a separate packaging process or tooling. Similarly, semiconductor design tools can be used for automation and for extracting electrical and mechanical properties, such as parasitics, from fixtures.

[0042] In addition to improved device parasitics, package parasitics are also enhanced through controlled and optimized impedances in a redistribution layout. Furthermore, exemplary embodiments provide excellent thermal properties, including the potential for dual-sided cooling with an optimized heat path. The described modules can be easily extended to include multiple (identical or different) base devices, as well as embedded passive devices and active circuit arrangements, including MEMS.

[0043] Various components and elements are mentioned above in relation to Fig. 1 and the Fig. Sections 2A to 2F and those described below should be understood as non-limiting examples. For instance, a substrate used may include Si, SiC, GaN, sapphire, diamond, or a similar semiconductor or insulating material. Accordingly, any specific quality or property of such a substrate (e.g., electrical, thermal, mechanical, chemical, or physical property) may be manufactured / selected. Substrates may be processed at the wafer level with standard wafer diameters (e.g., 2", 4", 6", 8", 12") and / or originate from sliced ​​ingots. Substrates may have an initial target thickness and may be thinned in a further processing step (e.g., after die and interlayer dielectric (ILD) / RDL application) to achieve the overall target thickness of the final product. Substrates may be preprocessed to incorporate semiconductor features (e.g.,Transistors, which are manufactured using standard semiconductor wafer manufacturing techniques such as doping or photodevelopment), and / or they can be pre-processed to include other features such as MEMS or metal-insulator-metal structures (MIM structures) such as MIM capacitors.

[0044] One or more of many types of backside treatments can be applied. For example, backside treatments (e.g., after wafer thinning) can be provided using known / standard processing techniques. For example, copper or diamond can be used due to their good thermal conductivity and / or heat distribution. Metallization with plating and / or an inert dielectric can be provided for passivation. Mechanical bonding (e.g., soldering, sintering, etching) can be used.

[0045] Mechanical bonding to the environment and / or electrical connection can be achieved, for example, by soldering, sintering, and / or etching. Back-side surface treatments also provide mechanical stress control, for example, to prevent wafer warping and to adjust the coefficient of thermal expansion. For example, a back-side metal (e.g., copper or aluminum with a plating / surface treatment such as silver or a silver alloy for contact formation and / or with a non-conductive material (e.g., a dielectric) for passivation) can be applied by sputtering or similar techniques. In addition to controlling wafer warping and other mechanical stresses, the thickness of the metal layer can be determined or optimized, for example, to...to achieve a minimum / maximum resistance value for a given layout (width, length), to meet target specifications for the melt flow such as a minimum value, a target value or a maximum value and / or to achieve cost targets (e.g. by using a thinner layer to reduce costs).

[0046] As mentioned above, dielectric layers can be formed using any suitable dielectric material that can be deposited using standard wafer processing techniques such as chemical vapor deposition (CVD), lamination, sputtering, or printing (e.g., screen printing) and, if required, associated processing such as photoresist / development, etching, drilling, grinding, or polishing. The composition and thickness of each layer can be tailored to and suited to a target blocking voltage, electrical potential to be blocked, and / or leakage current, e.g., such that the embedded semiconductor dies essentially determine the overall blocking voltage and / or leakage currents (e.g., using a thinner ILD for low-voltage applications and a thicker ILD for high-voltage applications).

[0047] Embedded semiconductor dies, which may be included in the described embodiments, can, in addition to the examples mentioned above, include non-power semiconductor devices such as digital, analog, or mixed-signal integrated circuit devices (ICs), e.g., a gate driver IC. In addition to Si, SiC, or GaN, composite devices such as silicon-on-insulator (SOI) or GaN-on-Si can be used. Embedded devices can also include non-semiconductor, passive, or discrete electronic components, such as a resistor, capacitor, or inductor, implemented in any form (e.g., semiconductor, thin film, multilayer ceramic chip (MLCC), or otherwise).More generally, virtually any device can be used whose thickness is compatible with the described embedding techniques, some of which are described and illustrated below, and which, for example, encloses MEMS components or a copper block.

[0048] A single semiconductor die or multiple (possibly different) dies can be enclosed in a single module. For example, a SiC transistor with a Si gate driver IC and decoupling capacitors can be embedded in a single module. It can also enclose an entire subcircuit, circuit, or even a complete system (e.g., a power supply system). Different dies can have different thicknesses and can be attached to the die using known / common techniques. Such techniques may include, but are not limited to, solder, diffusion bond, sintering, epoxy / adhesive, or other methods to achieve mechanical bonding and / or electrical conductivity. One or more dies can be enclosed in a flip-chip orientation (e.g., inverted compared to the examples from [reference]). Fig. 1 and from the Fig. 2A to 2F), wherein the enclosed metals are structured accordingly. For example, in embodiments with cavities, as in the following Fig. Figure 3 shows vertical current flow MOSFETs positioned so that the gate and source terminals point into the cavity and a drain points upwards / out of the cavity.

[0049] Vias can be fabricated at the wafer level using standard semiconductor fabrication techniques, such as photoresist etching or other well-known / standard techniques. Etching can be performed using a selective chemical process that exhibits a faster etch rate in the dielectric compared to the metal contact, thus achieving good depth control. Vias can be any shape and / or size deemed relevant and / or optimal in terms of processing, cost, and electrical properties. Multiple vias can be arranged in parallel to form an array.

[0050] Each RDL can be configured as a single layer (e.g., top metal) or as any number of layers (e.g., nested layers of ILD and RDL with vias connecting one metal layer to the next through the ILD). Similar to the other metal layers described above, each RDL can be configured using any metal (pure or alloyed), typically exhibiting high electrical conductivity, and can be plated or surface-treated. The metal used can have a thickness relevant for achieving a specific target resistance, melting current, or electromigration, e.g., on the order of about 1 µm to 50 µm.Metal can be deposited by standard wafer processing techniques such as CVD, sputtering or similar techniques, or it can be plated by electroless plating, electrolysis or other known techniques.

[0051] An RDL can be passivated using conductive or non-conductive passivation materials / techniques. An RDL can be processed using known techniques for purposes that include, but are not limited to, the implementation of MIM capacitors, embedded inductors or resistors, or MEMS. Many different applications can be achieved with such integrations, some of which are described and illustrated in detail below, such as integrated liquid cooling, sensors, or mechanical microrelays.

[0052] Fig. Figure 3 is a cross-sectional view of a semiconductor module 300 with a cavity 334 according to exemplary embodiments. Similar to in Fig. 1, closes Fig. 3 a semiconductor die 302 with a gate pad 304, which is connected to a gate contact 308 via a gate via 306, a source pad 310, which is connected to a source contact 314 via a source via 312, and a drain pad 316, which is connected to a metal layer 318 and thereby to a drain contact 322 via a drain via 320. In this way, an RDL 324 is formed on a surface of a dielectric 326, which embeds and encapsulates the semiconductor die 302.

[0053] A dielectric layer 328 (similar to the dielectric layer 128 made of Fig. 1 or the dielectric layer 204 from Fig. 2A) separates the metal layer 318 from a substrate 330. A metal layer 332 is arranged on a surface of the substrate 330 that faces the semiconductor die 302. Similar to the example from Fig. 2E are additional optional contacts 336, 338, 340 encapsulated in a dielectric layer 335. That is, contacts 336, 338, 340 represent metal contacts that provide a gate contact 336, a source contact 338, and a drain contact 340, which together provide a second RDL 341. The second RDL 341 thus enables additional connection options for the semiconductor die 302. More generally, as with respect to Fig. 2E noted that any number of such RDLs can be provided as required to enable desired connections to the semiconductor die 302.

[0054] In addition to compatibility with all possible variants of the embodiments of Fig. 1 and the Fig. 2A to 2F enables the inclusion of the cavity 334 in the embodiment shown Fig. 3 a precise and secure placement and embedding of the semiconductor die 302. The exemplary embodiment from Fig. 3 can be very similar to the example from Fig. It can be structured as 2A to 2F. For example, before the processes from the Fig. 2A to 2F the cavity 334 within the substrate 202 from Fig. 2A will be trained, after which the remaining processes will be completed from the Fig. 2A to 2F can be continued.

[0055] In Fig. 3. The cavity 334 can be formed using wafer processing techniques (or combinations thereof), including but not limited to the following techniques. For example, dry or wet etching processes can be used, such as reactive ion etching (RIE) or tetramethylammonium hydroxide (TMAH)-based etching, respectively. The cavity 334 can also be produced by mechanical grinding, drilling, or punching. In other examples, instead of forming the cavity within an existing substrate, mesa generation can be performed on a substrate surface to define a cavity relative to mesas formed by deposition (e.g., by CVD, sputtering, or lamination).

[0056] Although Fig. Figure 3 illustrates a single cavity containing a single semiconductor die. Other exemplary semiconductor modules may have multiple cavities, each containing one or more semiconductor dies, and / or a single cavity containing two or more dies. Different cavities within a single module / wafer may have different depths.

[0057] In other implementations, a single cavity can have local areas with different depths. For example, half of a cavity might have a depth suitable for one embedded die, while the other half of the cavity might be deeper to accommodate a different embedded die of a different thickness. Fig. 3 is the depth of the cavity 334 similar to the thickness of the semiconductor die 302. More generally, the depth of a cavity can essentially be the same as the thickness of an embedded die, or it can be deeper or shallower.

[0058] When one or more embedded dies are arranged in one or more cavities, a semiconductor die(s) can be embedded inside a cavity, on a mesa (outside a cavity), and / or a combination thereof (if multiple dies are enclosed). If multiple dies of different thicknesses are enclosed, then, as just mentioned, the dies can be arranged in cavities of different depths, with each cavity depth being partially determined by the corresponding thickness of the embedded die. In other implementations, the die(s) can be provided in a single cavity of uniform depth and / or in a single cavity of varying depth.

[0059] Fig. Figure 4 is a cross-sectional view of an exemplary embodiment of a semiconductor module 400 with a second substrate. Similar to the Fig. 1 and Fig. 3 closes Fig. 4 a semiconductor die 402 with a gate pad 404, which is connected to a gate contact 408 via a gate via 406, a source pad 410, which is connected to a source contact 414 via a source via 412, and a drain pad 416, which is connected to a metal layer 418 and thereby to a drain contact 422 via a drain via 420. In this way, an RDL 424 is formed on a surface of a dielectric 426b, which embeds and encapsulates the semiconductor die 402.

[0060] In Fig. 4 is the metal layer 418, similar to the examples from the Fig. 2B to 2F are arranged directly on a substrate 430. A metal layer 432 is arranged on a surface of the substrate 430 that faces the semiconductor die 402. Similar to in Fig. 3 is the semiconductor die 402 arranged in a cavity 434.

[0061] In Fig. 4 The semiconductor module 400 includes a first section 400a on which a second section 400b is arranged. As stated above and explained in more detail below, the semiconductor module 400 can be fabricated using wafer-to-wafer bonding or at the panel / reticle level.

[0062] In any case, a dielectric layer 426a is joined with the dielectric layer 426b, as shown below with reference to Fig. 5A is explained in more detail. A second substrate 436 borders the dielectric layer 426a, with a dielectric layer 438 arranged on the second substrate 436. Accordingly, the vias 406, 412, 420 extend through all dielectric layers 426a, 426b, the second substrate 436 and the dielectric layer 438, with the RDL 424 on the dielectric layer 438 in Fig. 4 is trained.

[0063] In addition to compatibility with all possible variants of the embodiments of Fig. 1 and 2A to 2F enable the inclusion of the second section 400b in the embodiment of the Fig. 4. Many different embodiments can be achieved by substituting different materials and / or thicknesses for the second section 400b, e.g., for the second substrate 436. For example, if the second substrate 436 includes silicon, one or more additional semiconductor dies can be included therein, as in the exemplary embodiment shown in [reference]. Fig. Figure 7 shows that these dies can then be connected to the semiconductor die 402 to achieve a design goal, such as using multiple interconnected devices to form a half-bridge.

[0064] Fig. 5A and Fig. Figure 5B shows cross-sectional views of a first processing stage and a second processing stage to form the exemplary embodiment. Fig. 4. In Fig. 5A will be a first section 500a using the techniques from the Fig. 2A and Fig. 2B with the cavity made of Fig. 3 constructed. As shown by the dashed line and the arrows in Fig. As shown in Figure 5A, a second section 500b is joined to the first section 500a. For example, the second section 500b can be part of a cap wafer bonded to a wafer enclosing the first section 500a. For example, opposing planar dielectric surfaces 526a, 526b of sections 500a, 500b can be bonded together to arrange a second substrate 536 above the semiconductor die 402.

[0065] In Fig. 5B the gate vias 406, the source vias 412 and the drain vias 420 are formed by, for example, the second substrate 536 from Fig. 5A is etched through to reveal the second substrate 436 from Fig. 4 to form, and by etching the bonded dielectric layers 526a, 526b to form the etched dielectric layers 426a, 426b from Fig. 4 to form. Accordingly, the gate contact 408, the source contacts 414 and the drain contacts 422 can be made from Fig. 4, as in Fig. 4 shown, provided to thereby transmit all electrical signals of the semiconductor die 402 to an upper surface of the module 400 as RDL 424. Fig. 4 to redistribute.

[0066] When wafer-to-wafer bonding is used, the second section 500b can be understood as part of a lid wafer bonded to the top surface of an underlying wafer of the first section 500a. For example, such bonding can include any suitable bonding technique(s), including hybrid bonding (where electrical contact points exist between the substrate surface of the first section 500a and the lid surface of the second section 500b) or wafer bonding (such as full oxide bonding between flat surfaces of dielectric layers 526a, 526b, where electrical contacts are made by vias after the bonding process, as in Fig. 5B shown).

[0067] Once the structure is made up Fig. Once step 4 is completed, further processing can be carried out. For example, further processing can be performed from Fig. 2E, including the addition of further RDLs, can be carried out. More generally, all of the above can be applied to the Fig. The variants described in points 1 to 3 are included, as well as many other variants, some of which are explained below in the context of other exemplary embodiments.

[0068] In the exemplary embodiments from the Fig. 4, Fig. 5A and Fig. 5B can be a top or cover wafer (e.g., of the second section 500b from Fig. 5A) include an unprocessed or processed version of the 436 / 536 substrate. For example, included or processed features may include any semiconductor circuit arrangement and / or associated wafer processing such as doping. The features may include passive elements such as copper blocks, resistors, capacitors, or inductors. The features may include MEMs or other devices that can be fabricated on a wafer.

[0069] Each of the substrates 430 and / or 436 / 536 can be made of, for example, an insulating material (e.g., sapphire), a semiconductor material (e.g., silicon or GaN), or a conductive material (e.g., a metal such as copper). The substrates 430 and / or 436 / 536 can be the same or different of these or other materials. If the material(s) include silicon, the various vias 406, 412, 420 can be configured as through-silicon vias (TSVs). One or both of the wafers used can have any desired and available thickness.

[0070] Fig. Figure 6 is a cross-sectional view of an exemplary embodiment with stacked devices. Fig. Section 6 includes a semiconductor die 602a with a gate pad 604a, which is connected to a gate contact 608a via a gate via 606a, a source pad 610a, which is connected to a source contact 614a via a source via 612a, and a drain pad 616a, which is connected to a metal layer 618a and thereby to a drain contact 622a via a drain via 620a. In this way, an RDL 624a is formed in a dielectric 626, which embeds and encapsulates the semiconductor die 602a.

[0071] In Fig. 6 is similar to the examples from the Fig. 1 and Fig. 2A, the metal layer 618a is arranged on a dielectric layer 628, which in turn is arranged on a substrate 630. A metal layer 632 is arranged on a surface of the substrate 630 that faces the semiconductor die 602a.

[0072] Fig. Figure 6 further illustrates a semiconductor die 602b with a gate pad 604b connected to a gate contact 608b via a gate via 606b, a source pad 610b connected to a source contact 614b via a source via 612b, and a drain pad 616b connected to a metal layer 618b and thereby to a drain contact 622b via a drain via 620b. In this way, an RDL 624b is formed on a surface of the dielectric 626 that embeds and encapsulates the semiconductor die 602b.

[0073] The embodiment from Fig. 6 and variants thereof can be developed using (e.g. by iteration) the above with respect to the Fig. The techniques described in sections 2A to 2F are used. Other variations can be included, e.g., one or both of the semiconductor dies 602a, 602b can be arranged in a cavity. Although in Fig. Figure 6 illustrates only the semiconductor dies 602a and 602b; however, virtually any desired number of semiconductor dies can be included. The various semiconductor dies and associated layers can have any desired thickness and can have the same or different thicknesses relative to each other. Fig. 6 can be used to implement a power half-bridge, but many other power or non-power circuits can also be constructed, e.g. full-bridge, T-type, parallel, antiparallel, series or anti-series circuits.

[0074] Fig. Figure 7 is a cross-sectional view of an exemplary embodiment with stacked modules 700a, 700b. Fig. Figure 7 includes the stacked module 700a with a semiconductor die 702a having a gate pad 704a, which is connected to a gate contact 708a via a gate via 706a, a source pad 710a, which is connected to a source contact 714a via a source via 712a, and a drain pad 716a, which is connected to a metal layer 718a and thereby to a drain contact 722a via a drain via 720a. In this way, an RDL 724a is formed at a junction of a dielectric 726a and a dielectric 726b, similar to the embodiment shown in Figure 7. Fig. 4, wherein the dielectric 726a embeds and encapsulates the semiconductor die 702a. As further illustrated, the semiconductor die 702a is arranged within a cavity 734a, similar to the embodiment shown in Fig. 3.

[0075] In Fig. Figure 7 shows the metal layer 718a arranged on a substrate 730a. A metal layer 732 is located on a surface of the substrate 730a that faces the semiconductor die 702a.

[0076] Fig. Figure 7 further illustrates the stacked module 700b with a semiconductor die 702b within a cavity 734b, which has a gate pad 704b connected to a gate contact 708b via a gate via 706b, a source pad 710b connected to a source contact 714b via a source via 712b, and a drain pad 716b connected to a metal layer 718b and thereby to a drain contact 722b via a drain via 720b. In this way, an RDL 724b is formed on a surface of the dielectric 726b, which embeds and encapsulates the semiconductor die 702b.

[0077] In Fig. Figure 7 shows the metal layer 718b arranged on a substrate 730b. A via 715a through the substrate 730b and the dielectric 726b is used to create a source contact 717a for the semiconductor die 702a. A via 715b through the substrate 730b and the dielectric 726b is used to create a contact 717b that is connected to the drain contact 722a of the semiconductor die 702a and to the source contact 714b of the semiconductor die 702b.

[0078] The embodiment from Fig. 7 and variants thereof can be developed using (e.g. by iteration) the above with respect to the Fig. 2A to 2F and the Fig. 5A, Fig. Techniques described in 5B are formed.

[0079] Other variants can be included, e.g. illustrated. Fig. 7 Two stacked modules 700a, 700b, but any number of modules can be stacked. In Fig. 7. The stacked modules 700a and 700b include the same types of semiconductor dies as 702a and 702b, but different devices can also be used. Similarly, the substrates 730a and 730b can be made of the same material, have the same thickness, or be different.

[0080] Bonding techniques for bonding the modules 700a and 700b may include wafer bonding (e.g., dielectric to dielectric), hybrid bonding (e.g., a mixture of conductor and dielectric, as shown), or any other suitable bonding method. In some embodiments, one wafer may be flip-mounted relative to the other wafer (e.g., flip-chip mounted), or the wafers may have the same orientation as each other. Similarly, wafers and enclosed devices may have the same grid / rotation as each other, or they may be rotated relative to each other with any desired target angle of rotation.

[0081] Fig. Figure 8 is a cross-sectional view of an exemplary embodiment of a semiconductor module with back-side contacting. Fig. Figure 8 comprises a semiconductor die 802, a gate pad 804 connected via a gate via 806 to a gate contact 808, a source pad 810 connected via a source via 812 to a source contact 814, and a drain pad 816 connected to a metal layer 818 and thereby via a drain via 820 to a drain contact 822. In this way, an RDL 824 is formed on a surface of a dielectric 826, which embeds and encapsulates the semiconductor die 402 in a cavity 834.

[0082] In Fig. In section 8, the metal layer 816 is arranged directly on a substrate 830 and on backside contacts 836, 838, which are connected to a metal layer 832. As shown, the backside contacts are formed by means of vias 837. In this way, contact can be made on both surfaces of the module. Fig. 8 an electrical connectivity to the drain pad 816 is established.

[0083] In Fig. In the case of die 8 and similar examples, a back side (drain) of the semiconductor die 802 can be achieved using various techniques. For example, wet or dry etching, or other silicon etching techniques, can be employed. Mechanical processes such as drilling, grinding, or milling / machining can also be used. Other possible techniques include laser or plasma drilling.

[0084] Fig. Figure 8 illustrates an example where parallel TSVs or other vias 837 are used to provide a structured metal contact. In other examples, the substrate 830 can be thinned to such an extent that the metal layer 818 directly contacts the metal layer 832.

[0085] In other aspects and examples, the 802 semiconductor die can be provided with a low-resistance contact on the back side (e.g., a drain) by any suitable method. For example, conductor deposition techniques (e.g., structured or unstructured) such as CVD, sputtering, or electroplating can be used. In other examples, the die attachment of a conductor connector (e.g., a copper puck) can be performed, for example, by soldering, diffusion soldering, sintering, or bonding with anisotropic conductive adhesive (ACA).

[0086] Different thickness levels can be selected for one or more of the metal layers 818, the backside contacts 836, 838, and / or the metal layer 832. During etching, a stop material can be used on the bottom of cavity 834 for backside machining; that is, a backside etch stop can be provided. In other examples, a washer can be installed between the semiconductor die and the bottom of cavity 834 (e.g., a piece of copper) to help stop backside grinding / etching / drilling. In this way, access to the drain contact 816 (or another conductive element of the semiconductor die 802) can be provided without penetrating completely to the semiconductor die 802 itself.

[0087] Fig. Figure 9 is an exemplary embodiment illustrating the simple connection of a semiconductor module constructed using the described techniques to allow adaptation of the footprint to existing packages (or other desired footprint(s)). Fig. Figure 9 illustrates a semiconductor module 900a, which is of the embodiment consisting of Fig. 3 is similar, but without the insulating layer 328. Or, in other words, similar to the embodiment from Fig. 2F, however with cavity 334 made of Fig. 3. The in Fig. However, the exemplary module 900a shown in Figure 9 is not restrictive, and any of the described embodiments or variants thereof may be used instead of module 900a.

[0088] In Fig. Module 900a includes a semiconductor die 902 and an RDL 924, which includes a gate contact 908, a source contact 914, and a drain contact 922, constructed using the techniques described above. Other elements of module 900a correspond to elements already described and are not specifically named or described here for the sake of brevity.

[0089] Furthermore, in Fig. Figure 9 illustrates a package 900b constructed using module 900a, which has a square flat footprint (Quad Flat No-lead, QFN) without lead connections. Fig. Figure 9 illustrates that the module 900a, with contacts 908, 914, and 922 and / or the RDL 924, can be designed to match and thus form the footprint of the package 900b, including contacts 901, 903, and 905. In other words, the module 900a illustrates a design approach in which the module 900a provides an embedded device designed to have the same physical and electrical layout as the QFN package 900b.

[0090] In particular, the QFN package 900b refers to a type of surface-mount integrated circuit package without protruding power terminals, wherein the electrical contacts 901, 903, 905 are flat and located on a lower surface, which generally allows direct soldering onto a printed circuit board (PCB) (in Fig. (9 not shown). By adapting to the footprint of the QFN package 900b, the 900a module can be seamlessly integrated into existing printed circuit board designs without requiring any changes to the board layout. This compatibility ensures that the 900a module can replace or operate interchangeably with traditionally packaged devices while maintaining the same or better electrical connections and performance characteristics. Fig. 9 corresponds to the specific QFN footprint shown in module 900b, a module with several different dies forming 2 half-bridges with corresponding gate drivers, while the example of embedded module 900a is simplified for brevity and illustration and does not explicitly show the corresponding number of embedded dies and connectivity.

[0091] In one specific exemplary embodiment, the embedded module 900a can be designed to replicate the footprint of a power stage, which is a component that includes gate driver circuits, high-side (HS) switches, and low-side (LS) switches. Gate drivers are circuits that control the switching of power transistors, while high-side and low-side switches are typically metal-oxide-semiconductor field-effect transistors (MOSFETs) used in power management applications such as voltage regulation or motor control. By adapting to this power stage footprint, the embedded module 900a can serve as a direct replacement, acting as a second source that is compatible in form, fit, and function with a QFN power stage product.Consequently, the embedded module 900a fits into the same physical space and pin layout while performing the same or better electrical functions, thus providing a reliable option that does not require redesigning existing circuit boards or other packaging elements.

[0092] Furthermore, the embedded module 900a offers improved thermal performance compared to traditional QFN packages. For example, conventional packages can be overmolded with epoxy resin (EMC), a plastic material that encapsulates a chip but has relatively poor thermal conductivity. In contrast, in one embodiment and using the disclosed techniques, the embedded module 900a can incorporate a heat sink attached to a surface of the substrate 930 of the module 900a, thereby enabling improved heat dissipation in one direction away from a printed circuit board. The substrate 930, as described herein, can incorporate silicon or another material(s) with high thermal conductivity to transfer heat more effectively than the EMC used in conventional packages.Thus, the embedding process described here effectively provides a package that allows the embedded 900a module to function like a conventionally packaged die, chip, system-on-chip (SoC) or system-in-package (SiP), while offering improved cooling and compatibility with standard QFN footprints.

[0093] Fig. Figure 10 is a cross-sectional view of an exemplary embodiment with nested modules. Fig. Module 1000 is trained according to the techniques described above. In particular, Module 1000 is similar to Module 900a from Fig. 9 trained, however any of the modules or variants described above can be used.

[0094] Furthermore, in Fig. 10. The module 1000 is arranged in a cavity 1034 formed in a substrate 1030, wherein an intermediate metal layer 1032 is arranged on the substrate 1030 and lines the walls and the lower surface of the cavity 1034. The module 1000 is embedded in a dielectric 1026. A gate contact 1036, a source contact 1038, and a drain contact 1040 form an RDL 1024 and can be formed using the techniques described above.

[0095] Thus, it illustrates Fig. 10. One or more semiconductor dies can be embedded using the described techniques, with further packaging that includes further embedding in another embedded module. Such recursive embedding can be provided any number of times. Further packaging can be provided using traditional packaging technologies such as leadframe, bond wires, EMC, and / or gel-filled module(s), to name just a few.

[0096] Further packaging can be provided using wafer-scaled / wafer-level packaging techniques and / or panel-level packaging techniques. Other examples may employ PCB embedding techniques or other packaging techniques.

[0097] Fig. Figure 11 illustrates a first exemplary use case for the exemplary embodiment from Fig. 10. In particular, illustrates Fig. 11 the integration of a component 1102, which can easily be connected to one or more of the contacts 1036, 1038, 1040 of the module of Fig. 10 can be added / connected to these. For example, component 1102 can represent a busbar, or it can represent various types of electrical components, as explained in the more detailed examples below.

[0098] As just mentioned, component 1102 can, for example, represent a busbar. In the context of semiconductor packaging, a busbar refers to a relatively thick conductive structure used to improve electrical performance. For example, a busbar might enclose a metal strip or rod (e.g., made of a highly conductive material such as copper or copper alloys) used to transmit high electrical currents or to efficiently distribute power.

[0099] As from the Fig. 10 and Fig. As can be seen in Figure 11, contacts 1036, 1038, and 1040 can be thicker than the corresponding contacts of module 1000, the thickness of which may be limited by size or manufacturing constraints during the manufacturing process(s). Consequently, such relatively thin conductors produced during wafer fabrication may exhibit relatively higher electrical resistance and / or be prone to problems such as overheating or electromigration. In contrast, busbars, such as those formed by component 1102, are thicker and can handle higher currents with lower resistance. Therefore, by attaching busbars as component 1102 to the embedded module 1000, performance targets (e.g.,Reduction of electrical resistance, increase in melting current and attenuation of electromigration) are achieved, thereby improving reliability and efficiency in applications such as power electronics or high-current systems.

[0100] In Fig. 11 The component 1102, which represents a busbar, can be bonded to the contacts 1038, 1040 via openings 1108 in an insulating layer 1104, e.g. using solder contacts 1106. More generally, any soldering, diffusion soldering, sintering or ACA bonding can be used.

[0101] Busbar integration can be performed prior to packaging steps such as gel filling, injection molding, or transfer forming. By placing busbars before these steps, the embedded Module 1000 gains electrical performance while remaining compatible with standard packaging processes. This approach enables the Module 1000 to operate in high-power applications and offers superior current handling capabilities compared to traditional thin conductors.

[0102] In other examples, as mentioned above, component 1102 can represent various other electrical components. For example, such components can include negative temperature coefficient (NTC) thermistors, multilayer ceramic capacitors (MLCCs), resistors, inductors, integrated circuits (ICs) for gate drivers, or other active or passive circuits, soldered or otherwise bonded to contacts 1036, 1038, and 1040 as described above. These and other components can be integrated to add specific, corresponding functionalities compatible with the existing PCB layout, while the various components can be directly integrated into the embedded module of Fig. 11 or other exemplary embodiments described herein, including the examples from the Fig. 1 to 9 will be integrated.

[0103] Other non-restrictive examples of components that can be embedded as component 1102 include semiconductor components, passive electronic components, and sensors. For example, semiconductor components such as transistors, diodes, microprocessors, or application-specific integrated circuits (ASICs) can be used to add processing or switching capabilities. Gate driver ICs can be used to drive power transistors in applications such as motor drives or inverters. Passive components such as resistors, capacitors, inductors, or transformers, or copper blocks (e.g., as an alternative to busbars for low-impedance conduction), can be used to facilitate or improve electrical performance.Sensors such as microelectromechanical systems (MEMS) or NTC thermistors enable environmental monitoring, including current monitoring (to provide a circuit breaker), as well as temperature measurement for thermal management in high-performance systems. Bonding one or more of these components before the final packaging steps (e.g., gel filling or EMC encapsulation) makes it possible to create compact, multifunctional modules that can be easily integrated into systems requiring high reliability and performance.

[0104] Fig. Figure 12 illustrates an exemplary use case for the exemplary embodiment from Fig. 9. In Fig. Module 1200a is constructed using the described techniques to provide contacts 1208, 1214, 1222, and can be used similarly to the one in Fig. 9 are enclosed in a QFN package, which is represented as module 1200b. A magnetic structure 1200c, for example, represents an inductor or inductors. The operation of the illustrated modules 1200a and 1200b is illustrated by a circuit diagram 1200d.

[0105] In detail, the magnetic structure 1200c, like an inductor, is illustrated as being connected to one side of module 1200a, which is opposite the side with the RDL 1224. This connection allows module 1200c to interface with the windings of the inductor, enabling compact integration of energy management functions directly onto the module, thereby reducing the need for external components and minimizing the overall size of the system.

[0106] As shown in the circuit diagram 1200d, a back-side connection to a Fig. 12 switching nodes, designated “1”, e.g., a midpoint of a half-bridge configuration, an electrical connection point where the inductor is connected to manage, for example, current or voltage fluctuations. The inductor windings are illustrated as dashed lines between nodes 1 and 2, 3 and 4, and 5 and 6. Conductive traces or thin metal paths, shown as dashed lines connecting nodes 2 and 3 and nodes 4 and 5, complete the windings of the magnetic structure 12000c (e.g., the inductor windings shown). These conductive traces effectively act as wires that wrap around or are connected to the core of the inductor, enabling the module 1200a to contribute to generating a magnetic field. Integrating these windings directly onto the surface of the module 1200a simplifies assembly and reduces parasitic losses (e.g.,Resistance or inductance from external connections are reduced, and performance in high-frequency or high-power applications is improved. In other examples, a self-contained instance of such a magnetic element can be integrated similarly without implementing the partial windings in the 1200a module.

[0107] Furthermore, the output of the magnetic structure can be redistributed, allowing an electrical output from the inductor (e.g., filtered or regulated current) within the 1200a / 1200b module to be redirected to other components, such as a filter capacitor, or routed externally via alternative paths. Such redistribution might involve, for example, additional backside traces or internal routing to optimize signal integrity or power supply. For instance, the inductor output could be connected to a filter capacitor within the module to stabilize the power supply for an embedded SoC or SiP, or it could be routed to an external capacitor outside the module for system design flexibility.

[0108] As mentioned above, many other components and associated functionalities can be enclosed in semiconductor modules constructed using the described techniques. For example, any substrate enclosed in such a module can contain virtually any component / functionality available in the context of wafer processing. This includes, for example, all active semiconductor elements, passive elements (e.g., resistors, inductors, or capacitors, including MIM capacitors), sensors, and MEM elements, including cooling channels and electromechanical relays.

[0109] In a specific example, Fig. 13 A circuit diagram illustrating the operation of a module according to exemplary embodiments, which operates as a solid-state relay, e.g. for switching high-voltage direct current (DC). In Fig. 13. The circuit arrangement 1302 can be an integrated / embedded or external / discrete circuit arrangement, which includes, for example, gate driver circuit(s). The circuit arrangement 1302 forms an interface with the gate of a power transistor 1304, which can be any of the semiconductor dies described above (e.g., the semiconductor die 102 from Fig. 1) The circuit arrangement 1302 further controls the actuation inputs of two relays 1306, 1308 of microelectromechanical systems (MEMS) which are arranged along a current path from an input node (In) to an output node (Out).

[0110] Furthermore, in Fig. The source of transistor 1304 is connected to the IN node, with MEMS relay 1306 positioned between the source and the drain to provide galvanic isolation between the IN and OFF terminals when the relay is in the OFF state. MEMS relay 1308 is connected between the drain of the transistor and the OFF node, thus completing the path. When the OFF state is activated (e.g., in response to an overcurrent condition), circuit arrangement 1302 sends signals to open the transistor and both MEMS relays 1306 and 1308, thereby establishing galvanic isolation between the IN and OFF terminals. If conductivity between ON and OFF is desired (e.g., when the relay is in the ON state), the MEMS relay 1308 ensures a very low resistance conduction path, independent of the resistance (or voltage drop) of the transistor in the ON state.The transistor ensures an extremely fast response time and the ability to interrupt a high DC current, which would otherwise lead to deterioration (arc formation) in a purely mechanical relay. The switch-on sequence, for example, consists of first closing relay 1308 (no current flow), then semiconductor 1304 (which establishes current flow without the risk of arcing / welding), and finally relay 1306, which improves current flow (reduces line resistance) but without the risk of arcing / welding, since current flow is already established and the voltage across relay 1306 is essentially 0 V at the time of switch-on. The switch-on sequence can be performed much faster than with traditional mechanical contactor operation.The switch-off sequence is reversed: First, relay 1306 is switched to OFF, thus switching the current to semiconductor channel 1304, preventing arcing at the relay contacts. Then, semiconductor 1304 is switched off to interrupt the current. Due to the nature of the semiconductor in the described embodiments, no arcing or other problems occur during this switch-off. After the current is completely interrupted, relay 1308 is switched off, ensuring galvanic isolation between ON and OFF. This switch-off occurs at a current of 0 A and therefore does not cause arcing or other problems that could affect the relay's service life.The shutdown sequence can be significantly faster than with traditional purely mechanical relay types, and the reliability / lifespan is considerably extended compared to purely mechanical relays, especially regarding the number of shutdown / start-up sequences that can be performed before performance deteriorates. The configuration consists of... Fig. 13 ensures safe, isolated operation because the MEMS relays 1306 and 1308 function as mechanical switches that physically open or close contacts without any electrical continuity between the input and output sides. Furthermore, since the components are integrated into an embedded module, the entire system is extremely small and easy to implement compared to, for example, non-integrated and / or non-embedded designs.

[0111] Power semiconductors, such as the transistor 1304, can be embedded elements, external elements, elements attached to the surface of the embedded module, or integrated as processed semiconductor elements in a substrate wafer (e.g., by doping). Similarly, the circuit arrangement 1302 can be an embedded element or elements, attached to the surface of an embedded module, or external (not integrated). The MEMS relays 1306 and 1308 can be implemented by wafer processing of an embedded wafer, or embedded as dies, attached to the surface of the embedded module, or external.

[0112] During operation, when a switching command is received, the circuit arrangement 1302 first applies the gate voltage to prepare transistor 1304 if needed, and then actuates the MEMS relays 1306 and 1308, closing their contacts sequentially. MEMS relay 1306 can thus be configured to route current for a low-loss path around transistor 1304, while MEMS relay 1308 directs the current flow to the output node. Opening MEMS relays 1306 and 1308 reverses the process, immediately isolating the path due to mechanical interruption without any residual voltage or current leakage.

[0113] Thus, the embodiment represents Fig. 13. A high-speed, low-loss (high current), very long-life solid-state relay is provided, capable of handling high-voltage direct current and offering galvanic isolation with minimal heat generation. The combination of the transistor's fast switching speed and the mechanical robustness of the MEMS relay enables rapid on / off times while handling high currents and voltages, surpassing the lifespan of traditional electromechanical relays. The galvanic isolation of the MEMS relay prevents high-voltage faults from propagating to the low-voltage control side, increasing safety in applications such as electric vehicles or renewable energy inverters. Specific implementation examples for the circuit are provided below. Fig. 13 and other exemplary modules that include MEM devices are described below, for example, in relation to the Fig. 34 to 36 provided.

[0114] Fig. Figure 14 shows a top view of section 1400 of a wafer used to fabricate modules, each containing four semiconductor dies. More specifically, a module 1402 is shown to contain four dies 1408, while a module 1406 is shown to contain four dies 1410. The lines 1404 define fields in which modules such as modules 1402 and 1406 can be formed. By providing multiple modules arranged in an array on the wafer, the parallel / simultaneous processing of multiple modules is enabled.

[0115] Fig. Figure 15 is a top view of the entire wafer made of Fig. 14. Fig. Figure 15 illustrates an exemplary wafer layout for a 300 mm wafer (1500). In the example from Fig. 89 modules or plates measuring 25 mm x 25 mm can be mapped onto the 1500 wafer. For example, plates 1502 and 1504 can be used to create modules 1402 and 1406. Fig. 14 correspond (i.e., be intended for their construction). In the specific example from Fig. 15 can be used for the layout Fig. Each of the four dies, 1408 or 1410, could be constructed as a square element with, for example, 5000 micrometers per side. Of course, many other sizes and dimensions are also possible.

[0116] Fig. Figure 16 is an exemplary implementation demonstrating dual thermal and electrical connectivity. Fig. 16 represents an embedded module 1602, any of the module implementations described above, such as the QFN-compatible module 900b from Fig. 9. As above, for example, with regard to Fig. As explained in Figure 9, the embedded module 1602 can be easily connected to a printed circuit board 1610 at its electrical surface 1608, for example, using conventional connection techniques. The embedded module 1602 can also be connected to a heat sink 1606 at an opposing thermal surface 1604. Accordingly, the implementation of Fig. 16 provided electrical connectivity with improved thermal management.

[0117] Thus, the foregoing exemplary embodiments illustrate embedded modules with an electrical surface that can be soldered onto a printed circuit board and / or other component(s). Similarly, leadframes, busbars, copper blocks, or similar elements can also be soldered to such embedded modules, which in turn can be connected to, for example, DC link capacitors, electrical machines, gate driver ICs, or similar elements.

[0118] The embedded modules described herein may be partially or completely covered with a dielectric material. Leadframes, busbars, copper blocks, or similar elements soldered to the electrical surface of such an embedded module may protrude from the dielectric material, thereby facilitating the electrical connection to the embedded module.

[0119] Fig. Figure 17 is an alternative exemplary implementation demonstrating dual thermal and electrical connectivity. Fig. Figure 17 shows both an embedded module 1702a and an embedded module 1702b having solder connections 1704 to a heat sink 1706. The connections 1708 join the embedded modules 1702a and 1702b to a printed circuit board 1710, which may also include any standard components 1714, such as integrated circuits, resistors, capacitors, or inductors. Thus, the following is illustrated: Fig. 17, that the described implementations can be easily scaled and otherwise efficiently combined to take advantage of the benefits provided.

[0120] Fig. Figure 18 illustrates an exemplary embodiment with multiple cavities. Fig. 18 includes a semiconductor die 1802 with a gate pad 1804, which is connected to a gate contact 1808 via a gate via 1806, a source pad 1810, which is connected to a source contact 1814 via source vias 1812, and a drain pad 1816, which is connected to a drain contact 1822 via drain vias 1820.

[0121] In Fig. The semiconductor die 1802 is arranged between a first substrate 1830 with a first cavity 1827 and a second substrate 1836 with a second cavity 1829. The cavities 1827 and 1829 together form a cavity 1834 in which the semiconductor chip 1802 is located. For example, the cavity 1834 can be an air cavity or, in other implementations, can be filled with a dielectric material or another insulating material.

[0122] As in previous embodiments, the substrates 1830, 1836 can be formed using any suitable material, including any semiconductor material such as silicon or GaN. Consequently, it is easy to form the cavities 1827, 1829 and the various vias 1806, 1812 and 1820 and to bond the substrates 1830, 1836 together. Fig. In 18, cavity 1827 is smaller (not as deep) than cavity 1829. However, in other versions, cavity 1827 may be larger / deeper than cavity 1829, or cavities 1827 and 1829 may be essentially the same size.

[0123] As in the example in Fig. As can be seen in Figure 18, the gate contact 1808 and the source contact 1814 are located on the same surface, while the drain contact 1822 is located on an opposite surface. Consequently, various corresponding types of electrical connections can be made.

[0124] For example, as in Fig. Figure 19 shows that several modules 1902, 1904, and 1906 can be joined together and used jointly. For example, modules 1902, 1904, and 1906 can be joined together and used with a common drain contact.

[0125] Fig. Figure 20A is an isometric view of an exemplary embodiment with a cooling block. Fig. 20B is a cross-sectional view of the exemplary embodiment from Fig. 20A. In the Fig. 20A and Fig. 20B thermally connects a multitude of thermally conductive vias 2014 to a cooling block and the embedded die 2008. The cooling block 2012 can effectively distribute the generated heat to another heat sink attached to the cooling block 2012. The heat is conducted both in the x / y plane for distribution and in the z direction for dissipation to the cooling block 2012 and / or another heat sink / heat exchanger.

[0126] Fig. Figure 21 is a 3D exploded view showing a cavity 2114 on the underside of a cover wafer 2104 and a cavity 2112 on the top side of a base wafer 2102. The electrical connections for source 2106, drain 2108, and gate 2110 are redistributed to the underside of the base wafer 2102. Fig. Figure 21 thus represents an example of an assembled package for the embodiments from the Fig. 18 to 20B ready.

[0127] Fig. Figure 22 illustrates an example of single-metal-layer routing for multiple dies, where die 2218 has a source pad 2212 routed via S1 routing to a source landing 2206, which can make electrical contact with module 2202. Die 2220 also has a source pad 2212 routed via S2 routing to S-landing 2206. Similarly, the gate of die 2218 is routed via G1 routing to G-landing 2210, while the gate of die 2220 is routed via G2 routing to the same G-landing 2210. Finally, the common drains of dies 2218 and 2220 are routed along the bottom of the package, as indicated by the dashed lines in Figure 22. Fig. 22 shown.

[0128] Fig. Figure 23 is a cross-sectional view of an exemplary double cavity design. Fig. Figure 23 illustrates a semiconductor die 2302 with a gate pad 2304 connected to a gate contact 2308 via a gate via 2306, a source pad 2310 connected to a source contact 2314 via source vias 2312, and a drain pad 2316 connected to a metal layer 2318 and thus to a drain contact 2322 via drain vias 2320. Accordingly, the module can be constructed from Fig. 23. can be connected to other elements using any suitable technique, including those mentioned above, as well as Cu columns, bond wires or various other methods.

[0129] In Fig. Figure 23 shows that the semiconductor die 2302 is arranged between a first substrate 2330 with a first cavity 2327 and a second substrate 2336 with a second cavity 2329. The cavities 2327 and 2329 together form a cavity 2334 in which the semiconductor die 2302 is arranged. For example, the cavity 2334 can be, as in Fig. 18, an air cavity or, in other implementations, it may be filled with a dielectric material or another insulating material.

[0130] Furthermore, in Fig. 23 an RDL 2324 is formed on a surface of the second substrate 2336. Accordingly, and in contrast to the example from Fig. 18 A dielectric or other electrically insulating layer 2332 can be formed on the first substrate 2330, and a metal heat sink 2333 can be connected to it.

[0131] In the example from Fig. 23. The gate vias 2306 and the source vias 2312 are formed by a relatively thin section of the second substrate 2336 between the cavity 2334 and the gate contact 2308 / source contact 2314. Meanwhile, the drain vias 2320 are formed by a thicker section of the second substrate 2336 adjacent to the cavity 2334.

[0132] Metal attachment points 2335 are fabricated to join the semiconductor die 2302 to layer 2318 and thus to the first substrate 2330, and to connect the second substrate 2336 to the first substrate 2330 and the semiconductor die 2302. Fig. The 23 metal attachment points 2335 are metal-to-metal connections, but other connections can also be used. The metal attachment points 2335 can be referred to as die attachment points when they are connected to the leads of the semiconductor die 2302, or as substrate attachment points when they are connected to the first substrate 2330 and / or the second substrate 2336. Fig. As illustrated, the cavity 2327 is shallower than the cavity 2329, or, in other words, the cavity 2327 has a first depth that is less than a second depth of the cavity 2329. For example, the shallower cavity 2327 and the overall structure of the first substrate 2330 can effectively facilitate heat transfer to the heat sink 2333.

[0133] As in Fig. As can be seen in Figure 23, the semiconductor die 2302 extends out of cavity 2327 and into cavity 2329. Consequently, given the relative depths of cavities 2327 and 2329, metal attachment points 2335 emerge at three different levels or planes within the exemplary module. Fig. 23 on, i.e., on a first level between the drain pad 2316 and the metal layer 2318, on a second level between the two substrates 2330, 2336, and on a third level between the gate / source pads 2304 / 2310 and the gate-source contacts 2308 / 2314. In other words, the die attachment of the substrates 2330, 2336 takes place between the die attachment of the substrates 2330, 2336 at the gate / source / drain pads 2304, 2310, 2316.

[0134] Fig. Figure 24 is a cross-sectional view of an alternative exemplary double cavity design. Fig. Figure 24 illustrates a semiconductor die 2402 with a gate pad 2404 connected to a gate contact 2408 via a gate via 2406, a source pad 2410 connected to a source contact 2414 via source vias 2412, and a drain pad 2416 connected to a metal layer 2418 and thus to a drain contact 2422 via drain vias 2420. Accordingly, the module can be constructed from Fig. 24, as that's from Fig. 23, to be connected to other elements using any suitable technique, including those mentioned above, as well as Cu columns, bonding wires or various other.

[0135] In Fig. The semiconductor die 2402 is arranged between a first substrate 2430 with a first cavity 2427 and a second substrate 2436 with a second cavity 2429. The cavities 2427 and 2429 together form a cavity 2434, e.g., a compound cavity or a combined cavity, in which the semiconductor die 2402 is arranged.

[0136] Furthermore, in Fig. 24 an RDL 2424 is formed on a surface of the second substrate 2436. On the first substrate 2430 a dielectric or other electrically insulating layer 2432 can be formed, and a metallic heat sink 2433 can be connected to it.

[0137] In the example from Fig. 24 are, as in Fig. The gate vias 2406 and the source vias 2412 are formed by a relatively thinner section of the second substrate 2436 between the cavity 2434 and the gate contact 2408 / source contact 2414. The drain vias 2420 are formed by a thicker section of the second substrate 2436 adjacent to the cavity 2434.

[0138] As opposed to Fig. 23 The cavity 2427 of the first substrate 2430 is larger / deeper than the cavity 2429 of the second substrate 2436. The drain redistribution occurs partly via additional drain vias 2417 and drain vias 2419 through the first substrate 2430, as shown.

[0139] Metal attachment points 2435 are manufactured to join the semiconductor die 2402 to layer 2418 and thus to the first substrate 2430, and to connect the second substrate 2436 to the first substrate 2430 and the semiconductor die 2402. Fig. Although the cavity 2327 is deeper than the cavity 2329, heat transfer is facilitated by the rear metal 2418 as part of the drain redistribution. For example, the rear metal 2418 can be located close to the heat sink 2333 and separated from it only by the electrically insulating layer 2432.

[0140] Fig. Figure 25 is a cross-sectional view of an exemplary single-cavity design on metal. Fig. Figure 25 illustrates a semiconductor die 2502 with a gate pad 2504 connected to a gate contact 2508 via a gate via 2506, a source pad 2510 connected to a source contact 2514 via source vias 2512, and a drain pad 2516 connected to a leadframe 2530 (or other metal element) and thus to a drain contact 2522 via drain vias 2520. The semiconductor die 2502 is positioned between the leadframe 2530 and a substrate 2536 with a cavity 2534.

[0141] Furthermore, in Fig. 25 an RDL 2524 is formed on a surface of the substrate 2536. A dielectric or other electrically insulating layer 2532 can be formed on the leadframe 2530, and a metal heat sink 2533 can be connected to it.

[0142] In the example from Fig. 25 are, as in Fig. 23 and Fig. The gate vias 2506 and the source vias 2512 are formed by a relatively thinner section of the substrate 2536 between the cavity 2534 and the gate contact 2508 / source contact 2514. The drain vias 2520 are formed by a thicker section of the substrate 2536 adjacent to the cavity 2534.

[0143] In contrast to the Fig. 23 and Fig. In section 24, cavity 2534 is the only enclosed cavity. This means that leadframe 2530 has a flat surface and no cavity. Drain redistribution occurs partially via leadframe 2530, as shown.

[0144] Metal attachment points 2535 are manufactured to join the semiconductor die 2502 to the leadframe 2530 and to connect the substrate 2536 to the leadframe 2530 and the semiconductor die 2502. Fig. 25 The heat transfer is facilitated by the metal leadframe 2530 and the heat sink 2533.

[0145] Fig. Figure 26 is a cross-sectional view of an exemplary double-cavity design with silicon bonded to diamond. Fig. Figure 26 illustrates a semiconductor die 2602 with a gate pad 2604 connected to a gate contact 2608 via a gate via 2606, a source pad 2610 connected to a source contact 2614 via source vias 2612, and a drain pad 2616 connected to a metal layer 2618 and thereby to a drain contact 2622 via drain vias 2620.

[0146] In Fig. The semiconductor die 2602 is arranged between a first substrate 2630 with a first cavity 2627 and a second substrate 2636 with a second cavity 2629. The cavities 2627 and 2629 together form a cavity 2634 in which the semiconductor die 2602 is arranged.

[0147] Metal attachment points 2635 are manufactured to join the semiconductor die 2602 to the layer 2618 and thus to the first substrate 2630, and to connect the second substrate 2636 to the first substrate 2630 and the semiconductor die 2602.

[0148] Furthermore, in Fig. 26 an RDL 2624 is formed on a surface of the second substrate 2636. The material selected, for example, is layer 2632, which is electrically insulating and has good thermal properties. For example, layer 2632 can consist of diamond, which is bonded directly to the first substrate 2630.

[0149] Fig. Figure 27 is a cross-sectional view of an exemplary double-cavity design with a drain-side redistribution layer. Fig. Figure 27 illustrates a semiconductor die 2702 with a gate pad 2704, which is connected to a gate contact 2708 in a first substrate 2730 via a gate via 2706 in a second substrate 2736, a die attachment 2735, and a gate via 2707. The semiconductor die 2702 further features a source pad 2710, which is connected to a source contact 2714 in the first substrate 2730 via source vias 2712 in the second substrate 2736, a die attachment 2735, and a source via 2713. A drain pad 2716 is connected to a metal layer 2718 and thereby to a drain contact 2722 via drain vias 2720.

[0150] In Fig. The semiconductor die 2702 is arranged between the first substrate 2730 with a first cavity 2727 and the second substrate 2736 with a second cavity 2729. The cavities 2727 and 2729 are aligned together to form a cavity 2734 in which the semiconductor die 2702 is located.

[0151] In Fig. 27 is thus an RDL 2724 formed on a surface of the first substrate 2730, i.e. on a bottom side of the module made of Fig. 27, as illustrated, in comparison to the various RDLs 2324, 2424, 2524, 2624 of the preceding Fig. 23, Fig. 24, Fig. 25, Fig. 26, which were formed on the top surfaces of these modules, as illustrated. A dielectric or other electrically insulating layer 2732 can thus be formed on the second substrate 2736, and a metal heat sink 2733 can be associated with it, i.e., on a top surface of the module made of Fig. 27, as illustrated.

[0152] Metal attachment points 2735 are manufactured to join the semiconductor die 2702 to the layer 2718 and thus to the first substrate 2730, and to connect the second substrate 2736 to the first substrate 2730 and the semiconductor die 2702.

[0153] Fig. Figure 28 is a cross-sectional view of an alternative exemplary double cavity design with a drain-side redistribution layer. Fig. Figure 28 illustrates a semiconductor die 2802 with a gate pad 2804, which is connected to a metal layer 2805, a die attachment 2835, and a gate via 2806 in a first substrate 2830, and thus to a gate contact 2808. The semiconductor die 2802 further comprises a source pad 2810, which is connected to a metal layer 2811, a die attachment 2835, and via source vias 2812 in the first substrate 2830, and thus to a source contact 2814. A drain pad 2816 is connected to a metal layer 2818, and thus to a drain contact 2822 via drain vias 2820.

[0154] In Fig. In figure 28, the semiconductor die 2802 is arranged between the first substrate 2830 with a first cavity 2827 and the second substrate 2836 with a second cavity 2829. The cavities 2827 and 2829 together form a cavity 2834 in which the semiconductor die 2802 is arranged. Fig. 28 and in the various double-cavity structures described herein, the cavities are not necessarily shown to scale. For example, a deeper cavity may be ten times larger than a shallow cavity in a double-cavity structure (e.g., 150 micrometers compared to 15 micrometers or less). More generally, any suitable size / depth and ratio may be chosen.

[0155] In Fig. 28 is thus an RDL 2824 formed on a surface of the first substrate 2830, i.e. on a bottom side of the module made of Fig. 28, as illustrated, and similar to the example from Fig. 27. However, as shown and described, the RDL 2824 is made of Fig. 28 without the need for vias in the second substrate 2836.

[0156] A dielectric or other electrically insulating layer 2832 can be formed on the second substrate 2836. As shown in Fig. 27 a metal heat sink 2833 can be connected to it, i.e. on a top side of the module made of Fig. 28, as illustrated.

[0157] Fig. Figure 29 is a cross-sectional view of an exemplary double cavity design, wherein one cavity is formed using a metal substrate and a substrate frame. Fig. Figure 29 illustrates a semiconductor die 2902 with a gate pad 2904 connected to a gate contact 2908 via a gate via 2906, a source pad 2910 connected to a source contact 2914 via source vias 2912, and a drain pad 2916 connected to a leadframe 2918 and thus to a drain contact 2622 via drain vias 2917 in a first substrate 2930 and drain vias 2620 in a second substrate 2936.

[0158] In Fig. The semiconductor die 2902 is located between a combination of the leadframe 2918 and the first substrate 2630, which defines a first cavity 2927, and a second substrate 2936 with a second cavity 2929. The cavities 2927 and 2929 together form a cavity 2934 in which the semiconductor die 2902 is located.

[0159] More precisely, the first substrate 2930 can be configured as a frame (e.g., similar to a picture frame) that defines a perimeter around the semiconductor die 2902. The leadframe 2918 can, as illustrated, have a flat surface with sections that lie beneath and support the first substrate 2930.

[0160] Metal attachment points 2935 are manufactured to join the semiconductor die 2902 to the leadframe 2918 and to connect the second substrate 2936 to the first substrate 2930, the semiconductor die 2902 and the leadframe 2918.

[0161] Thus, in Fig. 29 an RDL 2924 is formed on a surface of the second substrate 2936. A layer 2932 can be selected as an electrically insulating material (e.g. silicon nitride, such as Si3N4), and a heat sink 2933 can be attached to it.

[0162] Fig. Figure 30 is a cross-sectional view of an exemplary double substrate single cavity design. Fig. Figure 30 illustrates a semiconductor die 3002 with a gate pad 3004, which is connected to a metal layer 3005, a die attachment 3035, and a gate via 3006 in a first substrate 3030, and thus to a gate contact 3008. The semiconductor die 3002 further comprises a source pad 3010, which is connected to a metal layer 3011, a die attachment 3035, and via source vias 3012 in the first substrate 3030, and thus to a source contact 3014. A drain pad 3016 is connected to a metal layer 3018 and thus to a drain contact 3022 via drain vias 3020.

[0163] In Fig. The semiconductor die 3002 is arranged between the first substrate 3030, which has a cavity 3034, and the second substrate 3036. The second substrate 3036 has no cavity and provides a flat surface for connection with the gate contact 3005 and the source contact 3011. The second substrate 3036 can be thinned appropriately to ensure good thermal properties with respect to heat transfer through the electrically insulating layer 3032 and to a heat sink 3033.

[0164] In Fig. 30 is an RDL 3024 formed on a surface of the first substrate 30, i.e. on a bottom side of the module made of Fig. 30, as illustrated, and similar to the example from the Fig. 27 and Fig. 28. As shown and described, and similar to the example from Fig. 28 is the RDL 30 from Fig. 30 without vias in the second substrate 2836. In Fig. 30 The metal attachment points are located on two levels or planes, i.e. between the drain pad 3016 and the metal layer 3018, and between the first substrate 3030 and the second substrate 3036, which also includes the gate / source connections, as shown and described.

[0165] Fig. Figure 31 is a cross-sectional view of an exemplary double-cavity design with a redistribution layer formed between substrates. Fig. Figure 31 illustrates a semiconductor die 3102 with a gate pad 3104, which is connected via a gate via 3106 in a second substrate 3136 to a die attachment 3135 and thus to a gate contact 3108. The semiconductor die 3102 further has a source pad 3110, which is connected via source vias 3112 in the second substrate 3136, via a die attachment 3135, and thus to a source contact 3114. A drain pad 3116 is connected via the die attachment 3135 and via drain vias 3117 to a metal layer 3118 and thus via drain vias 3120 to a drain contact 3122.

[0166] In Fig. The semiconductor die 3102 is arranged between the first substrate 3130 with a first cavity 3127 and the second substrate 3136 with a second cavity 3129. Together, the cavities 3127 and 3129 form a cavity 3134 in which the semiconductor die 3102 is arranged.

[0167] In Fig. Thus, an RDL 3124 is formed on a surface of the first substrate 3130, i.e., between or in the middle of the first substrate 3130 and the second substrate 3136, as illustrated. A dielectric or other electrically insulating layer 3132a can therefore be formed on the first substrate 3130, and a metal heat sink 3133a can be associated with it, i.e., on a bottom surface of the module. Fig. 31, as illustrated. With the RDL 3124 in the middle of the module made of Fig. 31 can thus form a dielectric or other electrically insulating layer 3132b on the second substrate 3136, and a metal heat sink 3133b can be associated with it, i.e. on a top side of the module made of Fig. 31, as illustrated.

[0168] Fig. Figure 32 is a cross-sectional view of an exemplary double-cavity design with integrated passive devices. Fig. Figure 32 and similar figures described below do not list or explain in detail many of the various components and elements already described, for the sake of brevity. It is understood, however, that practically any of the above embodiments (e.g., embodiments with a single cavity) can replace or combine elements in conjunction with the various embodiments described below.

[0169] For example, in Fig. 32 a gate contact 3208, a source contact 3214 and a drain contact 3222 an RDL 3224, which includes metal layers 3209a, 3209b which are connected to the gate contact 3208 via gate vias 3206, and metal layers 3215a, 3215b which are connected to the source contact 3214 via source vias 3212. As shown, the embodiment from Fig. 32 the integration of integrated passive devices, such as capacitors 3217, e.g. MIM capacitors (MIMCAPs). Other types of passive devices, such as resistors or inductors, can also be easily integrated.

[0170] Fig. Figure 33 is a cross-sectional view of an exemplary double-cavity embodiment with an integrated active circuit arrangement. That is, similar to the embodiment shown in Fig. Figure 32 illustrates the embodiment from Fig. 33 the integration of an active circuit arrangement 3301. The active circuit arrangement 3301 can be connected to other circuits (not shown) via terminals 3303 and can be connected to the gate contact 3308 and the source contact 3314, as shown. Accordingly, the active circuit arrangement 3301 can be connected in conjunction with the RDL 3324, which includes the drain contact 3322.

[0171] Furthermore, the active circuit arrangement 3301 can be easily formed within the substrate 3336, e.g., using conventional or future silicon processing / fabrication techniques. Any suitable and available circuits can be included. As a specific example, a gate driver for a discrete power semiconductor die 3302 can be included.

[0172] Fig. Figure 34 is a cross-sectional view of an exemplary double-cavity design with integrated MEMs technology. Similar to in Fig. 32 A gate contact 3408, a source contact 3414, and a drain contact 3422 form an RDL 3424, which includes metal layers 3409a, 3409b, which are connected to the gate contact 3408 via gate vias 3406, and metal layers 3415a, 3415b, which are connected to the source contact 3414 via source vias 3412. As shown, the embodiment from Fig. 34 the inclusion of MEMS technology, including various types of MEMS devices.

[0173] Fig. Figure 35 is a cross-sectional view of an exemplary double-cavity design with integrated MEMS tubes for liquid cooling. That is to say, Fig. 35 provides a more specific example of MEMS technology than in Fig. 34 shown. In particular, the embodiment excludes Fig. 35 the integration of microfluidic heat pipes 3501, 3503 for double-sided liquid cooling.

[0174] Fig. Figure 36 is a cross-sectional view of an alternative exemplary double-cavity design with integrated MEMs technology and / or active circuit arrangement 3601. In particular, it illustrates Fig. 36, as shown, an embodiment which is derived from Fig. 31 is similar, but with a gate contact 3608 and a source contact 3614, which are connected to the MEMs technology / active circuit arrangement 3601. As mentioned above and in relation to Fig. As described in detail in section 13, the embodiment can be derived from Fig. 36, for example, can be configured to provide a fast, reliable solid-state relay.

[0175] Fig. Figure 37 is a cross-sectional view of an exemplary double-cavity / double-die design. Fig. Figure 37 illustrates a semiconductor die 3702a with a gate pad 3704a connected to a gate contact 3708 via a gate via 3706a, a source pad 3710a connected to a source contact 3714 via source vias 3712a, and a drain pad 3716a connected to a metal layer 3718a and thereby to a drain contact 3722 via drain vias 3720a.

[0176] In Fig. The semiconductor die 3702a is arranged between a first substrate 3730 with a cavity 3727a and a second substrate 3736 with a cavity 3729a. The cavities 3727a and 3729a together form a cavity 3734a in which the semiconductor die 3702a is arranged.

[0177] Furthermore, in Fig. 37 an RDL 3724 is formed on a surface of the second substrate 3736. On the first substrate 3730 a dielectric or other electrically insulating layer 3732 can be formed, and a metallic heat sink 3733 can be connected to it.

[0178] Fig. Figure 37 further illustrates a semiconductor die 3702b with a gate pad 3704b connected to the gate contact 3708 via a gate via 3706b, a source pad 3710b connected to the source contact 3714 via source vias 3712b, and a drain pad 3716b connected to a metal layer 3718b and thus to the drain contact 3722 via drain vias 3720b.

[0179] The semiconductor die 3702b is arranged between the first substrate 3730 with a cavity 3727b and the second substrate 3736 with a cavity 3729b. Together, the cavities 3727b and 3729b form a cavity 3734b in which the semiconductor die 3702b is located.

[0180] Metal attachment points 3735 are manufactured to join the semiconductor dies 3702a, 3702b to the layer 3718 and thus to the first substrate 3730, and to connect the second substrate 3736 to the first substrate 3730 and the semiconductor dies 3702a, 3702b.

[0181] Fig. Figure 38 is a top view of an exemplary embodiment, which is shown using various exemplary embodiments, e.g. from Fig. 37 and / or from the Fig. 39 to 50 and / or from the Fig. 1 to 13 and / or from the Fig. 23 to 26, can be constructed. Fig. Figure 38 illustrates dies 3802, 3804, 3806, and 3808. As shown, gate connections 3809 connect all dies 3802, 3804, 3806, and 3808 to a common gate contact 3810. Similarly, source connections 3811 connect all dies 3802, 3804, 3806, and 3808 to a common source contact 3812. Finally, drain connections 3813 connect all dies 3802, 3804, 3806, and 3808 to a common drain contact 3814.

[0182] As can be seen from the preceding description and as shown and described in various examples below, the various connections 3809, 3811, 3813 can be made using substrate routing, e.g., using TSVs and RDLs. Furthermore, the dies 3802, 3804, 3806, and 3808 can be enclosed in a compact form, with the connections 3809, 3811, 3813 being formed without the need for wire bonds or other conventional joining techniques. Accordingly, the example from Fig. Figure 38 provides a four-die module that is small, reliable, has good thermal management, and is easy to manufacture. It should also be noted that while a parallel connection of four dies is shown, forming a single functional switch, many different connections can be made to create desirable configurations. Such configurations can include, for example, functional half-bridges, high-side and low-side functional switches (each consisting of one or more dies), full bridges, T-types, 6-packs, or bidirectional anti-series blocking. The configurations shown above are merely examples, and many other configurations can be implemented.

[0183] Fig. Figure 39 is a cross-sectional view of an exemplary dual-die embodiment, which has a substrate with a cavity on metal to provide a common drain connection. Fig. 39 A leadframe 3930 is used as the first surface or substrate, and an optional electrical insulation layer 3932 electrically separates the leadframe 3930 from the rest of the example. Fig. 39. Cavities 3929a and 3929b are formed in a substrate 3936. Thus, in Fig. 39 of the leadframe 3930 provides a common drain connection, and the various advantages of embodiments with cavities, as described herein, can be achieved by forming the cavities 3929a, 3929b in the single substrate 3936 (e.g. a Si substrate) without having to form corresponding cavities in another substrate.

[0184] Fig. Figure 40 illustrates an exemplary gate / source routing, while Fig. Figure 41 illustrates an exemplary gate / source / drain routing. For example, it resembles... Fig. 40 from the example Fig. 22, but includes additional routing / wiring 4002, 4004. Fig. 41 can be combined with the embodiments from Fig. 22 or Fig. Figure 40 is used and illustrates an example routing for a die 4102a and a die 4102b. For example, a source landing 4110 is connected to a source pad 4114 via vias 4112. A drain pad 4122 is connected to die 4102a and die 4102b via vias 4120. A gate landing 4104 is connected to a gate pad 4108 via vias 4106.

[0185] Fig. Figure 42 is a cross-sectional view of an exemplary double-cavity / double-die design with a single redistribution layer. Fig. 42 Both semiconductor dies 4202a and 4202b have a common gate connection 4208. The semiconductor dies 4202a and 4202b have a common source connection 4214. Via the metal layers 4218a and 4218b, the semiconductor dies 4202a and 4202b have a common drain connection 4222.

[0186] In the example from Fig. 42 RDL 4224 includes three metal layers, as shown. Meanwhile, a single metal layer 4218a, 4218b, as already mentioned, is included in Fig. 42 is redistributed to an upper surface or top surface to be enclosed in the RDL 4224. In other examples, a single drain connection for the two dies 4202a, 4202b can be made on a bottom side of the exemplary module. Fig. 42 may be formed, or the drains of the two dies 4202a, 4202b may be led individually to a top side of the module.

[0187] Fig. Figure 43 is a cross-sectional view of an exemplary stacked module with multiple double-cavity / double-die modules. In the example from Fig. 43 Both module 4300a and module 4300b resemble the module from Fig. 42. A gate connection 4308a, enclosed in an RDL 4324b of module 4300b, provides a connection to gates of module 4300a via an RDL 4324a of module 4300a. A gate connection 4308b and a source connection 4314b of module 4300b are also enclosed in the RDL 4324b.

[0188] In the example from Fig. 43 is a redistributed switching node 4322b enclosed in the RDL 4324b, which is connected to a drain connection 4318b of module 4300b and to a source connection 4314a of module 4300a. A drain connection 4322a within the RDL 4324b provides the connection to the drains of module 4300a.

[0189] Fig. Figure 44 is a cross-sectional view of an exemplary stacked module in a half-bridge configuration. Fig. 44 resembles Fig. 43 and includes a module 4400a and a module 4400b with separate, respective gate connections 4408a, 4408b, a source connection 4414b and a redistributed switching node 4422b.

[0190] In Fig. However, modules 4300a and 4300b each include double substrates and double cavities. In contrast, module 4400a is a double-substrate, double-cavity module that includes a first substrate 4430a and a second substrate 4436a, but module 4400b includes a second substrate 4436b, while module 4400a itself is used as the lower substrate. In further contrast to Fig. 43 will be in Fig. 44. A drain connection 4422a of module 4400b is not connected to an RDL 4424 of module 4400b. Instead, drain connection 4422a is provided as input VDD, while the redistributed switching node 4422b is used as output and source connection 4414b is used as ground. Thus, it shows Fig. 44 the provision of a half-bridge configuration with the positive connection VDD on one surface, a negative / ground connection on the opposite surface and the switching node 4422b in between.

[0191] Fig. Figure 45 is a cross-sectional view of an alternative exemplary stacked module in a half-bridge configuration. Fig. 45 resembles Fig. 44, including a module 4500a and a module 4500b, with separate, respective gate connections 4508a, 4508b, a source connection 4514b (GND) and a redistributed switching node 4522b (OUT). In Fig. However, 45 becomes a substrate 4430a from Fig. 44 is replaced by a leadframe (e.g. a copper plate) to provide a drain connection 4522a (VDD / IN).

[0192] Fig. Figure 46 is a cross-sectional view of a second alternative exemplary stacked module in a half-bridge configuration. Fig. 46 resembles Fig. 45, including a module 4600a and a module 4600b, with separate, respective gate connections 4608a, 4608b, a source connection 4614b (GND) and a redistributed switching node 4622b (OUT). As in Fig. 45 becomes a substrate 4430a from Fig. 44 is replaced by a leadframe (e.g. a copper plate) to provide a drain connection 4622a (VDD / IN).

[0193] In Fig. However, 46 modules are provided in a terraced configuration with respect to the leadframe / drain connection 4622a. That is, as shown, module 4600a is shorter / smaller than the leadframe 4622a, while module 4600b is shorter / smaller than module 4600a.

[0194] Consequently, many of the described exemplary embodiments include double-sided electrical connectivity, as is also the case with the example from Fig. 46, the example illustrates this. Fig. 46 also provides a connection 4646. As in Fig. 47 as well as in the top view of Fig. 48 shows that the embodiment from Fig. 46 a simple connection of the busbars 4702, 4704 and 4706, including a connection of the power busbar 4704 to the connection 4646.

[0195] Fig. Figure 48 illustrates a top view of the exemplary embodiment from Fig. 47, wherein the switching node busbar (OUT busbar) is attached to the terraced connection and the VDD and GND busbars are attached to the upper and lower surfaces. In such a configuration, with respect to Fig. 47 the tab / busbar 4804 of the busbar 4706 in Fig. 47, while busbar 4806 corresponds to 4704 and busbar 4802 to 4702.

[0196] Fig. Figure 49 is a cross-sectional view of another exemplary stacked module in a half-bridge configuration. Fig. 49 resembles Fig. 45, however, with the three-stage or upper / middle / lower GND / OUT / VDD connections from the Fig. 46 to 48. As shown, it concludes Fig. 49, in particular a module 4900a and a module 4900b with separate, respective gate connections 4908a, 4908b and a source connection 4914b (GND). A leadframe 4922a (e.g., a copper plate) provides a drain connection (VDD / IN). A redistributed switching node 4949 (OUT) is provided as a third power connection.

[0197] Fig. Figure 50 is a circuit diagram for a stacked module in a half-bridge configuration, where a high-side function switch 5000a comprises two power semiconductors (transistors) connected in parallel to input 5008a, and the low-side function switch 5000b comprises two transistors connected in parallel to input 5008b. The drain of the HS function switch is electrical terminal 5022a for VDD (or positive DC), and the source of LS is electrical terminal 5014b for GND (or negative DC). The common HS source and LS drain connection is the switching node 5022b, which acts as the output. For example, in a traction inverter application, VDD is the positive battery terminal, GND is the negative battery terminal, and OUT is the phase node connected to one of the motor phases. A typical electric vehicle motor has 3 phases, each connected by a half-bridge in a configuration similar to that in Fig. 50 would be driven, with the HS and LS function switches comprising one or more (any number) parallel semiconductors (transistors).

[0198] Fig. Figure 51 is a cross-sectional view of a double cavity form factor packaged with a printed circuit board 5104 and a heat sink 5102. Fig. Figure 51 illustrates that several modules 5100a, 5100b, each enclosing multiple dies, can share the common heat sink 5102. Furthermore, the modules 5100a, 5100b can be connected to a common printed circuit board 5104, for example, using any standard assembly technique such as soldering. Additional printed circuit board components 5106 can also be easily incorporated. In one example, three such half-bridge modules are combined—for example, on a single cooling structure and / or control circuit board—to form a three-phase traction inverter power stage.

[0199] Fig. Figure 52 is a cross-sectional view of a single-cavity design with alternative gate routing and a bonded interface. Fig. Figure 52 illustrates a semiconductor die 5202 with a sintered or soldered connection or a similar connection 5215 to a metal layer 5218. The semiconductor die 5202 has a gate pad 5204 connected to a gate contact 5208 via a gate via 5206, a source pad 5210 connected to a source contact 5214 via source vias 5212, and a drain pad 5216 connected to a metal layer 5218 and thereby to a drain contact 5222 via drain vias 5220.

[0200] In Fig. 52 The semiconductor die 5202 is arranged between a first substrate 5230 with a cavity 5234 and a second substrate 5236. Similar to the exemplary embodiment from Fig. 3 The semiconductor die 5202 is enclosed within a dielectric 5226, which is arranged within the cavity 5234. Dielectric layers 5233 and 5237 are arranged on each surface of the second substrate 5236.

[0201] The gate junction 5208, the source junction 5214, and the drain junction 5222 are formed on the dielectric layer 5237, thereby defining an RDL 5224. A dielectric or other electrically insulating layer 5228 may be formed between the first substrate 5230 and the metal layer 5218, and a leadframe 5232 may be mechanically connected to the substrate 5230 on a side opposite the semiconductor die 5202, but not electrically connected to the semiconductor die 5202.

[0202] Fig. Figure 52 illustrates an example in which a bottom-side arrangement 5200a encloses the semiconductor die 5202 within the cavity 5234 with associated elements as described above. Meanwhile, an upper wafer section 5200b encloses the various vias and other interconnects, also as described above. The bottom-side arrangement 5200a and the upper wafer section 5200b can be joined and bonded at a bonded interface 5235.

[0203] Metal attachment points 5235 are provided to connect the second substrate 2436 to the first substrate 2430 and to the semiconductor die 2402. Thus, in some examples, the embodiment consisting of Fig. 52 are manufactured using wafer-to-wafer bonding techniques, such as one or more of the techniques described above.

[0204] Also in Fig. In section 52, the gate connection 5208 is routed from the gate via 5206 via the source via 5212 using a routing layer 5207 such that the gate connection 5208 is on a different side of the source connection 5214 than the gate pad 5204 is relative to the source pad 5210. It is understood that the RDLs, which use one or more metal layers, can be used to rearrange (redistribute) the sequence and physical position of the upper connections, as illustrated here.

[0205] Fig. Figure 53 is a cross-sectional view of a single-cavity design with alternative gate and source routing for accommodating a heat sink 5301. Fig. Figure 53 illustrates a semiconductor die 5302 with a sintered or soldered connection or similar connection 5315 to a metal layer 5318. The semiconductor die 5302 has a gate pad 5304 connected to a gate contact 5308 via a gate via 5306, a source pad 5310 connected to a source contact 5314 via source vias 5312, and a drain pad 5316 connected to a metal layer 5318 and thereby to a drain contact 5322 via drain vias 5320.

[0206] The semiconductor die 5302 is arranged between a first substrate 5330, which has a cavity 5334, and a second substrate 5336. The semiconductor die 5302 is embedded in a dielectric 5326 located in the cavity 5334. Dielectric layers 5333 and 5337 are arranged on each surface of the second substrate 5336.

[0207] The gate junction 5308, the source junction 5314, and the drain junction 5322 are formed on the dielectric layer 5337, thus defining an RDL 5324. A dielectric or other electrically insulating layer 5328 may be formed between the first substrate 5330 and the metal layer 5318, and a leadframe 5332 may be mechanically connected to the substrate 5330 on a side opposite the semiconductor die 5302, but not electrically connected to the semiconductor die 5302.

[0208] Also in Fig. In section 53, the gate connection 5308 is routed from the gate via 5306 away from the source via 5312 using a routing layer 5307, while the source connection 5314 is routed away from the source via 5312 using a routing layer 5313. Accordingly, space is created on a surface of the dielectric layer 5337 for a heat sink 5301. Advantageously, in Fig. 53 of the heat sink 5301 can thus be positioned directly above or otherwise near the semiconductor die 5302.

[0209] The exemplary embodiment from Fig. 53 can be manufactured using wafer fabrication techniques without the need for wafer-to-wafer bonding. In the example from Fig. 53 a metal layer 5319 is added to a section of the metal layer 5318 and is coplanar with a landing pad 5304a of the gate pad 5304 and a landing pad 5310a of the source pad 5310 to ensure planarity for the further construction of the dielectric layer 5333 and the remaining layers of the example. Fig. 53 to maintain. With the understanding that a heat sink can be attached to the thermal surface (5332) and the electrical surface (5301), the exemplary embodiment from Fig. 53 a double-sided cooling system. Similarly, double-sided cooling can be achieved for each of the embodiments disclosed herein, as well as for any embodiments not disclosed herein, by extension.

[0210] Fig. Figure 54 is a cross-sectional view of a single-cavity design with alternative gate routing. Fig. Figure 54 illustrates a semiconductor die 5402 with a solder connection 5415 to a metal layer 5418. The semiconductor die 5402 has a gate pad 5404, which is connected to a gate contact 5408 via a gate via 5406, a source pad 5410, which is connected to a source contact 5414 via source vias 5412, and a drain pad 5416, which is connected to a metal layer 5418 and thereby to a drain contact 5422 via drain vias 5420.

[0211] In Fig. The semiconductor die 5402 is arranged between a first substrate 5430, which has a cavity 5434, and a second substrate 5436. The semiconductor die 5402 is embedded in a dielectric 5426 located in the cavity 5434.

[0212] Each surface of the second substrate 5436 has dielectric layers 5433 and 5437, with the dielectric layer 5433 being arranged on an insulating layer 5425. For example, the dielectric layers 5433 and 5437 can be provided using the same or a similar material as the encapsulating dielectric layer 5426.

[0213] The gate junction 5408, the source junction 5414, and the drain junction 5422 are formed on the dielectric layer 5437, thus defining an RDL 5424. A dielectric or other electrically insulating layer 5428 may be formed between the first substrate 5430 and the metal layer 5418, and a leadframe 5432 may be mechanically connected to the substrate 5430 on a side opposite the semiconductor die 5402, but not electrically connected to the semiconductor die 5402.

[0214] Also in Fig. 54 the gate connection 5408 is routed from the gate via 5406 via the source connection 5412 using a routing layer 5407 such that the gate connection 5408 is on a different side of the source connection 5414 than the gate pad 5404 relative to the source pad 5410. Fig. 54 thus illustrates an example that is structurally similar to the example from Fig. 52 is similar, but using the techniques from Fig. 53 is constructed. That is, the embodiment from Fig. 54 can be manufactured using silicon fabrication techniques without the need for wafer-to-wafer bonding.

[0215] Fig. Figure 55 is a cross-sectional view of a single-cavity design with an embedded magnetic element. For example, in relation to Fig. As described in section 12, various embodiments may include a magnetic element instead of (or in addition to) the types of semiconductor dies described here. Fig. 55 is represented as magnetic element 5502. For example, magnetic element 5502 can enclose an iron(III) or iron(II) material or iron powder.

[0216] Furthermore, in Fig. 55 represents a winding 5501, a metal element embedded in a spiral pattern around the magnetic element 5502. The remaining elements of Fig. The 55 should be understood as non-limiting examples of embodiments described herein, such that any suitable or desired embodiment described should be understood as usable in conjunction with the magnetic element 5502 and the spiral windings 5501.

[0217] Thus, for example, it illustrates Fig. 55, that a cylindrical iron(III) or iron(II) puck can be used as a magnetic core and positioned within a cavity 5534 of a module, being completely encapsulated by one or more insulating dielectric layers 5526 to provide electrical insulation while allowing heat conduction.

[0218] The spiral winding 5501 can be formed from structured metal layers and wind in several turns around the magnetic element 5502. Fig. 55 not shown, the terminals of the spiral windings 5501 may be connected, for example, to the die contacts or external package leads to provide electrical access.

[0219] Fig. 56 is a top view of the example from Fig. 55. Fig. Figure 56 illustrates the winding 5501 surrounding the magnetic element 5502. In particular, the magnetic element 5502 is illustrated as a circular puck surrounded by the windings 5501 as a series of concentric spiral tracks forming inductive windings that encircle the magnetic element 5502 for magnetic coupling. The spirals 5501, e.g., made of copper or aluminum, are illustrated such that they fan out from an inner starting point near an edge of the magnetic element 5502 to an outer termination point. Fig. 56 not shown, but as from Fig. As can be seen in Figure 55, an insulating dielectric can be used to separate winding levels and prevent short circuits.

[0220] Fig. 57A illustrates a first exemplary embodiment of the examples from Fig. 55 and Fig. 56. In Fig. The windings 5701a surround the magnetic element 5702a, while the windings 5702b surround the magnetic element 5702b. An input 5700a is illustrated at an innermost terminal of the windings 5701a, while an output of the windings 5701a at an outermost terminal 5705 is connected to an input at an outermost terminal 5707 of the windings 5702b. An output 5700b is illustrated at an innermost terminal of the windings 5702b.

[0221] In Fig. For example, the magnetic elements 5702a and 5702b can be placed side by side within their respective cavities, with the windings 5701a and 5701b being wound in opposite directions to generate opposing magnetic fields. As shown in an isolated isometric view 5703, the flux lines 5703a enter the magnetic element 5702a perpendicularly from below (south pole) and exit the magnetic element 5702b in a similar manner, resulting in cancellation between the magnetic elements 5702a and 5702b, for example, for applications such as differential inductors or noise suppression. The spirals 5701a, 5701b allow currents to be guided in opposite directions, resulting in flux arrows 5703a that are curved outwards from the magnetic element 5702a and inwards towards the magnetic element 5702b, minimizing crosstalk while maintaining insulation through dielectric encapsulation.

[0222] Fig. 57B illustrates a second exemplary embodiment of the examples from Fig. 55 and Fig. 56. In Fig. The windings 5701c surround the magnetic element 5702c, while the windings 5702d surround the magnetic element 5702d. An input 5700c is illustrated at an innermost terminal of the windings 5701c, while an output of the windings 5701c at an outermost terminal 5708 is connected to an input at an innermost terminal 5710 of the windings 5702d. An output 5700d is illustrated at an outermost terminal of the windings 5702d.

[0223] As shown in an isolated isometric view 5704, the flux lines 5703c enter the magnetic elements 5702c, 5702d perpendicularly from below (south pole) and exit the magnetic elements 5702c, 5702d in a similar manner, resulting in additive fields that enhance the mutual inductance for coupled applications such as common-mode chokes.

[0224] Fig. 58 illustrates a third exemplary embodiment of the examples from Fig. 55 and Fig. 56. Fig. Figure 58 illustrates an embedded transformer application in which a magnetic element 5802a is encircled by helical windings 5801a to provide a primary winding, and a magnetic element 5802b is encircled by helical windings 5801b to provide a secondary winding.

[0225] As shown in the corresponding illustrated circuit diagram 5800, a transformer can thus be provided with a primary winding 5804 with a ratio of 2:1 to a secondary winding 5806 in order to achieve, for example, a desired step-down voltage ratio. Although in Fig. Although not explicitly shown in Figure 58, it is evident from the present description that vias at the inner and outer terminals of windings 5801a, 5801b can be used to establish electrical connections. In an exemplary application, the secondary output can be connected to a load resistor via a rectifier diode for DC conversion, thereby providing the desired voltage step-down within a power module for applications such as isolated power supplies in traction converters. The puck shape described and illustrated above can be cylindrical, as shown, or implemented in a number of other shapes. Such shapes may include, for example, a chocolate bar shape, a donut shape, a U-shape, an E-shape, or many others. Likewise, it should be noted that multiple winding layers can be implemented (e.g.,Spirals in multiple metal layers in embodiments such as the one in . Fig. 3 or others, e.g., using vias to connect layers / windings accordingly). Although the windings are shown here as spirally closed around the z-axis, it should be noted that it is also possible to realize windings in the x- and / or y-axis using multiple metal layers and vias to connect the metal layers in z, as shown in the example in Fig. As can be seen in Figure 12. Furthermore, inductors, coupled inductors, transformers, matrix transformers and other magnetic structures can be realized using the general techniques described here.

[0226] Fig. Figure 59 is a cross-sectional view of an alternative single-cavity design. Fig. Figure 59 illustrates a semiconductor die 5902 with a solder connection 5901 to a metal layer 5918. The semiconductor die 5902 has a gate pad 5904 with a solder connection 5906 to a metal layer 5903, which has a solder connection 5905 to a metal layer 5907, which has a solder connection 5909 to a gate contact 5908. A source pad 5910 has a solder connection 5912 to a metal layer 5911, which has a solder connection 5913 to a metal layer 5915, which is connected via a solder connection 5917b to a source contact 5914. A drain pad 5916 is connected via the solder connection 5901 to a metal layer 5918 and thus to a drain contact, which has a cross-section of Fig. 59 is not shown.

[0227] The semiconductor die 5902 is arranged between a first substrate 5930, which has a cavity 5934, and a second substrate 5936. The semiconductor die 5902 is embedded in a dielectric 5926 located in the cavity 5934. Dielectric layers 5931 and 5933 serve to insulate the various metal layers 5918, 5903, and 5911, while a dielectric layer 5935 electrically insulates the second substrate 5936.

[0228] Furthermore, in Fig. A backplate metal 5937 may be attached to the first substrate 5930 and / or a backplate metal 5932 may be attached to the second substrate 5936. An encapsulation material 5938 may be used to insulate the gate contact 5908 from the second substrate 5936, while an encapsulation material 5940 may be used to insulate the source contact 5914 from the second substrate 5936.

[0229] Thus, it illustrates Fig. 59 a lower or bottom-side arrangement 5900a covered by an upper or top-side arrangement 5900b. Exemplary techniques for manufacturing the example from Fig. 59 are described in detail below, and other examples can also be constructed.

[0230] Fig. Figure 60 is an exemplary top view of the embodiment from Fig. 59. In Fig. 60 becomes a lower arrangement 6000a, which is the lower arrangement 5900a Fig. 59 corresponds, as illustrated, to four dies 6002, which can be SiC or GaN power dies. An arrangement 6000b, which corresponds to the arrangement 5900b above. Fig. 59 corresponds to, according to the embodiment, from Fig. 59 transparent as cover of Dies 6002 illustrated.

[0231] The 6014 source lines and 6022 drain lines enable parallel current sharing / distribution for high-power applications, e.g., in a half-bridge configuration. The 6008 gate connection is also shown. Of course, many other layouts are possible.

[0232] The Fig. Sections 61A to 61G illustrate exemplary methods for forming a lower arrangement from Fig. 59. In Fig. 61A is a cavity 6134 etched into a substrate 6130a. First, a dielectric layer 6128 is deposited, then a conductive layer 6118a. In Fig. 61B is where the semiconductor die 6102 is soldered to the conductive layer 6118, including a gate pad 6104a and a source pad 6110a.

[0233] In Fig. In 61C, an electrically insulating / dielectric material 6126a, which does not include, for example, a molding compound, is deposited. Fig. 61D grinding and polishing operations are carried out to provide a planar surface with the dielectric material 6126, the conductive layer 6118, the gate pad 6108, the source pad 6114 and the conductive layer 6118.

[0234] In Fig. 61E Glass 6140 (or adhesive tape or other suitable material) can be bonded to the array using the bonding layer 6138. In this way, the thinning of the substrate 6130a can continue to obtain the thinned substrate 6130. The back side of the wafer can be chemically etched to relieve grinding stresses and prepare the surface for backside metal plating. Subsequently, a backside metal plate 6132 can be added. Accordingly, as in Fig. 61G shows that the glass 6140 is removed to obtain the bottom-side arrangement 6100.

[0235] The Fig. Figures 62A to 62D illustrate exemplary methods for forming an upper arrangement from Fig. 59. In Fig. In 62A, a substrate 6236a has a dielectric layer 6235 formed on it. Fig. 62B has a structured metal layer added, which includes metal layers 6211, 6233, which (as shown in Fig. 59 can be seen) for source / gate connections to the lower arrangement 6100 from Fig. 61G can be used. Then, as shown, the electrically insulating layer 6233 can be added.

[0236] In Fig. 62C is fitted with adhesive tape or glass 6240 to allow the folding and thinning of substrate 6236a. As in Fig. As shown in Figure 62D, a rear metal layer 6232 can be added following such thinning to obtain the thinned substrate 6236. Not illustrated separately, assembly can continue with adhesive tape and the associated framing, followed by peeling and separating for assembly (e.g., soldering) on ​​the lower arrangement. Fig. 59 or Fig. 61G using a suitable encapsulation / backfilling material.

[0237] Thus, the Fig. 59, 60, 61A to 61G and 62A to 62D generally state that any desired die or other element can be bonded within a cavity of a first (bottom) wafer, and that the wafer can be thinned and back-coated if required. A second (top) wafer, built with a single-stage RDL (or multiple), can be thinned and back-coated if required. The second wafer can then be cut, and the resulting cut pieces can be bonded to the first wafer. Subsequently, the leadframe can be attached and the final encapsulation performed to create, for example, the exemplary package made of Fig. to receive 60.

[0238] Numerous variations of the resulting modules are possible. For example, the second wafer, and thus the separated pieces, can have active devices mounted in or on it. Similarly, temperature sensors (e.g., negative temperature coefficient (NTC) sensors or similar) and / or passive elements can be mounted on either the first or the second substrate, or on both.

[0239] Many other processing variations are also possible. For example, one or both wafers can be thinned, and one or both sides of the module(s) can have backplate metal(s). The choice of thinning / backplate metal can be made, for example, to facilitate mechanical stress / bending control and for reliability at high temperatures and under thermal cycling.

[0240] The Fig. Sections 63A to 63J illustrate exemplary processes for forming an alternative embodiment with metal columns. Fig. In step 63A, a first or bottom / lower substrate 6330a (wafer) is cleaned and a dielectric layer 6328 is formed on it. A metal layer 6318 is then deposited on the dielectric layer 6328. Fig. 63B, metal columns 6319 are formed on the metal layer 6318, e.g., plated. As described and illustrated below, the metal columns 6319, in conjunction with the metal layer 6318, effectively provide a cavity 6334. Therefore, for example, the height of the metal columns 6334 can be chosen to correspond to the height of a semiconductor die or other element to be enclosed in the cavity 6334.

[0241] In Fig. 63C is a semiconductor die 6302 with a gate pad 6304, a source pad 6310, and a drain pad 6316 connected to the metal layer 6318 by a solder joint 6307 (or sintered joint). Subsequently, an electrically insulating material 6326a, e.g., silicon dioxide or oxide / nitride, is provided. Fig. An etching process is carried out in 63C, forming an electrically insulating layer 6326 and an end 6327 of the metal columns 6319, while exposing the gate pad 6304 and the source pad 6310. Accordingly, a lower section or arrangement 6300a is formed.

[0242] In Fig. 63E a second or top / upper wafer 6336a is cleaned and a dielectric layer 6335 is formed on it. As in Fig. As shown in Figure 63F, the second wafer 6336 can then be flipped and mounted onto the bottom-side assembly 6300a, for example, in a wafer-to-wafer bonding process. As illustrated, a section of the cavity 6334 can remain open or filled with air. The columns 6319 can be formed without wrapping around the semiconductor die 6302 if underfilling processes are used after subsequent separation, and the metal columns 6319 are set back from an outer edge of the module so that they do not protrude into the separation channels.

[0243] In Fig. In step 63G, the second wafer 6336a is thinned to provide a thinned second substrate 6336. Subsequently, a gate via 6306 is formed to create a gate contact 6308, a source via 6312 is formed to create a source contact 6314, and a drain via 6320 is formed to create a drain contact 6322. Accordingly, an RDL 6324 is fabricated.

[0244] In Fig. 63H is fitted with adhesive tape 6340 (or a glass adhesive bond), which, as in Fig. Figure 63I shows that a backside thinning of the first substrate 6330a is possible to obtain a thinner first substrate 6330. A metal layer 6332 can then be formed, for example, by sputtering or plating, wherein the metal layer 6332 can be structured or uniform (e.g., depending on a separation method to be used). Finally, in Fig. 63J a saw 6344 or another cutting process in conjunction with an assembly belt 6342 to separate a module 6300(1) and a module 6300(2).

[0245] Fig. Figure 64 is a cross-sectional view of an exemplary embodiment with heat sinks 6404 formed in vias 6402. As in Fig. As shown in Figure 64, additional heat sinks 6404 can be configured as dummy metal posts in vias 6402. The vias 6402 can be formed during the creation of other vias of the module. Fig. 64 can be configured, for example, simply by including a mask modification for the mask already used to create existing vias. Therefore, the 6404 heat sinks can be configured at any desired location.

[0246] Fig. Figure 65 illustrates an exemplary process flow for forming cavities that can be used in various embodiments. Fig. In process 6500a, a wafer 6502 is coated with a photoresist 6504, which is applied, exposed and developed to define an opening 6505.

[0247] Subsequently, in process 6500b, a combination of an anisotropic and an isotropic reactive ion etching (RIE) process can be carried out, which etches a cavity 6506 with sloping sidewalls 6508. The shape of the cavity can be controlled by changing the process parameters (e.g., gas flows, pressures, power, bias, or others). Finally, in process 6500c, after the removal of the photoresist 6504, a second RIE process is carried out to smooth the sloping sidewalls 6508.

[0248] Accordingly, the side walls 6508 have a smooth and gradual inclination suitable for dielectric and metallic covering and can be used in any of the embodiments described herein.

[0249] Fig. Figure 66 is a first flowchart illustrating exemplary embodiments. Fig. Figure 66 illustrates exemplary embodiments that include providing a semiconductor die on a substrate, wherein the semiconductor die has at least one first contact on a first side and at least one second contact on a second side opposite the first side (6602), and encapsulating the semiconductor die with a dielectric encapsulation material (6604). The exemplary embodiments from Fig. 66 further includes forming vias in the dielectric encapsulation material (6606) and forming a redistribution layer on the dielectric encapsulation material, which is connected to the first contact and the second contact via the vias (6608).

[0250] Fig. Figure 67 is a second flowchart illustrating exemplary embodiments. Fig. Figure 67 illustrates exemplary embodiments that include arranging a semiconductor die on a first substrate (6702) and forming a cavity in a second substrate, wherein the cavity defines a first section of the second substrate with a first depth and a second section of the second substrate with a second depth greater than the first depth (6704). The exemplary embodiments from Fig. 67 further include attaching the second substrate to the first substrate through the second section of the second substrate and with the semiconductor die arranged within the cavity (6706), forming a via through the first section of the second substrate (6708) and arranging a contact on the second substrate which is electrically connected to the semiconductor die via the via (6710).

[0251] Fig. Figure 68 is a third flowchart illustrating exemplary embodiments. Fig. Figure 68 illustrates exemplary embodiments that include forming a cavity in a substrate (6802), arranging a magnetic element in the cavity (6804), providing a metallic winding on the substrate, and enclosing the magnetic element (6806). The exemplary embodiments from Fig. 68 further include encapsulating the magnetic element and the metallic winding with a dielectric encapsulation material (6808), forming a via in the dielectric encapsulation material (6810) and electrically connecting a contact to the metallic winding via the via (6812).

[0252] Fig. Figure 69 is a fourth flowchart illustrating exemplary embodiments. Fig. Figure 69 illustrates exemplary embodiments, which include forming a metal layer on a first substrate (6902), arranging metal columns on the metal layer to define a cavity (6904), and arranging a semiconductor die in the cavity with a first surface arranged on the metal layer (6906). The exemplary embodiments from Fig. 69 further include encapsulating the semiconductor die, including a second surface of the same opposite the first surface, and at least one section of the metal columns (6908) with an encapsulating means, and forming a second substrate on the encapsulating means and the metal columns (6910). The exemplary embodiments from Fig. 69 further include forming vias through the second substrate (6912) and forming a redistribution layer on the second substrate, which is connected to the first surface of the semiconductor die, the second surface of the semiconductor die and at least one of the metal pillars via the vias (6914).

[0253] As described herein, exemplary embodiments may include a device embedded in a substrate to provide heat dissipation, compatibility of the coefficient of thermal expansion, lower thermal / electrical resistance of the package, and other electrical or thermal properties. The device may include a semiconductor die, a packaged electronic device, or a multi-chip module, and the substrate may include a semiconductor substrate. The device and the substrate may include silicon, silicon carbide, GaN, GaaS, other wide-bandgap materials, hybrid materials, or any other electronic / semiconductor material. The substrate may include one or more vias for electrical connections to one or more electrical interconnects on the device.

[0254] The device may include a MOSFET, IGBT, or other power, sensor, processor, or other integrated circuits. The device may include one or more electrical interconnects on a top and / or bottom main surface, such as a gate, source, drain, other signals, or a dummy circuit. The substrate includes one or more blocks integrated into a larger substrate block with a cavity, a lid, a top surface, and a bottom surface. The substrate includes one or more redistribution layers on the top and / or bottom surface, with the redistribution layer including one or more exposed external electrical interconnect surfaces.

[0255] A non-conductive material can be used to mount the device(s) within a cavity. The device can be attached to the substrate, the RDL, or vias using an electrically conductive material. The cover wafer / substrate / assembly and / or the RDL can include conductive and non-conductive layers. The substrate and / or device can include one or more structured layers for forming electrical circuits, blind and / or vias, and / or the substrate and / or device can include one or more electrical connections comprising one or more wire bonds, terminals, diffusion bonds, pillars, or combinations thereof. The non-conductive metal layers can include, for example, gold, silver, aluminum, titanium, nickel, TiW, copper, nickel-vanadium, or any combination or alloy thereof.

[0256] Various exemplary embodiments may include an arrangement comprising one or more of the device implementations described above. Various exemplary embodiments may include a method for manufacturing the device or an arrangement thereof and / or a method for assembling the device or an arrangement thereof. Various exemplary embodiments may include a power system including one or more of the devices or an arrangement thereof, a traction motor system including one or more of the devices or an arrangement thereof, and / or a multiphase motor system including one or more of the devices or an arrangement thereof.

[0257] Exemplary embodiments include one with a single piece of silicon (e.g., with a cavity) on the top surface of a metal plate. Such embodiments may include a single device or multiple devices in parallel (e.g., with directly connected drain(s)).

[0258] Embodiments may include one cavity per device or one cavity for multiple dies. The number of cavities (of varying sizes) in a bottom / bottom arrangement may differ from the number in an top / top arrangement. One or more cavities in a bottom / bottom arrangement substrate may have a different depth than those in the top / top arrangement. Different cavities in a single substrate may have different depths (e.g., to accommodate dies of varying thicknesses), including a cavity that extends completely through the depth of one or more substrates. One or more cavities may be present in only one of the bottom / top arrangements.

[0259] As described above, electrical insulation and heat conduction can be provided on one side of exemplary modules, while all electrical conduction / connection is provided on the opposite side of the module, e.g. using an RDL and vias (e.g. TSVs).

[0260] For example, an upper / top surface can provide electrical connectivity, while a lower / bottom surface provides thermal conductivity, or vice versa. In other examples, a top or bottom surface can be electrically conductive on part of its area, while another part is electrically insulated (but thermally conductive), thus enabling partial double-sided cooling.

[0261] Exemplary embodiments redistribute signals along the upper surface of a lower / bottom substrate, wherein the upper / top substrate is recessed to provide electrical connectivity while simultaneously enabling electrically isolated double-sided cooling. Alternatively, redistribution can occur along the underside of the upper substrate.

[0262] The spacing of the discrete power components in the substrates can be designed to optimize heat generation, distribution and / or signature.

[0263] The embedded active circuitry can be located in either the upper or the lower substrate, or in both. One of the upper / lower substrates can be recessed to provide an exposed middle surface for connectivity. The active circuitry can be enclosed in a second embedded die, which is connected to a first embedded die via a redistribution layer (or layers).

[0264] Exemplary embodiments provide the ability to bond one or both substrates with different materials, e.g., for thermal conductivity with electrical insulation. For example, direct bonding of silicon to diamond can be provided.

[0265] In some examples, diamond produced by chemical vapor deposition (CVD) can be used. In some examples, the insulators used can be both electrically insulating and highly thermally conductive. Such insulators can include, for example, Si3N4 or CVD-coated diamond.

[0266] In some examples, one or more cooling elements may be used, enclosing a thermoelectric cooler (TEC), a heat sink, or a low-temperature co-fired ceramic (LTCC) cavity (a cavity created within a multilayer LTCC substrate; used to fabricate high-performance passive components such as filters and antennas). In this context, LTCC technology refers to a method of fabricating multilayer circuits from ceramic substrates. An exemplary LTCC device may include multiple dielectric layers, screen-printed or photo-imaged low-loss conductors, embedded baluns, resistors and / or capacitors, and through-holes for connecting the multiple layers.Other examples include a thin-film substrate with microfluidic channels, flexible thermoelectric generator (TEG) cooling, one or more microfluidic channels (on any desired / available side of a device), liquid cooling, a heat exchanger (e.g., an evaporative heat exchanger), and / or air / refrigerant flow.

[0267] Various techniques can be used to connect two or more of the aforementioned cooling elements or parts thereof. For example, techniques and / or connection components may include a thermal clamp, thermal vias and / or vias through silicon (TSVs), thermal adhesive, thermal paste, a heat pipe, sintering, or soldering.

[0268] Exemplary embodiments may include electrically conductive, redistributed terminals that are soldered onto a printed circuit board using standard PCB manufacturing / assembly techniques and technologies such as soldering (e.g., reflow and / or wave soldering). In other embodiments, such terminals may be soldered, welded, screwed, or otherwise (mechanically and electrically, e.g., using ACA bonding) connected to any electrically conductive traces such as printed circuit boards, busbars, or the like.

[0269] Exemplary embodiments may include embedded MEMS technology in one or both of the upper / lower substrate(s) and / or in a separate embedded die. For example, the MEMS technology may be integrated into a discrete power die (e.g., SiC or GaN power FET) or could furthermore be integrated with an embedded active circuitry in one or both substrates. For example, the MEMS technology and active circuitry may be embedded in one substrate, or there may be one substrate for MEMS and another for analog / digital / mixed ICs.

[0270] In exemplary embodiments, a semiconductor switching device can be embedded / integrated in parallel with a MEMS relay / contactor (or multiple relays connected in series), so that the semiconductor can make and break connections (without arcing), while the MEMS relay / contactor can achieve a very low (mechanical contact) resistance in the ON state. In one exemplary embodiment, the MEMS relay / contactor is connected in series with a semiconductor and provides galvanic isolation in the OFF state. In another exemplary embodiment, the semiconductor has one MEMS relay / contactor connected in parallel and another connected in series to achieve all the functions of a high-voltage DC-capable, high-speed solid-state relay / contactor.In one exemplary embodiment, the MEMS technology can include microfluidics, which enables liquid cooling of the module without the need for an external liquid-cooled heat sink.

[0271] Exemplary embodiments include embedded integrated passive devices (IPDs) such as MIMCAPs using multiple metal routing layers / RDL or other standard silicon processes. Other types of integrated capacitors (such as MOSCAPS) can also be included, as well as inductors and resistors. Such elements can be located in a bottom / bottom-side and / or top / top-side substrate or in a second embedded die.

[0272] Geometry / impedance-controlled redistribution routing (manual or automatic) can be provided. For example, a target value of 50 ohms or a similar routing / termination impedance can be set. Accordingly, a specific transmission delay target can be achieved, or the redistribution inductance / impedance of two routes / connections, such as parallel-connected power semiconductors, can be adjusted. For example, automatic routing of the RDL can be provided to achieve specific impedance targets. In exemplary embodiments, machine learning (ML) and / or other implementations of artificial intelligence (AI), such as generative AI, can be used to optimize specific goals (e.g., size, cost, or number of metal layers) and / or to achieve automation.

[0273] Two or more dies can be embedded in a single substrate sandwich. Two or more discrete power dies can be present, connected in parallel via substrate redistribution. Multiple devices or sets of devices in parallel can be present in half-bridge configurations. Multiple devices or sets of devices / half-bridges in parallel can be present, forming a pack of six or more half-bridges for multi-phase systems (e.g., three-phase or six-phase traction converters). Different dies can be present, serving different purposes and made from different materials (e.g., a Si IC die embedded along with a SiC and / or GaN transistor). Such dies can have different thicknesses.

[0274] There can be one die per cavity or multiple dies in a single cavity. There can be multiple dies per cavity in one substrate, while the other substrate has only a single die per cavity. Two or more modules can be combined in a horizontal arrangement, or two or more modules can be stacked vertically to form multilayer systems. There can be two or more vertically stacked modules using, for example, four, three, or two silicon substrates. There can be "terraced" implementations, where one level is a POS terminal (VDD) of a half-bridge, the next level is the OUTPUT (switching node), and the top level is a NEG terminal (GND, Rtn). In another example, the terminals can be arranged in a different order.

[0275] Electrical routing can be provided in a middle layer or on one or both of the top / bottom surfaces of a module, with the thermal interface (and electrical insulation) located partially or completely on one or both surfaces of the module. "N" layers can be stacked vertically. Example modules can be electrically configured in a half-bridge configuration with a positive terminal on one surface, an output in the middle, and a negative terminal on the other surface.

[0276] In exemplary embodiments, a finished module can itself be considered a base device and can be embedded in or nested within a larger module.

[0277] As mentioned previously, various implementations (single-die, multi-die, multi-stack) can be combined. The combination of multiple dies, chips, modules, and systems (horizontally and / or vertically) enables the formation of fully integrated miniaturized systems. For example, such a system may include multiple discrete power dies (e.g., WBG devices such as SiC or GaN power transistors), MEMS relays, nanotubes (microfluidics), temperature sensors, drivers for the discrete power devices, as well as other analog, digital, and mixed-signal ICs and / or passive devices (IPDs) for filtering, decoupling, local energy storage, and current limiting.

[0278] In more specific examples, a fully integrated miniaturized traction motor driver can be provided for integration into a motor, including a power stage with drivers, current sensing, feedback (shaft / rotor position), PWM generation, motor drive / control, filtering, decoupling and local energy storage, as well as protection, where this protection can include temperature reduction, overcurrent protection, short-circuit protection, or an electrical fuse for the busbar (e.g., an extremely fast high-voltage DC circuit breaker with galvanic isolation).

[0279] Small size can be achieved by using a higher switching frequency (e.g., above 20 kHz) and multiple (lower current) modules working together, including, for example, in combination with advanced inverter topologies such as multi-level inverters (e.g., Hybrid Switched Cap [HSC], Flying Cap Multi-Level [FCML], or similar).

[0280] Exemplary embodiments can have a final total finished thickness of less than, for example, 875 µm, which allows processing on standard wafer handling equipment.

[0281] The described techniques can be used in any context as a replacement for wire bonds and other conventional interconnection techniques, and are well-suited for power supply applications, for example, due to the improvements in electrical and thermal performance described herein. The described techniques can be implemented using standard semiconductor processing methods such as lithography structuring and can also utilize soldering, polymer jet printing, or screen printing through a metal mask.

[0282] In some implementations, soldering may be or include a process of joining two surfaces (e.g., metal surfaces) using a molten filler metal (e.g., metal alloy, tin (Sn), lead (Pb), silver (Ag), copper (Cu)) that may be referred to as a solder.

[0283] In some implementations, sintering can be a process of fusing particles into a solid mass by using, for example, a combination of pressure and / or heat, or it can include this process without melting the materials. In some implementations, sintering can involve fusing a material (e.g., a powdered material) into a solid or porous mass by heating, and usually also compressing the material without liquefaction. In some implementations, the materials usable for sintering can include metals such as silver (Ag), copper (Cu), and / or metal alloys. In some implementations, sintered compounds can exhibit desirable electrical and / or thermal conductivity, durability, and a relatively high melting point.

[0284] In some implementations, one or more of the components described herein can be coupled using materials such as a solder, a sintered material (e.g., silver, copper material) and / or other metal-to-metal bonding materials.

[0285] In some implementations, coupling of components can be carried out, for example, using a soldering process, a sintering process (e.g., a silver sintering process, a copper sintering process) and / or other metal-to-metal bonding processes.

[0286] In some implementations, the direct-bonded metal substrate (DBC substrate) (e.g., direct-bonded copper (DBC)) can enclose an insulating layer positioned between a first metal layer and a second metal layer. The insulating layer can be, for example, a ceramic layer. In some implementations, the insulating layer can be, for example, a ceramic material such as aluminum oxide (Al₂O₃) or aluminum nitride (AlN).

[0287] In some implementations, a DBM substrate can be formed by bonding one or more of the metal layers (e.g., first metal layer, second metal layer) to the insulating layer. In some implementations, one or more of the metal layers can be bonded to the insulating layer, for example, using a high-temperature process.

[0288] In some implementations, the first and / or second metal layer of the DBM substrate can be or function as a heat sink. In some implementations, the first and / or second metal layer can be coupled to a heat sink. In some implementations, at least a portion of one or more of the first or second metal layers can be exposed by a molding material.

[0289] In some implementations, the first and / or second metal layer of the DBM substrate may be or include a structured metal layer that incorporates one or more electrically conductive traces. In some implementations, the first and / or second metal layer may be or include a structured layer configured to form one or more electrical circuits, one or more conductive vias (both reactive and / or through-holes), and / or so forth.

[0290] In some implementations, a DBM substrate may be a directly bonded copper substrate (DBC) or include one (e.g., a DBM with copper metal layers). In some implementations, such as DBC substrate implementations, the first metal layer and / or the second metal layer is a copper layer.

[0291] In some implementations, one or more semiconductor dies (e.g., one or more semiconductor components) may be or include a power semiconductor die. In some implementations, one or more semiconductor dies may be (e.g., be a section of) one or more metal-oxide-semiconductor field-effect transistors (MOSFETs), an insulated two-pole gate transistor (IGBT), an integrated circuit (IC), an inverter, a power conversion circuit, a bridge circuit, a fast recovery diode (FRD), a diode, and / or so on. In some implementations, one or more semiconductor chips may be (e.g., be a part of) a component for an electric vehicle (EV).

[0292] More than one semiconductor die can be included in the implementations described herein. In some implementations, different semiconductor dies (where more than one semiconductor die is included) can be fabricated using different semiconductor substrates (e.g., a silicon carbide substrate (SiC substrate), a silicon substrate (Si substrate), a gallium nitride substrate (GaN substrate), etc.). In other words, the different semiconductor dies can be fabricated on different semiconductor wafers or materials, for example. This can be referred to as a hybrid die configuration. For example, a first semiconductor die can be formed using a SiC substrate, and a second semiconductor die (separate from the first semiconductor die) can be formed using a silicon substrate.As another example, an IGBT can be manufactured using a SiC substrate, while a controller can be manufactured using a silicon substrate.

[0293] In exemplary implementations, a first semiconductor die can be connected to a second semiconductor die, for example, by an electrical connection (e.g., a wire bond, an electrical clip connection) extending directly from the first die to the second die, or by a conductor formed in the first conductive layer (e.g., a metal layer) of the power electronics substrate. The first of the multiple semiconductor dies can also be connected to terminal frame posts by electrical connections such as wire bonds or clips.

[0294] In exemplary implementations, a package (e.g., a power module) can be a hybrid device package enclosing a semiconductor die or a plurality of semiconductor dies integrated on a unifying power electronics substrate (e.g., a ceramic substrate, a DBM or DBC substrate, or an AMB substrate). In some implementations, multiple semiconductor devices (e.g., fabricated on the same substrate, such as a SiC substrate) may be suitable for high-power applications.

[0295] Although referred to as a connection frame in at least some sections of this detailed description, the connection frame can encompass any type of conductive section of a package (e.g., conductive section, conductive terminal) that can provide an external connection point from the package. Accordingly, the connection frame can be referred to as the conductive section of the package.

[0296] In some implementations, one or more sections of a leadframe can be coupled to a pad (e.g., a bond pad) on at least one section of a DBM substrate.

[0297] The semiconductor device packages described herein can include a variety of signal connections. These connections can be power connections, input signal connections, output signal connections, and so on. In some implementations, the various signal connections can be enclosed within a leadframe. In some implementations, a leadframe can include any type of conductive section of a package (e.g., conductive section, conductive terminal) that can provide an external connection point from the package. Accordingly, a leadframe can be described as the conductive section of a package or assembly. In some implementations, one or more sections of a leadframe can be coupled to a pad (e.g., a bond pad) on at least one section of a DBM substrate and / or a semiconductor die.

[0298] In some implementations, a molding compound (e.g., a molding material or encapsulation material) can be or include a non-conductive layer / material. In some implementations, the molding compound is a non-conductive material, such as an epoxy resin, that can be formed (applied, etc.) using a transfer molding or compression molding process. In some implementations, the molding compound can include a separate plastic housing that is enclosed within the semiconductor device assembly.

[0299] One or more wire bonds, which may be enclosed in at least some of the implementations described herein, can be replaced by a conductive component. For example, in some implementations, one or more wire bonds can be replaced by a conductive clip. The conductive clip can be coupled to another component (e.g., a connection pad, a leadframe, a semiconductor die, and / or so on) using, for example, solder (e.g., a soldering process), a sintered connection (e.g., a sintering process), a weld, and / or so on. In some implementations, one or more wire bonds and / or clips can function as input and / or output power connectors, signal connectors, power connectors, etc.

[0300] In some implementations, one or more semiconductor chips associated with the implementations described herein may be embedded in a layer (rather than being mounted on the surface). For example, one or more semiconductor dies may be arranged in a depression (which may be a cavity or also be referred to as such) of a layer (e.g., a substrate, a printed circuit board, a conductive layer, or an insulating layer).

[0301] In some implementations, one module (e.g., a package enclosing a semiconductor device) can be enclosed within another module. The module can be referred to as a package. For example, one or more modules can be one or more submodules contained within another module. In other words, a first module can be contained as a submodule within a second module.

[0302] In some implementations, a spacer material can be an epoxy resin, a silicone adhesive, a conductive material, a non-conductive material, an organic material, a semiconductor material, a metal alloy, a metal foam, a phase-change material, etc.

[0303] In the present description, the semiconductor die(s) that may be used can be one of a wide variety, including, as a non-limiting example, power semiconductor dies, diodes, metal-oxide field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), hybrid devices, rectifiers, random-access memory, high electron mobility transistors, image sensors, wide-bandgap semiconductor devices (WBGs), hybrid devices, or any other type of semiconductor die / device. For the semiconductor die that is packaged with the semiconductor package designs disclosed in this document, a wide variety of semiconductor substrate types can be used, including, as a non-limiting example, silicon, silicon carbide, gallium arsenide, gallium nitride, silicon on insulator, ruby, sapphire, or any other type of semiconductor material.A wide variety of semiconductor package configurations can be formed using the principles disclosed herein.

[0304] It is understood that in the foregoing description, when an element, such as a layer, region, substrate, or component, is described as being on, connected to, electrically connected, coupled, or electrically coupled to another element, it may be directly on, connected to, or coupled to the other element, or one or more intervening elements may be present. Conversely, when an element is described as being "directly on," "directly connected to," or "directly coupled to" another element or layer, no intervening elements or layers are present. Although the terms "directly on," "directly connected to," or "directly coupled to" may not be used in the detailed description, elements shown as being "directly on," "directly connected to," or "directly coupled" may be identified as such.The claims of the application may be amended, if necessary, to specify exemplary relationships that are described in the patent specification or shown in the figures.

[0305] As used in the patent specification and claims, a singular form may include a plural form unless a specific case is clearly indicated in relation to the context. Spatial terms (e.g., above, over, upper, under, below, beneath, lower, and the like) are intended to include various orientations of the device in use or operation in addition to the orientation shown in the figures. In some implementations, the relative terms "above" and "below" may each include "vertically above" and "vertically below," respectively. In some implementations, the term "adjacent" may include "laterally adjacent to" or "horizontally adjacent to."

[0306] Some implementations can be implemented using various semiconductor processing and / or packaging techniques. Some embodiments can be implemented using different types of semiconductor processing techniques in conjunction with semiconductor substrates, including, but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and / or the like.

[0307] Several exemplary embodiments are provided in the following list. 1. A semiconductor package, comprising: a substrate; a semiconductor die arranged on the substrate and having at least one first contact on a first side and at least one second contact on a second side opposite the first side; a dielectric encapsulation material that encapsulates the semiconductor die and has vias formed therein; and a redistribution layer formed on the dielectric encapsulation material and connected to the first and second contacts via the vias. 2. The semiconductor package according to Example 1, further comprising a conductive layer electrically connected to the second contact and arranged between the second contact and the substrate, wherein the conductive layer is electrically connected to the redistribution layer via at least one of the vias. 3. The semiconductor package according to Example 1, wherein the substrate is electrically isolated from the semiconductor die by the dielectric encapsulation material. 4. The semiconductor package according to Example 1, wherein the semiconductor die is arranged on a first surface of the substrate and further comprising a heat sink arranged on a second surface of the substrate opposite the first surface of the substrate. 5. The semiconductor package according to Example 1, wherein the second contact of the semiconductor die is electrically connected to the substrate. 6. The semiconductor package according to Example 1, further comprising: an insulating layer formed on the dielectric encapsulation material and on the redistribution layer, wherein the insulating layer has second vias formed therein; and a second redistribution layer formed on the insulating layer, which is connected to the redistribution layer via the second vias. 7. The semiconductor package according to Example 1, further comprising a cavity formed in the substrate, wherein the semiconductor die is arranged inside the cavity. 8. The semiconductor package according to Example 1, further comprising: a second substrate formed from semiconductor material and arranged on the dielectric encapsulation material, wherein the second substrate has second vias formed therein, wherein the redistribution layer is formed on the second substrate and is connected to the first contact and the second contact via the vias and the second vias. 9. The semiconductor package according to Example 1, further comprising: a second semiconductor die that is located on the redistribution layer; a second dielectric encapsulation material formed on the redistribution layer and encapsulating the second semiconductor die, wherein the second dielectric encapsulation material has second vias formed therein; and a second redistribution layer formed on the second dielectric encapsulation material and connected to the semiconductor die via the vias and the second vias. 10. The semiconductor package according to Example 1, further comprising: a second substrate formed from semiconductor material; a second semiconductor die, which is arranged on a first side of the second substrate that faces the semiconductor die; a second dielectric encapsulation material that at least partially encapsulates the second semiconductor die; second vias formed by the second dielectric encapsulation material, wherein the semiconductor die and the second semiconductor die are connected via the second vias; third vias formed by the second dielectric encapsulation and the second substrate; fourth vias formed through the second substrate; and a second redistribution layer, which is formed at least partially on a second side of the second substrate, opposite the first side of the second substrate, and which is connected to the redistribution layer and the second semiconductor die via the second vias, the third vias and the fourth vias. 11. The semiconductor package according to Example 1, further comprising: second vias formed through the substrate; and a conductive layer that is formed on the substrate and connected to the semiconductor die via the second vias. 12. The semiconductor package according to Example 1, wherein individual contacts of the redistribution layer are positioned in a square, flat footprint without conductor connections (QFN). 13. The semiconductor package according to Example 1, wherein individual contacts of the redistribution layer are electrically connected to corresponding contacts of a printed circuit board. 14. The semiconductor package according to Example 1, further comprising: a second substrate with a cavity formed therein, wherein the substrate is positioned within the cavity. 15. The semiconductor package according to Example 1, wherein individual contacts of the redistribution layer are positioned in a square flat base without conductor connections and further comprising a magnetic structure arranged on a surface of the substrate opposite the redistribution layer. 16. A method for manufacturing a semiconductor package, comprising: Providing a semiconductor die on a substrate, wherein the semiconductor die has at least one first contact on a first side and at least one second contact on a second side opposite the first side; Encapsulation of the semiconductor die with a dielectric encapsulation material; Formation of vias in the dielectric encapsulation material; and Forming a redistribution layer on the dielectric encapsulation material, which is connected to the first contact and the second contact via the vias. 17. The procedure according to Example 16, comprising: Providing a conductive layer that is electrically connected to the second contact and is arranged between the second contact and the substrate, wherein the conductive layer is electrically connected to the redistribution layer via at least one of the vias. 18. The method according to Example 16, wherein the substrate is electrically isolated from the semiconductor die by the dielectric encapsulation material. 19. The procedure according to Example 16, further comprising: Arranging the semiconductor die on a first surface of the substrate; and Arranging a heat sink on a second surface of the substrate, opposite the first surface of the substrate. 20. The procedure according to Example 16, further comprising: Forming an insulating layer on the dielectric encapsulation material and on the redistribution layer; Forming second vias in the insulating layer; and forming a second redistribution layer on the insulating layer, which is connected to the redistribution layer via the second vias. 21. The procedure according to Example 16, further comprising: Forming a cavity in the substrate; and Arranging the semiconductor die within the cavity. 22. The procedure according to Example 16, further comprising: Arranging a second substrate formed from semiconductor material on the dielectric encapsulation material; Forming second vias in the second substrate; and forming the redistribution layer on the second substrate, and connecting to the first contact and the second contact via the vias and the second vias. 23. The procedure according to Example 16, further comprising: Arranging a second semiconductor die on the redistribution layer; Forming a second dielectric encapsulation material on the redistribution layer and encapsulating the second semiconductor die; Formation of second vias in the second dielectric encapsulation material; and Forming a second redistribution layer on the second dielectric encapsulation material and connecting to the semiconductor die via the vias and the second vias and connecting to the second semiconductor die via the second vias. 24. The procedure according to Example 16, further comprising: Arranging a second semiconductor die on a first side of a second substrate formed from semiconductor material, which faces the semiconductor die; at least partially encapsulating the second semiconductor die with a second dielectric encapsulation material; Forming second vias through the second dielectric encapsulation material, wherein the semiconductor die and the second semiconductor die are connected via the second vias; Formation of third vias through the second dielectric encapsulation material and through the second substrate; Forming fourth vias through the second substrate; and forming a second redistribution layer at least partially on a second side of the second substrate, opposite the first side of the second substrate, and connected to the redistribution layer and the second semiconductor die via the second vias, the third vias and the fourth vias. 25. The procedure according to Example 16, further comprising: Formation of secondary vias through the substrate; and Forming a conductive layer on the substrate and connecting it to the semiconductor die via the second vias. 26. The procedure according to Example 16, further comprising: Forming a cavity in a second substrate; and Arranging the substrate within the cavity. 27. A semiconductor package, comprising: a first substrate; a semiconductor die that is arranged on the first substrate; a second substrate with a cavity formed therein, wherein the cavity defines a first section of the second substrate with a first depth and a second section of the second substrate with a second depth greater than the first depth, and wherein the second substrate is attached to the first substrate by the second section of the second substrate and wherein the semiconductor die is arranged inside the cavity; a via formed through the first section of the second substrate; and a contact that is positioned on the second substrate and electrically connected to the semiconductor die via the via. 28. The semiconductor package according to Example 27, wherein the via is a second via, the contact is a second contact and further comprising: a first through-hole connection formed by the first substrate; and a first contact that is placed on the first substrate and electrically connected to the semiconductor die via the first via. 29. The semiconductor package according to Example 27, further comprising: a second via formed by the second section of the second substrate; a metal layer formed between the semiconductor die and the first substrate, extending between the first substrate and the second section of the second substrate; and A redistribution layer formed on the second substrate includes the contact and a second contact that is electrically connected to the metal layer via the second via. 30. The semiconductor package according to Example 27, wherein the cavity is a second cavity and further comprising: a first cavity formed in the first substrate and aligned with the second cavity to form a combined cavity, wherein the semiconductor die is arranged within the combined cavity. 31. The semiconductor package according to Example 30, wherein the cavity has a first depth which differs from a second depth of the second cavity. 32. The semiconductor package according to Example 27, further comprising a redistribution layer on the second substrate and a heat sink on the first substrate. 33. The semiconductor package according to Example 27, further comprising: a first metal attachment point between the first substrate and the second substrate; a second metal attachment point between the semiconductor die and the second substrate; and a third metal attachment point between the semiconductor die and the first substrate. 34. The semiconductor package according to Example 27, wherein the first substrate comprises a metal substrate. 35. The semiconductor package according to Example 34, further comprising: a second via formed by the second section of the second substrate; a third substrate arranged around a circumference of the first substrate and having a third via formed through it; and a redistribution layer formed on the second substrate and connected to the first substrate and thereby to the semiconductor die via the second via and the third via. 36. The semiconductor package according to Example 27, wherein the first substrate comprises a directly bonded metal substrate. 37. The semiconductor package according to Example 27, further comprising: a dielectric layer formed on the second substrate; and a heat sink formed on the dielectric layer. 38. The semiconductor package according to Example 27, further comprising: a first metal layer that extends through the first substrate and parallel to a surface of the semiconductor die and is electrically connected to the semiconductor die; a second metal layer that encloses the contact and extends through the second substrate and parallel to the surface of the semiconductor die; a second via formed by the second section of the second substrate; a third via formed through the first substrate; and a redistribution layer formed on the first substrate between the first substrate and the second substrate, which is electrically connected to the first metal layer by means of the third via and to the second metal layer by means of the second via. 39. The semiconductor package according to Example 27, wherein the second substrate includes a semiconductor substrate and further comprising an electronic element formed in the second substrate and connected to the semiconductor die by means of the contact. 40. The semiconductor package according to Example 27, wherein at least one of the first substrate and the second substrate includes a semiconductor substrate and further comprising a microelectromechanical system element formed in at least one of the first substrate and the second substrate and connected to the semiconductor die by means of the contact. 41. The semiconductor package according to Example 40, wherein the semiconductor die and the microelectromechanical system element are combined to provide a relay. 42. The semiconductor package according to Example 27, wherein at least one of the first substrate and the second substrate includes a semiconductor substrate and further comprising microelectromechanical systems and microfluidic heat conduction formed in at least one of the first substrate and the second substrate. 43. A method for manufacturing a semiconductor package, comprising: Arranging a semiconductor die on a first substrate; Forming a cavity in a second substrate, wherein the cavity defines a first section of the second substrate with a first depth and a second section of the second substrate with a second depth greater than the first depth; Attaching the second substrate to the first substrate through the second section of the second substrate, wherein the semiconductor die is arranged within the cavity; Forming a through-hole connection through the first section of the second substrate; and Arranging a contact on the second substrate, which is electrically connected to the semiconductor die via the through-hole. 44. The method according to Example 43, wherein the via is a second via, the contact is a second contact, and further comprising: Forming an initial through-hole through the first substrate; and Arranging a first contact on the first substrate and electrically connecting it to the semiconductor die via the first via. 45. The procedure according to Example 43, further comprising: Forming a second via through the second section of the second substrate; Forming a metal layer between the semiconductor die and the first substrate and expanding between the first substrate and the second section of the second substrate; and Forming a redistribution layer on the second substrate, which includes the contact and a second contact that is electrically connected to the metal layer via the second via. 46. ​​The method according to Example 43, wherein the cavity is a second cavity, and further comprising: Forming a first cavity in the first substrate and aligning it with the second cavity to form a combined cavity, with the semiconductor die being arranged inside the combined cavity. 47. The method according to Example 46, wherein the first cavity has a first depth which differs from the second depth of the second cavity. 48. The procedure according to Example 43, further comprising: Forming a redistribution layer on the second substrate; and Providing a heat sink on the first substrate. 49. The procedure according to Example 43, further comprising: Providing an initial metal attachment point between the first substrate and the second substrate; Providing a second metal attachment point between the semiconductor die and the second substrate; and Providing a third metal attachment point between the semiconductor die and the first substrate. 50. The method according to Example 43, wherein the first substrate comprises a metal substrate. 51. The procedure according to Example 43, further comprising: Forming a second via through the second section of the second substrate; Arranging a third substrate around a circumference of the first substrate; Forming a third via through the third substrate; and forming a redistribution layer on the second substrate and connecting to the first substrate and thereby, via the second via and the third via, to the semiconductor die. 52. The procedure according to Example 43, further comprising: Providing a first metal layer that extends through the first substrate and parallel to a surface of the semiconductor die and is electrically connected to the semiconductor die; Providing a second metal layer that encloses the contact and extends through the second substrate and parallel to the surface of the semiconductor die; Forming a second via through the second section of the second substrate; Forming a third via through the first substrate; and forming a redistribution layer on the first substrate between the first substrate and the second substrate, which is electrically connected to the first metal layer by means of the third via and to the second metal layer by means of the second via. 53. The method according to Example 43, wherein the second substrate includes a semiconductor substrate, and further comprising: Providing an electronic element that is formed in the second substrate and connected to the semiconductor die via the contact. 54. The method according to Example 43, wherein at least one of the first substrate and the second substrate includes a semiconductor substrate, and further comprising: Providing an element for microelectromechanical systems (MEMS) in at least one of the first substrate and the second substrate. 55. A semiconductor package, comprising: a substrate with a cavity formed within it; a magnetic element that is arranged in the cavity; a metallic winding that is arranged on the substrate and surrounds the magnetic element; a dielectric encapsulation material that encapsulates the magnetic element and the metallic winding; and a contact that is electrically connected to the metallic winding via a through-hole formed in the dielectric encapsulation material. 56. The semiconductor package according to Example 55, wherein the magnetic element encloses a cylindrical iron(II) puck. 57. The semiconductor package according to Example 55, wherein the metallic winding comprises structured metal layers wound around the magnetic element in at least two turns. 58. The semiconductor package according to Example 55, wherein the metallic winding has an inner terminal near an edge of the magnetic element and spirals to an outer terminal distal to the magnetic element. 59. The semiconductor package according to Example 58, wherein the substrate encloses a second cavity adjacent to the cavity and further comprising: a second magnetic element located in the second cavity; a second metallic winding arranged on the substrate and surrounding the second magnetic element; and at least one second contact which is electrically connected to the second metallic winding via a second through-hole formed in the dielectric encapsulation material. 60. The semiconductor package according to Example 59, wherein the second metallic winding has a second inner terminal and a second outer terminal, and wherein the outer terminal is furthermore electrically connected to the second inner terminal. 61. The semiconductor package according to Example 59, wherein the second metallic winding has a second inner terminal and a second outer terminal, and wherein furthermore the inner terminal and the second inner terminal have a first common contact and the outer terminal and the second outer terminal have a second common contact. 62. The semiconductor package according to Example 59, wherein the metallic winding has a first number of turns around the magnetic element and the second metallic winding has a second number of turns around the second magnetic element, which is less than the first number of turns. 63. A method for manufacturing a semiconductor package, comprising: Forming a cavity in a substrate; Arranging a magnetic element in the cavity; Providing a metallic winding on the substrate that surrounds the magnetic element; Encapsulation of the magnetic element and the metallic winding with a dielectric encapsulation material; Forming a through-hole in the dielectric encapsulation material; and Electrical connection of a contact to the metallic winding via the through-hole. 64. The method for producing a semiconductor package according to Example 63, wherein the magnetic element encloses a cylindrical iron(II) puck. 65. The method for manufacturing a semiconductor package according to Example 63, further comprising: Providing the metallic winding, including structured metal layers wound around the magnetic element in at least two turns. 66. The method for producing a semiconductor package according to Example 63, wherein the metallic winding has an inner terminal near an edge of the magnetic element and spirals to an outer terminal distal to the magnetic element. 67. The method for producing a semiconductor package according to Example 66, wherein the substrate includes a second cavity adjacent to the cavity and further comprising: Arranging a second magnetic element in the second cavity; Providing a second metallic winding on the substrate that surrounds the second magnetic element; Forming a second through-hole through the dielectric encapsulation material; and Electrical connection of a second contact to the second metallic winding via the second via. 68 The method for manufacturing a semiconductor package according to Example 67, wherein the second metallic winding has a second inner terminal and a second outer terminal, and further comprising: Electrical connection of the outer terminal to the second inner terminal. 69. The method for manufacturing a semiconductor package according to Example 67, wherein the second metallic winding has a second inner terminal and a second outer terminal, and further comprising: Providing the inner connection and the second inner connection with a first common contact; and

[0308] Providing the outer connection and the second outer connection with a second common contact. 70. The method for manufacturing a semiconductor package according to Example 67, further comprising: Providing the metallic winding with a first number of turns around the magnetic element; and

[0309] Providing the second metallic winding with a second number of turns around the second magnetic element, which is less than the first number of turns. 71. A semiconductor package, comprising: a first substrate; a metal layer that is arranged on the first substrate; Metal columns arranged on the metal layer, defining a cavity; a semiconductor die arranged in the cavity with a first surface that is located on the metal layer; an encapsulation material that encapsulates the semiconductor die, including a second surface of the same opposite the first surface, and at least one section of the metal columns; a second substrate formed on the encapsulation material and the metal columns; and a redistribution layer that is formed on the second substrate and is connected to the first surface of the semiconductor die, the second surface of the semiconductor die and at least one of the metal pillars via vias formed by the second substrate. 72. A method for manufacturing a semiconductor package, comprising: Forming a metal layer on a first substrate; Arranging metal columns on the metal layer to define a cavity; Arranging a semiconductor die in the cavity, wherein a first surface is arranged on the metal layer; Encapsulation of the semiconductor die with an encapsulating agent, including a second surface of the same opposite the first surface, and at least one section of the metal columns; Forming a second substrate on the encapsulation material and the metal columns; Forming vias through the second substrate; and Forming a redistribution layer on the second substrate, and connecting it to the first surface of the semiconductor die, the second surface of the semiconductor die and at least one of the metal columns via vias.

[0310] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents are now apparent to the person skilled in the art. It is therefore understood that the accompanying claims are intended to cover all such modifications and changes that fall within the scope of protection of the implementations. It is understood that they have been presented only as examples, without being limiting, and that various changes to form and details may be made.

[0311] Each section of the setup and / or procedure described herein can be combined in any combination, except for mutually exclusive combinations. The implementations described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the various implementations described.

[0312] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents are now apparent to the person skilled in the art. It is therefore understood that the appended claims are intended to cover all such modifications and changes that fall within the scope of protection of the embodiments. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 715.912

[0001] US 63 / 736.415

[0001] Cited non-patent literature

[0000] US-Anmeldung xx / xxx.xxx mit dem Titel „Semiconductor Module with Power Bridge for Integrated Die Interconnection

[0001]

Claims

[1] Semiconductor package, comprising: a substrate; a semiconductor die arranged on the substrate and having at least one first contact on a first side and at least one second contact on a second side opposite the first side; a dielectric encapsulation material that encapsulates the semiconductor die and has vias formed therein; and a redistribution layer formed on the dielectric encapsulation material and connected to the first and second contacts via the vias. [2] Semiconductor package according to claim 1, further comprising a conductive layer which is electrically connected to the second contact and is arranged between the second contact and the substrate, wherein the conductive layer is electrically connected to the redistribution layer via at least one of the vias. [3] Semiconductor package according to claim 1, further comprising a cavity formed in the substrate, wherein the semiconductor die is arranged inside the cavity. [4] Semiconductor package according to claim 1, further comprising: a second substrate formed from semiconductor material and arranged on the dielectric encapsulation material, wherein the second substrate has second vias formed therein, wherein the redistribution layer is formed on the second substrate and is connected to the first contact and the second contact via the vias and the second vias. [5] Semiconductor package according to claim 1, further comprising: a second semiconductor die that is located on the redistribution layer; a second dielectric encapsulation material formed on the redistribution layer and encapsulating the second semiconductor die, wherein the second dielectric encapsulation material has second vias formed therein; and a second redistribution layer formed on the second dielectric encapsulation material and connected to the semiconductor die via the vias and the second vias. [6] Semiconductor package according to claim 1, further comprising: a second substrate formed from semiconductor material; a second semiconductor die, which is arranged on a first side of the second substrate that faces the semiconductor die; a second dielectric encapsulation material that at least partially encapsulates the second semiconductor die; second vias formed by the second dielectric encapsulation material, wherein the semiconductor die and the second semiconductor die are connected via the second vias; third vias formed by the second dielectric encapsulation and the second substrate; fourth vias formed through the second substrate; and a second redistribution layer, which is formed at least partially on a second side of the second substrate, opposite the first side of the second substrate, and which is connected to the redistribution layer and the second semiconductor die via the second vias, the third vias and the fourth vias. [7] Semiconductor package according to claim 1, further comprising: a second substrate with a cavity formed therein, wherein the substrate is positioned within the cavity. [8] Semiconductor package, comprising: a first substrate; a semiconductor die that is arranged on the first substrate; a second substrate with a cavity formed therein, wherein the cavity defines a first section of the second substrate with a first depth and a second section of the second substrate with a second depth greater than the first depth, and wherein the second substrate is attached to the first substrate by the second section of the second substrate and wherein the semiconductor die is arranged inside the cavity; a via formed through the first section of the second substrate; and a contact that is positioned on the second substrate and electrically connected to the semiconductor die via the via. [9] Semiconductor package according to claim 8, wherein the via is a second via, the contact is a second contact and further comprising: a first through-hole connection formed by the first substrate; and a first contact that is placed on the first substrate and electrically connected to the semiconductor die via the first via. [10] Semiconductor package according to claim 8, further comprising: a second via formed by the second section of the second substrate; a metal layer formed between the semiconductor die and the first substrate, extending between the first substrate and the second section of the second substrate; and A redistribution layer formed on the second substrate includes the contact and a second contact that is electrically connected to the metal layer via the second via. [11] Semiconductor package according to claim 8, wherein the cavity is a second cavity and further comprising: a first cavity formed in the first substrate and aligned with the second cavity to form a combined cavity, wherein the semiconductor die is arranged within the combined cavity. [12] Semiconductor package according to claim 8, further comprising: a first metal attachment point between the first substrate and the second substrate; a second metal attachment point between the semiconductor die and the second substrate; and a third metal attachment point between the semiconductor die and the first substrate. [13] Semiconductor package according to claim 8, further comprising: a first metal layer that extends through the first substrate and parallel to a surface of the semiconductor die and is electrically connected to the semiconductor die; a second metal layer that encloses the contact and extends through the second substrate and parallel to the surface of the semiconductor die; a second via formed by the second section of the second substrate; a third via formed through the first substrate; and a redistribution layer formed on the first substrate between the first substrate and the second substrate, which is electrically connected to the first metal layer by means of the third via and to the second metal layer by means of the second via. [14] Semiconductor package according to claim 8, wherein the second substrate includes a semiconductor substrate and further comprising an electronic element formed in the second substrate and connected to the semiconductor die by means of the contact. [15] Semiconductor package according to claim 8, wherein at least one of the first substrate and the second substrate includes a semiconductor substrate and further comprising a microelectromechanical system element formed in at least one of the first substrate and the second substrate and connected to the semiconductor die by means of the contact. [16] Semiconductor package according to claim 15, wherein the semiconductor die and the microelectromechanical system element are combined to provide a relay. [17] Semiconductor package, comprising: a substrate with a cavity formed within it; a magnetic element that is arranged in the cavity; a metallic winding that is arranged on the substrate and surrounds the magnetic element; a dielectric encapsulation material that encapsulates the magnetic element and the metallic winding; and a contact that is electrically connected to the metallic winding via a through-hole formed in the dielectric encapsulation material. [18] Semiconductor package according to claim 17, wherein the magnetic element encloses a cylindrical iron(II) puck. [19] Semiconductor package according to claim 17, wherein the metallic winding comprises structured metal layers which wind around the magnetic element in at least two turns. [20] Semiconductor package according to claim 17, wherein the metallic winding has an inner terminal near an edge of the magnetic element and spirals to an outer terminal distal to the magnetic element. [21] Semiconductor package according to claim 20, wherein the substrate includes a second cavity adjacent to the cavity, and further comprising: a second magnetic element located in the second cavity; a second metallic winding arranged on the substrate and surrounding the second magnetic element; and at least one second contact which is electrically connected to the second metallic winding via a second through-hole formed in the dielectric encapsulation material.

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