Parallel high-bandwidth programming method with dynamic latch for three-dimensional memory layout

Abstract

A three-dimensional storage device is provided. The device comprises an array of memory cells, including a plurality of memory blocks with a first memory block. The first memory block contains a plurality of sets of subblocks. The device further comprises a global bit line; a controller; and a plurality of dynamic latch devices connected between the global bit line and the plurality of sets of subblocks. A first dynamic latch device of the plurality of dynamic latch devices is connected to a first set of subblocks. Different dynamic latch devices of the plurality of dynamic latch devices are connected to different sets of subblocks.The first dynamic latch device is controllable by the controller to store program data during a programming operation, where the first set of subblocks connected to the first dynamic latch device are not selected subblocks during the programming operation.

Description

RELATED REGISTRATIONS

[0001] This application claims priority over U.S. Preliminary Application No. 63 / 716,935, filed on November 6, 2024, entitled “HIGH BANDWIDTH PARALLEL PROGRAM METHOD WITH DYNAMIC LATCH FOR THREE-DIMENSIONAL MEMORY ARRAY,” and U.S. Non-Preliminary Application No. 19 / 370,476, filed on October 27, 2025, entitled “HIGH BANDWIDTH PARALLEL PROGRAM METHOD WITH DYNAMIC LATCH FOR THREE-DIMENSIONAL MEMORY ARRAY.” The contents of U.S. Preliminary Application No. 63 / 716,935 and U.S. Non-Preliminary Application No. 19 / 370,476 are hereby incorporated by reference in their entirety for all purposes. AREA OF TECHNOLOGY

[0002] This disclosure relates to one or more storage systems, including techniques related to dynamic latch devices, used to perform parallel read and program operations of a three-dimensional non-volatile memory arrangement in a storage device. GENERAL STATE OF THE ART

[0003] Storage devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a storage device to different states. For example, binary memory cells can be programmed to one of two supported states, often referred to as logical 1 or logical 0. In some examples, a single memory cell can support more than two states, each of which can be stored. To access the stored information, the storage device can read states from the memory cells (e.g., sense, detect, retrieve, determine). To store information, the storage device can write states to the memory cells (e.g., program, set, assign).Information can also be deleted from the memory cells, and new information can be stored in the memory cells.

[0004] There are various types of memory devices, including magnetic disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), self-selecting memory, chalcogenide memory technologies, not-or (NOR) and not-and (NAND) memory devices, and others. Memory cells can be described as volatile or non-volatile. Memory cells configured in a non-volatile configuration can retain stored logical states for extended periods, even without an external power source. Memory cells configured in a volatile configuration can lose stored states when disconnected from an external power source. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram of a storage device communicating with a storage control unit of a storage system, according to the examples disclosed herein. Fig. Figures 2A-2C are illustrative diagrams of parts of an arrangement of memory cells in a storage device, according to the examples disclosed herein. Fig. Figure 2D illustrates an example of a storage device comprising multiple blocks of memory cells, according to the examples disclosed herein. Fig. Figure 3 is a block diagram of an example device for implementing one or more systems and for carrying out one or more of the methods described herein, according to the examples disclosed herein. Fig. 4A and Fig. Figure 4B illustrates an exemplary three-dimensional construction of a storage device according to the examples disclosed herein. Fig. Figure 5 is a block diagram illustrating parts of a storage device with dynamic latch devices arranged over a three-dimensional storage arrangement, according to examples disclosed herein. Fig. Figure 6 is an example scheme of two dynamic latch devices, each connected to a set of subblocks in a memory block for storing program data, according to the examples disclosed herein. Fig. 7A is an example of two dynamic latch devices, each connected to a set of subblocks in a memory block, which is used to perform programming operations on multiple subblocks in parallel, according to examples disclosed herein. Fig. Figure 7B is a flowchart showing a procedure for programming a single subblock using a dynamic latch device, according to the examples disclosed herein. Fig. 7C is a flowchart showing a method for parallel programming of multiple sub-blocks using the dynamic latch devices with a single programming pulse, according to examples disclosed herein. Fig. 8A is an example of two dynamic latch devices, each connected to a set of subblocks in a memory block, which is used to perform parallel read or program verification operations on multiple subblocks, according to examples disclosed herein. Fig. Figure 8B is a flowchart showing a method for reading from a single subblock using a dynamic latch device, according to examples disclosed herein. Fig. 8C is a flowchart showing a method for reading multiple subblocks in parallel using multiple dynamic latch devices, according to examples disclosed herein. Fig. Figure 9 is an example waveform to show how to apply a programming pulse to cause the voltage of a potential-free column to change, according to the examples disclosed herein. DETAILED DESCRIPTION

[0005] Aspects of the present disclosure relate to dynamic latch devices that operate with a three-dimensional (3D) non-volatile memory array in a storage device to perform memory operations in parallel. A storage device may include one or more memory levels. In some types of non-volatile memory devices (e.g., NAND flash memory devices), each memory level includes a set of physical memory blocks (or simply "blocks"). Each block includes a set of subblocks. Each subblock includes a string of memory cells. A memory cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logical states that correlate with the number of bits stored.Logical states can be represented by binary values ​​such as "0" and "1" or combinations of such values.

[0006] A storage device comprises memory cells arranged in a two-dimensional or three-dimensional grid. Memory cells are formed on a silicon wafer in an arrangement of columns or strands and rows. Each column of memory cells corresponds to a subblock of memory cells connected by the same bit line. Each row of memory cells is connected by the same word line. The intersection of a bit line and a word line forms the address of the memory cell. A block, as used hereafter, refers to a unit of the storage device used to store data and can contain many subblocks (e.g., many strands of memory cells, each connected by a bit line). The subblocks within a memory block are typically connected by a global bit line to perform read and program operations. The global bit line is connected to a side buffer.One or more blocks can be grouped into separate partitions (e.g., levels) of the storage device to allow concurrent operations on each level. An example storage device with blocks and subblocks is described in more detail below.

[0007] During a programming operation on a non-volatile storage device, certain phases can occur, including programming and program verification. A program verification operation is similar to a read operation. For example, during a programming phase, a high programming voltage may be applied to a selected word line of a block of the storage device, followed by a program verification phase in which a verification voltage is applied to the selected word line. In existing technologies, a programming operation is a single programming operation in which a subblock is programmed with a programming pulse in each operation. In such a single programming operation, a data pattern is read from a temporary memory location (e.g., a memory location).A latch within a page buffer is read to determine whether the memory cell associated with a selected word line, located in a single subblock, should be programmed. A single programming pulse can then be applied before the programming verification phase begins. The same process can then be repeated for each remaining subblock to be programmed. However, this process would require multiple programming pulses, which would need to be applied to program multiple memory cells, resulting in increased latency.

[0008] A dynamic latch device is provided to enable parallel programming operations, such as dual programming operations. For example, two subblocks can be programmed in a single operation. Dynamic latch devices can be used in such dual programming operations. In some examples, a dynamic latch device is used for one or more subblocks within a memory block, and all dynamic latch devices in the memory block are connected to a local bit line. Consequently, all dynamic latch devices must be enabled when a particular subblock is selected for programming. This configuration may not be an efficient use of dynamic latch devices and can also decrease overall efficiency, as it may still exhibit a longer latency due to the multiple programming pulses required, as described in detail below.

[0009] Using a double programming operation as an example of a parallel programming operation, two subblocks are programmed using two separate programming pulses before the programming verification phase begins. Depending on the implementation, certain memory devices may use either a double verification operation or a seamless verification operation during the subsequent programming verification phase. In either case, programming multiple subblocks involves causing multiple separate programming pulses to be applied to the selected word line. Each programming pulse introduces latencies, including the multiple ramping up and down of the programming voltage. These latencies increase the duration of the programming operation, which can be particularly significant for high-priority and time-critical operations.

[0010] To reduce latency and improve overall operational efficiency, it is therefore desirable to have a storage device capable of implementing parallel programming operations (e.g., dual programming operations) using a single programming pulse. Based on dynamic latch devices, a storage device can program memory cells in two or more separate subblocks using a single programming pulse applied to the selected word line. For example, controlling the storage device as part of a programming operation causes a forward voltage to be applied to each word line in a block of the storage device, including the word line connected to a selected subblock containing memory cells to be programmed, and word lines connected to unselected subblocks.The forward voltage increases a memory column channel voltage in each subblock of the memory block to a higher boost voltage during this phase of the programming operation. Once each column channel voltage is increased, the controller can selectively discharge the columns of one or more subblocks according to a data pattern of bits to be programmed into the selected subblock during the programming operation. Such a process can be repeated for two or more subblocks.

[0011] Once the column voltage increase is complete, the controller can apply a single programming pulse to the word lines of the selected subblocks. The columns of the selected subblocks are discharged to ground voltage, and the memory cells within these subblocks are programmed. Meanwhile, the columns of the unselected subblocks remain at the boost voltage. These unselected subblocks are inhibited. In this way, the memory device allows multiple subblocks to be programmed simultaneously via the single programming pulse. During the subsequent programming verification phase, either a double verification operation or a seamless verification operation can then be performed.

[0012] As the number of bits to be programmed per memory cell increases (for example, in triple-level cell (TLC) or quad-level cell (QLC) memory, three or more bits are programmed into each memory cell), the number of latches used to store data associated with the programming operation increases dramatically. For example, to program a memory device configured as TLC memory, at least five latches may be required to program each subblock (e.g., three latches to hold the three data bits, one programming inhibit latch, and one slow programming latch). If multiple subblocks are to be programmed using a single programming pulse, the number of latches required also increases proportionally. Many memory devices enclose the programming latches in a side buffer located beneath the memory array.A page buffer can occupy a significant physical area within the physical layout of a storage device. In one example, the page buffer occupies approximately 50% of the total physical layout of the storage device. The page buffer is typically located physically below the array of memory cells, and therefore its space is limited. However, to perform parallel programming operations, it may be necessary to store more data in the page buffer. Therefore, the limited physical area of ​​the page buffer also makes it difficult to add more latches to the page buffer. This, in turn, complicates the implementation of parallel programming operations.

[0013] Aspects of the present disclosure address the aforementioned and other shortcomings by providing dynamic latch devices arranged over a non-volatile 3D memory array in a storage device. For example, a dynamic latch device can be connected to one or more subblocks within a memory block, referred to as a set of subblocks. Different dynamic latch devices are connected to different sets of subblocks within a memory block. In other words, there are essentially no local bit lines connecting a dynamic latch device to all subblocks within a memory block. This configuration allows some of the dynamic latch devices to be used as a storage device for storing program data during parallel programming operations.These dynamic latch devices, used for storing program data, are connected to unselected subblocks during a given programming operation. As described above, the page buffer occupies a large physical layout area, and therefore only a fixed number of latches can be implemented in the page buffer below the memory array of the storage device. The dynamic latch devices described in this disclosure are placed above the memory array and can be used to hold program data for the parallel programming of multiple selected subblocks. In this way, the dynamic latch devices are effectively used to compensate for the lack of storage devices in the page buffer and, in turn, enable parallel programming operations with a single programming pulse.This circuit configuration of the dynamic latch devices therefore reduces the latency of programming operations through more effective use of the dynamic latch devices.

[0014] In some examples, the latches in the side buffer and the dynamic latch devices placed above the memory array can be used together to enable efficient parallel programming operations. The latches in the side buffer can include a read amplifier latch, as well as a set (e.g., a pair) of even cache register latches and a set (e.g., a pair) of odd cache register latches, allowing each side buffer circuit to be used with multiple subblocks of the array. The other latches used to program multiple subblocks with a single programming pulse (e.g., those latches used to store the data patterns to be programmed into the multiple subblocks) can be the dynamic latch devices placed above the memory array.The latches above the array can be coupled to the latches in the side buffer located below the array, allowing data to be routed between them. Generally, the open area above the memory array is not limited in size, and multiple layers (e.g., CMOS layers) can be created to contain the associated latches.

[0015] Advantages of this approach include, but are not limited to, improved performance in the memory device. The dynamic latch devices arranged above the memory array can be used as additional storage devices to hold program data during parallel programming operations when connected to unselected subblocks. The arrangement of the dynamic latch devices above the memory array provides the number of dynamic latch devices used to program multiple subblocks in the memory block at the same time (e.g., simultaneously) using a single programming pulse, without increasing the footprint of the memory device. This results in the ability to perform fewer programming operations (e.g.,(Half the number of programming operations) must be performed for the same amount of data programmed into the storage device, without significantly increasing the size and / or area occupied by the storage device. Accordingly, the increased parallelism enabled by the dynamic latch device configuration described herein reduces the latency associated with the entire programming operation and improves overall operational efficiency and programming performance.

[0016] Fig. Figure 1 is a simplified block diagram of a storage device 130 communicating with a control unit 115 of a storage system. A storage system can be or include any device or collection of devices, wherein the device or collection of devices includes at least one storage arrangement. For example, a storage system can be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among others. A storage system can communicate with a host system, which may include a host control unit.The host system can be implemented using one or more processors and a storage system to write data to the storage system, read data from the storage system, delete data, or refresh data.

[0017] A storage system can include one or more storage devices, such as Device 130. A Storage Device 130 can include one or more memory arrays of any type of memory cell (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). For example, Storage Device 130 can include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), NOR (e.g., NOR flash) memory, etc. In some cases, Storage Device 130 is a NAND Storage Device 130 and can include memory cells configured to store one bit of information each, which can be referred to as single-level cells (SLCs).Additionally or alternatively, a NAND flash memory device can include 130 memory cells configured to each store multiple bits of information. These can be referred to as multi-level cells (MLCs) when configured to store two bits of information each, tri-level cells (TLCs) when configured to store three bits of information each, quad-level cells (QLCs) when configured to store four bits of information each, or more generally, multi-level memory cells. Multi-level memory cells can offer a higher storage density relative to SLC memory cells, but in some cases, they may result in tighter read or write margins or greater complexity for supporting circuitry.

[0018] As in Fig. As shown in Figure 1 and described in more detail below, the storage device 130 includes an array of memory cells 104 logically arranged in rows and columns. Memory cells of a logical row are typically associated with the same access line (e.g., a word line), while memory cells of a logical column are typically selectively associated with the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. Memory cells (not shown in Figure 1) are Fig. 1 shown) at least part of the arrangement of memory cells 104 are able to be programmed to one of at least two target data states in order to store any number of information bits.

[0019] With continued reference to Fig. A row decoding circuit 108 and a column decoding circuit 111 are provided to decode address signals. Address signals are received and decoded to access the array of memory cells 104. The memory device 130 also includes an input / output (I / O) control circuit 112 to manage the input of commands, addresses, and data to the memory device 130, as well as the output of data and status information from the memory device 130. An address register 114 communicates with the I / O control circuit 112 and the row decoding circuit 108 and the column decoding circuit 111 to latch the address signals before decoding. The row decoding circuit 108 and the column decoding circuit 111 can be referred to simply as the row decoder 108 and the column decoder 111, respectively.An instruction register 124 communicates with the I / O control circuit 112 and the local control 135 to latch incoming instructions.

[0020] A memory controller (e.g., the local controller 135 within the memory device 130) controls access to the array of memory cells 104 in response to commands and generates status information for the external control unit 115. That is, the local controller 135 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) on the array of memory cells 104. The local controller 135 communicates with the row decoding circuit 108 and the column decoding circuit 111 to control them according to the addresses.

[0021] In some embodiments, the local controller 135 communicates with the external system controller 115, which may be a host controller (e.g., a UFS or eMMC controller, or a CPU communicating with the local controller 135) located in a host system, or a memory system controller located in a memory system. In some embodiments, the local controller 135 is located on the same semiconductor die as the memory array (e.g., array 104), and a separate system controller 115 is located on a different die. In other examples, some parts of the memory device 130 may be located on a first die, and other parts of the memory device 130 may be located on a second die that is different from the first die. For example, the first die may contain the array of memory cells 104 and their associated circuitry, such as the column decoder 111 and the row decoder 108, etc.The second die can include logic circuits, power circuits, or other circuits of the device 130. Thus, the second die can include the system controller 115, the I / O controller 112, etc. In this example, the first die has no local controller, and the second die includes the system controller 115. The first die and the second die can be hybrid bonded to each other using, for example, through-vias (TSVs) so that they are electrically connected. The first die and the second die can also be wafer-bonded using flip-chip bonding technologies, etc. In this disclosure, a system controller 115 and a local controller 135 can both be referred to as memory controllers, or as a first memory controller and a second memory controller, for the sake of simplicity.It is understood that, while they may be different controllers, certain operations disclosed herein may be initiated or performed by one or both of the memory controllers unless otherwise specified.

[0022] The local controller 135 also communicates with a cache register 118 and a data register 121. In some embodiments, one or more cache registers 118 together can form at least part of a cache buffer. The cache register 118 latches or buffers data, either incoming or outgoing, as instructed by the local controller 135, to temporarily store data while the array of memory cells 104 is busy writing or reading other data. During a programming operation (e.g., a write operation), data can be transferred from the cache register 118 to the data register 121 for transmission to the array of memory cells 104; then, new data can be latched into the cache register 118 by the I / O control circuit 112.During a read operation, data can be transferred from the cache register 118 to the I / O control circuit 112 for output to the system controller 115; then, new data can be transferred from the data register 121 to the cache register 118. In some embodiments, the cache register 118 and / or the data register 121 can form at least part of a side buffer 152 of the storage device 130. The side buffer 152 can further include scanning devices such as a read amplifier to sense a data state of a memory cell of the arrangement of memory cells 104, e.g., by sensing a state of a data line connected to that memory cell. A status register 122 can communicate with the I / O control circuit 112 and the local memory controller 135 to latch the status information for output to the system controller 115.

[0023] Fig. Figure 1 also illustrates that dynamic latch devices 106 can be arranged above the array of memory cells 104, with the side buffer 152 normally located below the array 104. Dynamic latch devices 106 are connected to the subblocks of memory blocks in the array of memory cells 104. Dynamic latch devices 106 are also connected to a global bit line (shown in Figure 1). Fig. 5) As described in more detail below, during parallel programming operations where multiple subblocks are programmed in parallel, some of the dynamic latch devices 106 can be configured as additional storage devices for storing program data. In some examples, dynamic latch devices 106 are also connected to the side buffer 152. As a result, both latches in the side buffer 152 and dynamic latch devices 106 can be used in programming operations to program multiple subblocks in parallel. Dynamic latch devices 106 are controlled by the controller 135 (and / or controller 115) and are described in more detail below.

[0024] As in Fig. As shown in Figure 1, the storage device 130 receives various control signals from the system controller 115 via a control link 132 through the local controller 135. For example, the control signals can include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write-protect signal WP#. Additional or alternative control signals (not shown) can also be received via the control link 132, depending on the type of storage device 130. In one embodiment, the storage device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the system controller 115 via a multiplexed input / output (I / O) bus 134 and outputs data to the system controller 115 via the I / O bus 134.

[0025] For example, commands can be received via input / output (I / O) pins [7:0] of I / O bus 134 at I / O control circuit 112 and then written to instruction register 124. Addresses can be received via input / output (I / O) pins [7:0] of I / O bus 134 at I / O control circuit 112 and then written to address register 114. Data can be received via input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device at I / O control circuit 112 and then written to cache register 118. The data can then be written to data register 121 to program the arrangement of memory cells 104.

[0026] In one embodiment, the cache register 118 can be omitted, and the data can be written directly to the data register 121. Data can also be output via input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device. Although reference is made to I / O pins, they can include any conductive node that provides an electrical connection to the storage device 130 through an external device (e.g., the system controller 115), such as conductive pads or conductive bumps as are commonly used. While the above description uses a 16-bit I / O bus 134 as an example, it is understood that the bus 134 can be configured to any number of bits (e.g., 64 bits).

[0027] Experts can see that additional circuits and signals can be provided and that the storage device 130 of Fig. 1 has been simplified. It should be acknowledged that the functionality of the various block components, which are related to Fig. 1. This does not necessarily have to be divided into separate components or component parts of an integrated circuit device. For example, a single component or component part of an integrated circuit device could be adapted to provide the functionality of more than one block component of Fig. 1. Alternatively, one or more components or component parts of an integrated circuit device could be combined to extend the functionality of a single block component of Fig. 1. Additionally, while specific I / O pins are described according to common conventions for receiving and outputting the various signals, it is noted that other combinations or numbers of I / O pins (or other I / O node constructions) may be used in the various embodiments.

[0028] Fig. Figures 2A-2B are example schematics of parts of an array of memory cells 200A, such as a NAND flash memory array. The array of memory cells 200A can be an example of the memory array 104 of a memory device 130, as described with reference to Fig. 1 according to one embodiment. The memory arrangement 200A includes access lines, such as word lines 2020 to 202. N , and data lines, such as bit lines 2040 to 204 M The word lines 202 can be used with global access lines (e.g., global word lines) that are in Fig. 2A, which are not shown, are connected in a many-to-one relationship. For some embodiments, the memory arrangement 200A can be formed over a semiconductor, which may be doped, for example, to have a conductive type, such as p-type conductivity, e.g., to form a p-well, or n-type conductivity, e.g., to form an n-well.

[0029] The 200A memory array can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a string of serially connected memory cells (e.g., non-volatile memory cells), such as one of the NAND strands 2060 to 206. M . Each NAND strand 206 can be connected (e.g. selectively connected) to a common source (SRC) 216 and memory cells 2080 to 208 Ninclude. The memory cells 208 can represent non-volatile memory cells for storing data. The memory cells 208 of each NAND string 206 can be connected in series between a selection transistor 210 (e.g., a field-effect transistor), such as one of the selection gates 2100 to 210. M (e.g., source selection transistors, commonly referred to as source selection gate), and a selection transistor 212 (e.g., a field-effect transistor), such as one of the selection gates 2120 to 212 M (e.g., drain selection transistors, commonly referred to as drain selection gates). Selection gates 2100 to 210 M can be linked together with a selection line 214, such as a Source Selection Line (SGS), and selection gates 2120 to 212. MThey can be connected together with a select line 215, such as a drain select line (SGD). Although depicted as conventional field-effect transistors, the select transistors 210 and 212 can utilize a similar (e.g., the same) construction as the memory cells 208. The select transistors 210 and 212 can represent a number of select transistors connected in series, with each select gate in series configured to receive an identical or independent control signal.

[0030] A source of each select transistor 210 can be connected to the common source 216. The drain of each select transistor 210 can be connected to a memory cell 2080 of the corresponding NAND strand 206. For example, the drain of the select gate 2100 can be connected to memory cell 2080 of the corresponding NAND strand 2060. Therefore, each select transistor 210 can be configured to selectively connect a corresponding NAND strand 206 to the common source 216. A control gate of each select transistor 210 can be connected to the select line 214.

[0031] The drain of each selection transistor 212 can be connected to the bit line 204 for the corresponding NAND strand 206. For example, the drain of the selection gate 2120 can be connected to the bit line 2040 for the corresponding NAND strand 2060. The source of each selection transistor 212 can be connected to a memory cell 208. Nof the corresponding NAND strand 206. For example, the source of the selection gate 2120 can be connected to memory cell 208. N of the corresponding NAND strand 2060. Therefore, each selection transistor 212 can be configured to selectively connect a corresponding NAND strand 206 to the corresponding bit line 204. A control gate of each selection transistor 212 can be connected to the selection line 215.

[0032] The 200A storage arrangement in Fig. 2A can be a quasi-two-dimensional memory arrangement and generally have a planar construction, e.g., where the common source 216, the NAND strands 206, and the bit lines 204 extend in substantially parallel planes. Alternatively, the memory arrangement 200A can be in Fig. 2A may be a three-dimensional memory arrangement, e.g., wherein the NAND strands 206 may extend substantially perpendicular to a plane containing the common source 216 and to a plane containing the bit lines 204, which may be substantially parallel to the plane containing the common source 216.

[0033] The typical structure of memory cells 208 includes a data storage device 234 (e.g., a floating gate, a charge trap, and the like) that can determine a data state of the memory cell (e.g., by changing the threshold voltage), and a control gate 236, as shown in Fig. Figure 2A shows that the data storage structure 234 can include both conductive and dielectric structures, while the control gate 236 is generally formed from one or more conductive materials. In some cases, memory cells 208 can further have a defined source / drain (e.g., source) 230 and a defined source / drain (e.g., drain) 232. Memory cells 208 have their control gates 236 connected to (and in some cases form) a word line 202.

[0034] A column of memory cells 208 can be a NAND strand 206 or a number of NAND strands 206 selectively connected to a given bit line 204. A row of memory cells 208 can be memory cells 208 that are connected together to a given word line 202. A row of memory cells 208 may, but need not, include all memory cells 208 that are connected together to a given word line 202. Rows of memory cells 208 can often be subdivided into one or more groups of physical pages of memory cells 208, and physical pages of memory cells 208 often include every second memory cell 208 that is connected together to a given word line 202. For example, the memory cells 208 that are connected together to word line 202 Nconnected and selectively linked to even bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.), be a physical side of the memory cells 208 (e.g., even memory cells), while memory cells 208, which are connected to the word line 202 N connected and selectively connected to odd bit lines 204 (e.g. bit lines 2041, 2043, 2045 etc.), can be another physical side of the memory cells 208 (e.g. odd memory cells).

[0035] Although the bit lines 2043-2045 in Fig. Although bit lines 2A are not explicitly shown, it can be seen from the figure that the bit lines 204 of the arrangement of memory cells 200A run continuously from bit line 2040 to bit line 204. MThey may be numbered. Other groupings of memory cells 208 that are connected together to a given word line 202 may also define a physical page of memory cells 208. In certain storage devices, all memory cells that are connected together to a given word line may be considered a physical page of memory cells. The portion of a physical page of memory cells (which in some embodiments may still be the entire row) that is read during a single read operation or programmed during a single program operation (e.g., an upper or lower page of memory cells) may be considered a logical page of memory cells. A block of memory cells may include those memory cells that are configured to be erased together, such as all memory cells connected to word lines 2020-202. Nare connected (e.g., all NAND strands 206 that share common word lines 202). Unless expressly distinguished, a reference to a page of memory cells herein refers to the memory cells of a logical page of memory cells. A logical page may or may not be identical to a physical page. Although the example of Fig. 2A in conjunction with NAND flash is discussed, the embodiments and concepts described herein are not limited to any particular arrangement architecture or construction and may include other constructions (e.g. SONOS, phase switching, ferroelectric, etc.) and other architectures (e.g. AND arrangements, NOR arrangements, etc.).

[0036] Fig. 2B is another scheme of part of an arrangement of memory cells 200B, as it could be used in a storage device 130, e.g., as part of the arrangement of memory cells 104. Equally numbered elements in Fig. 2B correspond to the description as it relates to Fig. 2A is provided. Fig. 2B provides additional details on an example of a three-dimensional NAND memory array design. The three-dimensional NAND memory array 200B can include vertical structures that may enclose semiconductor columns, with a portion of a column serving as the channel region for the memory cells of NAND strands 206. Each NAND strand 206 can be selectively connected to a bit line 2040-204. MNAND strands 206 can be selectively connected to the same bit line 204 by a selection transistor 212 (e.g., these can be drain selection transistors, commonly referred to as select-gate-drain) and to a common source 216 by a selection transistor 210 (e.g., these can be source selection transistors, commonly referred to as select-gate-source). Multiple NAND strands 206 can be selectively connected to the same bit line 204. Subsets of NAND strands 206 can be connected to their respective bit lines 204 by selecting the select lines 2150-215. KThe selection transistors 210 are biased to selectively activate specific selection transistors 212 between a NAND strand 206 and a bit line 204. The selection transistors 210 can be activated by biasing the selection line 214. In some embodiments, each subblock or strand of memory cells has a separate selection line 214 from other subblocks or strands. In some embodiments, a pair of subblocks shares a selection line 214. Each word line 202 can be connected to multiple rows of memory cells of the memory arrangement 200B. Rows of memory cells that are connected to each other by a specific word line 202 can be collectively referred to as tiers.

[0037] The three-dimensional NAND 200B memory array can include multiple stacked layers of memory cells connected using vertical channels, such as semiconductor columns. The number of layers in the three-dimensional NAND 200B memory array can be, for example, 32, 48, 64, 96, 112, or any number of layers. In some examples, a group of layers may be collectively referred to as a deck. A deck in a three-dimensional NAND memory array can be processed together (e.g., etched together to form part of the semiconductor column). A memory device using three-dimensional NAND memory arrays can provide more memory cells on a single chip than a memory device made up of two-dimensional NAND arrays; and therefore, it can provide a higher storage capacity.Furthermore, in a storage device with three-dimensional NAND memory arrangements, transistors in memory cells are spatially separated, and therefore interference and electron leakage can be reduced.

[0038] In some examples, memory cells can be grouped into memory blocks. Fig. Figure 2C shows groupings of NAND strands 206 into blocks of memory cells 250, e.g., blocks of memory cells 2500-250. LBlocks of memory cells 250 can be groupings of memory cells 208 that can be erased together in a single erase operation. The group of memory cells that can be erased together is also called an erase block. Each block of memory cells 250 can represent those NAND strands 206 that are typically associated with a single select line 215, e.g., select line 2150. The common source 216 for the block of memory cells 2500 can be the same source 216 as the source 216 for the block of memory cells 250. L be. For example, each block of memory cells can be 2500-250 L They may be jointly and selectively connected to source 216. Access lines 202 and selection lines 214 and 215 of a block of memory cells 250 cannot be directly connected to access lines 202 or selection lines 214 and 215 of another block of memory cells within blocks of memory cells 2500-250. Lexhibit.

[0039] The bit lines 2040-204 M can be connected (e.g., selectively connected) to a buffer section 240, which can be part of the side buffer 152 of the storage device 130. The buffer section 240 can be connected to a storage level (e.g., the set of blocks of memory cells 2500-250). L ). The buffer section 240 can include sampling circuits (which may include read amplifiers) for sensing data values ​​that are displayed on the respective bit lines 204.

[0040] Fig. Figure 2D is a block diagram of part of an example arrangement of memory cells 260. The arrangement of memory cells 260 can be used as an arrangement 104 in a storage device 130. The arrangement of memory cells 260 is shown to have four storage levels 261 (e.g., storage levels 261a-261d). Each of the storage levels 261 can refer to a group of memory blocks of memory cells 250. Each storage level 261 can communicate with a respective buffer section 240, which together can form a side buffer 262. The side buffer 262 can be used to store the data in Figure 261. Fig. to implement the page buffer 152 shown. While four memory levels 261 are shown, other numbers of memory levels 261 can typically communicate with a page buffer 262. Each memory level 261 is shown to hold L+1 blocks of memory cells 250 (e.g., blocks of memory cells 2500-250). Lincludes.

[0041] In some cases, simultaneous operations can be performed on different levels. For example, simultaneous operations can be performed on memory cells within different blocks 250, as long as the different blocks 250 are located in different levels 261. In some cases, a single memory block 250 can be referred to as a physical block, and a virtual block can refer to a group of blocks 250 within which simultaneous operations can occur. For example, simultaneous operations can be performed on four blocks 2500, each located within levels 261a, 261b, 261c, and 261d, and the four blocks 2500 can be collectively referred to as a virtual block. In some cases, a virtual block can include blocks from different storage devices.In some cases, the physical blocks within a virtual block can have the same block address within their respective levels. In some cases, performing concurrent operations in different levels 261 may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different pages that have the same page address within their respective levels 261 (e.g., in connection with instruction decoding, page address decoding circuitry, or other circuitry shared across levels 261).

[0042] In some cases, a block can contain 250 memory cells, organized into rows (pages) and columns (e.g., strands, not shown). For example, memory cells in the same page can share a common word line (e.g., be coupled to it), and memory cells in the same strand can share a common digit line (which can alternatively be called a bit line) (e.g., be coupled to it).

[0043] In some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at the page level or a portion thereof), but can be erased at a second granularity level (e.g., at the block level). That is, a page can be the smallest unit of memory (e.g., a set of memory cells) that can be programmed or read independently (e.g., programmed or read simultaneously as part of a single program or read operation), and a memory block can be the smallest unit of memory (e.g., a set of memory cells) that can be erased independently (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data.For example, in some cases a page in use cannot be updated until the entire block containing the page has been deleted.

[0044] A general block diagram of an example device 300, which can be used to implement systems, devices and procedures described herein, is shown in Fig. Figure 3 illustrates this. It is understood that various systems, devices, and methods described herein may be implemented using analog and / or digital circuitry or using one or more computers with known computer processors, memory systems, storage devices, computer software, and other components. Typically, a computer includes a processor for executing instructions and one or more memory systems for storing instructions and data. A computer may also include or be coupled with one or more mass storage devices, such as one or more magnetic disks, internal hard disks and removable disks, magneto-optical disks, optical disks, etc.

[0045] Various systems, devices, and procedures described herein can be implemented using computers operating in a client-server relationship. Typically, in such a system, the client computers are located remotely from the server computers and interact over a network. The client-server relationship can be defined and controlled by computer programs running on the respective client and server computers. Examples of client computers include desktop computers, workstations, portable computers, mobile smartphones, tablets, or other types of computing devices.

[0046] Various systems, devices, and methods described herein can be implemented using a computer program product materially embodied in an information carrier, e.g., in a non-volatile, machine-readable storage device, for execution by a programmable processor; and the procedures and processes described herein, including one or more of the steps of at least some of the Fig. 1-9, can be implemented using one or more computer programs that can be executed by such a processor. A computer program is a set of computer program instructions that can be used directly or indirectly in a computer to perform a specific activity or achieve a specific result. A computer program can be written in any form of programming language, including compiled or interpreted languages, and it can be provided in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0047] As in Fig. As shown in Figure 3, the device 300 can be used to implement a host system that includes a storage system (e.g., the one in Figure 3). Fig. 1 storage system shown) includes, is coupled to, or uses this. The device 300 can be used to perform operations of a controller (e.g., to run an operating system, to perform operations that are the responsibility of the system controller 115 and / or the local controller 135). Fig. 1 corresponds).

[0048] In some embodiments, the device 300 comprises a processor 310, which is coupled in an operational state with a data storage device 320 and a main memory device 330. The processor 310 controls the overall operation of the device 300 by executing computer program instructions 324 that define such operations. The instructions 324 include instructions for implementing the functionality of a controller (e.g., system controller 115 and / or local controller 135). Fig. 1) The computer program instructions 324 can be stored in the data storage device 320 or another computer-readable medium and loaded into the main memory device 330 when execution of the computer program instructions is desired. For example, the processor 310 can be used to implement one or more of the components and systems described herein, such as the system control 115 and / or the local control 135 (shown in Fig. 1) Thus, the procedural steps of at least some of the Fig. 1-9 are defined by the computer program instructions 324, which are stored in the main memory device 330 and / or the data storage device 320 and are controlled by the processor 310, which executes the computer program instructions 324. For example, the computer program instructions 324 can be implemented as computer executable code programmed by a person skilled in the art to carry out an algorithm defined by the instructions herein in conjunction with at least some of the Fig. The process steps discussed in Figures 1-9 are defined. Accordingly, the processor 310 executes an algorithm, defined by the process steps of these aforementioned figures, by carrying out the computer program instructions in order to perform operations (e.g., reading, programming, erasing, etc.). The device 300 also includes one or more network interfaces 380 for communication with other devices over a network. The device 300 may also include one or more input / output devices 390 that enable user interaction with the device 300 (e.g., display, keyboard, mouse, speakers, buttons, etc.).

[0049] The processor 310 can include both general-purpose and specialized microprocessors and can be the sole processor or one of several processors in the device 300. The processor 310 can include one or more central processing units (CPUs) and one or more graphics processing units (GPUs), which can operate independently and / or in multitasking with one or more CPUs to accelerate processing, for example, for various image processing applications described herein. The processor 310, the data storage device 320, and / or the main memory device 330 can include, be augmented by, or be integrated with one or more application-specific integrated circuits (ASICs) and / or one or more field-programmable gate arrays (FPGAs).

[0050] The data storage device 320 and the main storage device 330 each comprise a physical, non-volatile, computer-readable storage medium. The data storage device 320 and the main storage device 330 can each include high-speed random-access memory, such as dynamic random-access memory (DRAM), static random-access memory (SRAM), double data rate synchronous dynamic random-access memory (DDR RAM), or other solid-state random-access memory devices, and can include non-volatile memory, such as one or more magnetic disk storage devices like internal hard disks and removable hard disks, magneto-optical disk storage devices, optical disk storage devices, flash storage devices (NAND flash memory devices, NOR flash memory devices), semiconductor storage devices, such as...Erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM), digital versatile disc read-only memory (DVD-ROM) discs, or other non-volatile solid-state storage devices. For example, the data storage device 320 can be used with the storage system described herein (e.g., the one described in ). Fig. (System shown in Figure 1). In some examples, the data storage device 320 and the main storage device 330 can be implemented as one or more storage devices 130 ( Fig. 1) include.

[0051] Input / output devices 390 can include peripheral devices such as a printer, scanner, display screen, etc. For example, input / output devices 390 can include a display device such as a cathode ray tube (CRT), plasma, or liquid crystal display (LCD) monitor for displaying information to a user, a keyboard, and a pointing device such as a mouse or trackball with which the user can input information into the device 300.

[0052] Any or all of the functions of the systems and devices discussed herein may be performed by the Processor 310 and / or integrated into a device or system such as the System 100. Furthermore, the System 100 and / or the Device 300 may utilize one or more neural networks or other deep learning techniques performed by the Processor 310 or other systems or devices discussed herein.

[0053] A person skilled in the art will recognize that an implementation of an actual computer or computer system may have different designs and may also contain different components, and that Fig. 3 is a higher-level representation of some of the components of such a computer for illustrative purposes.

[0054] Fig. 4A- Fig. Figure 4B shows a side view (e.g. a cross-section with respect to the XZ directions) of part of the three-dimensional construction of the storage device 130, including a construction of the memory cell string 231 (e.g. a NAND string) with a column 441, according to some embodiments described herein. Fig. Figure 4A shows the construction of a memory cell string (e.g., memory cell string 231) of the storage device 130. Other memory cell strings (e.g., NAND strings 2060–206) are shown. M in Fig. 2A and NAND strands 206 in Fig. 2B) However, they may have a similar or the same construction as the one in Fig. 4A shows memory cell string 231.

[0055] Starting at the top edge of Fig. 4A has the storage device 130 data lines 401 and 402 (e.g. corresponding to the bit lines 204 in Fig. 2A, Fig. 2B and Fig. 2C) which are coupled to conductive structures 431 and 432, respectively, and to conductive contacts 411 and 412. The data lines 401 and 402 are therefore electrically connected to the columns 441 and 442 via the conductive contacts 411 and 412, respectively. It is understood that the storage device 130 may include many other similar data lines, conductive structures, and conductive contacts, which are not shown for the sake of simplicity.

[0056] Fig. Figures 4A-4B show the directions X, Y, and Z, which can be relative to the physical directions (e.g., dimensions) of the storage device 130's construction. For example, the Z direction can be a direction perpendicular to (e.g., vertical direction relative to) a substrate (e.g., a semiconductor substrate) of the storage device 130. The Z direction is perpendicular to the X and Y directions (e.g., the Z direction is perpendicular to an XY plane of the storage device 130).

[0057] As in Fig. As shown in Figure 4A, data lines 401 and 402 can carry signals (e.g., bit line signals) BL1 and BL2, respectively. In the physical structure of the storage device 130, data lines 401 and 402 can be constructed as conductive lines and have respective lengths extending in the Y direction. The data lines (e.g., data lines 401 and 402) of the storage device 130 can be formed at different levels (e.g., layers) in the physical structure of the storage device 130. For example, data lines 401 can be formed at one level (e.g., a lower level 461) of the storage device 130, and data lines 402 can be formed at another level (e.g., an upper level 462) of the storage device 130. Although not shown in Figure 4A, the data lines 401 and 402 can be formed at different levels (e.g., layers) of the storage device 130. Fig. As shown in Figure 4A, multiple data lines can be located next to each other in any given layer. For example, layer 461 can have multiple data lines, and layer 462 can also have multiple data lines. Data lines in the same layer can be separated from each other by a gap (e.g., a gap) in the X direction. The gap between data lines in the same layer can be the same or different. As shown in Figure 4A, multiple data lines can be located next to each other in any given layer. Fig. As shown in Figure 4A, each of the data lines 401 and 402 can have a thickness in the Z direction and a width in the X direction. Each of the thicknesses (in the Z direction) and widths (in the X direction) is less than the length (in the Y direction). The thickness can be less than, equal to, or greater than the width.

[0058] In Fig. 4A Each of the conductive structures 431 and 432 can have a length extending in the Z-direction. In some examples, the length of conductive structure 431 can be less than the length of conductive structure 432 because level 461 is a lower level located closer to storage arrangement 201. Each of the conductive structures 431-432 can include (or be formed from) a conductive material extending in the Z-direction. Examples of the conductive material include metal, alloy, conductively doped polysilicon, or other conductive materials. Although not in Fig. As shown in Figure 4A, the storage device 130 can enclose a dielectric material (e.g., silicon dioxide) formed between the layers 462 and 461. The dielectric material can be formed in front of the conductive structures 431 and 432. Openings (e.g., holes (e.g., vertical vias)) can then be formed in the dielectric material. The material of each of the conductive structures 431-432 can be formed (e.g., deposited) within a respective opening of the openings.

[0059] As in Fig. As shown in Figure 4A, each of the conductive structures 431 and 432 can be coupled to (e.g., in electrical contact with) a respective conductive contact below the conductive contacts 411 and 412, and to (e.g., in electrical contact with) a respective data line below the data lines 401 and 402. For example, the conductive structure 431 can include one end (e.g., lower end) that is coupled to (e.g., directly contacting) the conductive contact 411, and another end (e.g., upper end) that is coupled to (e.g., directly contacting) the data line 401. In another example, the conductive structure 432 can include one end (e.g., lower end) that is coupled to (e.g., directly contacting) the conductive contact 412, and another end (e.g., upper end) that is coupled to (e.g., directly contacting) the data line 402.

[0060] As in Fig. As shown in Figure 4A, the memory cell string can include 231 columns (e.g., vertical columns) 441 and 442. Columns 441 and 442 can include column contacts 441C and 442C, respectively, located on the same level (e.g., level 459) of the memory device 130. Columns 441 and 442 can be located under (e.g., directly under) respective conductive contacts 411 and 412, which are located under (e.g., directly under) respective conductive structures 431 and 432. Conductive structures 431 and 432 can be coupled to (e.g., in electrical contact with) columns 441 and 442 via conductive contacts 411 and 412, respectively. As shown in Figure 4A, the columns 441 and 442 can be connected to (e.g., in electrical contact with) columns 441 and 442. Fig. As shown in Figure 4A, data lines 401 and 402 can thus be coupled to (e.g. electrically coupled to) the columns 441 and 442 respectively via respective conductive structures 431 and 432 and respective conductive contacts 411 and 412.

[0061] As described above, data lines 401 and 402 are located in layers 461 and 462, respectively. Layers 461 and 462 are located in a portion of the memory device 130 that is positioned above the memory array 201 in the Z-direction. The memory array 201 is positioned above a substrate 490 of the memory device 130 in the Z-direction. As described above, a memory array such as memory array 201 comprises multiple memory cell strands (one of which is shown as memory cell strand 231).

[0062] As in Fig. As shown in Figure 4A, the column (e.g., a vertical column) 441 can be part of the memory cell string 231 and have a length extending in the Z direction (e.g., extending vertically with respect to the substrate 490). The column 441 can extend through memory cells 2080, 2081, 2082, and 2083 of the memory cell string 231. The column 441 can enclose (e.g., be formed from) a conductive material (e.g., conductively doped polysilicon). Each of the memory cells 2080, 2081, 2082, and 2083 can enclose a transistor assembly (e.g., a memory cell transistor). Part of column 441 can form the channel area (e.g., for conducting current) of the transistor of each memory cell 2080, 2081, 2082, and 2083. It is understood that Fig. Although 4A only shows four memory cells 2080-2083, the memory cell string 231 can include any number of memory cells that share a common column (e.g., column 441).

[0063] As described above, the column contact 441C can be formed from conductively doped polysilicon, metal, or other conductive materials. The column 441 can enclose a section 444. The column contact 441C and the section 444 of the column 441 can enclose the same conductive material or different conductive materials. The conductive structure 431, the conductive contact 411, and the column 441 can be part of a circuit path (e.g., a conductive channel of the memory cell string 231) between the data line 401 and a conductive area 498 (associated with an SRC line). The conductive area 498 can be part of a common source line (e.g., common source line or source plate 216 in Fig. 2A). The conductive structure 431 and the column 441 can be made of the same material or different materials. In Fig. 4A During a storage operation (e.g., read or write operation) of the storage device 130, a circuit path (e.g., a current path) can be formed between the data line 401 and the conductive area 498 through the conductive structure 431, the conductive contact 411, and the column 441 (which includes the column contact 441C and the section 444 of the column 441).

[0064] The substrate 490 of the storage device 130 can include a semiconductor substrate (e.g., a silicon-based substrate). For example, the substrate 490 can include a p-type silicon substrate or an n-type silicon substrate. As shown in Fig. As shown in Figure 4A, the memory cells 2080, 2081, 2082, and 2083 of the memory cell string 231 can be arranged along (e.g., adjacent to) respective sections of the column 441 in different planes (in the Z direction) of the storage device 130. For example, the memory cells 2080, 2081, 2082, and 2083 can be arranged one above the other (e.g., vertically) in planes 470, 471, 472, and 473, respectively, of the storage device 130. Memory cells from other memory cell strings of the storage device 130 can also be located in the respective planes 470, 471, 472, and 473.

[0065] By stacking the memory cells in different layers, the storage device forms a 3D structure that has a higher capacity than a 2D device. In a typical 3D storage device (e.g., Device 130, which is in Fig. As shown in Figure 4A, for example, several layers (e.g., layers 470, 471, 472, and 473) are stacked together, with one or more storage columns (e.g., columns 441 and 442) arranged vertically in the center. The storage columns can serve as the channel area of ​​the storage device. The multiple layers (e.g., levels or tiers) of the storage device can form groups or decks. A deck of a 3D storage device can be processed together (e.g., patterned and / or etched together) when the associated storage column is formed. A layer of the storage device can have one or more access lines (e.g., word lines) or access line groups (e.g., word line groups). Each deck can have one or more access line segments (e.g., word line segments). An access line segment can have fewer or more access lines than those in a deck.For example, a deck can have two word line segments distributed across one or more levels. In some cases, certain memory operations (e.g., a delete operation) can be performed on a group of word lines (e.g., a deck) rather than on the entire memory block. By not performing an operation on the entire memory block, the specific operation can be performed more quickly.

[0066] Fig. Figure 4A further illustrates that access lines 450, 451, 452, and 453 of the storage device 130 can be arranged along (e.g., adjacent to) respective sections (in the Z-direction) of the column 441 in the same planes (e.g., planes 470, 471, 472, and 473, respectively) in which the memory cells 2080, 2081, 2082, and 2083 are located. Access lines can include, for example, word lines or control gates. The access lines 450, 451, 452, and 453 can include (e.g., be formed from) a conductive material (or materials). Example materials for the access lines 450, 451, 452, and 453 include metal, alloy, doped polysilicon, and other conductive materials.

[0067] In Fig. 4A can include a selector line (e.g., drain selector gate or SGD) 481 having a length extending in the X direction (e.g., perpendicular to the lengths (in the Y direction) of the data lines 401 and 402). The materials of the selector line 481 can include a conductive material (e.g., conductively doped polysilicon, metal, other conductive material). Fig. Figure 4A shows an example where another selection line (e.g., source selection gate or SGS) 480 may have a construction (e.g., shape, material, or both) that is similar to (or the same as) that of selection line 481. In some examples, selection line 480 may have a construction (e.g., shape, material, or both) that is similar to (or the same as) that of each of the access lines 450, 451, 452, and 453.

[0068] As in Fig. As shown in Figure 4A, a transistor (e.g., source selection transistor) 465 and a transistor (e.g., drain selection transistor) 463 can be arranged along (e.g., adjacent to) respective sections of column 441 in the Z-direction. Memory cells 2080, 2081, 2082, and 2083 of the memory cell string 231 can be arranged along the section of column 441 located between transistors 465 and 463.

[0069] Memory cell strand 231 can include materials 403, 404, and 405 formed between section 444 of column 441 and a respective access line under access lines 450, 451, 452, and 453. Material 403 can also be formed between column 441 and each of the selection lines 480 and 481. Materials 403, 404, and 405 located at a particular memory cell (under memory cells 2080, 2081, 2082, and 2083) can be a part (e.g., a memory element) of that particular memory cell. As in Fig. As shown in Figure 4A, the combination of materials 403, 404 and 405 of one memory cell (under memory cells 2080, 2081, 2082 and 2083) can be separated from (in the Z direction) the combination of materials 403, 404 and 405 of another memory cell (under memory cells 2080, 2081, 2082 and 2083).

[0070] Material 403 may include a charge-blocking material (or materials), such as a dielectric material (e.g., silicon nitride), capable of blocking charge tunneling. Material 404 may include a charge-storage material (or materials) capable of providing a charge-storage function to represent a value of information stored in memory cells 2080, 2081, 2082, and 2083. For example, Material 404 may include polysilicon (e.g., conductively doped polysilicon), which may be either p-type or n-type polysilicon. The polysilicon may be configured to act as a floating gate (e.g., for storing charge) in a memory cell (e.g., memory cells 2080, 2081, 2082, and 2083). In another example, material 404 can be a dielectric material (e.g.Material 405 may include a silicon nitride-based material or other dielectric materials that can trap charge in a memory cell (e.g., a memory cell 2080, 2081, 2082, and 2083). Material 405 may include a tunneling dielectric material (or materials), such as silicon dioxide, capable of allowing tunneling of a charge (e.g., electrons).

[0071] As in Fig. As shown in Figure 4A, the storage device 130 can include a circuit 495 located beneath (e.g., formed) the memory arrangement 201 (e.g., directly beneath the memory cell string 231). The circuit 495 can include circuit elements (e.g., transistors T) that are coupled to other circuit elements (e.g., to the data lines 401-402) of the storage device 130. The circuit elements (e.g., transistors T) of the circuit 495 can be configured to perform part of a function of a storage device (e.g., storage device 130). For example, the circuit 495 can include decoding circuits, driver circuits, buffers (e.g., side buffers), read amplifiers, charge pumps, and other circuits of the storage device 130. In an alternative design of the storage device 130, the circuit 495 can be located above (e.g. formed) the storage arrangement 201 (instead of below the storage arrangement 201).For example, in the alternative design of the storage device 130, the circuit 495 can be located above the storage arrangement 201 and below the data lines 401 and 402, or between the data lines 401 and 402 of the storage arrangement 201 in the Z direction. In another example, in the alternative design of the storage device 130, the circuit 495 can be located above the storage arrangement 201 and above the data lines 401 and 402 in the Z direction.

[0072] Another view of column 441 along a cross-sectional line 4B-4B is shown in Fig. 4B shown. Fig. Figure 4B shows a top view (e.g., a cross-section with respect to the XY plane) of section 444 of column 441 along line 4B-4B of Fig. 4A. As in Fig. As shown in Figure 4B, section 444 of column 441 can include material 444A and material 444B surrounded by material 444A. Material 444A can be (or include) part of a conductive structure (e.g., a conductive channel) of column 441. Material 444B can include a dielectric material. In an alternative design of column 441, material 444B can be omitted from column 441, so that the entire section 444 of column 441 can include material 444A (without material 444B).

[0073] Fig. Figure 5 is a block diagram illustrating parts of a storage device (e.g., storage device 130) with dynamic latch devices arranged over a three-dimensional non-volatile memory array according to some embodiments of the present disclosure. As shown, the storage device includes an array of memory cells (e.g., array 104 in Figure 5). Fig. 1) with multiple memory blocks 5500-550 L one (collectively referred to as 550). The multiple memory blocks 550 can be contained in multiple levels of the arrangement of memory cells. The in Fig. The storage device shown in Figure 5 also includes a side buffer 540, which may be the same as or similar to the side buffer 152 or 240 shown in Figure 5. Fig. Figure 1 or 2C is shown. In one embodiment, the side buffer 540 is physically located below the memory arrangement comprising the memory blocks 550. In another embodiment, the side buffer 540 includes a fixed number of latches or other data storage elements, such as the data register 121 and cache register 118 described above.

[0074] As in Fig. As shown in Figure 5, in one embodiment a plurality of dynamic latch devices 506A-506N are physically arranged above the memory array comprising memory blocks 550 (e.g., physically arranged on a side opposite the memory blocks 550 from the side buffer 540). As described above, the physical area below the memory blocks 550 is limited in space, and therefore it is difficult to place more latch devices than those in the side buffer 540. Dynamic latch devices 506 in Fig. 5 correspond to the dynamic latch devices 106 in Fig. 1.

[0075] In some examples, dynamic latch devices 506 include additional latches used to program multiple subblocks (e.g., one of subblock 0 to subblock M in each set of subblocks 505A-505N) of memory blocks 550 in parallel with a single programming pulse. The additional latches include memory devices used to store the data patterns to be programmed into multiple selected subblocks. The dynamic latch devices used to store program data are connected to unselected subblocks during certain programming operations. As in the example of Fig. As shown in section 5, a storage level of the storage device can contain multiple storage blocks (5500-550). LEach memory block 550 can contain multiple sets of subblocks. For example, memory block 5500 contains sets of subblocks 505A-505N (collectively referred to as 505). Within each set of subblocks 505, there are multiple subblocks containing strands of memory cells. For example, the set of subblocks 505A includes subblock 0 - subblock M (represented as subblocks 502A0-502A). M Similarly, the set of subblocks 505B closes its corresponding subblock 0 - subblock M (represented as subblocks 502B0-502B). M ) and so on. A set of subblocks can, for example, include 1, 2, 4, etc. subblocks. Each subblock in a set of subblocks includes, for example, a strand of memory cells (e.g., a NAND strand 206, as in Fig. 2A and Fig. (2B shown). Therefore, each subblock includes serially connected memory cells. Each subblock can also include selection transistors such as SGD 212 and SGS 210, which are shown in Fig. 2A and Fig. 2B are shown.

[0076] In the Fig. In the configuration shown in Figure 5, one or more sub-blocks in a set of sub-blocks are connected by the same dynamic latch device. As shown in Figure 5. Fig. As shown in section 5, the sub-blocks are 502A0-502A M in the set of sub-blocks 505A all connected to the dynamic latch device 506A; the sub-blocks 502B0-502B MIn the set of subblocks 505B, all are connected to the dynamic latch device 506B; and so on. When a dynamic latch device 506 is used to store program data, it is connected to unselected subblocks in a set of subblocks. The unselected subblocks are inhibited during programming operations (e.g., the memory locations in the unselected subblocks have already been programmed). Therefore, the dynamic latch devices that store program data are sometimes called inhibit latches. As described in more detail below, during parallel programming operations, several selected subblocks are programmed in parallel. In some embodiments, one subblock is programmed in each of several sets of subblocks, and thus several subblocks in different sets of subblocks can be programmed in parallel (e.g., simultaneously).During programming operations, dynamic latch devices that store program data (e.g., a data pattern) can transfer the stored data to the selected subblocks within the multiple sets of subblocks to program the selected subblocks in parallel. Storing program data in dynamic latch devices connected to unselected subblocks and the programming processes are described in more detail below.

[0077] In some embodiments, the dynamic latch device described in the present disclosure can not only be used as a storage device for storing program data, but can also be configured to perform read amplification during a read operation. Such a dynamic latch device can also be referred to as a sense latch. The read amplification capability of the dynamic latch device can improve the sampling capability of the 3D storage device because the column current decreases due to the long column distance. In particular, a string of memory cells in a subblock can have many memory cells fabricated in a 3D structure. The column of these memory cells (e.g., the channel region) becomes longer and longer as the number of memory cells increases. As a result, the column current decreases because the resistance of the column increases.During a read operation, the column current is typically sensed using read amplifiers in the side buffer. However, if the column current is small (e.g., in the picoampere range), sensing using the read amplifiers in the side buffer can become difficult and time-consuming. The dynamic latch device described herein can perform read amplification during a read operation, thus providing an amplified current for sensing by the read amplifier in the side buffer. Consequently, the sampling capability can be improved by using the dynamic latch device.

[0078] As described above, the 540 page buffer can include latches for storing program data (e.g., three latches for storing three bits of program data to program a TLC cell). In one example, the 540 page buffer is also connected to the 506 dynamic latch devices, so that they can be used together or in any desired way to enable efficient parallel programming operations on multiple subblocks. It is understood that Fig. 5 is simplified and therefore does not represent any other additional latches, e.g., those that store temporary information that can be used to speed up the programming operation and reduce programming time (e.g., the status information of a memory cell(s) on an adjacent word line, SSPC (selective slow programming convergence) data for another subblock(s)), etc.

[0079] With continued reference to Fig. In one embodiment, the multiple dynamic latch devices 506A-506N are all connected to a global bit line 504. The global bit line 504 is connected to the side buffer 540, so that the bit line current can be sensed by the read amplifiers in the side buffer 540. In contrast to existing designs, the one in Fig. The circuit configuration shown in Figure 5 does not include local bit lines connecting multiple dynamic latch devices and subblocks. For example, in an existing design, each dynamic latch can be connected via a local bit line to all subblocks of the multiple sets of subblocks within a memory block. Consequently, when a particular subblock is selected to perform an operation, all dynamic latches connected to the memory block are activated. Therefore, it would be difficult to effectively use any latches connected to the unselected subblocks to store program data, as there are no inhibit latches for the memory block.

[0080] As in Fig. 5 shown, indicates that in Fig. The circuit configuration shown in Figure 5, unlike existing designs, does not have a local bit line connecting all subblocks in a memory block. Each dynamic latch device 506 is connected only to its specific set of subblocks 505 and no other sets of subblocks in the same memory block 550. For example, dynamic latch device 506A is connected only to the set of subblocks 505A and no other sets of subblocks. Dynamic latch device 506B is connected only to the set of subblocks 505B and no other sets of subblocks. Other dynamic latch devices 506 are connected in a similar manner. Thus, while the multitude of dynamic latch devices 506 is connected between the global bit line 504 and the multitude of sets of subblocks 505, each specific dynamic latch device (e.g., device 506A, 506B, etc.) is connected to its own set of subblocks 505.The multitude of dynamic latch devices 506 are connected only to a corresponding set of subblocks (e.g., set 505A, 505B, etc.) within the multitude of sets of subblocks 505, and not to any other sets of subblocks. In other words, different dynamic latch devices 506 are connected to different sets of subblocks 505. In this way, as described in more detail below, each dynamic latch device is activated only when a subblock within a corresponding set of subblocks is selected to perform operations (e.g., read / program / program verification). Other dynamic latch devices are not activated if the corresponding sets of subblocks are not selected. Some of these dynamic latch devices can therefore be used to store program data.This circuit configuration enables parallel programming operations that can program multiple sub-blocks simultaneously, thereby improving overall operational efficiency.

[0081] In one embodiment, as in Fig. Figure 5 shows a dynamic latch device 506 connected to several subblocks (e.g., 2, 4, 6, etc.) in a set of subblocks. As described herein, some of these dynamic latch devices can hold data to be programmed in parallel into several subblocks using a single programming pulse. For example, using a single programming pulse, dynamic latch devices 506A and 506B can be activated to program subblock 502A0 in set 505A and subblock 502B0 in set 505B, while other dynamic latch devices (e.g., 506N) are deactivated and used to store and provide program data for programming subblocks 502A0 and 502B0. In particular, a controller (e.g.,The controller (135) may be configured to receive program data during a programming operation from the dynamic latch device (506N), which stores the program data instead of or in addition to the page buffer (540). The controller can perform the programming operation on one or more subblocks (502, e.g., 502A0 and 502B0) that are not connected to the dynamic latch device (506). Nare connected. The one or more subblocks are selected subblocks from the plurality of sets of subblocks for performing the programming operation. The selected memory cells in the selected subblocks 502 (e.g., 502A0 and 502B0) are thus programmed with a single programming pulse using the data stored in the dynamic latch device 506N. Typically, to program multilevel memory cells (e.g., TLC, QLC), several programming pulses are applied in a sequence with increasing voltage levels. Using the dynamic latch devices 506 disclosed herein, for each programming pulse in the sequence, a selected memory cell in each of the selected subblocks 502 (e.g., 502A0 and 502B0) can be programmed in parallel. In some examples, multiple programming pulses are required if a program has not yet been completed.On the other hand, subsequent programming pulses may not be necessary if the first programming pulse is sufficient to complete the programming of the memory cells.

[0082] An example circuit for dynamic latch devices is shown in Fig. 6 shown. Fig. Figure 6 shows two dynamic latch devices 606A and 606B, which can be used to connect the dynamic latch device 506 in Fig. 5 or the device 106 in Fig. 1 to implement. The dynamic latch device 606A is described in detail below, with the assumption that similar descriptions can be used for the dynamic latch device 606B, since it has the same configuration as the device 606A. As in Fig. As shown in Figure 6, the dynamic latch device 606A comprises a write transistor group (designated WSG_0), a read transistor group (designated RSG_0), and a storage device 612A (designated STFT_0). The storage device 612A can be a transistor, a capacitor, or any other circuit element capable of storing electrical charges.

[0083] In one embodiment, the write transistor group (designated WSG_0) comprises a plurality of write transistors 608A1, 608A2, 610A1, and 610A2. The read transistor group (designated RSG_0) includes a plurality of read transistors 608A3 and 610A3. As shown in Fig. As shown in Figure 6, in one example, write transistors 608A1 and 610A1 are connected in series; and write transistors 608A2 and 610A2 are also connected in series. Both write transistors 608A1 and 608A2 are connected to the global bit line 604 (e.g., at their drain or source electrodes). Write transistor 610A1 is directly connected to the set of subblocks 605A (e.g., via its source or drain electrode), and the connection node is called the sample memory node (designated SN_0). Read transistors 608A3 and 610A3 are connected in series (e.g., at their drain or source electrodes). Read transistor 608A3 is connected to the source line 618 (e.g., at its drain or source electrode). The storage device 612A is connected between the write transistor group and the read transistor group, and in particular between the write transistor 610A2 and the read transistor 610A3.For example, the drain electrode of device 612A can be connected to the write transistor 610A2, and the source electrode can be connected to the read transistor 610A3, or vice versa. The gate electrodes of transistors 608A1, 608A2, and 608A3 are controlled by the control signal RE_0; and the gate electrodes of transistors 610A1, 610A2, and 610A3 are controlled by the control signal WE_0. In some examples, RE_0 and WE_0 each include several bits of control signals for individual or joint control of the transistors.

[0084] As in Fig. As shown in Figure 6, the set of subblocks 605A includes two subblocks 602A0 and 602A1, and only a portion of the subblocks are shown. Each of the subblocks 602A0 and 602A1 includes a strand of memory cells (e.g., a strand 206, as shown in Figure 6). Fig. 2A and Fig. (2B shown). Each strand of memory cells in a subblock 602 is connected to a select gate drain (e.g., SGDO or SGD1) transistor. While Fig. 6 only shows that the set of subblocks 605A includes two subblocks; it can include more subblocks.

[0085] Continue with Fig. In Figure 6, the write transistor 610A1 (e.g., at its source electrode), the storage device 612A (e.g., at its gate electrode), and the SGDO and SGD1 transistors (e.g., at their drain electrodes) of subblocks 602A0 and 602A1, respectively, are all connected to the sample memory node SN_0. In this example, the storage device 612A can be a transistor whose source and drain electrodes are connected to the write transistor 610A2 and the read transistor 610A3, respectively (or vice versa). Program data can be stored on this sample memory node SN_0. For example, during a programming operation, the results of a programming verification phase can be sent to a side buffer (e.g., side buffer 640, which can be the same as side buffer 540). Once the cell has been verified as programmed, no further programming is required.For example, if the selected memory cells in subblocks of the set of subblocks 605A have been verified to have the desired logical states, no further programming is required for the selected memory cells. The controller therefore switches off the selection gate drain transistors SGDO and SGD1 in the set of subblocks 605A. As a result, subblocks 602A0 and 602A1 in the set of subblocks 605A become unselected subblocks that are not to be programmed further. The dynamic latch device 606A, which is connected to the unselected subblocks 602A0 and 602A1, can thus be used as a latch for storing program data for programming other selected subblocks (not in ). Fig. 6 shown) can be used. Fig. 6. Both sets of subblocks 605A and 605B can contain memory cells that have been programmed and thus contain unselected subblocks. Therefore, the corresponding dynamic latch devices 606A and 606B can also be called inhibit latches, which can be used to store inhibit data (e.g., program data for programming other subblocks) at the respective sample memory nodes SN_0 and SN_1.

[0086] With continued reference to Fig. 6. The controller can control the side buffer 640 (or another dynamic latch device) and the dynamic latch device 606A to transfer data to the sample memory node SN_0 for storing program data (or inhibit data). For example, the write transistors 608A1 and 610A1 can be enabled by the controller to turn on (e.g., by controlling the gate control signals RE_0 and WE_0) so that the side buffer 640 (or another dynamic latch device) can send data to the sample memory node SN_0 via the global bit line 604. The gate capacitance of the storage device 612A can be configured or sized to hold the electrical charges. Similarly, the side buffer 640 can modify the data stored at the sample memory node SN_0. After the data has been saved or modified, transistors 608A1 and 610A1 can be deactivated (e.g.The selection gates SGDO and SGD1 in the set of subblocks 605A are also deactivated (e.g., switched off) by the controller. Storing and modifying data at the sample storage node SN_1 can be done in a similar way.

[0087] With continued reference to Fig. Figure 6 uses the right side of this figure to illustrate how the stored data can be obtained and used to select subblocks (not in Fig. (shown in Figure 6) to program. Referring to the dynamic latch device 606B, the program data is stored at the sample memory node SN_1 using the storage device 612B (designated STFT_1). The controller can cause the data stored at the sample memory node SN_1 to be retained during a programming operation and transferred to one or more selected subblocks or to the side buffer 640. For example, during a programming operation, the controller can activate transistors 608B2 and 610B2 ​​to turn on (by controlling the gate control signals RE_1 and WE_1), so that the data stored at the sample memory node SN_1 is transferred via the global bit line 604 to the side buffer 640 or another dynamic latch device (the data path is shown on the right side of Figure 6). Fig. 6 shown) will be sent.

[0088] Fig. Figure 6 illustrates, as described above, an exemplary configuration of a dynamic latch device and the use of the dynamic latch device to store data when the corresponding subblocks are not selected subblocks (e.g., memory cells in the unselected subblocks are already programmed). Fig. Figure 7A illustrates further dynamic latch devices 706A and 706B, which are connected to sets of sub-blocks 705A and 705B, respectively. The circuit configuration of the dynamic latch devices 706A and 706B may be the same or similar to that of the dynamic latch devices 606A and 606B and is therefore not described again. Fig. 7A is used to illustrate the use of dynamic latch devices for performing programming operations separately (e.g., one subblock at a time) or in parallel (e.g., multiple subblocks at the same time).

[0089] With reference to Fig. 7A and that in Fig. The flowchart shown in Figure 7B causes the control in process 730, which performs a programming operation for a memory cell in a selected subblock (block 732), to raise all word lines connected to all sets of subblocks (e.g., all sets of subblocks 705) to a first word line voltage (e.g., 10 V) based on a single programming pulse. As described above, the word lines are connected to the gate electrodes of the memory cells in the subblocks (selected and not selected for programming). Due to the capacitive coupling between the gate electrodes of the memory cells and the columns of the memory cells in the subblocks, the columns are charged and potential-free (if no discharge path is present).

[0090] The concept of the potential-free column is implemented using Fig. 4 and Fig. Figure 9 is illustrated in more detail. As described below, the concept of the potential-free column can also enable the parallel programming of multiple sub-blocks in a more efficient manner. Parallel programming is described below using... Fig. 7A and Fig. 7C is described in more detail. Fig. For example, 9 shows a single programming pulse 902 in a sequence of programming pulses. Fig. Figure 9 shows two programming pulses. The programming operation has a programming phase in which the word line voltage is increased to, for example, 10 V. Fig. Figure 4A illustrates that capacitive coupling exists between memory cells 208 and column 441 (e.g., gate-channel coupling). Since the gate electrode of memory cells 208 receives the voltage applied to the word lines, the capacitive coupling effect therefore charges column 441. As a result, the controller does not need to directly apply a voltage to column 441 (e.g., via the bit lines). This is referred to in this disclosure as the floating column effect. The column is floating because the select gates (e.g., select line 481 and SGDO or SGD1 in) Fig. 7A) are switched off, thus isolating the column from other circuits.

[0091] Referring back to Figures 7A, 7B, and 9, the controller in block 734 causes the global bit line 704 to rise to a global bit line voltage (e.g., 3 V). In this example, we assume that a memory cell in subblock 702A0 is selected for programming. It is understood that other memory cells in other subblocks can be programmed in a similar manner. The controller also activates (block 736) one or more write transistors in the dynamic latch device 706A and activates one of a subblock's select gates. For example, if subblock 702A0 is to be programmed, the controller (e.g., using the control signals RE_0 and / or WE_0) activates the write transistors 708A1 and 710A1 (e.g., switches these write transistors on) to receive the program data from the side buffer 740 or from another dynamic latch device that stores the program data.The controller also activates the SGDO selection gate of subblock 702A0. To activate (e.g., switch on) the write transistors 708A1 and 710A1 and the SGDO selection gate, the controller can apply a control voltage (e.g., 3 V) to the gate electrodes of these write transistors and the selection gate.

[0092] Next, the controller modulates the voltage level of the global bit line 704 (block 736) by, for example, the side buffer 740, depending on the program data. If the program data is, for example, a logical "0", the controller can cause the global bit line 704 to discharge to 0 V. Conversely, the column of the selected subblock, which was pre-charged due to the capacitive coupling effect described above, discharges to 0 V because the column is electrically connected to the global bit line 704. If the program data is, for example, a logical "1", the controller can cause the global bit line 704 to remain at the global bit line voltage (e.g., 3 V).

[0093] In the next block, 737, the controller can cause the word lines connected to the memory cells in a selected subblock to rise to a second word line voltage (e.g., 20 V), so that this is a forward voltage to turn on all memory cells not selected for programming. In block 738, the controller causes the selected memory cell in the selected subblock to be programmed according to the program data. In block 739, the controller can cause a programming verification operation to be performed to verify the state of the selected memory cell. If it is verified that the selected memory cell has a desired logical state, the programming operation is complete, and process 730 can stop. If not, process 730 can be repeated, e.g., from block 732.

[0094] With reference to Fig. 7A and Fig. Section 7C describes a process 750 for performing parallel programming operations using the dynamic latch devices described herein. In block 752, the controller causes all word lines connected to all sets of subblocks (e.g., all sets of subblocks 705) to rise to an initial word line voltage (e.g., 10 V) based on a single programming pulse. As described above, the word lines are connected to the gate electrodes of the memory cells in the subblocks (selected and not selected for programming). Due to the capacitive coupling between the gate electrodes of the memory cells and the columns of the memory cells in the subblocks, the columns are charged and potential-free (if no discharge path is present).

[0095] In block 754, the controller causes the global bit line 704 to rise to a global bit line voltage (e.g., 3 V). In this example, we assume that a memory cell in subblock 702A0 of set 705A and a memory cell in subblock 702B0 of set 705B are to be programmed in parallel. That is, for each set of subblocks 705 connected to a respective dynamic latch device 706, a subblock is selected for programming a memory cell within it. Thus, in this example, selected memory cells from two selected subblocks 702A0 and 702B0 in two different sets 705A and 705B are programmed in parallel using a single programming pulse. It is understood that other memory cells in other subblocks can be programmed in parallel in a similar manner.

[0096] In process 750, blocks 755 and 756 are executed repeatedly for each of the selected subblocks. For example, the controller can first (block 755) activate one or more write transistors in the dynamic latch device 706A and then activate one of a selection gate (e.g., SGDO) of a subblock (e.g., subblock 702A0). Thus, if, for example, subblock 702A0 is to be programmed, the controller (e.g., using the control signals RE_0 and / or WE_0) activates the write transistors 708A1 and 710A1 (e.g., turns these write transistors on) to receive the program data from the side buffer 740 or from another dynamic latch device that stores the program data. The controller also activates the selection gate SGDO of subblock 702A0. To activate (e.g., switch on) the write transistors 708A1 and 710A1 and the selection gate SGDO, the control system can cause a control voltage (e.g.,3 V) is applied to the gate electrodes of these write transistors and the selection gate.

[0097] Next, the controller modulates the voltage level of global bit line 704 (block 756) by, for example, the side buffer 740, depending on the program data. If the program data is a logical "0", the controller can cause global bit line 704 to switch to 0 V. Conversely, the column of the selected subblock, which was precharged due to the capacitive coupling effect described above, discharges to 0 V. If the program data is a logical "1", the controller can cause global bit line 704 to remain at the global bit line voltage (e.g., 3 V).

[0098] Blocks 755 and 756 are then repeated for the next selected subblock (e.g., subblock 702B0). In this case, the controller uses a different dynamic latch device 706B. The controller (block 755) activates one or more write transistors in the dynamic latch device 706B and activates one from a selection gate (e.g., SGD2) of a subblock. Thus, for example, if subblock 702B0 is to be programmed, the controller (e.g., using the control signals RE_1 and / or WE_1) activates the write transistors 708B1 and 710B1 (e.g., turns these write transistors on) to receive the program data from the side buffer 740 or from another dynamic latch device that stores the program data. The program data for programming subblock 702B0 can be the same or different from the program data for programming subblock 702A0.The controller also activates the selection gate SGD2 of subblock 702B0. To activate (e.g., switch on) the write transistors 708B1 and 710B1 and the selection gate SGD2, the controller can apply a control voltage (e.g., 3 V) to the gate electrodes of these write transistors and the selection gate.

[0099] Next, the controller modulates the voltage level of global bit line 704 (block 756) by, for example, side buffer 740, depending on the program data for programming subblock 702B0. For example, if the program data is a logical "0", the controller can cause global bit line 704 to switch to 0 V. Conversely, the column of the selected subblock, which was precharged due to the capacitive coupling effect described above, discharges to 0 V. If the program data is a logical "1", for example, the controller can cause global bit line 704 to remain at the global bit line voltage (e.g., 3 V).

[0100] The two blocks 755 and 756 in process 750 above can be repeated any number of times, depending on the number of subblocks selected for programming. Since each selected subblock is located in a different set of subblocks 705, the program data for different selected subblocks can be delivered to different subblocks 705 without interfering with each other. This is made possible by the circuit configuration in which different dynamic latch devices 706 are connected to different sets of subblocks 705 and no other set of subblocks, as shown in Fig. 7A is shown.

[0101] In the next block 757 of the in Fig. In process 750 shown in Figure 7C, the controller can cause the word lines connected to the memory cells in the several selected subblocks to rise to a second word line voltage (e.g., 20 V), so that this is a forward voltage to turn on all memory cells that are not selected for programming. In block 758, the controller causes the selected memory cells in the several selected subblocks to be programmed in parallel (e.g., simultaneously) according to their respective program data. Therefore, using the circuit configuration shown in Figure 7C, the controller can... Fig. The dynamic latch devices shown in Figure 7A allow programming operations to be performed on multiple subblocks in parallel, thus improving operational efficiency. In this example, the multiple subblocks come from different sets of subblocks and cannot be in the same set of subblocks (unless more than one dynamic latch device is used for each set of subblocks). Furthermore, the programming operations are performed using a single programming pulse. In other words, the controller applies only one programming pulse to the word lines to program all selected subblocks in parallel. Ramping up the word line voltages can take a considerable amount of time. Consequently, by programming multiple subblocks in parallel, the latency when programming multiple memory cells in selected subblocks can be greatly reduced.In block 759, the controller can initiate a programming verification operation to verify the state of several memory cells. If the verification is successful, the programming is complete, and process 750 can stop. If not, process 750 can be repeated, for example, starting from block 752.

[0102] The above description of the parallel programming operation uses two subblocks (e.g., subblocks 702A0 and 702B0) as an example. In other embodiments, more subblocks can be programmed in parallel using Process 750 and the circuit configuration described herein. For example, if a memory level has two memory blocks, and each block has four sets of subblocks, the controller can be configured to program at least four subblocks in one memory block and at least four other subblocks in another memory block in parallel, using the plurality of dynamic latch devices associated with the different sets of subblocks.It is understood that the number of subblocks that can be programmed in parallel can vary depending on the number of dynamic latches, the number of sets of subblocks in a memory block, and the number of memory blocks in a memory level. For example, in one instance, each of the plurality of dynamic latches can be associated with between one and four subblocks. The plurality of dynamic latches comprises at least 5–80 dynamic latches (e.g., 20) per global bit line per level. Parallel programming capabilities can thus be scaled by increasing the number of dynamic latches.

[0103] In a parallel programming operation, the controller can be configured to perform operations to cause at least two selected subblocks to be programmed in parallel, using program data obtained from the page buffer and / or other dynamic latch devices that store program data. In some examples, the program data can come from a combination of page buffers and dynamic latch devices connected to unselected subblocks (e.g., inhibited latches).

[0104] Fig. Figures 8A-8C illustrate the use of the dynamic latch device configuration described herein to perform a read operation or a programming verification operation. The Fig. The circuit configuration shown in Figure 8A is the same as, or similar to, those shown in Figure 8A. Fig. 6 and Fig. Figure 7A shows this process, and therefore it will not be described again. When performing read or program verification operations, the sample memory node (e.g., SN_0 or SN_1) in a dynamic latch device connected to a subblock selected for reading is not used to store data. During read operations, the dynamic latch device (e.g., 806A or 806B) may be configured to perform read amplification to improve the page buffer's sampling capability.

[0105] With reference to Fig. 8A and Fig. In block 832, control 8B causes the global bit line to rise to a global bit line voltage (e.g., 3 V). In block 833, the control activates one or more write transistors (e.g., 808A1 and 810A1) and activates a select gate (e.g., SGDO) of a selected subblock (e.g., subblock 802A0) from which a memory cell is read. As a result, the column (or channel) of memory cells in the selected subblock is also raised to the global bit line voltage (e.g., 3 V) because the column is electrically connected to the global bit line 804.

[0106] In block 834, the controller causes word lines connected to a selected memory cell in a selected subblock (e.g., subblock 802A0) to rise to a first word line voltage (e.g., 2 V). In block 835, the controller causes word lines connected to unselected memory cells in the selected subblock (e.g., subblock 802A0) to rise to a second word line voltage (e.g., 6 V). The second word line voltage can be higher than the first word line voltage, thus energizing the unselected memory cells to enable the read operation of the selected memory cell.

[0107] In block 836, the control causes one or more write transistors (e.g., 808A1 and 810A1) in the dynamic latch device (e.g., device 806A) to be disabled, thereby isolating the global bit line from the set of subblocks (e.g., set 805A) connected to the dynamic latch device. In some examples, the control also activates another select gate (e.g., the one in Fig. 2A shown SGS, not in Fig. 8B) of the selected subblock. The other selected gate can be the selection gate source (SGS), located at the opposite end of the strand of memory cells from the selected gate drain (SGD, both shown in Figure 8B). Fig. (shown in Figure 2A). When the selection gate source is activated, the string of memory cells in the selected subblock is connected to the source line SRC (e.g., source line 818). Therefore, if the threshold voltage of the memory cell to be read in the selected subblock is greater than the applied word line voltage (e.g., if Vt > 2 V), the sample memory node of the dynamic latch device (e.g., the SN_0 node) remains unchanged. Otherwise, the sample memory node is discharged via the source line.

[0108] Next, the controller (block 837) can activate one or more read transistors. Continuing with the example above, the controller can use the control signals RE_0 and WE_0 to activate (i.e., turn on) transistors 808A3 and 810A3. The controller can also activate transistors 808A2 and 810A2. If the sample memory node remains constant (i.e., the threshold voltage of the memory cell to be read is greater than the applied word line voltage), the memory device 812A is activated because the gate-source voltage of device 812A is greater than its threshold voltage. Since the combination of read transistors 808A3 and 810A3 is connected to the source line 818, the global bit line 804 is pulled down. When the sample memory node SN_0 is discharged (i.e.,If the threshold voltage of the memory cell to be read in the selected subblock is not greater than the applied word line voltage, the memory device 812A is not activated (e.g., it remains switched off). Conversely, the global bit line 804 is not pulled down and remains unchanged. In this way, the data stored in the memory cell in the selected subblock (e.g., subblock 802A0) can be read (block 838) or transferred to the side buffer 840.

[0109] During a read operation, the memory device in a dynamic latching circuit thus acts as a switch, and the read transistors (and / or other transistors) can be scaled to provide read amplification during a read operation. As described above, modern 3D memory devices increasingly feature a growing number of memory cells in a string of cells within a subblock. The memory cells in the same string share the same column (or channel area). Therefore, the column current becomes smaller and smaller as the number of memory cells increases. The column current can be, for example, in the picoampere range. This small column current makes it difficult and slows down the paging through the side buffer during a read operation. Specifically, the column of the string of memory cells in a subblock is connected to the global bit line, which in turn is connected to the side buffer.Thus, the read amplifier in the side buffer conventionally senses the column current directly. Since the column current is so small, sensing it can be challenging and time-consuming.

[0110] In the present disclosure, the global bit line is no longer directly connected to the column of the strand of memory cells in a subblock. A dynamic latch device is arranged between the global bit line and the strands of memory cells in a subblock, as shown in Fig. Figure 8A shows the following. As described above, during the read operation, the memory device 812A acts as a switch controlled by the sample memory node SN_0, which remains at the same voltage or discharges depending on the threshold voltage of the memory cell being read. Therefore, the memory device 812A is enabled or disabled depending on the state of the memory cell being read (via the column current). The read transistors (and other transistors) in the dynamic latch device (e.g., 808A2, 808A3, 810A2, and / or 810A3 of device 806A) can be scaled (e.g., have a larger device area) to supply a sufficiently large current to the read amplifier in the side buffer (e.g., side buffer 840) so that the read amplification can be performed more effectively with higher accuracy and lower latency. In other words, the read amplifier in side buffer 840 no longer directly senses the column current.The column current in each subblock is used only to switch transistor 812A. As such, the dynamic latching device disclosed herein also improves the read operation performance.

[0111] The dynamic latch devices disclosed herein can further enable parallel read operations in which multiple memory cells are read in parallel. Fig. Section 8C illustrates a flowchart of an example process 850 for performing parallel read operations to read multiple memory cells. For illustrative purposes, the description below uses two memory cells in two selected subblocks, 802A0 and 802B0, as an example. It is understood that more memory cells in different selected subblocks can be read in a similar manner. With reference to Fig. 8A and Fig. In block 852, control 8C causes the global bit line to rise to a global bit line voltage (e.g., 3 V). In block 853, the control activates one or more write transistors in each of the plurality of dynamic latch devices and activates a select gate of a subblock in each set of subblocks of the plurality of sets of subblocks. For example, the control in Fig. 8A controls the signals RE_0, WE_0, RE_1, and / or WE_1 to activate transistors 808A1 and 810A1 in device 806A and transistors 808B1 and 810B1 in device 806B. Thus, two dynamic latch devices, 806A and 806B, operate in parallel to connect the global bit line 804 to their respective selected subblocks for reading. Consequently, the columns (or channels) of the memory cells in the two selected subblocks (e.g., subblocks 802A0 and 802B0) are also raised to the global bit line voltage (e.g., 3 V).

[0112] In block 854, the controller causes word lines connected to a selected memory cell in each of the selected subblocks (e.g., subblocks 802A0 and 802A1) to rise to a first word line voltage (e.g., 2 V). In block 855, the controller causes word lines connected to the unselected memory cells in the same selected subblocks (e.g., subblocks 802A0 and 802A1) to rise to a second word line voltage (e.g., 6 V). The second word line voltage can be higher than the first word line voltage, thus energizing the unselected memory cells.

[0113] In block 856, the control circuitry causes one or more write transistors in each of the multiple dynamic latch devices to be disabled, thereby isolating the global bit line from the multiple sets of subblocks connected to the dynamic latch devices. Referring to Fig. For example, 8A controls the control signals RE_0, WE_0, RE_1, and / or WE_1 to disable the write transistors 808A1, 810A1, 808B1, and 810B1, thereby isolating the global bit line 804 from the sets of subblocks 805A and 805B. In some examples, the control also activates another select gate (e.g., the one in Fig. 2A shown SGS, not in Fig. (shown in 8A) of the selected subblocks. The other selected gate can be the selection gate source (SGS), located at the opposite end of the string of memory cells from the selected gate drain (SGD, in Fig. 2A). After the selection gate source is activated, the string of memory cells in each of the selected subblocks (e.g., 802A0 and 802B0) is connected to the source line SRC (e.g., source line 818). Therefore, if the threshold voltage of a read memory cell in a selected subblock is greater than the applied word line voltage (e.g., if Vt > 2 V), the sample memory node of the respective dynamic latch device remains unchanged. Otherwise, the sample memory node is discharged via the source line. Referring to Fig. For example, for a selected memory cell in subblock 802A0, the sample memory node SN_0 remains at the same voltage if the threshold voltage Vt of the selected memory cell is greater than the word line voltage; otherwise, it discharges to ground (e.g., 0 V). Similarly, for a selected memory cell in subblock 802B0, the sample memory node SN_1 remains at the same voltage if the threshold voltage Vt of the selected memory cell is greater than the word line voltage; otherwise, it discharges to ground (e.g., 0 V). Therefore, the voltages of sample memory nodes SN_0 and SN_1 in different dynamic latch devices 806A and 806B represent the logical states of the selected memory cells in different subblocks of different sets of subblocks 805A and 805B, respectively.In this way, the data stored in multiple memory cells in different subblocks of different sets are transferred in parallel to the sampling memory nodes in different dynamic latch devices.

[0114] Next, the controller (block 857) can serially activate one or more read transistors in each of the plurality of dynamic latch devices. Continuing with the example above, the controller activates read transistors in dynamic latch device 806A, followed by the activation of read transistors in dynamic latch device 806B. Specifically, the controller can use the control signals RE_0 and WE_0 to activate (i.e., turn on) read transistors 808A3 and 810A3, as well as transistors 808A2 and 810A2, in device 806A. If the sample memory node SN_0 remains constant (i.e., the threshold voltage of the read memory cell is greater than the applied word line voltage), memory device 812A is activated because the gate-source voltage of device 812A is greater than its threshold voltage.Since transistors 808A3 and 810A3 are connected to source line 818, global bit line 804 is pulled down. When the sampling node SN_0 is discharged (i.e., the threshold voltage of the memory cell to be read in the selected subblock is no greater than the applied word line voltage), memory device 812A is not activated (i.e., it remains off). Conversely, global bit line 804 is not pulled down and remains unchanged. In this way, the data stored in the selected memory cell in subblock 802A0 is read (block 858) or transferred to the side buffer 840.

[0115] Next, the controller can use the control signals RE_1 and WE_1 to activate (i.e., turn on) the read transistors 808B3 and 810B3, as well as the transistors 808B2 and 810B2 in the dynamic latch device 806B. If the sample memory node SN_1 remains constant (i.e., the threshold voltage of the memory cell to be read is greater than the applied word line voltage), the memory device 812B is activated because the gate-source voltage of device 812B is greater than its threshold voltage. Since transistors 808B3 and 810B3 are connected to the source line 818, the global bit line 804 is pulled down. If the sample memory node SN_1 is discharged (i.e., the threshold voltage of the memory cell to be read in the selected subblock is not greater than the applied word line voltage), the memory device 812B is not activated (i.e., it remains off).Conversely, the global bit line 804 is not pulled down and remains unchanged. In this way, the data stored in the selected memory cell in subblock 802B0 is read (block 858) or transferred to the side buffer 840.

[0116] Accordingly, during parallel read operations, data stored in different memory cells in different subblocks can be read or transferred in parallel to the respective sample memory nodes (e.g., SN_0 and SN_1) and then serially sampled by the read amplifier in the side buffer. This also improves the efficiency of the read operation.

[0117] Embodiments of devices, systems and methods according to the disclosure are set forth below:

[0118] Design 1. A three-dimensional storage device comprising: an arrangement of memory cells comprising a plurality of memory blocks with a first memory block, wherein the first memory block contains a plurality of sets of subblocks; a global bit line; a control system; and a multitude of dynamic latch devices connected between the global bit line and the multitude of sets of subblocks, wherein: a first dynamic latch device of the plurality of dynamic latch devices is connected to a first set of subblocks of the plurality of sets of subblocks, various dynamic latch devices of the multitude of dynamic latch devices are connected to various sets of subblocks of the multitude of sets of subblocks, and The first dynamic latch device is controllable by the controller to store program data during a programming operation, where the first set of subblocks connected to the first dynamic latch device are not selected subblocks during the programming operation. Embodiment 2. The three-dimensional storage device according to embodiment 1, further comprising a side buffer, wherein during the programming operation the controller is configured to: to obtain the program data from the first dynamic latch device instead of the side buffer; and to perform the programming operation of one or more subblocks that are not connected to the first dynamic latch device, wherein the one or more subblocks are selected subblocks in the plurality of sets of subblocks for performing the programming operation. Embodiment 3. The three-dimensional storage device according to one of embodiments 1-2, wherein each dynamic latch device comprises the plurality of dynamic latch devices: a storage device; a large number of write transistors connected between the global bit line and the storage device; and a plurality of read transistors connected between the storage device and a source line; wherein: the storage device is connected between the plurality of write transistors and the plurality of read transistors, wherein the storage device is controllable to store data at a sample storage node. Embodiment 4. The three-dimensional storage device according to one of embodiments 1-3, wherein the control is further configured to: to cause word lines connected to all sets of subblocks of the multitude of sets of subblocks to rise to an initial word line voltage based on a single programming pulse, so that columns of memory cells in the multitude of sets of subblocks are charged and potential-free; to cause the global bit line to rise to a global bit line voltage; to perform the following for each subblock in the multiple set of multiple sets subblocks: to activate one or more write transistors in at least one dynamic latch device of the plurality of dynamic latch devices and to activate a selection gate of a subblock in a corresponding set of subblocks of the plurality of sets of subblocks; Modulating the global bit line voltage so that it remains constant or changes based on the program data; to cause word lines associated with a selected subblock in each set of subblocks of the multitude of sets of subblocks to rise to a second word line voltage; and To program several selected sub-blocks across a multitude of dynamic latches based on a single programming impulse. Embodiment 5. Three-dimensional storage device according to one of claims 1-4, wherein the control is configured to program at least four sub-blocks of the first storage block and at least four other sub-blocks in another storage block in parallel using the plurality of dynamic latch devices. Embodiment 6. The three-dimensional storage device according to one of embodiments 1-5, wherein a dynamic latch device of the plurality of latch devices comprises a plurality of read transistors configured to perform read amplification during a read operation. Embodiment 7. The three-dimensional storage device according to one of embodiments 1-6, wherein the control is further configured to: to cause the global bit line to rise to a global bit line voltage; to activate one or more write transistors in each of the plurality of dynamic latch devices and to activate a selection gate of a subblock in each set of subblocks of the plurality of sets of subblocks; to cause word lines associated with a selected memory cell of a subblock in each set of subblocks of the multitude of sets of subblocks to rise to a first word line voltage; to cause word lines connected to unselected memory cells of the subblock in each set of subblocks of the multitude of sets of subblocks to rise to a second word line voltage; to disable one or more write transistors in each of the plurality of dynamic latch devices and to enable another select gate of a subblock in each set of subblocks of the plurality of sets of subblocks; and to serially activate one or more read transistors for each of the multitude of dynamic latch devices and to cause several selected subblocks to be read using the multitude of dynamic latch devices based on a single read pulse. Embodiment 8. The three-dimensional storage device according to one of embodiments 1-7, wherein the first set of sub-blocks comprises at least two sub-blocks, wherein the at least two sub-blocks are connected to the first dynamic latch device and no other dynamic latch devices. Embodiment 9. The three-dimensional storage device according to one of embodiments 1-8, wherein the plurality of dynamic latch devices is physically arranged above the arrangement of memory cells, wherein other latch devices are physically arranged below the arrangement of memory cells in a side buffer. Embodiment 10. The three-dimensional storage device according to one of embodiments 1-9, wherein the plurality of dynamic latch devices comprises at least 20 dynamic latch devices per global bit line per level. Embodiment 11. The three-dimensional storage device according to one of embodiments 1-10, further comprising a side buffer connected to the global bit line, wherein the controller is further configured to perform operations to cause at least two selected subblocks of the plurality of sets of subblocks to be programmed in parallel, using program data obtained from the side buffer. Embodiment 12. The three-dimensional storage device according to one of embodiments 1-11, wherein the controller is configured to cause the program data to be stored at a read storage node in the first dynamic latch device. Embodiment 13. The three-dimensional storage device according to one of embodiments 1-12, wherein the first dynamic latch device comprises a storage device comprising a switching transistor with a gate terminal connected to the read storage node. Embodiment 14. The three-dimensional storage device according to one of embodiments 1-13, wherein each of the plurality of dynamic latch devices is connected to between one and four sub-blocks. Embodiment 15. The three-dimensional storage device according to one of embodiments 1-14, wherein the arrangement of memory cells comprises three-level or four-level memory cells. Embodiment. 16. Method performed by a three-dimensional storage device comprising a plurality of storage blocks with a first storage block, wherein the first storage block comprises a plurality of sets of subblocks, the method comprising: To cause a global bit line to rise to a global bit line voltage; Activating one or more write transistors in each of a plurality of dynamic latch devices and activating a selection gate of a subblock in each set of subblocks of the plurality of sets of subblocks; Causing word lines associated with a selected memory cell of a subblock in each set of subblocks of the multitude of sets of subblocks to rise to an initial word line voltage; Causing word lines connected to unselected memory cells of the subblock in each set of subblocks of the multitude of sets of subblocks to rise to a second word line voltage; Disabling one or more write transistors in each of the plurality of dynamic latch devices and enabling another select gate of a subblock in each set of subblocks of the plurality of sets of subblocks; and serial activation, for each of the multitude of dynamic latch devices, of one or more read transistors, and causing multiple selected subblocks to be read using the multitude of dynamic latch devices based on a single read pulse. Embodiment 17. Method carried out by a three-dimensional storage device comprising a plurality of storage blocks with a first storage block, wherein the first storage block comprises a plurality of sets of subblocks, the method comprising: Causing word lines connected to all sets of subblocks of the multitude of sets of subblocks to rise to an initial word line voltage based on a single programming pulse, so that columns of memory cells in the multitude of sets of subblocks are charged and potential-free; Causing the global bit line to rise to a global bit line voltage; Perform the following for each subblock in the multiple set of multiple sets subblocks: Activating one or more write transistors in a dynamic latch device of a plurality of dynamic latch devices and activating a selection gate of a subblock in a corresponding set of subblocks of the plurality of sets of subblocks; Modulating the global bit line voltage so that it remains constant or changes based on program data; Causing word lines associated with a selected subblock in each set of subblocks of the multitude of sets of subblocks to rise to a second word line voltage; and Programming multiple selected sub-blocks across a multitude of dynamic latches based on a single programming impulse. Embodiment 18. A system, such as a storage system, comprising: a processor; and a storage device coupled to the processor, wherein the storage device comprises: an arrangement of memory cells comprising a plurality of memory blocks with a first memory block, wherein the first memory block contains a plurality of sets of subblocks; a global bit line; a control system; and a multitude of dynamic latch devices connected between the global bit line and the multitude of sets of subblocks, wherein: a first dynamic latch device of the plurality of dynamic latch devices is connected to a first set of subblocks of the plurality of sets of subblocks, various dynamic latch devices of the multitude of dynamic latch devices are connected to various sets of subblocks of the multitude of sets of subblocks, and The first dynamic latch device is controllable by the controller to store program data during a programming operation, where the first set of subblocks connected to the first dynamic latch device are not selected subblocks during the programming operation.

[0119] It should be noted that the described techniques include possible implementations, and that the operations and blocks can be regrouped, rearranged, or otherwise modified, and that other implementations are possible. Furthermore, parts of two or more of the methods can be combined.

[0120] The information and signals described herein can be represented using any of a wide variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols referenced in the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may depict signals as a single signal; however, the signal may also represent a bus of signals, the bus being capable of having a variety of bit widths.

[0121] The terms "electronic communication," "conductive contact," "connected," and "coupled" can refer to a relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) when there is a conductive path between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact, connected, or coupled) can be an open circuit or a closed circuit, depending on the operation of the device that includes the connected components.The conductive path between connected components can be a direct conductive path between the components themselves, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components can be interrupted for a period of time, for example, by using one or more intermediate components such as switches or transistors.

[0122] The term "coupling" (e.g., "electrical coupling") can refer to a transitional state from an open-circuit relationship between components, in which signals cannot currently be communicated via a conductive path between the components, to a closed-circuit relationship between components, in which signals can be communicated via the conductive path between the components. When a component, such as a controller, couples other components, the component initiates a change that allows signals to flow between the other components via a conductive path that previously did not permit signal flow.

[0123] The term "isolated" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other when there is an open circuit between them. For example, two components separated by a switch positioned between them are isolated when the switch is open. When a controller isolates two components, it causes a change that prevents signals from flowing between them using a conductive path that previously allowed signal flow.

[0124] The terms "if", "when", "based on", or "at least partially based on" can be used interchangeably. In some examples, when the terms "if", "when", "based on", or "at least partially based on" are used to describe a conditional action, a conditional process, or a connection between parts of a process, the terms can be used interchangeably.

[0125] The term "in response to" can refer to a condition or action occurring at least partially, if not entirely, as a result of a previous condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the previous condition or action (whether directly after it or after one or more other intermediate conditions or actions have occurred following the first condition or action).

[0126] The devices discussed herein, including a memory arrangement, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate or of subregions of the substrate may be controlled by doping using various chemical species, including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other dopant.

[0127] A switching component or transistor discussed herein may be a field-effect transistor (FET) and comprise a three-terminal device consisting of a source, a drain, and a gate. The terminals may be connected to other electronic elements by conductive materials, such as metals. The source and drain may be conductive and may comprise a heavily doped, such as degenerate, semiconductor region. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate.For example, applying a positive or negative voltage to an n-type or p-type FET can cause the channel to become conductive. A transistor can be "on" or "activated" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor can be "off" or "disabled" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

[0128] The description presented herein, in conjunction with the accompanying drawings, describes example configurations and does not represent all examples that can be implemented or that fall within the scope of the embodiments. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "advantageous over other examples." The detailed description includes specific details to facilitate an understanding of the techniques described. However, these techniques can be practiced without these specific details. In some cases, known designs and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0129] In the accompanying figures, similar components or features may share the same reference symbol. Furthermore, different components of the same type may be distinguished by following the reference symbol with a hyphen and a second symbol that differentiates between the similar components. If only the first reference symbol is used in the description, the description applies to any of the similar components that share the same first reference symbol, regardless of the second reference symbol.

[0130] The functions described herein can be implemented in hardware, in software executed by a processor, in firmware, or in any combination thereof. If implemented in software executed by a processor (e.g., processor 310 of Fig.3) When executed, the functions can be stored or transmitted as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and the accompanying embodiments. For example, due to the nature of software, the described functions can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations thereof. Features implementing functions can also be physically located in different places, including a distribution such that portions of functions are implemented in different physical locations.

[0131] As used herein, including in the embodiments, "or," as used in a list of elements (for example, a list of elements preceded by a phrase such as "at least one of" or "one or more of"), indicates an inclusive list, such that, for example, a list of at least one of A, B, or CA, or B or C, or AB or AC, or BC or ABC (i.e., A and B and C) means. Also as used herein, the phrase "based on" is not to be interpreted as indicating a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without exceeding the scope of this disclosure. In other words, as used herein, the phrase "based on" is to be interpreted in the same way as the phrase "at least partially based on."

[0132] The description herein is provided to enable a person skilled in the art to manufacture or use the disclosure. Various modifications to the disclosure will be obvious to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is intended to have the widest possible scope consistent with the principles and new features disclosed herein. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 716.935

[0001] US 19 / 370.476

[0001]

Claims

[1] Three-dimensional storage device comprising: an arrangement of memory cells comprising a plurality of memory blocks with a first memory block, wherein the first memory block contains a plurality of sets of subblocks; a global bit line; a control system; and a multitude of dynamic latch devices connected between the global bit line and the multitude of sets of subblocks, wherein: a first dynamic latch device of the plurality of dynamic latch devices is connected to a first set of subblocks of the plurality of sets of subblocks, various dynamic latch devices of the multitude of dynamic latch devices are connected to various sets of subblocks of the multitude of sets of subblocks, and The first dynamic latch device is controllable by the controller to store program data during a programming operation, where the first set of subblocks connected to the first dynamic latch device are not selected subblocks during the programming operation. [2] Three-dimensional storage device according to claim 1, further comprising a side buffer, wherein the controller is configured during the programming operation to: to obtain the program data from the first dynamic latch device instead of the side buffer; and to perform the programming operation of one or more subblocks that are not connected to the first dynamic latch device, wherein the one or more subblocks are selected subblocks in the plurality of sets of subblocks for performing the programming operation. [3] The three-dimensional storage device according to one of claims 1-2, wherein each of the plurality of dynamic latch devices comprises: a storage device; a large number of write transistors connected between the global bit line and the storage device; and a plurality of read transistors connected between the storage device and a source line; wherein: the storage device is connected between the plurality of write transistors and the plurality of read transistors, wherein the storage device is controllable to store data at a sample storage node. [4] The three-dimensional storage device according to one of claims 1-3, wherein the control is further configured to: to cause word lines connected to all sets of subblocks of the multitude of sets of subblocks to rise to an initial word line voltage based on a single programming pulse, so that columns of memory cells in the multitude of sets of subblocks are charged and potential-free; to cause the global bit line to rise to a global bit line voltage; to perform the following for each subblock in the multiple set of multiple sets subblocks: Activating one or more write transistors in a dynamic latch device of the plurality of dynamic latch devices and activating a selection gate of a subblock in a corresponding set of subblocks of the plurality of sets of subblocks; Modulating the global bit line voltage so that it remains constant or changes based on the program data; to cause word lines associated with a selected subblock in each set of subblocks of the multitude of sets of subblocks to rise to a second word line voltage; and To program several selected sub-blocks across a multitude of dynamic latches based on a single programming impulse. [5] The three-dimensional storage device according to one of claims 1-4, wherein the control is configured to program at least four sub-blocks of the first storage block and at least four other sub-blocks in another storage block in parallel using the plurality of dynamic latch devices. [6] The three-dimensional storage device according to any one of claims 1-5, wherein a dynamic latch device of the plurality of latch devices comprises a plurality of read transistors configured to perform read amplification during a read operation. [7] The three-dimensional storage device according to any one of claims 1-6, wherein the control is further configured to: to cause the global bit line to rise to a global bit line voltage; to activate one or more write transistors in each of the plurality of dynamic latch devices and to activate a selection gate of a subblock in each set of subblocks of the plurality of sets of subblocks; to cause word lines associated with a selected memory cell of a subblock in each set of subblocks of the multitude of sets of subblocks to rise to a first word line voltage; to cause word lines connected to unselected memory cells of the subblock in each set of subblocks of the multitude of sets of subblocks to rise to a second word line voltage; to disable one or more write transistors in each of the plurality of dynamic latch devices and to enable another select gate of a subblock in each set of subblocks of the plurality of sets of subblocks; and to serially activate one or more read transistors for each of the multitude of dynamic latch devices and to cause several selected subblocks to be read using the multitude of dynamic latch devices based on a single read pulse. [8] The three-dimensional storage device according to any one of claims 1-7, wherein the first set of sub-blocks comprises at least two sub-blocks, wherein the at least two sub-blocks are connected to the first dynamic latch device and no other dynamic latch devices. [9] A method carried out by the three-dimensional storage device according to claim 1, the method comprising: Causing the global bit line to rise to a global bit line voltage; Activating one or more write transistors in each of the plurality of dynamic latch devices and activating a selection gate of a subblock in each set of subblocks of the plurality of sets of subblocks; Causing word lines associated with a selected memory cell of a subblock in each set of subblocks of the multitude of sets of subblocks to rise to an initial word line voltage; Causing word lines connected to unselected memory cells of the subblock in each set of subblocks of the multitude of sets of subblocks to rise to a second word line voltage; Disabling one or more write transistors in each of the plurality of dynamic latch devices and enabling another select gate of a subblock in each set of subblocks of the plurality of sets of subblocks; and serial activation, for each of the multitude of dynamic latch devices, of one or more read transistors, and causing multiple selected subblocks to be read using the multitude of dynamic latch devices based on a single read pulse. [10] A method carried out by the three-dimensional storage device according to claim 1, the method comprising: Causing word lines connected to all sets of subblocks of the multitude of sets of subblocks to rise to an initial word line voltage based on a single programming pulse, so that columns of memory cells in the multitude of sets of subblocks are charged and potential-free; Causing the global bit line to rise to a global bit line voltage; Perform the following for each subblock in the multiple set of multiple sets subblocks: Activating one or more write transistors in a dynamic latch device of the plurality of dynamic latch devices and activating a selection gate of a subblock in a corresponding set of subblocks of the plurality of sets of subblocks; Modulating the global bit line voltage so that it remains constant or changes based on program data; Causing word lines associated with a selected subblock in each set of subblocks of the multitude of sets of subblocks to rise to a second word line voltage; and Programming multiple selected sub-blocks via the multitude of dynamic latches based on the single programming impulse.

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