METHOD AND SYSTEMS FOR PERFORMING THRESHOLD VERIFICATION USING MULTI-LEVEL SAMPLING OF STORAGE CELLS

Abstract

Methods, systems, and devices for faster voltage threshold verification techniques are provided. In one embodiment, a storage device comprises a memory cell and a side buffer. The memory cell is connected to a word line to receive a word line voltage corresponding to a first level of the memory cell. The side buffer is coupled to a bit line associated with the memory cell. The side buffer includes a sampling amplifier configured to sample a current on the bit line. The sampling amplifier is configured to determine a voltage of the sampling amplifier based on the current at a first time point, corresponding to a first-level PV voltage.The sampling amplifier is configured to determine the sampling amplifier circuit voltage based on the current at a second time point, which corresponds to an SPPV voltage of a second level of the memory cell.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] This application claims priority over the preliminary US application No. 63 / 717,802, filed on November 7, 2024, entitled “METHODS AND SYSTEMS TO PERFORM THRESHOLD VERIFICATION USING MULTI-LEVEL SENSING OF MEMORY CELLS”, and the non-preliminary US application No. 19 / 363,557, filed on October 20, 2025, entitled “METHODS AND SYSTEMS TO PERFORM THRESHOLD VERIFICATION USING MULTI-LEVEL SENSING OF MEMORY CELLS”, the contents of both hereby incorporated by reference in their entirety and for all purposes. AREA OF TECHNOLOGY

[0002] This disclosure relates to one or more memory systems, including techniques for methods and systems for performing threshold verification using multi-level sampling of memory cells. GENERAL STATE OF THE ART

[0003] Storage devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within a storage device to different states. For example, binary memory cells can be programmed to one of two supported states, often denoted by a logical 1 or a logical 0. In some examples, a single memory cell can support more than two states, each of which can be stored. To access stored information, the storage device can read states from the memory cells (e.g., capture, detect, program verify, retrieve, determine, etc.). To store information, the storage device can write states to the memory cell (e.g.,(programming, setting, assigning, etc.). Information can also be deleted from the memory cells and new information can be stored in the memory cells.

[0004] There are various types of memory devices, including magnetic disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), self-selecting memory, chalcogenide memory technologies, not-or (NOR) and not-and (NAND) memory devices, and others. Memory cells can be described as volatile or non-volatile. Memory cells configured in a non-volatile configuration can retain stored logical states for extended periods, even without an external power source. Memory cells configured in a volatile configuration can lose stored states when disconnected from an external power source. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram of a storage device communicating with a storage system controller of a storage system, in accordance with the examples disclosed in this document. Fig. Figures 2A-2C show schematic representations of parts of an array of memory cells in a storage device in accordance with the examples disclosed in this document. Fig. Figure 2D illustrates an example of a storage device including multiple blocks of memory cells in accordance with examples disclosed in this document. Fig. Figure 3 illustrates a graphical representation of a circuit voltage over a certain period of time during threshold verification in accordance with examples disclosed in this document. Fig.Figure 4 illustrates a graphical representation of example cell distributions and example verification levels corresponding to different logical levels, in accordance with the examples disclosed in this document. Fig. Figure 5 illustrates a graphical representation of cell distributions of exemplary logical levels of three cells of an array of memory cells in accordance with the examples disclosed in this paper. Fig. Figure 6 illustrates a flowchart showing a procedure to support techniques for performing threshold verification using multi-level sampling of a memory cell in accordance with the examples disclosed in this document. DETAILED DESCRIPTION

[0005] Memory devices can use cell distributions of threshold voltages (Vt) corresponding to memory cells to determine the current logic level of the memory cells. These cell distributions of threshold voltages specify voltage levels which, when applied to selected gates of the corresponding memory cells programmed to specific logic levels, cause the memory cells (e.g., the transistors that make up the memory cells) to conduct and be read, written, or both. For example, the threshold voltages of memory cells programmed to a logic level of 010 (e.g., a lower logic level) can range from 1.4 volts (Vt) to 1.8 V, and the threshold voltage of memory cells programmed to a logic level of 011 (e.g., a higher logic level) can range from 1.9 V to 2.3 V.

[0006] A storage device can verify (e.g., determine) the cell distributions of the threshold voltages by performing programming loops. During each programming loop, for example, a controller of the storage device causes predetermined voltages (e.g., in the form of program pulses) to be applied to word lines connected to the memory cells at different verification levels, corresponding to different logical levels. These predetermined voltages are also called word line voltages. In an example described in more detail below, multiple verification levels can correspond to the same logical level. Thus, a first verification level and a second verification level of the word line voltages can both correspond to a first logical level. A third verification level of the word line voltages can correspond to a second logical level.In the example above, two verification levels correspond to one logical level. In other examples, three verification levels may correspond to one logical level. As described below, a larger number of verification levels can provide higher accuracy in determining the cell distribution for threshold voltages, but can also cause a longer delay.

[0007] During programming loops, the controller can initiate a current sampling on one or more bit lines electrically connected to the memory cells to determine whether the memory cells are conducting at the various verification levels. For example, a sampling amplifier of the storage device can sample the currents on the bit lines (e.g., read, detect, sample, retrieve, program verify, or determine). Based on the current sampled by the sampling amplifier, the controller of the storage device can adjust the bit line voltages to control the current on the bit lines for subsequent programming loops. Controlling the current on the bit lines can limit (e.g., reduce) or prevent (e.g., lock) changes in the current on the bit lines that occur during subsequent programming loops.

[0008] Next, the example of two verification levels corresponding to one logical level is described. During programming loops, a sampling amplifier of a storage device can sample the current on the bit lines for only two verification levels per logical level. For example, a controller of the storage device can determine whether the memory cells are conducting for only one Pre-Program Verify (PPV) voltage verification level (generally referred to in this disclosure as a first PPV (FPPV) voltage) and one Program Verify (PV) voltage verification level (generally referred to in this disclosure as a PV voltage) for each logical level.Furthermore, during programming loops, a memory device controller can cause the word line voltage to be applied to the two verification levels so that the sampling amplifier can sample the current on the bit lines for the two different verification levels. However, if the controller determines whether the memory cells are only conductive for two different verification levels per logic level, the accuracy of determining the cell distributions of the threshold voltages may be reduced. Additionally, errors may occur during subsequent operations of the memory device.

[0009] Certain technologies employ three verification levels to improve determination accuracy. Specifically, during programming loops, the sampling amplifier of a storage device can sample the current on the bit lines for three verification levels per logical level. For example, the controller of a storage device can determine whether the memory cells are conducting for a super-PPV voltage verification level (generally referred to in this disclosure as a second PPV voltage (SPPV)), the FPPV voltage, and the PV voltage for each logical level of the memory cells. Therefore, during programming loops, a controller of the storage device can cause the word line voltage to be applied to each of the three verification levels (SPPV, FPPV, and PV) so that the sampling amplifier can sample the current on the bit lines for the three distinct verification levels.Compared to two verification levels per logical level, determining whether memory cells are conducting for three verification levels per logical level can improve the accuracy of cell distributions and reduce errors during subsequent storage device operations. However, during such an operation, the controller must ensure that the word line voltage is applied at each of the three verification levels per logical level. This increases the time required to verify the cell threshold voltage distributions compared to sampling the current on the bit lines for only two different verification levels per logical level. In other words, sampling the current on the bit lines for three verification levels per logical level can introduce additional delay compared to applying it to only two verification levels.

[0010] Another limiting factor in sampling the bit line current for three verification levels is the sampling range of the sampling amplifier. During programming loops, the sampling amplifier of a storage device can determine whether the bit lines are conducting current by measuring a circuit voltage (e.g., a node voltage) at the sampling amplifier's input at various times while a word line voltage corresponding to a specific logic level is applied. For example, the storage device's sampling amplifier can determine whether the circuit voltage decreases (e.g., drops) at different times to determine whether the bit lines are conducting current. Each of these different times can correspond to a different verification level of the respective logic level.However, the sampling amplifier may have a limited sampling range capability, and a potential difference of the circuit voltage between three different verification levels of a given logic level may be greater than the sampling range capability of the sampling amplifier. For example, a potential difference of the circuit voltage between three verification levels of a given logic level may be four hundred millivolts (mV), and the sampling range capability of the sampling amplifier may be limited to seventy mV. Consequently, the limited sampling range capability of the sampling amplifier may prevent it from being able to determine the circuit voltage corresponding to each of the three verification levels of a given logic level while applying a single word line voltage corresponding to that logic level to the memory cells.

[0011] To compensate for the limited sampling range capability of the sampling amplifier, the controller, during the programming loops, causes a first word line voltage, associated with the specified logic level, to be applied to the word line connected to the memory cells. The sampling amplifier determines the circuit voltage at two time points, corresponding to two of the verification levels of the specified logic level. Subsequently, during the programming loops, the controller causes a second word line, also associated with the specified logic level, to be applied to the word line connected to the memory cells. The sampling amplifier determines the circuit voltage at another time point, corresponding to another verification level of the specified logic level.To mitigate the limited sampling range of the sampling amplifier, the controller applies two word line voltages for three verification levels per logical level. While this technology can solve the limited sampling range problem, it can also increase the time required to verify the cell distribution of the memory cells compared to a controller that applies only one word line voltage per logical level for all three verification levels.

[0012] The present disclosure provides techniques for avoiding or reducing the technical difficulties described above. In particular, some embodiments described in the present disclosure include a storage device configured during programming loops to sample the circuit voltage at various times corresponding to multiple verification levels of multiple logic levels, while applying a word line voltage corresponding to a single logic level. For example, a local controller of the storage device causes the application of a word line voltage corresponding to a first logic level.In these and other embodiments, a sampling amplifier of the storage device determines the circuit voltage at various time points corresponding to several verification levels of the first logic level and a second logic level, while the word line voltage corresponding to the first logic level is applied. For example, the sampling amplifier can determine the circuit voltage at a first time point corresponding to the FPPV voltage of the first logic level, at a second time point corresponding to the PV voltage of the first logic level, or at a third time point corresponding to the SPPV voltage of the second logic level. The sampling amplifier can perform such a determination because a value of the SPPV voltage of the second logic level can be equal to, similar to, or close to a value of the PV voltage of the first logic level.Such an overlap of verification voltage levels on different logic levels, in turn, reduces the potential difference of the sampling amplifier's circuit voltages between multiple verification levels of several logic levels. For example, the SPPV voltage of the second logic level can be equal to, similar to, or close to the PV voltage of the first logic level. This can reduce the potential difference of the circuit voltages between three verification levels of two logic levels compared to the potential difference of the circuit voltages between three verification levels of a single logic level. The potential difference between circuit voltages between three verification levels of a single logic level can be one and a half or two times the potential difference between three verification levels of two logic levels.In one example, the potential difference of the circuit voltages between three verification levels, corresponding to two logic levels, can be 0.2 V, and the potential difference of the circuit voltage between the three verification levels, corresponding to a single logic level, can be 0.5 V. By reducing the circuit voltage differences (e.g., the voltage differences at the input node of the sampling amplifier), the problem of the sampling amplifier's limited sampling voltage capability is mitigated or eliminated.

[0013] During a programming loop, the local controller can identify logic levels used to verify the cell distribution of the threshold voltage of a current logic level of the memory cells. For example, the local controller can identify that the first and second logic levels of the memory cells need to be verified. The local controller can then instruct a controller of the memory device to apply a word line voltage corresponding to a lower logic level among the identified logic levels. In other words, the controller can pre-charge the word line to a voltage level corresponding to the lower logic level among the identified logic levels. For example, the controller can apply the word line voltage at the PV voltage of the first logic level.

[0014] As described above, the sampling amplifier can sample the current of the bit lines. Additionally, the sampling amplifier can determine the circuit voltage at different times, corresponding to different verification levels of a lower and a higher logic level, using only the word line voltage corresponding to the lower logic level. In other words, the sampling amplifier can allow the circuit voltage to develop and be sampled for three verification levels, corresponding to two logic levels, while applying a single word line voltage.For example, the sampling amplifier can determine the circuit voltage at a first time point corresponding to the FPPV voltage of the first identified logic level, at a second time point corresponding to the PV voltage of the first identified logic level, and / or at a third time point corresponding to the SPPV voltage of the second identified logic level, all while the controller only causes the word line voltage to be applied at the PV voltage of the first identified logic level.

[0015] As described above, the storage device described in this disclosure is configured to perform threshold voltage verification by sampling the circuit voltage at various times corresponding to multiple verification levels of different logic levels, without altering the word line voltage. Consequently, the technologies described in this document can increase the accuracy in determining the cell distributions for the threshold voltages compared to determining the cell distribution using only two different verification levels. Unlike some existing technologies, this increase in accuracy in determining the cell distribution does not come at the cost of increasing the time delay for such determination.As briefly described above and explained in more detail below, the techniques of a storage device disclosed in this paper enable the time and / or latency for verifying the threshold voltages to be reduced by not having to adjust the word line voltage multiple times per programming loop.

[0016] Fig.Figure 1 is a simplified block diagram of a storage device 130 communicating with a system controller 115 of a storage system according to one embodiment. A storage system can be or include any device or collection of devices, wherein the device or collection of devices includes at least one storage array. For example, a storage system can be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among others. A storage system can communicate with a host system, which may include a host control panel.The host system can be implemented with one or more processors and a storage system to write data to the storage system, read data from the storage system, delete data, or refresh data.

[0017] A storage system can contain one or more storage devices, such as storage device 130. Storage device 130 can contain one or more memory arrays of any type of memory cell (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Storage device 130 can, for example, include NAND memory (e.g., NAND flash), ROM, phase-change memory (PCM), NOR memory (e.g., NOR flash), and so on. In some cases, storage device 130 is a NAND storage device 130 and may contain memory cells configured to store one bit of information each, which can be referred to as single-level cells (SLCs).Additionally or alternatively, a NAND flash memory device can include 130 memory cells configured to store multiple bits of information. These cells are referred to as multi-level cells (MLC) if configured to store two bits of information each, tri-level cells (TLC) if configured to store three bits of information each, and quad-level cells (QLC) or, more generally, multi-level memory cells if configured to store four bits of information each. Multi-level memory cells can provide higher storage density compared to single-level condenser (SLC) memory cells, but in some cases, they may result in tighter read or write spans or increased complexity in supporting circuitry.

[0018] As in Fig.As shown in Figure 1 and described in more detail below, the storage device 130 comprises an array of memory cells 104, logically arranged in rows and columns. Memory cells of a logical row are typically associated with the same access line (e.g., a word line), while memory cells of a logical column are typically selectively associated with the same bit line (e.g., a bit line). A single access line can be associated with more than one logical row of memory cells, and a single data line can be associated with more than one logical column. Memory cells (not shown in Figure 1) Fig. 1 shown) at least part of the arrangement of memory cells 104 are able to be programmed to one of at least two target data states in order to store any number of information bits.

[0019] With continued reference to Fig.A row decoding circuit 108 and a column decoding circuit 111 are provided to decode address signals. Address signals are received and decoded to access the array of memory cells 104. The memory device 130 also includes an input / output (I / O) control circuit 112 to manage the input of commands, addresses, and data to the memory device 130, as well as the output of data and status information from the memory device 130. An address register 144 communicates with the I / O control circuit 112 and the row decoding circuit 108 and column decoding circuit 111 to temporarily store the address signals before decoding. The row decoding circuit 108 and the column decoding circuit 111 can be referred to simply as the row decoder 108 and the column decoder 111, respectively.An instruction register 124 communicates with the I / O control circuit 112 and a local controller 135 to temporarily store incoming instructions.

[0020] A memory controller (e.g., the local controller 135 within the memory device 130) controls access to the array of memory cells 104 in response to instructions and generates status information for the external system controller 115. That is, the local controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on the array of memory cells 104. The local controller 135 communicates with the row decoding circuit 108 and the column decoding circuit 111 to control the row decoding circuit 108 and the column decoding circuit 111 according to the addresses.

[0021] In some embodiments, the local controller 135 may also include a bias control circuit 137 that communicates with a controller 109. The controller 109 can apply specific bias voltages or currents to the word lines, the bit lines, or both, connected to the array of memory cells 104. The controller 109 can be controlled by the memory controller according to the addresses provided by the row decoding circuit 108 and the column decoding circuit 111. For example, the controller 109 can apply bias voltages and / or currents to specific word and bit lines for selected memory cells to perform read, write, program, and erase operations. The controller 109 may include one or more circuits for generating bias voltages and currents and for controlling or driving the word and bit lines of the selected memory cells.

[0022] In some embodiments, the local controller 135 communicates with the external system controller 115, which may be a host controller (e.g., a UFS or eMMC controller, or a CPU communicating with the local controller 135) in a host system or a storage system controller in a storage system. In some embodiments, the local controller 135 is located on the same semiconductor chip as the memory array (e.g., an array of memory cells 104), and a separate system controller 115 is located on a different die. In other examples, some parts of the storage device 130 may be located on a first die, and other parts of the storage device 130 may be located on a second die, different from the first. The first die may, for example, contain the array of memory cells 104 and the associated circuitry, such as the column decoder 111 and the row decoder 108, etc.The second die can contain logic circuits, power supply circuits, or other circuitry of the storage device 130. For example, the second die can contain the system controller 115, the I / O control circuit 112, and so on. In this example, the first die has no local controller, and the second die contains the system controller 115. The first die and the second die can be hybrid-connected, for example, using through-holes (TSVs) so that they are electrically connected. The first die and the second die can also be bonded to wafers using flip-chip bonding technologies, etc. In this disclosure, for the sake of simplicity, the system controller 115 and the local controller 135 can both be referred to as memory controllers, or as a first memory controller and a second memory controller.It is understood that, although different controllers may be involved, certain operations disclosed in this document may be caused or performed by one or both memory controllers, unless otherwise specified.

[0023] The local controller 135 also communicates with a cache register 118, registers 121, and a sampling amplifier 140. In some embodiments, one or more cache registers 118 together can form at least part of a cache buffer. The cache register 118 stores or buffers incoming or outgoing data according to the instructions of the local controller 135 to temporarily store data while the array of memory cells 104 is busy writing or reading other data. During a program operation (e.g., a write operation), data can be passed from the cache register 118 to the registers 121 for transfer to the array of memory cells 104; then, new data can be temporarily stored in the cache register 118 by the I / O control circuit 112.During a read operation, data from the cache register 118 can be forwarded to the I / O control circuit 112 for output to the system controller 115; then, new data from the registers 121 can be forwarded to the cache register 118. In some embodiments, the cache register 118 and / or the registers 121 can form at least part of a page buffer 152 of the storage device 130. The sampling amplifier 140 can be configured to sample a data state of a memory cell of the array of memory cells 104, for example, by sampling a state of a bit line (e.g., bit lines) connected to that memory cell. The sampling amplifier 140 is described in more detail below. A status register 122 can communicate with the I / O control circuit 112 and the local controller 135 to store the status information for output to the system controller 115.

[0024] As in Fig.As shown in Figure 1, the storage device 130 receives various control signals from the system controller 115 via a control connection 132 through the local controller 135. For example, the control signals can include a chip enable signal CE#, a command buffer enable signal CLE, an address buffer enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write-protect signal WP#. Additional or alternative control signals (not shown) can also be received via the control connection 132, depending on the type of storage device 130. In one embodiment, the storage device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the system controller 115 via a multiplexed input / output (I / O) bus 134 and outputs data to the system controller 115 via the I / O bus 134.

[0025] The commands can be received, for example, via input / output (I / O) pins [7:0] of I / O bus 134 at I / O control circuit 112 and then written to instruction register 124. The addresses can be received via input / output (I / O) pins [7:0] of I / O bus 134 at I / O control circuit 112 and then written to address register 144. The data can be received via input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device at I / O control circuit 112 and can then be written to cache register 118. The data can subsequently be written to registers 121 to program the array of memory cells 104.

[0026] In one embodiment, the cache register 118 can be omitted, and the data can be written directly to the registers 121. Data can also be output via input / output (I / O) pins [7:0] for an 8-bit device or via input / output (I / O) pins [15:0] for a 16-bit device. Although reference can be made to I / O pins, they can include any conductive node that provides an electrical connection to the storage device 130 through an external device (e.g., system controller 115), such as conductive pads or conductive bumps, as are commonly used. In the description above, the 16-bit I / O bus 134 is used as an example, but it is understood that the bus 134 can be configured to any number of bits (e.g., 64 bits).

[0027] The person skilled in the art will recognize that additional circuits and signals can be provided and that the storage device 130 consists of Fig. 1 has been simplified. It should be acknowledged that the functionality of the various block components, which are related to Fig. 1. This does not necessarily have to be divided into separate components or component parts of an integrated circuit device. For example, a single component or component section of an integrated circuit device can be adapted to provide the functionality of more than one block component. Fig. 1. Alternatively, one or more components or component sections of an integrated circuit device can be combined to provide the functionality of a single block component. Fig.1. Additionally, while specific I / O pins are described in accordance with popular conventions for receiving and outputting various signals, it is noted that other combinations or numbers of I / O pins (or I / O node structures) may be used in the various embodiments.

[0028] The Fig. Figures 2A-2B are exemplary schematic representations of sections of an array of memory cells 200A, e.g., a NAND flash memory array. The array of memory cells 200A can be an example of the array of memory cells 104 of a storage device 130, as described with reference to Fig. 1 according to one embodiment. The storage array 200A includes access lines such as word lines 2020 to 202. N and bit lines such as bit lines 2040 to 204 M The word lines 202 can be used with global access lines (e.g., global word lines) that are in Fig. 2A, which are not shown, are connected in a many-to-one relationship. For some embodiments, the memory arrangement 200A can be formed over a semiconductor, which may be doped, for example, to have a conductive type, such as p-type conductivity, e.g., to form a p-well, or n-type conductivity, e.g., to form an n-well.

[0029] The 200A memory array can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a string of serially connected memory cells (e.g., non-volatile memory cells), such as one of the NAND strands 2060 to 206. M . Each NAND strand 206 can be connected (e.g. selectively connected) to a common source (SRC) 216 and memory cells 2080 to 208 Ninclude. The memory cells 208 can represent non-volatile memory cells for storing data. The memory cells 208 of each NAND string 206 can be connected in series between a selection transistor 210 (e.g., a field-effect transistor), such as one of the selection gates 2100 to 210. M (e.g., source selection transistors, commonly referred to as source selection gates), and a selection transistor 212 (e.g., a field-effect transistor), such as one of the selection gates 2120 to 212 M (e.g., drain selection transistors, commonly referred to as drain selection gates). Selection gates 2100 to 210 M can be linked together with a selection line 214, such as a Source Selection Line (SGS), and selection gates 2120 to 212. MThey can be connected together with a select line 215, such as a drain select line (SGD). Although depicted as conventional field-effect transistors, the select transistors 210 and 212 can utilize a similar (e.g., the same) construction as the memory cells 208. The select transistors 210 and 212 can represent a number of select transistors connected in series, with each select gate in series configured to receive an identical or independent control signal.

[0030] A source of each select transistor 210 can be connected to the common source 216. The drain of each select transistor 210 can be connected to a memory cell 2080 of the corresponding NAND array 206. For example, the drain of the select gate 2100 can be connected to memory cell 2080 of the corresponding NAND array 2060. Therefore, each select transistor 210 can be configured to selectively connect a corresponding NAND array 206 to the common source 216. A control gate of each select transistor 210 can be connected to the select line 214.

[0031] The drain of each selection transistor 212 can be connected to the bit line 204 for the corresponding NAND strand 206. For example, the drain of the selection gate 2120 can be connected to the bit line 2040 for the corresponding NAND strand 2060. The source of each selection transistor 212 can be connected to a memory cell 208. Nof the corresponding NAND strand 206. For example, the source of the selection gate 2120 can be connected to memory cell 208. N of the corresponding NAND strand 2060. Therefore, each selection transistor 212 can be configured to selectively connect a corresponding NAND strand 206 to the corresponding bit line 204. A control gate of each selection transistor 212 can be connected to the selection line 215.

[0032] The 200A storage arrangement in Fig. 2A can be a quasi-two-dimensional memory arrangement and generally have a planar construction, e.g., where the common source 216, the NAND strands 206, and the bit lines 204 extend in substantially parallel planes. Alternatively, the memory arrangement 200A can be in Fig.2A may be a three-dimensional memory arrangement, e.g., wherein the NAND strands 206 may extend substantially perpendicular to a plane containing the common source 216 and to a plane containing the bit lines 204, which may be substantially parallel to the plane containing the common source 216.

[0033] The typical structure of memory cells 208 includes a data storage device 234 (e.g., a floating gate, a charge trap, and the like) that can determine a data state of the memory cell (e.g., by changing the threshold voltage), and a control gate 236, as shown in Fig.Figure 2A shows that the data storage structure 234 can include both conductive and dielectric structures, while the control gate 236 is generally formed from one or more conductive materials. In some cases, memory cells 208 can further have a defined source / drain (e.g., source) 230 and a defined source / drain (e.g., drain) 232. Memory cells 208 have their control gates 236 connected to (and in some cases form) a word line 202.

[0034] A column of memory cells 208 can be a NAND strand 206 or a number of NAND strands 206 selectively connected to a given bit line 204. A row of memory cells 208 can be memory cells 208 that are connected together to a given word line 202. A row of memory cells 208 may, but need not, include all memory cells 208 that are connected together to a given word line 202. Rows of memory cells 208 can often be subdivided into one or more groups of physical pages of memory cells 208, and physical pages of memory cells 208 often include every second memory cell 208 that is connected together to a given word line 202. For example, the memory cells 208 that are connected together to word line 202 Nconnected and selectively linked to even bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.), be a physical side of the memory cells 208 (e.g., even memory cells), while memory cells 208, which are connected to the word line 202 N connected and selectively connected to odd bit lines 204 (e.g. bit lines 2041, 2043, 2045 etc.), can be another physical side of the memory cells 208 (e.g. odd memory cells).

[0035] Although the bit lines 2043-2045 in Fig. Although bit lines 2A are not explicitly shown, it can be seen from the figure that the bit lines 204 of the arrangement of memory cells 200A run continuously from bit line 2040 to bit line 204. MThey may be numbered. Other groupings of memory cells 208 that are connected together to a given word line 202 may also define a physical page of memory cells 208. In certain storage devices, all memory cells that are connected together to a given word line may be considered a physical page of memory cells. The portion of a physical page of memory cells (which in some embodiments may still be the entire row) that is read during a single read operation or programmed during a single program operation (e.g., an upper or lower page of memory cells) may be considered a logical page of memory cells. A block of memory cells may include those memory cells that are configured to be erased together, such as all memory cells connected to word lines 2020-202. Nare connected (e.g., all NAND strands 206 that share common word lines 202). Unless expressly distinguished, a reference to a page of memory cells herein refers to the memory cells of a logical page of memory cells. A logical page may or may not be identical to a physical page. Although the example of Fig. While 2A is discussed in communication with NAND flash, the embodiments and concepts described in this document are not limited to a specific array architecture or structure and may also include other structures (e.g., SONOS, phase change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0036] Fig.2B is another schematic representation of a section of an array of memory cells 200B, as it can be used in the storage device 130, e.g., as a section of the array of memory cells 104. The equally numbered elements in Fig. 2B correspond to the description as it relates to Fig. 2A was provided. Fig. 2B provides additional details on an example of a three-dimensional NAND memory array design. The three-dimensional NAND memory array 200B can include vertical structures that may enclose semiconductor columns, with a portion of a column serving as the channel region for the memory cells of NAND strands 206. Each NAND strand 206 can be selectively connected to a bit line 2040-204. MNAND strands 206 can be selectively connected to the same bit line 204 by a selection transistor 212 (e.g., these can be drain selection transistors, commonly referred to as select-gate-drain) and to a common source 216 by a selection transistor 210 (e.g., these can be source selection transistors, commonly referred to as select-gate-source). Multiple NAND strands 206 can be selectively connected to the same bit line 204. Subsets of NAND strands 206 can be connected to their respective bit lines 204 by selecting the select lines 2150-215. KThe selection transistors 210 are biased to selectively activate specific selection transistors 212 between a NAND strand 206 and a bit line 204. The selection transistors 210 can be activated by biasing the selection line 214. In some embodiments, each subblock or strand of memory cells has a separate selection line 214 from other subblocks or strands. In some embodiments, a pair of subblocks shares a selection line 214. Each word line 202 can be connected to multiple rows of memory cells of the memory arrangement 200B. Rows of memory cells that are connected to each other by a specific word line 202 can be collectively referred to as tiers.

[0037] The three-dimensional NAND 200B memory array can include multiple stacked layers of memory cells connected using vertical channels, such as semiconductor columns. The number of layers in the three-dimensional NAND 200B memory array can be, for example, 32, 48, 64, 96, 112, or any number of layers. In some examples, a group of layers may be collectively referred to as a deck. A deck in a three-dimensional NAND memory array can be processed together (e.g., etched together to form part of the semiconductor column). A memory device using three-dimensional NAND memory arrays can provide more memory cells on a single chip than a memory device made up of two-dimensional NAND arrays; and therefore, it can provide a higher storage capacity.Furthermore, in a storage device with three-dimensional NAND memory arrangements, transistors in memory cells are spatially separated, and therefore interference and electron leakage can be reduced.

[0038] In some examples, memory cells can be grouped into memory blocks. Fig. Figure 2C shows groupings of NAND strands 206 into blocks of memory cells 250, e.g., blocks of memory cells 2500-250. LBlocks of memory cells 250 can be groupings of memory cells 208 that can be erased together in a single erase operation. The group of memory cells that can be erased together is also called an erase block. Each block of memory cells 250 can represent those NAND strands 206 that are typically associated with a single select line 215, e.g., select line 2150. The common source 216 for the block of memory cells 2500 can be the same source 216 as the source 216 for the block of memory cells 250. L be. For example, each block of memory cells can be 2500-250 L They may be jointly and selectively connected to source 216. Access lines 202 and selection lines 214 and 215 of a block of memory cells 250 cannot be directly connected to access lines 202 or selection lines 214 and 215 of another block of memory cells within blocks of memory cells 2500-250. Lexhibit.

[0039] The bit lines 2040-204 M can be connected (e.g., selectively connected) to a buffer section 240, which can be part of the side buffer 152 of the storage device 130. The buffer section 240 can be connected to a storage level (e.g., the set of blocks of memory cells 2500-250). L ). The buffer section 240 can include sampling circuits (which may include read amplifiers) for sensing data values ​​that are displayed on the respective bit lines 204.

[0040] Fig.Figure 2D is a block diagram of a section of an exemplary array of memory cells 260. The array of memory cells 260 can be used in a storage device 130 like the array of memory cells 104. The array of memory cells 260 is represented with four memory levels 261 (e.g., memory levels 261a-261d). Each of the memory levels 261 can refer to a group of memory blocks of memory cells 250. Each memory level 261 can communicate with a respective buffer section 240, which together can form a side buffer 262. The side buffer 262 can be used to store the data in Fig. to implement the page buffer 152 shown. While four memory levels 261 are shown, other numbers of memory levels 261 can typically communicate with a page buffer 262. Each memory level 261 is shown to hold L+1 blocks of memory cells 250 (e.g., blocks of memory cells 2500-250). Lincludes.

[0041] In some cases, simultaneous operations can be performed on different levels. For example, simultaneous operations can be performed on memory cells within different blocks 250, as long as the different blocks 250 are located in different levels 261. In some cases, a single memory block 250 can be referred to as a physical block, and a virtual block can refer to a group of blocks 250 within which simultaneous operations can occur. For example, simultaneous operations can be performed on four blocks 2500, each located within levels 261a, 261b, 261c, and 261d, and the four blocks 2500 can be collectively referred to as a virtual block. In some cases, a virtual block can include blocks from different storage devices.In some cases, the physical blocks within a virtual block can have the same block address within their respective levels. In some cases, performing concurrent operations in different levels 261 may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different pages that have the same page address within their respective levels 261 (e.g., in connection with instruction decoding, page address decoding circuitry, or other circuitry shared across levels 261).

[0042] In some cases, a block can contain 250 memory cells, organized into rows (pages) and columns (e.g., strings, not shown). For example, memory cells on the same page can share a common word line (e.g., be connected to it), and memory cells on the same string can share a common data line (e.g., be connected to it) (which can alternatively be called a bit line).

[0043] In some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity level (e.g., at a page level, or a section thereof), but erased at a second granularity level (e.g., at a block level). That is, a page can be the smallest unit of memory (e.g., a set of memory cells) that can be programmed or read independently (e.g., programmed or read simultaneously as part of a single program or read operation), and a memory block can be the smallest unit of memory (e.g., a set of memory cells) that can be erased independently (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data.For example, in some cases a page in use can only be updated once the entire block containing the page has been deleted.

[0044] With continued reference to the Fig. 1 and 2A-2C can, during a real erase operation (where the memory cells are actually erased), cause the local controller 135 to cause a common source voltage line, e.g. the SRC 216 ( Fig. 2A), is driven up to a quenching voltage (VERA or Vera) with a quenching pulse, while the selection gates 2100 to 210 M (SGS transistors) are switched on. Ramping up to this high bias clearing voltage and the subsequent recovery from this voltage ramp can take a considerable amount of time. Simultaneously, the local controller 135 can switch the selection gates 2120 to 212. m ( Fig. 2A) switch off so that the drains of selection gates 2120 to 212 mcan float, which results in the bit lines being 2040 to 204 M also float. In addition, the local controller 135 can handle the word lines 202 ( Fig. 2A) to ground, e.g., zero volts, or hold the word lines 202 at a low voltage. This set of voltage levels on the memory array 200A can generate an erase potential that can erase memory cells 2080 to 208. N caused to erase, e.g. by forcing electrons through a body of each memory cell and out of the floating bit lines 2040 to 204 M to exit. In other embodiments, the reverse path can be taken, so that selection gates 2100 to 210 M be switched off, causing the SRC line 216 to float while the voltage of the bit lines on Vera is ramped up, while the selection gates 2120 to 212 Mcan be switched on. As mentioned earlier, in 3D NAND, one of the channel regions, a column, or a bit line can also be driven up in voltage to cause the connected memory cells to be erased. In some embodiments, one or more subblocks, including a physical block, of memory cells are erased during the same actual erase operation. A block of memory cells can generally be understood as comprising four or more subblocks, with each subblock containing a separate set of memory cells.

[0045] With continued reference to Fig.In embodiments 1 and 2A-2C, the array of memory cells 104 can be configured to store data at multiple logical levels. In some embodiments, the local controller 135 can be configured to cause one or more memory cells of the array of memory cells 104 to be programmed to a specific logical level (e.g., a current logical level). Each of the logical levels can correspond to different verification levels used to verify the cell distribution of threshold voltages. An example of the cell distribution across exemplary logical levels is given below with respect to Fig.5 described. As described above, in some embodiments a particular verification level of a lower logical level may be the same as, similar to, or close to another verification level of a higher logical level. An example of verification levels corresponding to different logical levels but being the same as, similar to, or close to each other is given below with respect to Fig. 4 described. These identical or similar verification levels of different logic levels can be used to accurately determine the cell distribution of the threshold voltages without additional time delay.

[0046] In some examples, the local controller 135 is configured to retrieve information about multiple logic levels without changing the verification levels associated with the word line voltage. The local controller 135 can identify multiple logic levels of the array of memory cells 104 that are used to verify the cell distribution of the threshold voltage of a current logic level of the array of memory cells 104. Accordingly, the local controller 135 can instruct the sampling amplifier 140 to select the multiple logic levels of the array of memory cells 104 to verify the current logic level of the array of memory cells 104. When selecting the multiple logic levels, the sampling amplifier 140 selects the multiple verification levels that correspond to the multiple logic levels.

[0047] The bias control circuit 137 can cause the controller 109 to apply the word line voltage (e.g., a bias voltage) to the corresponding word lines 202 at a verification level corresponding to one of the identified logic levels. In some embodiments, the bias control circuit 137 can cause the controller 109 to apply the word line voltage to the corresponding word lines 202 at a verification level corresponding to the lower logic level of the identified logic level. Additionally or alternatively, the bias control circuit 137 can cause the controller 109 to apply data line voltages (e.g., bias voltages) to the corresponding data lines 204 (e.g., bit lines) corresponding to one of the identified logic levels, so that the sampling amplifier 140 can detect the current of the bit lines.

[0048] The memory cells of the array of memory cells 104 along the corresponding word lines 202 can receive the word line voltage at the verification level. Additionally, the memory cells of the array of memory cells 104 along the corresponding data lines 204 can receive the data line voltage. Based on the current logic level of the memory cells, the verification level of the word line voltage, and / or the data line voltage, the array of memory cells 104 can conduct current on the data lines 204. The current is sampled by the sampling amplifier 140.

[0049] The sampling amplifier 140 can be a sampling amplifier register 241 (shown in Fig.2C) and / or circuits (e.g., transistors, amplifiers, current source, etc.) configured to sample the current on the corresponding bit lines 204. In some embodiments, the sampling amplifier 140 may wait a period of time to allow the controller 109 to precharge the corresponding word lines 202 at the corresponding verification levels. Furthermore, the sampling amplifier 140 may wait another period of time to allow a circuit voltage of the sampling amplifier 140 to develop. For example, the sampling amplifier 140 may wait this additional period of time to sample the current on the corresponding bit lines 204 and allow the node voltage at its input node to decrease or drop due to the current on the corresponding bit lines 204.The circuit voltage can include any suitable node voltage within the sampling amplifier 140, which can change depending on whether current flows on the corresponding data lines 204. The circuit voltage can, for example, include a voltage at the collector (Vcc) or an input voltage of the sampling amplifier 140.

[0050] After the corresponding word lines 202 have been pre-charged and the circuit voltage has developed, the sampling amplifier 140 can determine the circuit voltage at various times. These different times correspond to the other verification levels of the identified logic levels. Based on the determined circuit voltage at these different times, information corresponding to several logic levels can be determined, while the regulator 109 applies the word line voltage at a verification level corresponding to a single logic level.In particular, based on the determined circuit voltage of the sampling amplifier at different times, the controller can determine information corresponding to the FPPV voltage and the PV voltage, which correspond to a lower logic level, as well as the SPPV voltage, which corresponds to the higher logic level, while the regulator 109 applies the word line voltage with a verification level corresponding to the lower logic level. An example of an evolving circuit voltage determined (e.g., sampled) at different times, corresponding to verification levels of several logic levels, is given below in relation to [reference missing]. Fig. 3 described.

[0051] Fig.Figure 3 illustrates a graphical representation 300 of a circuit voltage 302 over a specific period during the verification of cell distribution of threshold voltages. In the graphical representation 300, the Y-axis represents a voltage level of the circuit voltage and the X-axis represents time. As described above, the circuit voltage 302 can be a node voltage associated with the sampling amplifier 140 (e.g., an input node voltage). The level of the circuit voltage 302 can change over time due to the current change on the corresponding bit lines of an array of memory cells. In some examples, as in Fig. As shown in Figure 3, the time span includes a preloading section 305, a development section 307 or a scanning section 309.

[0052] During pre-charge phase 305, the local controller 135 applies a word line voltage, corresponding to a lower logic level, to the word lines. During pre-charge phase 305, the word line reaches a pre-configured word line voltage and stabilizes. Allowing the word line voltage to stabilize allows the circuit voltage 302 to stabilize at a stable operating level. As shown in the example, the stable operating level is 2.2 V.

[0053] During development section 307, the circuit voltage 302 may begin to decrease (e.g., be pulled downwards) if the bit lines are conducting current. Furthermore, during development section 307, the circuit voltage 302 may continue to decrease until it reaches a reduced stable operating level (in Fig. (3 not shown). If the bit lines do not conduct current, the circuit voltage 302 must not drop.

[0054] During sampling section 309, the sampling amplifier 140 can determine the circuit voltage 302 at different times 304, 306, and 308. Sampling section 309 is shown to overlap part of development section 307 so that the circuit voltage 302 can be determined at three different times 304, 306, and 308 while the circuit voltage 302 is falling. As shown in Fig. As shown in Figure 3, the circuit voltage 302 determined by the sampling amplifier 140 is 2.0 V at the first time, 1.8 V at the second time and 1.6 V at the third time.

[0055] As described in more detail below, the sampling amplifier 140 can compare the specific circuit voltage 302 at the various times 304, 306 and 308 with corresponding thresholds to determine whether the bit lines are conducting current.

[0056] Back to Fig.In some examples, the sampling amplifier 140 can compare the circuit voltage sampled at different times with the threshold voltages of the memory cells. These threshold voltages are associated with the corresponding verification levels. For example, if the circuit voltages of the sampling amplifier 140 are equal to or less than the corresponding threshold voltages at one or more of the different times, the array of memory cells 104 can conduct current on the bit lines 204 at the corresponding verification levels of the logic level. Conversely, if the circuit voltage is greater than the corresponding threshold voltages at one or more of the different times, the array of memory cells 104 cannot conduct current on the bit lines 204 at the corresponding verification levels of the logic level.

[0057] The sampling amplifier 140 can store information or cause information to be stored. This information indicates whether the array of memory cells 104 conducts current on the bit lines 204 at the corresponding verification levels of the word line voltage. In some embodiments, the sampling amplifier 140 can store information or cause information to be stored as logic 1s or logic 0s in registers 121, the cache register 118, the sampling amplifier register 241, or a combination thereof. For example, the sampling amplifier 140 can store information corresponding to the SPPV voltage of the higher logic level in the sampling amplifier register 241. As another example, the sampling amplifier 140 can cause information corresponding to the FPPV voltage of the lower logic level to be stored in the cache register 118 or an additional register 243 of registers 121.As a further example, the sampling amplifier 140 can cause information corresponding to the FPPV voltage of the lower logic level to be stored in the cache register 118 or the additional register 243.

[0058] In some examples, the local controller 135, in accordance with the stored information, instructs the controller 109 to adjust the bit line voltages for subsequent programming loops to maintain or decrease an amount that the current on the bit lines 204 can change, or to prevent or suppress a change in the current on the bit lines 204. The local controller 135 can, in accordance with the stored information, instruct the controller 109 to adjust the bit line voltages (e.g., increase or decrease the bit line voltages) to initiate a general process, a first speed reduction process, a second speed reduction process, or a lockout process.

[0059] In some embodiments, the controller 109 increases the bit line voltages by a general amount in a general process. Increasing the bit line voltages by a general amount allows the current on the bit lines 204 to be reduced. In the first speed reduction process, the controller 109 increases the bit line voltages by a first speed reduction amount. In some embodiments, the first speed reduction amount is smaller than the general amount. Thus, when using the first speed reduction amount, the current on the bit lines 204 can be reduced less or maintained compared to increasing the bit line voltages by the general amount. In the second speed reduction process, the controller 109 further increases the bit line voltages by a second speed reduction amount.In some embodiments, the second rate reduction amount is larger than the first rate reduction amount. Thus, the current on the bit lines 204 can be further reduced when using the second rate reduction amount compared to the first rate reduction amount. During the lock operation, the controller increases the bit line voltages by an amount that locks the programming of the memory cell array 104. In some embodiments, the overall amount, the first rate reduction amount, the second rate reduction amount, or the amount for locking the array of memory cells 104 can be based on predefined fuse trim values ​​of the memory device 130. It is understood that the magnitude of the changes applied to the bit line voltages can be configured in any desired way and is not limited to the possibilities described above.

[0060] In other embodiments, the controller 109 reduces the bit line voltages by a general amount in a general process. Reducing the bit line voltages by a general amount allows the current on the bit lines 204 to be reduced. In the first speed reduction process, the controller 109 reduces the bit line voltages by a first speed reduction amount. In some embodiments, the first speed reduction amount is smaller than the general amount. Thus, when using the first speed reduction amount, the current on the bit lines 204 can be reduced less or maintained compared to reducing the bit line voltages by the general amount. In the second speed reduction process, the controller 109 further reduces the bit line voltages by a second speed reduction amount.In some embodiments, the second rate reduction amount is larger than the first rate reduction amount. Thus, the current on the bit lines 204 can be further reduced when using the second rate reduction amount compared to the first rate reduction amount. During the lock operation, the controller reduces the bit line voltages by an amount that locks the programming of the memory cell array 104. In some embodiments, the overall amount, the first rate reduction amount, the second rate reduction amount, or the amount for locking the array of memory cells 104 can be based on predefined fuse trim values ​​of the memory device 130. It is understood that the magnitude of the changes applied to the bit line voltages can be configured in any desired way and is not limited to the possibilities described above.

[0061] As described above, in a storage device, a specific logic level can correspond to several word line voltage verification levels. The respective word line voltage level can influence the bit line currents of the memory cells connected to that word line. Additionally, the bit line voltage can be adjusted according to the procedure described above to control the influence of the word line voltage on the bit line currents. Verification of the memory cell threshold voltages is performed by measuring the circuit voltages as a function of the bit line currents. Two different logic levels can be selected for verifying the cell threshold voltage distribution. As described above, they can correspond to the same or a similar verification level.

[0062] Fig.Figure 4 illustrates a graphical representation 400 of example cell distributions 402, 404, and 405 and example verification levels 410a-b and 411a-c, which correspond to different logical levels. In graphical representation 400, the Y-axis represents the number of cells in the memory array and the X-axis represents the threshold voltage. Fig. 4 corresponds to example verification level 410a 1.3 V and example verification level 410b 1.45 V. Furthermore, in Fig. 4. Example verification level 411a corresponds to 1.5 V, example verification level 411b to 1.7 V, and example verification level 411c to 2.0 V.

[0063] As in Fig.As shown in Figure 4, cell distribution 404 represents a verified distribution of a threshold voltage corresponding to a first logic level. Cell distribution 402 represents an unverified distribution of a threshold voltage corresponding to a first logic level and a second logic level. Cell distribution 405 further represents a verified distribution of a threshold voltage corresponding to a second logic level. In the example shown, cell distribution 402 covers a range between 1.1 V and 2.05 V, cell distribution 405 covers a range between 1.9 V and 2.3 V, and cell distribution 404 covers a range between 1.4 V and 1.8 V.

[0064] As in Fig.As shown in Figure 4, cell distribution 402 covers a larger area than cell distribution 405 because no threshold verification was performed to reduce the area of ​​cell distribution 405. Furthermore, in this example, cell distribution 402 completely overlaps with cell distribution 404, which corresponds to the first logical level. The overlap of cell distributions 402 and 404 can lead to errors when attempting to read data, store data, or both, if cell distribution 402 is not verified.

[0065] To reduce the risk of errors when attempting to read data, store data, or both, threshold verification can be performed using multiple verification levels 410a-b and 411a-c or additional verification levels in accordance with the methods described in this disclosure. For example, the sampling amplifier 140 can determine the circuit voltage (e.g., an input node voltage) at various time points corresponding to at least verification levels 410b and 411a, while the local controller 135 causes a single word line voltage corresponding to the first logic level to be applied to reduce the width of the cell distribution 402, resulting in the cell distribution 404.

[0066] In this in Fig.In the example shown, the difference between verification levels 410a-b and 411a (e.g., a difference between three verification levels corresponding to two logical levels) can be smaller than the difference between verification levels 411a-c (e.g., a difference between three verification levels corresponding to a single logical level). As shown, the difference between verification levels 410a-b and 411a is approximately 0.2V (e.g., 1.5V - 1.3V = 0.2V), while the difference between verification levels 411a-c is approximately 0.5V (e.g., 2.0V - 1.5V = 0.5V).

[0067] Since the difference between verification levels 410a-b and 411a is sufficiently small, the difference in circuit voltages at corresponding multiple time points caused by the different verification levels 410a-b and 411a lies within the sampling range capability of the sampling amplifier 140. This allows the sampling amplifier 140 to determine the circuit voltage at various time points corresponding to all three verification levels 410a-b and 411a, while the local controller 135 applies a single word line voltage. Therefore, the sampling amplifier 140 can sample the circuit voltage at multiple time points corresponding to the three verification levels 410a-b and 411a, while the local controller 135 applies a single word line voltage, corresponding to the first logic level, to the array of memory cells.Verification efficiency is improved without requiring the sampling amplifier to have a large sampling range capability.

[0068] In Fig. Verification level 410a corresponds to the PPV voltage of the first logical level, and verification level 410b corresponds to the PV voltage of the first logical level. Fig. Verification level 411a corresponds to the SPPV voltage of the second logical level, verification level 411b corresponds to the PPV voltage of the second logical level, and verification level 411c corresponds to the PV voltage of the second logical level. The technologies disclosed in this document enable sampling at multiple verification levels corresponding to multiple logical levels, thereby significantly improving efficiency while maintaining or improving sampling accuracy.

[0069] The technologies of sampling at multiple verification levels, corresponding to multiple logical levels, are described in more detail using Table 1, which contains an example of verifying the threshold voltages of the array of memory cells 104 when configured to be programmed according to Table 1. Table 1 Logical level deletion Logical Level 1 Logical Level 2 Logical Level 3 Logical Level 4 Logical level 5 Logical level 6 Logical level 7 Cell 1 1 1 1 0 0 0 0 1 Cell 2 1 1 0 0 1 1 0 0 Cell 3 1 0 0 0 0 1 1 1

[0070] Referring to Table 1, a controller (e.g., local controller 135) can, for example, identify logical level 1 and logical level 2, which are used to verify the cell distribution of the threshold voltage of the current logical level of the array of memory cells 104. Similar to the above in Fig.As shown in Figure 4, logic level 1 can include an SPPV voltage at a first level, an FPPV voltage at a second level, and a PV voltage at a third level. Additionally, logic level 2 can include an SPPV voltage at a fourth level, an FPPV voltage at a fifth level, and a PV voltage at a sixth level. In this example, the third level of the PV voltage of logic level 1 can be equal to, similar to, or close to the fourth level of the SPPV voltage of logic level 2. That is, the PV voltage of logic level 1 can be equal to or similar to the SPPV voltage of logic level 2 (similar to how level 410b is close to level 411a in Figure 4). Fig. 4 shown).

[0071] During the verification process for the identified logic levels 1 and 2, the controller 109 can apply a word line voltage to the word lines 202 at the third level (e.g., the PV voltage) of logic level 1. In some embodiments, the controller 109 can change the data line voltages of the data lines 204 between levels corresponding to logic level 1 or logic level 2. The sampling amplifier 140 can determine its circuit voltage at the first time point, which corresponds to the PV voltage of logic level 1. The sampling amplifier 140 can also determine its circuit voltage at the second time point, which corresponds to the FPPV voltage of logic level 1. Furthermore, the sampling amplifier 140 can determine the circuit voltage of the sampling amplifier 140 at the third time point, which corresponds to the SPPV voltage of logic level 2.As described above, the SPPV voltage of logic level 2 can be equal to or similar to the PV voltage of logic level 1.

[0072] The sampling amplifier 140 can compare the circuit voltage at the first time point with a first threshold voltage corresponding to the FPPV voltage of logic level 1 to determine whether specific memory cells in the array of memory cells 104 conduct current at the FPPV voltage. The sampling amplifier 140 can additionally compare the circuit voltage at the second time point with a second threshold voltage corresponding to the PV voltage of logic level 1 to determine whether the specific memory cells conduct current at the PV voltage. The sampling amplifier 140 can further compare the circuit voltage at the third time point with a third threshold voltage corresponding to the SPPV voltage of logic level 2 to determine whether the array of memory cells 104 conducts current at the SPPV voltage.

[0073] The sampling amplifier 140 can store information about whether the specific memory cells conduct current on the bit lines 204 at the FPPV voltage and the PV voltage of logic level 1 and the SPPV voltage of logic level 2 in registers 121, the cache register 118, the sampling amplifier register 241, or a combination thereof (generally referred to in this disclosure as information registers). For example, if the sampling amplifier 140 determines that the relevant memory cells on the bit lines 204 conduct current at the FPPV voltage, the PV voltage, or the SPPV voltage, the sampling amplifier 140 can store a logical 0 in a corresponding register.Alternatively, if the sampling amplifier 140 determines that the array of memory cells 104 on the bit lines 204 does not conduct current at the FPPV voltage, the PV voltage or the SPPV voltage, the sampling amplifier 140 can store a logical 1 in the corresponding register.

[0074] Examples of storing information about whether the memory cells conduct current on bit lines 204 for the verification levels corresponding to logical level 1 are now discussed. If the memory cells in question conduct current on bit lines 204 at the SPPV voltage, the FPPV voltage, and the PV voltage corresponding to logical level 1, the sampling amplifier 140 can store a logical sequence of "000" in the information registers. If the memory cells conduct current on bit lines 204 at the FPPV voltage and the PV voltage corresponding to logical level 1, but do not conduct current at the SPPV voltage corresponding to logical level 1, the sampling amplifier 140 can store a logical sequence of "100" in the information registers.If the memory cells on bit lines 204 conduct current at the PV voltage, corresponding to logic level 1, but do not conduct current at the SPPV and FPPV voltages, which also correspond to logic level 1, the sampling amplifier 140 can store a logic sequence of "110" in the information registers. If the memory cells on bit lines 204 do not conduct current at the SPPV, FPPV, and PV voltages, which also correspond to logic level 1, the sampling amplifier 140 can store a logic sequence of "111" in the information registers.

[0075] To return to the example of verifying the threshold voltages of the array of memory cells 104 when configured to be programmed according to Table 1, the local controller 135 can, in accordance with the stored information, cause the controller 109 to adjust the bit line voltages applied to the bit lines 204 for a subsequent programming loop in order to capture remaining information corresponding to logical level 2 and information corresponding to logical level 3 (e.g., information for a subsequent programming loop).As discussed above, the local controller 135 can, in accordance with the information stored in the information registers, cause the controller 109 to adjust the bit line voltages of the bit line 204 to cause the occurrence of the first speed reduction process, the occurrence of the second speed reduction process, the occurrence of the general process, or the lock process when the information for the subsequent programming loop is captured.

[0076] In some cases, if the stored information indicates that current is being conducted at the SPPV voltage, the FPPV voltage, and the PV voltage corresponding to logic level 1, the local controller 135 can instruct the controller 109 to adjust the bit line voltages to trigger the lock operation and prevent the memory cells from being programmed for subsequent programming loops. In other cases, if the stored information indicates that current is being conducted at the FPPV voltage and the PV voltage, but not the SPPV voltage corresponding to logic level 1, the local controller 135 can instruct the controller 109 to adjust the bit line voltages by the first value to trigger the first speed reduction process and control the current in the bit lines for subsequent programming loops.In other cases, if the stored information indicates that current is being conducted at the PV voltage, but not at the FPPV and SPPV voltages corresponding to logic level 1, the local controller 135 can instruct the controller 109 to set the bit line voltages by the second amount to trigger the second speed reduction process and control the current in the bit lines for subsequent programming loops. In some cases, if the stored information indicates that current is not being conducted at the SPPV, FPPV, and PV voltages corresponding to logic level 1, the local controller 135 can instruct the controller 109 to set the bit line voltages by the general amount to trigger the general process and control the current in the bit lines for subsequent programming loops.

[0077] The local controller 135, the regulator 109, and the sampling amplifier 140 can repeat the process described above with respect to logic levels 1 and 2, but instead, with respect to FPPV voltage and PV voltage, they can use logic levels 2 and SPPV voltage, respectively. Furthermore, the local controller 135, the regulator, and the sampling amplifier 140 can repeat the process described above to capture information relating to each of the logic levels from 3 to 7. In this way, the cell distribution of the memory cells can be verified.

[0078] Fig.Figure 5 illustrates a graphical representation 500 of cell distributions 502a-h of exemplary logical levels 504a-h of three cells of an array of memory cells in accordance with the examples disclosed in this document. In graphical representation 500, the Y-axis represents the number of cells in the memory array (e.g., three cells in the example of Fig. 5) and the X-axis represents the threshold voltage.

[0079] Each of the cell distributions 502a-h can correspond to one of the logical levels 504a-h. For example, cell distribution 502a corresponds to logical level 504a, which represents a logical sequence of "111" stored in the cells of the array of memory cells. As another example, cell distribution 502e corresponds to logical level 504e, which represents a logical sequence of "010" stored in the cells of the array of memory cells.

[0080] As the number of cells in the array of memory cells increases, the distances or gaps between the cell distributions 502a-h can become smaller. An example of a distance is shown by the arrow 501 in Fig. Figure 5 illustrates this. If the margins are not present (e.g., if two or more of the cell distributions 502a-h overlap), errors may occur when reading data, writing data, or both in the array of memory cells. To reduce the probability of errors when reading data, writing data, or both, the cell distributions 502a-h can be verified using the threshold voltage verification procedure described above to decrease the width of the cell distributions 502a-h and increase the margins. An example of the width of cell distribution 502b is shown by arrow 503 in Figure 5. Fig.5 shown. For example, the local controller 135, the sampling amplifier 140 or a combination thereof can verify the cell distributions of the cells of the array of memory cells using the methods described in the present disclosure in order to decrease the width of the cell distributions, increase the distance between the cell distributions or both.

[0081] It is understood that various systems, devices, and procedures described in this document can be implemented using analog and / or digital circuits or using one or more computers with known computer processors, memory systems, storage devices, computer software, and other components. Typically, a computer includes a processor for executing instructions and one or more memory systems for storing instructions and data. A computer may also include or be coupled with one or more mass storage devices, such as one or more magnetic disks, internal hard disks and removable disks, magneto-optical disks, optical disks, etc.

[0082] Various systems, devices, and procedures described herein can be implemented using computers operating in a client-server relationship. Typically, in such a system, the client computers are located remotely from the server computers and interact over a network. The client-server relationship can be defined and controlled by computer programs running on the respective client and server computers. Examples of client computers include desktop computers, workstations, laptops, smartphones, tablets, or other types of data processing devices.

[0083] Various systems, devices, and procedures described in this document can be implemented using a computer program product tangibly embodied in an information carrier, e.g., in a non-transient machine-readable storage device, for execution by a programmable processor; and the procedures and steps described in this document, including one or more of the steps of at least some of the Fig.1-2D systems can be implemented using one or more computer programs executable by such a processor. A computer program is a set of computer program instructions that can be used directly or indirectly in a computer to perform a specific activity or produce a specific result. A computer program can be written in any programming language, including compiled or interpreted languages, and it can be provided in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computer environment.

[0084] Fig.Figure 6 illustrates a flowchart showing Method 600, which supports techniques for voltage threshold verification using multi-level sampling of a memory cell in accordance with the examples disclosed in this document. At least some of the blocks in Method 600 can be performed by a sampling amplifier (e.g., Sampling Amplifier 140) during the verification of a memory cell threshold voltage. In block 602, the sampling amplifier detects a current on a bit line (e.g., bit lines 204) associated with a memory cell (e.g., array of memory cells 104) within a storage device (e.g., storage device 130). The current can be based on a word line voltage and a current logic level of the memory cell. The word line voltage can be applied by a controller (e.g., Controller 109) to word lines connected to the memory cell.In block 604, the sampling amplifier determines a circuit voltage within the memory device. This circuit voltage can be based on the current of the bit line connected to the memory cell at a first time point. The first time point can correspond to a PV voltage of a first logic level of the memory cell. In block 606, the sampling amplifier determines its circuit voltage based on the current of the bit line connected to the memory cell at a second time point. The second time point can correspond to a SPPV voltage of a second logic level of the memory cell.

[0085] Procedure 600 can contain additional blocks that are in Fig.Figure 6 is not shown. For example, method 600 may include a different block in which the sampling amplifier determines the sampling amplifier circuit voltage based on the current of the bit line connected to the memory cell at a third time point. The third time point may correspond to an FPPV voltage of the first logic level of the memory cell.

[0086] Embodiments of devices, systems and methods according to the disclosure are set forth below: Design 1. A storage device comprising: a memory cell connected to a word line, the word line being configured to receive a word line voltage corresponding to a first logical level of the memory cell; and a side buffer connected to a bit line assigned to the memory cell, the side buffer comprising a sampling amplifier configured to: Sampling a current of the bit line assigned to the memory cell, wherein the current is based on the word line voltage and a current logical level of the memory cell; Determining a circuit voltage of the sampling amplifier based on the current of the bit line assigned to the memory cell at a first time point, where the first time point corresponds to a program verification (PV) voltage of the first logic level of the memory cell; and Determining the circuit voltage of the sampling amplifier based on the current of the bit line assigned to the memory cell at a second time point, where the second time point corresponds to a second preprogram verification (SPPV) voltage of a second logical level of the memory cell. Embodiment 2. The storage device according to embodiment 1, wherein the sampling amplifier is configured to determine the circuit voltage of the sampling amplifier based on the current of the bit line assigned to the memory cell at a third time point, wherein the third time point corresponds to a first preprogram verification (FPPV) voltage of the first logical level of the memory cell. Embodiment 3. The storage device according to embodiment 2, wherein: the word line voltage includes a first word line voltage; the storage device includes a local controller configured to cause a second word line voltage to be applied to the word line associated with the memory cell, the second word line voltage corresponding to the second logic level; and the sampling amplifier is configured to: Sampling the current of the bit line assigned to the memory cell, where the current is based on the second word line voltage and the current logical level of the memory cell; Determining the circuit voltage of the sampling amplifier based on the current of the bit line assigned to the memory cell at a fourth time point, where the fourth time point corresponds to an FPPV voltage of the second logic level of the memory cell; Determining the circuit voltage of the sampling amplifier based on the current of the bit line assigned to the memory cell at a fifth time point, where the fifth time point corresponds to a PV voltage of the second logic level of the memory cell; and Determining the circuit voltage of the sampling amplifier based on the current of the bit line assigned to the memory cell at a sixth time point, where the sixth time point corresponds to a second SPPV voltage of a third logical level of the memory cell. Embodiment 4. The storage device according to one of embodiments 2-3, wherein the sampling amplifier is configured to: Comparing the circuit voltage at the first time point with a first threshold voltage, where the first threshold voltage corresponds to the PV voltage of the first logic level; Comparing the circuit voltage at the second time point with a second threshold voltage, where the second threshold voltage corresponds to the SPPV voltage of the second logic level; and Comparing the circuit voltage at the third time point with a third threshold voltage, where the third threshold voltage corresponds to the FPPV voltage of the first logic level. Embodiment 5. The storage device according to embodiment 4, wherein: that the circuit voltage at the first time is less than or equal to the first threshold voltage indicates that the first logic level is the current logic level of the memory cell and that a blocking operation is to be performed; that the circuit voltage at the second time point is less than or equal to the second threshold voltage indicates that a general process to verify the current logic level of the memory cell should be carried out; The fact that the circuit voltage at the second time point is greater than the second threshold voltage indicates that a first rate reduction process should be carried out to verify the current logic level of the memory cell; and The fact that the circuit voltage at the third time point is less than or equal to the third threshold voltage indicates that a second speed reduction process should be carried out to verify the current logic level of the memory cell. Embodiment 6. The storage device according to embodiment 5, wherein the storage device comprises a local controller configured to: To cause the locking process to be carried out to include reducing a bit line voltage applied to the bit line in order to prevent the memory cell from being programmed; To initiate the general process which involves reducing the bit line voltage by a general amount; Causing the first velocity reduction process to be carried out, which includes reducing the bit line voltage by a first velocity reduction amount, where the first velocity reduction amount is less than the general amount; and Causing the second speed reduction process to be carried out, which includes reducing the bit line voltage by a second speed reduction amount, where the second speed reduction amount is smaller than the first speed reduction amount. Embodiment 7. The storage device according to embodiment 6, wherein the current passed through the storage cell is based on the bit line voltage. Embodiment 8. The storage device according to one of embodiments 4-7, wherein: the side buffer includes a sampling amplifier register, a cache register, and an additional register; and the sampling amplifier is configured to: Storing information corresponding to the SPPV voltage in the sampling amplifier register; To ensure that information corresponding to the FPPV voltage is stored in at least one of the cache registers or the additional register; and To ensure that information corresponding to the PV voltage is stored in at least one of the cache registers or the additional register. Embodiment 9. The storage device according to one of embodiments 1-8, wherein: the memory cell is configured to store data at a variety of logical levels; and The storage device includes a local controller configured to cause the sampling amplifier to select the first logical level and the second logical level from the multitude of logical levels to verify the current logical level of the memory cell. Embodiment 10. The storage device according to one of embodiments 1-8, wherein: the storage device comprises a local controller and a regulator, the regulator being connected to the memory cell via the word line; the local controller is configured to cause the regulator to apply the word line voltage at a voltage level corresponding to the first logic level; and The circuit voltage is determined at the second time point to allow information corresponding to the SPPV voltage of the second logic level to be determined using the word line voltage at the voltage level corresponding to the first logic level. Embodiment 11. The storage device according to embodiment 10, wherein the local controller is configured to cause the memory cell to be programmed at the current logical level. Embodiment 12. The storage device according to one of embodiments 1-8, wherein the circuit voltage of the side buffer comprises a voltage at a collector (Vcc) of the side buffer. Embodiment 13. The storage device according to one of embodiments 1-8, wherein the second logical level comprises a larger logical level than the first logical level. Embodiment 14. A storage device comprising: a word line configured to receive a word line voltage corresponding to a first logical level of a plurality of memory cells; a multitude of bit lines; where the multitude of memory cells are electrically connected to the word line and the multitude of bit lines; a regulator that is electrically connected to the word line and configured to apply the word line voltage; and a side buffer electrically connected to the plurality of memory cells via the plurality of bit lines, the side buffer comprising a sampling amplifier configured to: Sampling a stream of the multitude of bit lines, wherein the stream is based on the word line voltage and a current logical level of the multitude of memory cells; Determining a circuit voltage of the sampling amplifier based on the current of the plurality of bit lines at a first time point, where the first time point corresponds to a first preprogram verification (FPPV) voltage of the first logical level of the plurality of memory cells; Determining the circuit voltage of the sampling amplifier based on the current of the plurality of bit lines at a second time point, where the second time point corresponds to a program verification (PV) voltage of the first logic level of the plurality of memory cells; and Determining the circuit voltage of the sampling amplifier based on the current of the plurality of bit lines at a third time point, where the third time point corresponds to a second preprogram verification (SPPV) voltage of a second logical level of the plurality of memory cells. Embodiment 15. The storage device according to claim 14, wherein: the word line voltage includes a first word line voltage; the storage device includes a local controller configured to cause the controller to apply a second word line voltage to the word line, the second word line voltage corresponding to the second logic level; and the sampling amplifier is configured to: Sampling the current of the multitude of bit lines, where the current is based on the second word line voltage and the current logical level of the multitude of memory cells; Determining the circuit voltage of the sampling amplifier based on the current of the plurality of bit lines at a fourth time point, where the fourth time point corresponds to an FPPV voltage of the second logic level of the plurality of memory cells; Determining the circuit voltage of the sampling amplifier based on the current of the plurality of bit lines at a fifth time point, where the fifth time point corresponds to a PV voltage of the second logic level of the plurality of memory cells; and Determining the circuit voltage of the sampling amplifier based on the current of the plurality of bit lines at a sixth time point, where the sixth time point corresponds to an SPPV voltage of a third logical level of the plurality of memory cells. Embodiment 16. The storage device according to one of embodiments 14-15, wherein the sampling amplifier is configured to: Comparing the circuit voltage at the first time point with a first threshold voltage, where the first threshold voltage corresponds to the FPPV voltage of the first logic level; Comparing the circuit voltage at the second time point with a second threshold voltage, where the second threshold voltage corresponds to the PV voltage of the first logic level; and Comparing the circuit voltage at the third time point with a third threshold voltage, where the third threshold voltage corresponds to the SPPV voltage of the second logic level. Embodiment 17. The storage device according to embodiment 16, wherein: The fact that the circuit voltage at the first time point is less than or equal to the first threshold voltage indicates that an initial speed reduction process should be carried out to verify the current logical level of the multitude of memory cells; that the circuit voltage at the second time point is less than or equal to the second threshold voltage indicates that the first logic level is the current logic level of the multitude of memory cells and that a blocking operation is to be performed; that the circuit voltage at the third time point is less than or equal to the third threshold voltage indicates that a general process for verifying the current logic level of the multitude of memory cells should be carried out; and The fact that the circuit voltage at the third time point is greater than the second threshold voltage indicates that a second speed reduction process should be carried out to verify the current logic level of the multitude of memory cells. Embodiment 18. The storage device according to embodiment 17, wherein the storage device comprises a local controller configured to: To cause the locking process to be carried out to include reducing a multitude of bit line voltages applied to the multitude of bit lines in order to prevent the multitude of memory cells from being programmed; To initiate the general process which involves reducing the multitude of bit line voltages by a general amount; Causing the first velocity reduction process to be carried out, which includes reducing the plurality of bit line voltages by a first velocity reduction amount, wherein the first velocity reduction amount is less than the general amount; and Causing the second speed reduction process to be carried out, which involves reducing the plurality of bit line voltages by a second speed reduction amount, where the second speed reduction amount is greater than the first speed reduction amount. Embodiment 19. The storage device according to embodiment 18, wherein the current conducted by the plurality of memory cells is based on the plurality of bit line voltages applied to the plurality of bit lines: Embodiment 20. The storage device according to one of claims 14-19, wherein: the side buffer includes a sampling amplifier register, a cache register, and an additional register; and the sampling amplifier is configured to: Storing information corresponding to the SPPV voltage in the sampling amplifier register; To ensure that information corresponding to the FPPV voltage is stored in at least one of the cache registers or the additional register; and To ensure that information corresponding to the PV voltage is stored in at least one of the cache registers or the additional register. Embodiment 21. The storage device according to one of embodiments 14-20, wherein: the storage device includes a local controller configured to cause the regulator to apply the word line voltage at a voltage level corresponding to the first logic level; and The circuit voltage is determined at the third time point to allow information corresponding to the SPPV voltage of the second logic level to be determined using the voltage level corresponding to the first logic level. Embodiment 22. A method comprising the following: Sampling a current of a bit line assigned to a memory cell within a storage device, wherein the current is based on a word line voltage and a current logical level of the memory cell; Determining a circuit voltage of the sampling amplifier within the storage device using the circuit voltage based on the current of the bit line assigned to the memory cell at a first time point, where the first time point corresponds to a program verification (PV) voltage of a first logic level of the memory cell; and Determining the circuit voltage of the sampling amplifier based on the current of the bit line assigned to the memory cell at a second time point, where the second time point corresponds to a second preprogram verification (SPPV) voltage of a second logical level of the memory cell. Embodiment 23. The method according to embodiment 22, further comprising determining the circuit voltage of the sampling amplifier on the basis of the current of the bit line assigned to the memory cell at a third time point, wherein the third time point corresponds to a first preprogram verification (FPPV) voltage of the first logical level of the memory cell. Embodiment 24. The method according to embodiment 23, wherein: the word line voltage includes a first word line voltage; the procedure further includes the following: To cause a second word line voltage to be applied to the memory cell, the second word line voltage corresponding to the second logical level; and Sampling the current of the bit line assigned to the memory cell, where the current is based on the second word line voltage and the current logical level of the memory cell; Determining the circuit voltage of the sampling amplifier based on the current of the bit line assigned to the memory cell at a fourth time point, where the fourth time point corresponds to an FPPV voltage of the second logic level of the memory cell; Determining the circuit voltage of the sampling amplifier based on the current of the bit line assigned to the memory cell at a fifth time point, where the fifth time point corresponds to a PV voltage of the second logic level of the memory cell; and Determining the circuit voltage of the sampling amplifier based on the current of the bit line assigned to the memory cell at a sixth time point, where the sixth time point corresponds to a second SPPV voltage of a third logical level of the memory cell. Embodiment 25. The method according to one of embodiments 23-24, further comprising: Comparing the circuit voltage at the first time point with a first threshold voltage, where the first threshold voltage corresponds to the PV voltage of the first logic level; Comparing the circuit voltage at the second time point with a second threshold voltage, where the second threshold voltage corresponds to the SPPV voltage of the second logic level; and Comparing the circuit voltage at the third time point with a third threshold voltage, where the third threshold voltage corresponds to the FPPV voltage of the first logic level. Embodiment 26. The method according to embodiment 25, wherein: in accordance with the circuit voltage at the first time, which is less than or equal to the first threshold voltage, the method further comprises causing a bit line voltage applied to the memory cell to be reduced in order to prevent the memory cell from being programmed; in accordance with the circuit voltage at the second time, which is less than or equal to the second threshold voltage, the method further includes causing the bit line voltage to be reduced by a general amount; in accordance with the circuit voltage at the second time point, which is greater than the second threshold voltage, the method further comprises causing the bit line voltage to be reduced by a speed reduction amount; and In accordance with the circuit voltage at the third time, which is less than or equal to the third threshold voltage, the method further comprises causing the bit line voltage to be reduced by a second speed reduction amount, wherein the second speed reduction amount is less than the first speed reduction amount. Embodiment 27. The method according to one of embodiments 25-26, further comprising: Storing information corresponding to the SPPV voltage in a sampling amplifier register; Storing information corresponding to the FPPV voltage in at least one cache register or additional register; and Storing information corresponding to the PV voltage in at least one of the cache registers or the additional register.

[0087] It should be noted that the described techniques include possible implementations, and that the operations and blocks can be regrouped, rearranged, or otherwise modified, and that other implementations are possible. Furthermore, parts of two or more of the methods can be combined.

[0088] The information and signals described herein can be represented using any of a wide variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols referenced in the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings may depict signals as a single signal; however, the signal may also represent a bus of signals, the bus being capable of having a variety of bit widths.

[0089] The terms "electronic communication," "conductive contact," "connected," and "coupled" can refer to a relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) when there is a conductive path between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact, connected, or coupled) can be an open circuit or a closed circuit, depending on the operation of the device that includes the connected components.The conductive path between connected components can be a direct conductive path between the components themselves, or it can be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components can be interrupted for a period of time, for example, by using one or more intermediate components such as switches or transistors.

[0090] The term "coupling" (e.g., "electrical coupling") can refer to a transitional state from an open-circuit relationship between components, in which signals cannot currently be communicated via a conductive path between the components, to a closed-circuit relationship between components, in which signals can be communicated via the conductive path between the components. When a component, such as a controller, couples other components, the component initiates a change that allows signals to flow between the other components via a conductive path that previously did not permit signal flow.

[0091] The term "isolated" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other when there is an open circuit between them. For example, two components separated by a switch positioned between them are isolated when the switch is open. When a controller isolates two components, it causes a change that prevents signals from flowing between them using a conductive path that previously allowed signal flow.

[0092] The terms "if", "when", "based on", or "at least partially based on" can be used interchangeably. In some examples, when the terms "if", "when", "based on", or "at least partially based on" are used to describe a conditional action, a conditional process, or a connection between parts of a process, the terms can be used interchangeably.

[0093] The term "in response to" can refer to a condition or action occurring at least partially, if not entirely, as a result of a previous condition or action. For example, a first condition or action may be performed, and a second condition or action may occur at least partially as a result of the occurrence of the previous condition or action (whether directly after it or after one or more other intermediate conditions or actions have occurred following the first condition or action).

[0094] The devices discussed herein, including a memory arrangement, may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or epitaxial layers of semiconductor materials on another substrate. The conductivity of the substrate or of subregions of the substrate may be controlled by doping using various chemical species, including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other dopant.

[0095] A switching component or transistor discussed herein may be a field-effect transistor (FET) and comprise a three-terminal device consisting of a source, a drain, and a gate. The terminals may be connected to other electronic elements by conductive materials, such as metals. The source and drain may be conductive and may comprise a heavily doped, such as degenerate, semiconductor region. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. The channel conductivity may be controlled by applying a voltage to the gate.For example, applying a positive or negative voltage to an n-type or p-type FET can cause the channel to become conductive. A transistor can be "on" or "enabled" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. The transistor can be "off" or "disabled" if a voltage less than the transistor's threshold voltage is applied to the transistor gate.

[0096] The description contained in this document, in conjunction with the accompanying drawings, describes example configurations and does not represent all examples that can be implemented or that fall within the scope of the claims. The term "exemplary" as used in this document means "serving as an example, case, or illustration" and not "preferred" or "advantageous over other examples." The detailed description includes specific details to facilitate an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, known designs and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0097] In the accompanying figures, similar components or features may share the same reference symbol. Furthermore, different components of the same type may be distinguished by following the reference symbol with a hyphen and a second symbol that differentiates between the similar components. If only the first reference symbol is used in the description, the description applies to any of the similar components that share the same first reference symbol, regardless of the second reference symbol.

[0098] The functions described in this document can be implemented in hardware, in software executed by a processor, in firmware, or in a combination thereof. If implemented in software executed by a processor, the functions can be stored on a computer-readable medium or transferred to it as one or more instructions or as code. Other examples and implementations are within the scope of the disclosure and the appended claims. For example, due to the nature of software, the described functions can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations thereof. Features implementing functions can also be physically located in different positions, including a distribution such that sections of functions are implemented at different physical locations.

[0099] As used in this document, including in the claims, "or" in a list of elements (e.g., in a list of elements preceded by a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that, for example, a list of at least one of A, B, or CA, or B or C, or AB or AC, or BC or ABC (i.e., A and B and C) means A and B and C. The expression "based on" used in this document is not to be interpreted as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without exceeding the scope of this disclosure. In other words, as used herein, the phrase "based on" is to be interpreted in the same way as the phrase "at least partially based on".

[0100] The description herein is provided to enable a person skilled in the art to manufacture or use the disclosure. Various modifications to the disclosure will be obvious to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the examples and designs described herein but is intended to have the widest possible scope consistent with the principles and new features disclosed herein. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 717,802

[0001] US 19 / 363,557

[0001]

Claims

[1] Storage device comprising the following: a memory cell connected to a word line, the word line being configured to receive a word line voltage corresponding to a first logical level of the memory cell; and a side buffer connected to a bit line assigned to the memory cell, the side buffer comprising a sampling amplifier configured to: Sampling a current of the bit line assigned to the memory cell, wherein the current is based on the word line voltage and a current logical level of the memory cell; Determining a circuit voltage of the sampling amplifier based on the current of the bit line assigned to the memory cell at a first time point, where the first time point corresponds to a program verification (PV) voltage of the first logic level of the memory cell; and Determining the circuit voltage of the sampling amplifier based on the current of the bit line assigned to the memory cell at a second time point, where the second time point corresponds to a second preprogram verification (SPPV) voltage of a second logical level of the memory cell. [2] Storage device according to claim 1, wherein the sampling amplifier is configured to determine the circuit voltage of the sampling amplifier based on the current of the bit line associated with the memory cell at a third time point, wherein the third time point corresponds to a first preprogram verification (FPPV) voltage of the first logical level of the memory cell. [3] Storage device according to claim 2, wherein: the word line voltage includes a first word line voltage; the storage device includes a local controller configured to cause a second word line voltage to be applied to the word line associated with the memory cell, the second word line voltage corresponding to the second logical level; and the sampling amplifier is configured to: Sampling the current of the bit line assigned to the memory cell, where the current is based on the second word line voltage and the current logical level of the memory cell; Determining the circuit voltage of the sampling amplifier based on the current of the bit line assigned to the memory cell at a fourth time point, where the fourth time point corresponds to an FPPV voltage of the second logic level of the memory cell; Determining the circuit voltage of the sampling amplifier based on the current of the bit line assigned to the memory cell at a fifth time point, where the fifth time point corresponds to a PV voltage of the second logic level of the memory cell; and Determining the circuit voltage of the sampling amplifier based on the current of the bit line assigned to the memory cell at a sixth time point, where the sixth time point corresponds to an SPPV voltage of a third logical level of the memory cell. [4] Storage device according to one of claims 2-3, wherein the sampling amplifier is configured to: Comparing the circuit voltage at the first time point with a first threshold voltage, where the first threshold voltage corresponds to the PV voltage of the first logic level; Comparing the circuit voltage at the second time point with a second threshold voltage, where the second threshold voltage corresponds to the SPPV voltage of the second logic level; and Comparing the circuit voltage at the third time point with a third threshold voltage, where the third threshold voltage corresponds to the FPPV voltage of the first logic level. [5] Storage device according to claim 4, wherein: that the circuit voltage at the first time is less than or equal to the first threshold voltage indicates that the first logic level is the current logic level of the memory cell and that a blocking operation is to be performed; that the circuit voltage at the second time point is less than or equal to the second threshold voltage indicates that a general process to verify the current logic level of the memory cell should be carried out; The fact that the circuit voltage at the second time point is greater than the second threshold voltage indicates that a first rate reduction process should be carried out to verify the current logic level of the memory cell; and The fact that the circuit voltage at the third time point is less than or equal to the third threshold voltage indicates that a second speed reduction process should be carried out to verify the current logic level of the memory cell. [6] Storage device according to claim 5, wherein the storage device comprises a local controller configured to: To cause the locking process to be carried out to include reducing a bit line voltage applied to the bit line in order to prevent the memory cell from being programmed; To initiate the general process which involves reducing the bit line voltage by a general amount; Causing the first velocity reduction process to be carried out, which includes reducing the bit line voltage by a first velocity reduction amount, where the first velocity reduction amount is less than the general amount; and Causing the second speed reduction process to be carried out, which includes reducing the bit line voltage by a second speed reduction amount, where the second speed reduction amount is smaller than the first speed reduction amount. [7] Storage device according to one of claims 4-6, wherein: the side buffer includes a sampling amplifier register, a cache register, and an additional register; and the sampling amplifier is configured to: Storing information corresponding to the SPPV voltage in the sampling amplifier register; To ensure that information corresponding to the FPPV voltage is stored in at least one of the cache registers or the additional register; and To ensure that information corresponding to the PV voltage is stored in at least one of the cache registers or the additional register. [8] Storage device according to any one of claims 1-7, wherein: the storage device comprises a local controller and a regulator, the regulator being connected to the memory cell via the word line; the local controller is configured to cause the regulator to apply the word line voltage at a voltage level equal to the first logic level; and The circuit voltage is determined at the second time point to allow information corresponding to the SPPV voltage of the second logic level to be determined using the word line voltage at the voltage level corresponding to the first logic level. [9] Method carried out by the storage device according to claim 1, the method comprising: Sampling the current of the bit line assigned to the memory cell within the storage device, wherein the current is based on the word line voltage and the current logical level of the memory cell; Determining the circuit voltage of the sampling amplifier within the storage device using the circuit voltage based on the current of the bit line assigned to the memory cell at the first time point, where the first time point corresponds to the PV voltage of the first logic level of the memory cell; and Determining the circuit voltage of the sampling amplifier based on the current of the bit line assigned to the memory cell at the second time point, where the second time point corresponds to the second SPPV voltage of the second logical level of the memory cell. [10] Method according to claim 9, further comprising determining the circuit voltage of the sampling amplifier on the basis of the current of the bit line assigned to the memory cell at a third time point, wherein the third time point corresponds to a first preprogram verification (FPPV) voltage of the first logical level of the memory cell.

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