Pulse darkening for a light-emitting diode control device

Abstract

A transistor control logic circuit has a first and a second input and an output. The output is coupled to the control terminal of a transistor. A peak current detector has a reference input, a detection input, and an output. The peak current detector provides a first signal at its output in a first logic state in response to a detection signal exceeding a reference signal. A trigger buffer has a first and a second input and an output. The first input of the trigger buffer is coupled to the output of the peak current detector. The output of the trigger buffer is coupled to the first input of the transistor control logic circuit.The trigger buffer provides a third signal in the first logic state at the output of the trigger buffer in response to the fact that the first signal at the output of the peak current detector is in the first logic state and a second signal at the second input of the trigger buffer is in a second logic state.

Description

BACKGROUND

[0001] A light-emitting diode (LED) driver controls the brightness of light produced by LEDs. One technique for controlling the brightness level uses pulse-width modulation (PWM) dimming. The PWM dimming regulates the output current to the LEDs by chopping the current based on a PWM signal. SUMMARY

[0002] In one example, a transistor control logic has a first and a second input and an output. The output is coupled to the control terminal of a transistor. A peak current detector has a reference input, a detection input, and an output. The peak current detector provides a first signal at its output in a first logic state in response to a detection signal exceeding a reference signal. A trigger buffer has a first and a second input and an output. The first input of the trigger buffer is coupled to the output of the peak current detector. The output of the trigger buffer is coupled to the first input of the transistor control logic.The trigger buffer provides a third signal in the first logic state at the output of the trigger buffer in response to the fact that the first signal at the output of the peak current detector is in the first logic state and a second signal at the second input of the trigger buffer is in a second logic state.

[0003] In another example, a device includes a trigger buffer having a first input, a second input, and an output. The trigger buffer is configured to provide a first signal in a first logic state at its output in response to both a second signal at the first input of the trigger buffer being in a second logic state and a third signal at the second input of the trigger buffer being in a second logic state. A pulse-feedback circuit has an output. An error amplifier has a first and a second input and an output. A switch has a first switch terminal, a second switch terminal, and a control terminal. The first switch terminal is coupled to the output of the pulse-feedback circuit.The second switch terminal is connected to the output of the error amplifier, and the switch's control terminal is connected to the output of the pulse feed control circuit. A comparator has a first input, a second input, and an output. The comparator's first input is connected to the second switch terminal. The comparator's second input is connected to the second input of the error amplifier, and the comparator's output is connected to the first input of the trigger buffer.

[0004] In yet another example, a device contains a transistor that has a control terminal. A transistor control logic has a first input, a second input, and an output. The output is coupled to the control terminal of the transistor. A peak current detector has a reference input, a sensing input, a third input, and an output. The peak current detector is configured to provide a first signal at the output of the peak current detector in a first logic state in response to a sensing signal at the sensing input exceeding a reference signal at the reference input. A pulse feeder circuit has an input and an output. The input of the pulse feeder circuit is coupled to the reference input of the peak current detector. A switch has a first switch terminal, a second switch terminal, and a control terminal.The first switch terminal is connected to the output of the pulse feed control circuit. The second switch terminal is connected to the third input. A trigger buffer has a first input, a second input, a first output, and a second output. The first input of the trigger buffer is connected to the output of the peak current detector. The first output of the trigger buffer is connected to the first input of the transistor control logic. The second output of the trigger buffer is connected to the control terminal of the switch. The trigger buffer is configured to provide a second signal in the first logic state at its first output in response to both the first signal at the peak current detector output being in the first logic state and a third signal at the second input of the trigger buffer being in a second logic state. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a diagram of a system that includes a microcontroller unit (MCU), an LED driver, a power stage circuit and one or more LEDs, in an example. Fig. 2 and Fig. 3 are schematic diagrams of examples of power stage circuits of Fig. 1. Fig. 4 and Fig. Figure 5 are example waveforms that illustrate the problem solved by the LED driver 120 described here. Fig. Figure 6 is a schematic diagram of an exemplary implementation of control logic used in the LED driver of Fig. 1 is usable. Fig. Figure 7 is a schematic diagram of a trigger buffer used in the control logic of Fig. 6 is usable, in an example. Fig. Figure 8 contains example waveforms that illustrate a pulse width modulation extension in one example. Fig. Figure 9 is a schematic diagram of another exemplary implementation of control logic used in the LED driver of Fig. 1 is usable. Fig. Figure 10 is a schematic diagram of a trigger buffer used in the control logic of Fig. 9 is usable, in an example. Fig. 11 is a schematic diagram of a pulse feedforward circuit used in the control logic of Fig. 9 is usable, in an example. Fig. Figure 12 is a schematic diagram of yet another exemplary implementation of a control logic used in the LED control device of Fig. 1 is usable. Fig. Figure 13 is a schematic diagram of a trigger buffer used in the control logic of Fig. 12 is usable, in an example. DETAILED DESCRIPTION

[0005] The same reference numerals or other reference designators are used in the drawings to denote the same or similar features (either in terms of function and / or structure).

[0006] As mentioned above, PWM dimming regulates the output current to the LEDs by chopping the current based on a PWM signal. At lower PWM frequencies, a high-speed camera pointed at the LEDs may exhibit flickering due to the LEDs switching on and off. Furthermore, at lower PWM frequencies, audible noise may be generated, for example, by a capacitor included in or coupled to the LED driver. Using PWM frequencies higher than, for example, 20 kHz can avoid such problems of flickering and audible noise. However, at PWM frequencies higher than 20 kHz, contrast ratios greater than, for example, 1000:1 are difficult, if not impossible, to achieve with conventional LED drivers.

[0007] Fig. Figure 1 is a diagram of a system 100 comprising a microcontroller unit (MCU) 102, an LED driver 120, a power stage circuit 130, and one or more LEDs 140. The LED driver 120 can be manufactured as an integrated circuit (IC). In one example, the power stage circuit 130 can be separate from the IC containing the LED driver 120. In another example, the power stage circuit 130 can be integrated with the LED driver 120, for example, within the same IC containing the LED driver.

[0008] In one example, the MCU 102 can contain a processor that executes machine instructions stored in it or in memory accessible to the processor by other means. The MCU 102 has an output 102a that is connected to a terminal 120c of an LED driver 120. The LED driver 120 also has terminals 120a, 120b, 120d, and 120e. Terminals 120a and 120b are power supply terminals connected to an input voltage VIN and ground, respectively. Terminals 120d and 120e are connected to terminals 130c and 130d, respectively, of a power stage circuit 130. Terminal 120d is a switching terminal. Terminal 130d of a power stage circuit 130 is a current sensing terminal that provides the ISENSE signal (e.g., a voltage) indicating the current through an inductor of the power stage circuit (described below). The power stage circuit 130 also has terminals 130e and 130f.The power stage circuit 130 generates an output voltage VOUT at its terminal 130e. One or more LEDs 140 can be connected in series between terminals 130e and 130f. The power stage circuit 130 also has terminals 130a and 130b, which are connected to the input voltage VIN and ground, respectively.

[0009] The MCU 102 generates an output PWM_DIMMING signal 111 for connection 120c of an LED driver 120. In response to the PWM_DIMMING signal being, for example, logic high, the LED driver 120 switches the LEDs 140 on. In response to the PWM_DIMMING signal being, for example, logic low, the LED driver 120 switches the LEDs 140 off. The frequency of the PWM_DIMMING signal is high enough (e.g., greater than at least 100 Hz) that the light from the LEDs 140 appears continuous to the human eye (i.e., not flickering when the LEDs are repeatedly switched on and off).

[0010] The LED driver 120 contains a control logic 122 and a transistor M1. The control logic 122 can be implemented as a logic circuit, examples of which are provided below. In this example, the transistor M1 is an n-channel field-effect transistor (NFET) having transistor terminals (e.g., a source and a drain) and a control terminal (e.g., a gate). The control logic 122 has inputs 122a, 122b, 122d, and 122e and an output 122c. Input 122a is connected to terminal 120c (e.g., a PWM dimming terminal) of an LED driver 120 and receives the PWM_DIMMING signal 111 from the MCU 102. Input 122b is connected to terminal 120a and receives the input voltage VIN. Output 122c is coupled to the gate of transistor M1 and provides a gate voltage (GATE) 113 at the transistor's gate. Input 122d is coupled to terminal 120e. A clock signal (CLK) (e.g.,The signal generated by an oscillator in the LED driver 120 is provided at input 122e of the control logic 122. In one example, the control logic 122 includes a peak-current-mode switching converter control unit, in which the control logic 122 turns transistor M1 on (closed state) in response to an edge (e.g., a rising edge) of the CLK and turns transistor M1 off (open state) when the current through an inductor of the power stage circuit 130 reaches a peak current reference level. In response to a logic high of the PWM signal, the control logic 122 can provide the GATE voltage 113 to a logic high to turn transistor M1 on, and then turn transistor M1 on and off based on a CLK while the PWM signal remains logic high. The control logic 122 can force the GATE voltage 113 to go logic low in order to turn off a transistor M1 when the PWM signal goes logic low.

[0011] Fig. 2 and Fig. Figure 3 shows schematic diagrams of examples of a power stage circuit 130. The example of Fig. 2 is the power level for an upward converter or a downward / upward converter. In Fig. The power stage circuit 130 contains an inductor L1, a diode D1, capacitors C1 and C2, and a current sensing circuit 210. Capacitor C1 and inductor L1 are connected to terminal 130a (VIN). The current sensing circuit 210 is connected to inductor L1 and generates the signal ISENSE, which indicates the current IL through the inductor. The anode of diode D1 is connected to inductor L1 (e.g., via the current sensing circuit 210) and to terminal 130c. One terminal of capacitor C2 is connected to the cathode of diode D1 and to terminal 130e (VOUT). The other terminal of capacitor C2 is connected to capacitor C1 and to ground.

[0012] The example of Fig. 3 is the power level for a downconverter. Fig. The power stage circuit 130 contains an inductor L2, a diode D2, capacitors C3 and C4, and a current sensing circuit 310. Capacitor C3 and the cathode of diode D2 are connected to each other and to terminal 130a (VIN). Inductor L2 is connected between the anode of diode D2 and terminal 130e, for example, by means of the current sensing circuit 310. The anode of diode D2 is connected to terminal 130c. The current sensing circuit 310 generates the signal ISENSE, which indicates the current IL through inductor L2. Capacitor C4 is connected between terminals 130a and 130e.

[0013] Fig. 4 and Fig. Figure 5 contains sample waveforms of the PWM_DIMMING signal 111, the GATE voltage 113, and the coil current IL, illustrating the problem solved by the LED driver 120 described here. While the PWM_DIMMING signal 111 is logic high, as indicated by 401, the control logic 122 switches a transistor M1 on and off at a significantly higher frequency than the frequency of the PWM_DIMMING signal 111. For example, the frequency at which transistor M1 is switched on and off may be 400 kHz, while the frequency of the PWM_DIMMING signal 111 is 20 kHz (or higher). For the sake of simplicity, only three pulses 402a, 402b and 402c for the GATE voltage 113 are illustrated; the control logic 122 generates much more than three pulses for GATE voltage 113 for each positive pulse 401 of the PWM_DIMMING signal 111.Each time the GATE voltage 113 is logic high, transistor M1 turns on and the current IL increases, as identified in 403a, 403b, and 403c. Each time the GATE voltage 113 is logic low, transistor M1 turns off and the current IL decreases, as identified in 405a, 405b, and 405c.

[0014] When the PWM_DIMMING signal 111 transitions from logic low to logic high (rising edge 401a), the current through inductor L1 is approximately 0 amperes. Accordingly, one or more switching cycles of the GATE voltage 113 are required for the inductor current IL to reach its target level 410. From this point onward, the current IL remains at the target level 410, with ripple due to the switching behavior of the control logic 122 (e.g., when transistor M1 is switched on and off, as explained above). When the falling edge 401b occurs, the inductor IL drops back to approximately 0 amperes. The PWM_DIMMING signal 111 remains logic high (401) long enough to allow the control logic 122 to regulate its current IL.

[0015] Fig. Figure 5 is an example where the duty cycle of the PWM_DIMMING signal 111 for a conventional LED driver is small enough that the duration 501, for which the PWM signal is logic high, is short enough that only a single pulse of the GATE voltage 113 occurs. The duration 502 of the single gate pulse is short enough that the inductor IL does not have enough time to rise to its target level 410 before transistor M1 turns off, causing the inductor current IL to return to 0 amperes. Fig. 5. The PWM_DIMMING signal 111 is not logic high long enough for the control logic 122 to achieve regulation of its current IL. The amount of charge supplied to the LEDs 140 is proportional to the product of the level of the current IL and the duration of the current. Because transistor M1 is switched off before the control current IL reaches its target level 410, the amount of charge supplied to the LEDs 140 is less than the desired charge level – where the desired charge level is the target current level 410 multiplied by the duration 502.

[0016] Fig. Figure 6 is a schematic diagram of an exemplary implementation of the control logic 122. As described above, for a conventional LED driver, the duty cycle of the PWM_DIMMING signal 111 can be small enough that the coil current IL does not reach the peak current reference for the peak current-mode switching converter implemented in the control logic 122. In the example of Fig. In section 6, control logic 122 implements a pulse-width modulation extension, which keeps transistor M1 on even after the PWM_DIMMING signal 111 becomes logic low, provided the inductor current IL has not yet reached the peak current reference. Control logic 122 switches transistor M1 off when both the PWM_DIMMING signal 111 is logic low and the inductor current IL has reached the peak current reference at least once, after the PWM_DIMMING signal 111 has previously become logic high.

[0017] In the example of Fig. The control logic 122 comprises a peak current detector 610, a transistor control logic 630, a gate drive device 640, and a trigger buffer 650. The peak current detector 610 has a reference input 610a, a detection input 610b, and an output 610c. The transistor control logic 630 has an input 630a, an input 630b, and an output 630c. The trigger buffer 650 has inputs 650a and 650b and an output 650c. A peak current reference signal IREF, generated, for example, by a reference current circuit, is provided at input 610a of the peak current detector 610. Input 610b receives the ISENSE signal from the power stage circuit 130. The peak current detector 610 contains an error amplifier (EA) 612 and a comparator 614. The positive (+) input of EA 612 is coupled to input 610a and the negative (-) input of EA 612 is coupled to input 610b.EA generates the signal VCTRL at its output based on the difference between IREF and ISENSE. The output of EA 612 is coupled to the negative input of comparator 614, and input 610b is coupled to the positive input of comparator 614. Comparator 614 generates a digital signal TRIGGER_IL_PEAK at its output. In the example of... Fig. 6. Comparator 614 forces the TRIGGER_IL_PEAK signal to a high logic level when the ISENSE signal reaches the peak current reference signal IREF; otherwise, comparator 614 forces the TRIGGER_IL_PEAK signal to a low logic level.

[0018] The output 610c of the peak current detector 610 is coupled to the input 630b of the transistor control logic 630. The input 122e of the control logic 122 is coupled to the input 630a of the transistor control logic 630. The output 630c of the control logic 630 is coupled to the input of the gate drive 640, and the output of the gate drive 640 is coupled to the output 122c of the control logic 122. The transistor control logic 630 contains an AND gate 632, an OR gate 634, and a set-reset buffer (SR buffer) 636. In this example, each of the inputs 630a and 630b contains two signal inputs. For example, input 630a has two inputs that couple to inputs 632a and 632b of the AND gate 632. Similarly, input 630b has two inputs that couple to inputs 634a and 634b of the OR gate 634.The output 610c of the peak current detector 610 is connected to the input 634b of the OR gate 634, and the output 650c of the trigger buffer 650 is connected to the input 634a of the OR gate 634. The trigger buffer 650 generates the TRIG1 signal at its output 650c. The PWM_DIMMING signal 111 and CLK are provided to the inputs 632a and 632b, respectively, of the AND gate 632. The output of the AND gate 632 is connected to the set input of the SR buffer 636, and the output of the OR gate 634 is connected to the reset input of the SR buffer 636. The Q output of the SR buffer 636 is coupled to the output 630c of the transistor control logic 630 and accordingly to the input of the gate control device 640.

[0019] SR buffer 636 is set when both the CLK and PWM_DIMMING signals 111 are logic high. SR buffer 636 is reset when either or both of the TRIG1 or TRIGGER_IL_PEAK signals are logic high. When SR buffer 636 is set, its Q output becomes logic high, which, via the gate drive 640, causes transistor M1 to turn on. When SR buffer 636 is reset, its Q output becomes logic low, causing transistor M1 to turn off. The trigger buffer 650 forces the TRIG1 signal to be logic high when both of the following conditions are true: (1) the PWM_DIMMING signal 111 is logic low and (2) the TRIGGER_IL_PEAK signal is logic high. In other words, the trigger buffer 650 forces TRIG1 to logically high when the MCU 102 has disabled PWM dimming (e.g.The PWM_DIMMING signal 111 is logic low, and the peak current detector 610 detects that the coil current IL has reached the peak current reference IREF. If PWM dimming is switched off (the PWM_DIMMING signal 111 is logic low), but the coil current IL has not yet reached the peak current reference, the trigger buffer 650 TRIG1 remains at a low logic level. Accordingly, as the PWM_DIMMING signal 111 becomes logic low, the SR buffer 636 is not reset, and transistor M1 is not switched off until the coil current IL has also reached the peak current reference IREF. The OR gate 634 performs a logical OR operation on TRIG1 and TRIGGER_IL_PEAK.In addition to the fact that the SR buffer 636 is reset in response to the PWM dimming being switched off and the coil current IL reaching the peak current reference, the SR buffer 636 is also reset every time the coil current IL reaches the peak current reference when the PWM dimming is on (e.g., the PWM_DIMMING signal 111 is logic high).

[0020] Fig. Figure 7 is a schematic diagram of an implementation of the trigger buffer 650 in the example of Fig. 6. In Fig. The trigger buffer 650 contains a D flip-flop (DFF) 710 and an AND gate 714. The DFF 710 has a reset input (RST input), a data input (D input), a clock input, and a Q output. The AND gate 714 has inputs 714a and 714b. Input 714a is an inverted input (e.g., the opposite polarity of input 714b). Input 650b (which provides the PWM_DIMMING signal 111) is connected to the reset input of DFF 710 and to input 714a of AND gate 714. The Q output of DFF 710 is connected to input 714b of AND gate 714. The D input of DFF 710 is logic high. Input 650a (which provides the TRIGGER_IL_PEAK signal) is connected to the clock input of DFF 710. The output of AND gate 714 is connected to output 650c and provides the TRIG1 signal.The transition of TRIGGER_IL_PEAK from logic low to logic high (a rising edge) clocks DFF 710, forcing its Q output to a logic high. Consequently, input 714b of AND gate 714 is logic high. AND gate 714 forces TRIG1 to logic high when both PWM_DIMMING 111 is logic low and the Q output of DFF 710 is logic high.

[0021] Fig. Figure 8 contains waveforms illustrating the PWM extension functionality of control logic 122. With a conventional LED driver, the width 801 of PWM_DIMMING 111 is small enough that transistor M1 would turn off on the falling edge 801b of PWM_DIMMING 111, as also indicated by the falling edge 811 of GATE, which represents an example signal received by the gate of M1 at 122c. Transistor M1 would therefore not be on long enough to allow the coil current IL to reach its target level 411 before decaying back to 0 amperes, as identified at 821. However, the PWM extension functionality of control logic 122 in Fig. 6 and Fig. 7, that transistor M1 remains on beyond the falling edge of GATE 801b. The falling edge of GATE 812 is extended to allow transistor M1 to remain on long enough to allow an inductor current IL to reach its target level according to the peak current reference IREF before it is then turned off.

[0022] Fig. Figure 9 is a schematic diagram of another exemplary implementation of the control logic 122. The control logic 122 in Fig. 9 controls the transient response (e.g., makes the transient response faster) of the LED driver 120 due to a sudden change in the duty cycle of the PWM_DIMMING signal 111. The control logic 122 in Fig. 9 does not exhibit the PWM extension functionality of the control logic 122 in Fig. 6. The control logic 122 in this example includes a peak current detector 610, a transistor control logic 930, a gate drive device 640, a trigger buffer 950, a switch SW1, a pulse feedforward circuit 980, and a sample-and-hold (S / H) circuit 990. The peak current detector 610 was described previously. The transient control logic 930 is similar to the transient control logic 630 in Fig. 6 and contains the AND gate 632 and the SR buffer 636, but does not have an OR gate 634. Instead of the OR gate 634, the output 610c of the peak current detector 610 is coupled to the reset input of the SR buffer 636.

[0023] The trigger buffer 950 has inputs 950a and 950b and one output 950c. The switch SW1 has switch terminals SW1a and SW1b and one control terminal SW1c. The pulse feedforward circuit 980 has inputs 980a, 980b, 980c, and 980d and one output 980e. Input 980a is coupled to input 610a of the peak current detector 610 and accordingly receives a peak current reference signal IREF. The S / H 990 has inputs 990a and 990b and one output 990c. Input 990a is coupled to input 610b of the peak current detector 610 and receives the ISENSE signal. Input 990b receives the PWM_DIMMING signal 111. Output 990c is coupled to input 980b of the pulse feed control circuit 980. The S / H 990 samples the ISENSE signal as a current IPWM_OFF based on a falling edge of the PWM_DIMMING signal 111. Accordingly, the IPWM_OFF current indicates the coil current IL (e.g.,...).(is proportional to it) when the PWM dimming is switched off. Inputs 980c and 980d of the pulse feed control circuit 980 receive an input voltage VIN and an output voltage VOUT, respectively. Output 980e of the pulse feed control circuit 980 is coupled to a switch terminal SW1a of switch SW1. The pulse feed control circuit 980 determines VPFF at its output 980e. The opposite switch terminal SW1b is coupled to an input 610d of the peak current detector 610. The peak current detector 610 in . Fig. 9 contains a resistor that is coupled between the output of EA 612 and the negative input of comparator 614. Input 610d is coupled to the connection between resistor R1 and the negative input of comparator 614. Output 950c of the trigger buffer 950 is coupled to a control terminal SW1c of switch SW1. Input 950b of the trigger buffer 950 receives the PWM_DIMMING signal 111. Input 950a of the trigger buffer 950 is coupled to output 610c of the peak current detector 610.

[0024] In Fig. The trigger buffer 950 detects when both: (1) the PWM dimming has been switched off (e.g., PWM_DIMMING is logic low) and (2) the coil current IL has not yet reached the peak current reference IREF (e.g., TRIGGER_IL_PEAK is also logic low). If both of the conditions (1) and (2) described above are met, the trigger buffer 950 sets the signal TRIG2 to a high logic state at its output 950c; otherwise, the trigger buffer 950 forces the signal TRIG2 to a low logic state. In response to TRIG2 being logic high, switch SW1 closes, and the voltage VPFF is supplied to the negative input of comparator 614 instead of VCTRL from EA 612. By forcing the negative input of comparator 614 to exhibit the voltage VPFF instead of VCTRL from EA 612, the control logic 122 responds faster to a sudden change in the duty cycle of the PWM_DIMMING signal 111.

[0025] The pulse feedforward circuit 980 generates a current IPFF according to the following equation: IPFF2=2∗IREF∗IPWMOFF∗max(VIN,VOUT)−min(VIN,VOUT)max(Vin,VOUT)

[0026] The pulse-feedback circuit 980 generates the voltage VPFF based on the current IPFF, for example, by passing a current IPFF through a resistor to produce the voltage VPFF. The current IPFF is the coil current IL that should be achieved to provide a sufficient amount of charge to the LEDs during PWM dimming, corresponding to the charge of an ideal case where the coil current IL has an infinite slope (i.e., does not rise / fall as a function of inductance and voltage) and is present for the entire duration of the PWM dimming-on state at the peak reference current level.

[0027] Fig. Figure 10 is a schematic diagram of an implementation of the trigger buffer 950 in the example of Fig. 9. In Fig. The trigger buffer 950 contains the DFF 710 and an AND gate 1014. The AND gate 1014 has inputs 1014a and 1014b. Inputs 1014a and 1014b are inverted inputs. Input 950b (which provides the PWM_DIMMING signal 111) is connected to the reset input of the DFF 710 and input 1014a of the AND gate 1014. The Q output of the DFF 710 is connected to input 1014b of the AND gate 1014. The D input of the DFF 710 is logic high. Input 950a (which provides the TRIGGER_IL_PEAK signal) is connected to the clock input of the DFF 710. The output of AND gate 1014 is coupled to output 950c and provides the TRIG2 signal. A transition of TRIGGER_IL_PEAK from logic low to logic high (a rising edge) clocks DFF 710, forcing its Q output to a high logic state; otherwise, if no rising edge for TRIGGER_IL_PEAK is present, the Q output remains logic low.Accordingly, if both inputs 1014a and 1014b of the AND gate 1014 are logic low, the AND gate 1014 forces TRIG2 to logic high. In other words, TRIG2 is forced to logic high if the PWM dimming is off and TRIGGER_IL_PEAK has not yet been forced too high.

[0028] Fig. Figure 11 is a circuit diagram illustrating an exemplary implementation of the pulse feed control circuit 980. The example pulse feed control circuit of Fig. 11 is an analog circuit based on bipolar junction transistors (BJTs) that implement equation (1) described above. In other examples, the pulse feedforward circuit can be implemented by a processor executing machine instructions (e.g., a microcontroller). In the example of Fig. The pulse-feedback circuit contains 980 transistors Q1, Q2, Q3, Q4, Q5, and Q6 (e.g., NPN-BJTs), a resistor R2, current mirrors 1104 and 1106, comparators 1120 and 1122, a subtractor 1124, voltage-controlled current sources 1126 and 1128, and a current source 1130. The collector of each transistor Q1-Q6 is coupled to its respective base. The emitters of transistors Q1 and Q4 are coupled together. The base of transistor Q1 is coupled to the emitter of transistor Q2, and the base of transistor Q2 is coupled to the emitter of transistor Q3. The bases of transistors Q3 and Q6 are coupled together. The emitter of transistor Q6 is coupled to the base of transistor Q5 and the emitter of transistor Q5 is coupled to the base of transistor Q4.

[0029] The current mirror 1104 has one input coupled to input 980a and receives a peak current reference signal IREF. The mirror ratio for the current mirror 1104 is 1:2, and accordingly, the output current from the current mirror 1104 is 2xIREF and is provided at the collector of transistor Q1. The collector of transistor Q2 is coupled to input 980b and receives the current IPWM_OFF.

[0030] Comparators 1120 and 1122 are voltage comparators. Each comparator 1120 and 1122 receives the voltages VIN and VOUT as its inputs. Comparator 1120 outputs the minimum (min(VIN,VOUT)) between VIN and VOUT as its output voltage to the input of subtractor 1124. Comparator 1122 outputs the maximum between VIN and VOUT (max(VIN,VOUT)) as its output voltage to another input of subtractor 1124. The subtractor 1124 subtracts the output voltage of the comparator 1120 from the output voltage of the comparator 1122 and provides an output voltage (max(VIN,VOUT) - min(VIN,VOUT)) at a control input of a voltage-controlled current source 1128. The current generated by the voltage-controlled current source 1128 is a current proportional to max(VIN,VOUT) - min(VIN,VOUT) and is provided at the collector of transistor Q3.The current source 1130 is coupled to an input of the current mirror 1106, which mirrors the current IPFF of the current source 1130 to the collectors of transistors Q5 and Q6. The mirror ratio of the current mirror 1106 is 1:1:1. The current from output 1106c of the current mirror 1106 is coupled to resistor R2, which converts the current IPFF from the current mirror 1106 to the corresponding voltage VPFF at output 980e.

[0031] The sum of the base / emitter voltages (Vbe) of transistors Q1-Q3 is equal to the sum of the Vbes of transistors Q4-Q6. Due to the exponential relationship between the collector current and Vbe of BJTs, the sum of the Vbes of transistors Q1-Q3 is equal to 2 * IREF * [max(VIN,VOUT) - min(VIN,VOUT)] and the sum of the Vbes of transistors Q4-Q6 is equal to IPFF * IPFF * max(VIN,VOUT). The current source 1130 generates a current IPFF, which causes the sum of the Vbes of transistors Q1-Q3 to be equal to the sum of the Vbes of transistors Q4-Q6. Accordingly, the circuit implements Fig. 11 Eq. (1), which was described above.

[0032] Fig. Figure 12 is a schematic diagram of another example of the control logic 122, which includes both a PWM extension and pulse feedforward control. Accordingly, the control logic 122 in the example of Fig. 12 a trigger buffer 1250, which generates both the TRIG1 signal and the TRIG2 signal described above. The control logic 122 in Fig. 12 also contains the peak current detector 610, the transistor control logic 630 (from Fig. 6), the pulse feed control circuit 980 and the switch SW1 ( Fig. 9) are the components whose descriptions were provided above. The trip buffer 1250 can set TRIG1 to logic high to ensure that transistor M1 remains on even after the PWM dimming is turned off, until the coil current IL reaches the peak current reference signal IREF. The trip buffer 125 can also set TRIG2 to logic high when the PWM dimming is turned off if the coil current IL has not reached the peak current reference signal IREF, in order to improve the transient response, as described above.

[0033] Fig. Figure 13 is a schematic diagram of the trigger buffer 1250. The trigger buffer 1250 is similar to the trigger buffers of Fig. 7 and Fig. 10 and contains the DFF 710, the AND gate 714 (from Fig. 7) and the AND gate 1014 (from Fig. 10) The operation of the DFF 710 and the AND gate 714 in Fig. 13, to generate TRIG1, is, as above regarding Fig. 7 was described. Accordingly, the operation of the DFF 710 and the AND gate 1014 is described in Fig. 13, to generate TRIG2, as above regarding Fig. 10 was described.

[0034] In this description, the term "couple" can encompass connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, when device A generates the signal to control device B, an action is to be performed: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B via an intermediary component C, provided that the intermediary component C does not alter the functional relationship between device A and device B such that device B is controlled by device A using the control signal generated by device A.

[0035] Furthermore, in this description, the recitation "based on" means "at least partially based on." Therefore, if X is based on Y, then X can be a function of Y and any number of other factors.

[0036] A device that is "configured" to perform a task or function can be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform that function, and / or it can be configured (or reconfigured) by a user after manufacture to perform that function and / or additional or alternative functions. Configuration can be achieved through firmware and / or software programming of the device, through the design and / or layout of the device's hardware components and connections, or a combination thereof.

[0037] As used herein, the terms "connector", "node", "connection", "pin", and "conduit" are used interchangeably. Unless specifically stated otherwise, these terms are generally used to mean a connection between, or an endpoint of, a device element, circuit element, integrated circuit, appliance, or other electronic or semiconductor component.

[0038] A circuit or device described herein as containing certain components may instead be designed to be coupled to those components to form the described circuit arrangement or device. For example, a structure described as containing one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead contain only the semiconductor elements in a single physical device (such as a semiconductor chip and / or an integrated circuit assembly (IC assembly)) and may be designed to be coupled either during manufacturing or after a period of time, such as...by an end user and / or a third party, to be coupled to at least some of the passive elements and / or the sources in order to form the described structure.

[0039] While the use of specific transistors is described here, other transistors (or equivalent devices) can be used instead with little or no change to the remaining circuit arrangement. For example, a field-effect transistor (“FET”) (such as an n-channel FET (NFET) or a p-channel FET (PFET)), a bipolar junction transistor (BJT—such as an NPN or PNP transistor), an insulated-gate bipolar transistor (IGBT), and / or a junction field-effect transistor (JFET) can be used instead of, or in conjunction with, the devices described here. The transistors can be depletion-mode devices, extended-drain devices, enhancement-mode devices, natural transistors, or other types of device-structure transistors.Furthermore, the devices can be implemented in / over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).

[0040] The claims may refer to a control input of a transistor and its current terminals. In the context of a FET, the control input is the gate, and the current terminals are the drain and the source. In the context of a BJT, the control input is the base, and the current terminals are the collector and the emitter.

[0041] References here to a FET being "ON" or "ENABLED" mean that the FET's conduction channel is present and a drain current can flow through the FET. References here to a FET being "OFF" or "DISABLED" mean that the conduction channel is not present, so no drain current flows through the FET. However, an "OFF" FET may still carry current flowing through the transistor's inverse diode.

[0042] Circuits described here are reconfigurable to include additional or different components to provide functionality that is at least partially similar to that available before the component exchange. Components shown as resistors, unless otherwise specified, generally represent one or more elements connected in series and / or parallel to provide an impedance value represented by the resistance shown. For example, a resistor or capacitor shown and described here as a single component may instead be multiple resistors or capacitors connected in parallel between the same nodes.For example, a resistor or capacitor shown and described here as a single component may instead be multiple resistors or capacitors connected in parallel between the same two nodes as the single resistor or capacitor.

[0043] While certain elements of the described examples are contained within an integrated circuit and other elements are located outside the integrated circuit, in other exemplary embodiments, additional or fewer features may be included in the integrated circuit. Additionally, features illustrated as being outside the integrated circuit may be partially or completely contained within the integrated circuit, and / or some features illustrated as being internal to the integrated circuit may be included outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) included in / over a semiconductor substrate; (ii) included in a single semiconductor assembly; (iii) included in the same module; and / or (iv) included in / on the same printed circuit board.

[0044] Uses of the compound word "mass" in the preceding description include landing gear mass, earth mass, suspended mass, virtual mass, digital mass, common mass, and / or other forms of mass compound applicable to or suitable for the instructions in this description. In this description, unless otherwise specified, "about," "approximately," or "essentially" preceding a parameter means a range of + / -10 percent around that parameter or, if the parameter is zero, a reasonable range of values ​​around zero.

[0045] Variations are possible in the examples described, and further examples are possible within the scope of the claims.

Claims

[1] Device comprising the following: a transistor that has a control terminal; a transistor control logic comprising a first input, a second input and an output, wherein the output is coupled to the control terminal of the transistor; a peak current detector having a reference input, a sensing input and an output, wherein the peak current detector is configured to provide a first signal at the output of the peak current detector in a first logic state in response to a sensing signal at the sensing input exceeding a reference signal at the reference input; and a trigger buffer having a first input, a second input and an output, wherein the first input of the trigger buffer is coupled to the output of the peak current detector, and the output of the trigger buffer is coupled to the first input of the transistor control logic, and the trigger buffer is configured to provide a third signal in the first logic state at the output of the trigger buffer in response to both the first signal at the output of the peak current detector being in the first logic state and a second signal at the second input of the trigger buffer being in a second logic state. [2] Device according to claim 1, wherein the output of the trigger buffer is a first output, the trigger buffer has a second output, the peak current detector has a second input and a third input, and the device further comprises: a pulse feedforward circuit having a first input and an output, wherein the first input is coupled to the second input of the peak current detector; and a switch having a first and a second switch terminal and a control terminal, the first switch terminal being coupled to the output of the pulse feed control circuit, the second switch terminal being coupled to the third input of the peak current detector, and the control terminal of the switch being coupled to the second output of the trigger buffer. [3] Device according to claim 2, wherein the pulse feedforward circuit is configured to determine a fourth signal at the output of the pulse feedforward circuit based on a reference signal at the first input of the pulse feedforward circuit. [4] Device according to claim 2, wherein the pulse feedforward circuit has a second input and a third input and the pulse feedforward circuit is configured to determine a fourth signal at the output of the pulse feedforward circuit based on a signal or voltage at the respective first, second and third input of the pulse feedforward circuit. [5] Device according to claim 2, wherein the trigger buffer is configured, in response to the fact that the first signal at the output of the peak current detector is in the second logic state and the second signal at the second input of the trigger buffer is in the second logic state, to provide the signal at the second output of the trigger buffer to cause the switch to be in a closed state. [6] Device according to claim 1, wherein the trigger buffer comprises the following: a data flip-flop (D flip-flop) having a clock input, a reset input and an output, wherein the clock input is coupled to the first input of the trigger buffer and the reset input is coupled to the second input of the trigger buffer; and an AND gate having a first input, a second input and an output, wherein the first input of the AND gate is coupled to the output of the D flip-flop, the second input of the AND gate is coupled to the second input of the trigger buffer and the output of the AND gate is coupled to the output of the trigger buffer. [7] Device according to claim 1, wherein the transistor has a transistor terminal and the device further comprises: a power stage having an input and an output, wherein the input of the power stage is coupled to the transistor terminal; and a light-emitting diode that has a connection coupled to the output of the power stage. [8] Device according to claim 1, wherein the device has a pulse width modulation dimming port (PWM dimming port) and the second input of the trigger buffer is coupled to the PWM dimming port. [9] Device comprising the following: a trigger buffer having a first input, a second input and an output, wherein the trigger buffer is configured to provide a first signal in a first logic state at the output of the trigger buffer in response to both a second signal at the first input of the trigger buffer being in a second logic state and a third signal at the second input of the trigger buffer being in a second logic state; a pulse feedforward circuit that has one output; an error amplifier having a first and a second input and an output; a switch having a first switch terminal, a second switch terminal and a control terminal, wherein the first switch terminal is coupled to the output of the pulse feeder circuit, the second switch terminal is coupled to the output of the error amplifier and the control terminal of the switch is coupled to the output of the pulse feeder circuit; and a comparator having a first input, a second input and an output, wherein the first input of the comparator is coupled to the second switch terminal, the second input of the comparator is coupled to the second input of the error amplifier and the output of the comparator is coupled to the first input of the trip buffer. [10] Device according to claim 9, wherein the pulse feedforward circuit has an input coupled to the second input of the error amplifier and the pulse feedforward circuit is configured to generate the signal at the output of the pulse feedforward circuit based on a signal at the input of the pulse feedforward circuit. [11] Device according to claim 9, wherein the pulse feedforward circuit has a first input and a second input, the first input of the pulse feedforward circuit is coupled to the second input of the error amplifier and the pulse feedforward circuit is configured to generate the signal at the output of the pulse feedforward circuit based on a signal at the first input of the pulse feedforward circuit and a voltage at the second input of the pulse feedforward circuit. [12] Device according to claim 9, wherein the pulse feedforward circuit has a first input and a second input, the first input of the pulse feedforward circuit is coupled to the second input of the error amplifier and the pulse feedforward circuit is configured to generate the signal at the output of the pulse feedforward circuit based on a product of a signal at the first input of the pulse feedforward circuit and a signal at the second input of the pulse feedforward circuit. [13] Device according to claim 9, wherein the pulse feedforward circuit has a first input, a second input and a third input, the first input of the pulse feedforward circuit is coupled to the second input of the error amplifier and the pulse feedforward circuit is configured to generate the signal at the output of the pulse feedforward circuit based on a signal at the first input of the pulse feedforward circuit, a first voltage at the second input of the pulse feedforward circuit and a second voltage at the third input of the pulse feedforward circuit. [14] Device according to claim 9, wherein the switch is configured to infer in response that the first signal at the output of the trigger buffer is in the first logic state. [15] Device according to claim 9, wherein the output of the trigger buffer is a first output, the trigger buffer has a second output and the device further comprises: a transistor control logic having a first input and a second input, wherein the first input of the transistor control logic is coupled to the second input of the trigger buffer, the second input of the transistor control logic is coupled to the first input of the trigger buffer, and the trigger buffer is configured to provide a fourth signal in the first logic state at the second output of the trigger buffer in response to both the second signal at the first input of the trigger buffer being in the first logic state and the third signal at the second input of the trigger buffer being in the second logic state. [16] Device comprising the following: a transistor that has a control terminal; a transistor control logic comprising a first input, a second input and an output, wherein the output is coupled to the control terminal of the transistor; a peak current detector having a reference input, a sensing input, a third input and an output, wherein the peak current detector is configured to provide a first signal at the output of the peak current detector in a first logic state in response to a sensing signal at the sensing input exceeding a reference signal at the reference input; a pulse feedforward circuit having an input and an output, wherein the input of the pulse feedforward circuit is coupled to the reference input of the peak current detector; a switch having a first switch terminal, a second switch terminal and a control terminal, wherein the first switch terminal is coupled to the output of the pulse feed control circuit and the second switch terminal is coupled to the third input; and a trigger buffer having a first input, a second input, a first output and a second output, wherein the first input of the trigger buffer is coupled to the output of the peak current detector, the first output of the trigger buffer is coupled to the first input of the transistor control logic, the second output of the trigger buffer is coupled to the control terminal of the switch and the trigger buffer is configured to provide a second signal in the first logic state at the first output of the trigger buffer in response to both the first signal at the output of the peak current detector being in the first logic state and a third signal at the second input of the trigger buffer being in a second logic state. [17] Device according to claim 16, wherein the trigger buffer is configured to provide a fourth signal in the first logic state at the second output of the trigger buffer in response to the fact that both the first signal at the output of the peak current detector is in the second logic state and the third signal at the second input of the trigger buffer is in the second logic state. [18] Device according to claim 16, wherein the trigger buffer contains the following: a data flip-flop (D flip-flop) that has a clock input, a reset input and an output; a first AND gate having a first input, a second input and an output, wherein the first input of the first AND gate is coupled to the second input of the trigger buffer, the second input of the first AND gate is coupled to the output of the D flip-flop and the output of a first AND gate is coupled to the second output of the trigger buffer; and a second AND gate having a first input, a second input and an output, wherein the first input of the second AND gate is coupled to the second input of the trigger buffer, the second input of the second AND gate is coupled to the output of the D flip-flop and the output of a second AND gate is coupled to the second output of the trigger buffer. [19] Device according to claim 18, wherein the second input of the first AND gate is of an opposite polarity to the second input of the second AND gate. [20] Device according to claim 18, wherein the input of the pulse feedforward circuit is a first input, the pulse feedforward circuit has a second input and a third input and the pulse feedforward circuit is configured to generate the signal at the output of the pulse feedforward circuit based on a signal or voltage at the respective first, second and third input of the pulse feedforward circuit.

Images