DISPLAY DEVICE

Abstract

Disclosed is a display device (100) comprising a display panel (200) with a display area (AA) and a non-display area (NAA) surrounding the display area (AA); a plurality of subpixels (SP) arranged in the display area (AA); a first area contained in the non-display area (NAA) surrounding three sides of the display area (AA) in a top view of the display device (100); a second area contained in the non-display area (NAA) located at a position different from that of the first area; a bendable area (BDA) contained in the non-display area (NAA); and a barrier structure of the first size arranged in the first area.and a further barrier structure of the first size and a barrier structure of the second size, arranged in the second area and spaced apart from each other, wherein the barrier structure of the first size and the barrier structure of the second size have different sizes in plan view.

Description

BACKGROUND OF THE REVELATION Area The present disclosure relates to a display device. Description of the related technology A display device is used in various electronic devices, such as televisions, smartphones, laptop computers, and tablets. To this end, research continues into the thinness, light weight, low power consumption, and similar aspects of the display device. Examples of display devices may include a liquid crystal display device (LCD device), a field emission display device (FED device), an organic light-emitting display device (OLED device), and the like. A display device's bezel can be visually perceived by a user and can diminish the sense of immersion in an image emitted by the display. Accordingly, there is a growing demand for display devices that implement a narrow bezel, reducing the area where the screen is not displayed while expanding the display area, or a zero bezel, essentially eliminating the bezel altogether. Furthermore, as demand for and use of a portable device, especially a smartwatch phone, increases, research into the application of organic light-emitting display devices to smartwatch phones also increases, in order to produce a smartwatch with reduced bezel or zero bezel. SUMMARY OF THE REVELATION One purpose of an embodiment of the present disclosure is to provide an indicator device that can prevent deterioration or a change in the element properties of a driver transistor containing an oxide semiconductor. Furthermore, one purpose of an embodiment of the present disclosure is to provide a display device having a minimized enclosing area while barrier structures are placed to prevent a change in the element properties of a driver transistor containing an oxide semiconductor. Furthermore, one purpose of an embodiment of the present disclosure is to provide a display device that can reduce a defect rate of the display device by maintaining the element stability of a driver transistor. Furthermore, one purpose of an embodiment of the present disclosure is to provide a display device that can reduce greenhouse gas emissions by preventing an increase in the production energy required for the additional production of the display device. The purposes according to this disclosure are not limited to the purpose mentioned above. Other purposes and advantages according to this disclosure, which are not mentioned, can be understood on the basis of the following descriptions and can be understood more clearly on the basis of embodiments according to this disclosure. Furthermore, it is easy to understand that the purposes and advantages according to this disclosure can be realized using means or combinations thereof shown in the claims. A display device according to an embodiment of the present disclosure comprises a display panel with a display area and a non-display area surrounding the display area; a plurality of subpixels arranged in the display area; a first area contained in the non-display area and surrounding three sides of the display area in plan view; a second area contained in the non-display area and arranged in a position different from a position of the first area; a bendable area contained in the non-display area; and a barrier structure of a first size arranged in the first area.and a further barrier structure of the first size and a barrier structure of the second size, arranged in the second area and spaced apart from each other, wherein the barrier structure of the first size and the barrier structure of the second size have different sizes in plan view. The display device according to an embodiment of the present disclosure can prevent the deterioration or change of the element properties of the driver transistor containing the oxide semiconductor by placing the plurality of barrier structures on the enclosure area defined outside the display area. Furthermore, according to one embodiment of the present disclosure, the display device can minimize the enclosure area while placing the multiple barrier structures to prevent changes to the element properties of the driver transistor. Accordingly, the display device according to one embodiment of the present disclosure can maintain the operational stability of the driver transistor containing the oxide semiconductor. As a result, the display device according to one embodiment of the present disclosure can prevent the bright spot defect from occurring on the outer section of the display panel. If the defect rate is reduced in such a way that the production energy required for the additional production of the display device can be reduced, the display device according to one embodiment of the present disclosure can reduce greenhouse gas emissions. The effects of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned are clearly understood by the person skilled in the art from the description set forth below. In addition to the effects mentioned above, specific effects of the present revelation are described together, while specific details for carrying out the present revelation are described. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a top view of a display panel according to an embodiment of the present disclosure. Fig. 2 is a diagram showing a portable display device incorporating a display panel according to an embodiment of the present disclosure. Fig. 3 is an enlarged view of region I' in Fig. 1. Figs. 4, 5 to 6 are diagrams showing threshold voltage values ​​measured based on digits on a display panel. Fig. 7 is an enlarged view of region II in Fig. 1. Fig. 8 is a cross-sectional view along a line VI-VI' in Fig. 7. Fig. 9 is an enlarged view of region III in Fig. 1. Fig. 10 is an enlarged view of region IV in Fig. 1. Fig. 11 is an enlarged view of region V in Fig. 1. Fig. 12 is a cross-sectional view along a line VII-VII' in Fig. 4 . DETAILED DESCRIPTION OF THE REVELATION The advantages and features of the present disclosure, and a method for achieving these advantages and features, will become apparent with reference to embodiments that will be described in detail later, together with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but can be implemented in various different forms. Thus, these embodiments are presented only to complete the present disclosure and to fully inform the person skilled in the art in the technical field to which the present disclosure belongs about its scope, and the present disclosure is defined only by the scope of the claims. For the sake of simplicity and clarity of illustration, elements in the drawings are not necessarily drawn to scale. The same reference symbols in different drawings represent the same or similar elements and, as such, fulfill a similar function. Furthermore, descriptions and details of well-known steps and elements are omitted for the sake of clarity. Moreover, numerous specific details are set forth in the following detailed description of the present disclosure to provide a thorough understanding of the present disclosure. It is understood, however, that the present disclosure can be implemented without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present disclosure.Examples of different embodiments are further illustrated and described below. It is understood that the description herein is not intended to limit the claims to the specific embodiments described. On the contrary, it is intended to cover alternatives, modifications, and equivalents that may be included within the scope of this disclosure, as defined by the accompanying claims. A shape, size, ratio, angle, number, etc., disclosed in the drawings to illustrate embodiments of the present disclosure are illustrative, and the present disclosure is not limited thereto. The terminology used herein is solely for the purpose of describing certain embodiments and is not intended to limit the present disclosure. As used herein, the singular denotes "a" and "an" and is intended to include the plural unless the context clearly indicates otherwise. It is further understood that the terms "have," "having," "containing," and "containing," when used in this disclosure, indicate the presence of the specified features, integers, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, operations, elements, components, and / or sections thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed elements.An expression like "at least one of" when preceding a list of elements can modify the entire list but may not modify individual elements. When interpreting numerical values, an error or tolerance can occur even without an explicit description. Furthermore, it is understood that when a first element or layer is described as being "on" a second element or layer, the first element may be arranged directly on top of the second element or indirectly on top of the second element, with a third element or layer positioned between the first and second elements or between the first and second layers. It is also understood that when an element or layer is described as being "connected to" or "coupled with" another element or layer, it may be directly connected or coupled to the other element or layer, or one or more intermediate elements or layers may be present between them.Furthermore, it is understood that when an element or layer is described as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present. Furthermore, as used herein, if a layer, film, area, plate, or the like is arranged "above" or "on" another layer, film, area, plate, or the like, the former may directly touch the latter, or another layer, film, area, plate, or the like may be arranged between the former and the latter. As used herein, if a layer, film, area, plate, or the like is arranged directly "above" or "on" another layer, film, area, plate, or the like, the former directly touches the latter, and no other layer, film, area, plate, or the like is arranged between the former and the latter.Furthermore, as used herein, if a layer, film, area, plate, or the like is arranged "below" or "under" another layer, film, area, plate, or the like, the former may directly touch the latter, or another layer, film, area, plate, or the like may be arranged between the former and the latter. As used herein, if a layer, film, area, plate, or the like is arranged directly "below" or "under" another layer, film, area, plate, or the like, the former directly touches the latter, and no other layer, film, area, plate, or the like is arranged between the former and the latter. In descriptions of temporal relationships, for example, temporally preceding relationships between two events such as "after", "subsequently", "before", etc., another event may occur in between, unless "directly after", "directly following" or "directly before" is specified. If a particular embodiment can be implemented differently, a function or operation specified in a specific block may occur in a different order than the order specified in a flowchart. For example, two blocks may actually be executed sequentially, essentially simultaneously, or the two blocks may be executed in reverse order depending on a function or operation involved. It is understood that, although the terms “first,” “second,” “third,” etc., may be used herein to describe different elements, components, regions, layers, and / or periods, these elements, components, regions, layers, and / or periods should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or section from another. Thus, a first element, component, region, layer, or section, as described below, could be referred to as a second element, component, region, layer, or period without altering the scope of this disclosure. If an embodiment can be implemented differently, functions or operations specified within a particular block may be performed in a different order than the order specified in a flowchart. For example, two consecutive blocks may actually be performed essentially simultaneously, or the blocks may be performed in reverse order depending on related functions or operations. The features of the various embodiments of the present disclosure can be partially or completely combined and can be technically associated with one another or work together. The embodiments can be implemented independently of one another and can be implemented together in an associative relationship. When interpreting a numeric value, the value is interpreted to include an error range unless there is a separate explicit description of it. Unless otherwise defined, all terms used herein, including technical and scientific terms, have the same meaning as generally understood by a person skilled in the art in the field to which this inventive concept belongs. It is further understood that terms such as those defined in commonly used dictionaries should be interpreted in a manner consistent with their meaning in the context of the relevant technology and not in an idealized or overly formal sense, unless expressly defined as such herein. As used here, “designs”, “examples”, “aspects” and the like should not be interpreted as implying that one aspect or design as described is superior to or advantageous over other aspects or designs. Furthermore, the term "or" means "including or" rather than "exclusively or". That is, unless otherwise stated or clear from the context, the expression means that "xa or b uses" any of the natural inclusive permutations. The terms used in the following description were chosen as general and universal within the related technical field. However, other terms may exist depending on the development and / or change of technology, convention, the preferences of engineers, etc. Therefore, the terms used in the following description should not be understood as restrictive technical concepts, but rather as examples of terms used to illustrate embodiments. Furthermore, in a specific case, a term may be arbitrarily chosen by the applicant, and in this case, its detailed meaning will be described in a corresponding descriptive section. Therefore, the terms used in the following description should not be understood simply on the basis of their names, but rather on the basis of their meaning and their content within the entire detailed description. In describing the flow of a signal, for example, when a signal is delivered from node A to node B, this may include a case where the signal is transmitted from node A to node B via another node, unless an expression 'immediately transmitted' or 'directly transmitted' is used. Throughout this disclosure, “A and / or B” means A, B or A and B, unless otherwise specified, and “C to D” means C inclusive to D inclusive, unless otherwise specified. "At least one" should be understood to include any combination of one or more of the listed components. For example, "at least one of the first, second, and third components" does not mean only a single first, second, or third component, but also any combination of two or more of the first, second, and third components. Embodiments of the present disclosure are described below with reference to the accompanying drawings. The scale of each of the components, as shown in the drawings, differs from an actual scale thereof for the sake of clarity, and therefore the present disclosure is not limited to the scale shown in the drawings. As used herein, a first direction, a second direction and a third direction, or an X-axis direction, a Y-axis direction and a Z-axis direction, should not only be designed to have a geometric relationship to each other in which the first direction, the second direction and the third direction are perpendicular to each other, or the X-axis direction, the Y-axis direction and the Z-axis direction are perpendicular to each other, but may be designed to have a geometric relationship to each other in which the first direction, the second direction and the third direction intersect each other at an angle other than 90 degrees (°), or the X-axis direction, the Y-axis direction and the Z-axis direction intersect each other at an angle other than 90 degrees (°) within a range in which a configuration of the present disclosure can function functionally. In the following, a display device according to an embodiment of the present disclosure is described with reference to the drawings. Fig. 1 is a top view of a display panel according to an embodiment of the present disclosure. With reference to Fig. 1, a display device according to an embodiment of the present disclosure may include a display panel 200, a printed circuit board 104, a driver circuit chip 103, a control circuit chip 105 and the like. The shape of the Display Panel 200 can be modified as needed. For example, the Display Panel 200 can be rectangular with gently rounded corners, square, circular, or oval. The Display Panel 200 can include a display area AA and non-display areas NAA1 and NAA2. The Display Area AA of the Display Panel 200 can be an area where an image is displayed and can have a plurality of pixels P, data lines DL, and gate lines GL arranged within it. The non-display area NAA1 and NAA2 can be an area where the image is not displayed. The non-display area NAA1 and NAA2 can contain a first non-display area NAA1 and a second non-display area NAA2. The first non-display area NAA1 can be located in a peripheral (or edge) area of ​​the display panel 200, but it is not limited to this. For example, an area other than a light-emitting area that emits light outwards onto the display area AA can be designated as the first non-display area NAA1. A border area of ​​the display device can be defined by the first non-display area NAA1. The border area can surround an outer surface of the display area AA. For example, the border area can refer to the first non-display area NAAl, which surrounds an edge of the display panel 200. The second non-display area NAA2 can be located below the display panel 200. The second non-display area NAA2 can contain a flexible area BDA and a pad area PDA. The pad area PDA can contain a plurality of pads that are electrically connected to a printed circuit board 104 on which the control circuit chip 105 or the like is located. The driver circuit chip 103 can transmit data signals, touch signals, or the like to the majority of pixels on the display area AA via the majority of data lines DL or touch lines. For example, the driver circuit chip 103 can be a data driver circuit chip, but it is not limited to that. Lines for supplying electrical signals to or receiving electrical signals from display area AA can be located on non-display areas NAA1 and NAA2. For example, a gate driver that supplies gate signals to a plurality of subpixels SP1, SP2, and SP3 of display area AA can be located on the first non-display area NAA1. The gate drivers can be arranged at the right and left edges of the first non-display area NAA1 in a gate-in-panel (GIP) configuration. The gate driver can transmit the gate signals via the gate lines GL. The gate lines GL can extend in a first direction (X) of the display panel 200, and the data lines DL can intersect the gate lines GL and extend in a second direction (Y) of the display panel 200. The display panel 200 can be made of a flexible material. Accordingly, a section of the second non-display area NAA2 of the display panel 200 can be bent such that the circuit board 104, on which the control circuit chip 105 is located, faces a rear surface of the display area AA of the display panel 200. Consequently, the size of the second non-display area NAA2 on a lower side, as seen from the front of a display device 1, is reduced, so that a section of the bezel area in a lower section of the display panel 200 can be further reduced. The control circuit chip 105 can control the driver circuit chip 103 and the gate driver. A plurality of pixels is located on the display area AA. A pixel P on the display area AA can be composed of a plurality of subpixels SP1, SP2, and SP3. The image can be displayed on the display area AA using a plurality of subpixels SP1, SP2, and SP3. The plurality of subpixels SP1, SP2, and SP3 can be arranged in an array on the display area AA. For example, the plurality of subpixels SP1, SP2, and SP3 can be arranged in a matrix by spacing them from each other in the first direction and the second direction, which intersects the first direction of the display area AA. The first direction can be a horizontal direction, an X-axis direction, or a row direction, and the second direction can be a vertical direction, a Y-axis direction, or a column direction.However, the present disclosure is not limited to this, and the arrangement, order, and direction of the subpixels SP1, SP2, and SP3 can be modified in various ways. In the present disclosure, one embodiment is described in which a pixel P is composed of a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3, but the present disclosure is not limited thereto. For example, a pixel P may further include additional subpixels. The subpixels SP1, SP2, and SP3 can be implemented to emit light of the same color, such as white light, or they can be implemented to emit light of different colors, such as red, green, or blue light. For example, the first subpixel SP1 can emit red, the second subpixel SP2 can emit green, and the third subpixel SP3 can emit blue. Fig. 2 is a diagram showing a portable display device that includes a display panel according to an embodiment of the present disclosure. The display panel 200 according to one embodiment of the present disclosure can be applied to various types of display devices. One of the display devices to which the display panel 200 is applied is a portable display device. Referring to Fig. 2, a portable display device 100 according to one embodiment of the present disclosure can include the display panel 200, a frame 20, and a strap 30. In one example, the portable display device 100 can include a smartwatch phone. The display can include the display panel 200 shown in Fig. 1, which contains the display area AA and the non-display areas NAA1 and NAA2. The frame 20 can be a structure assembled to form the outer appearance of the portable display device 100. The display panel 200 according to one embodiment of the present disclosure can be placed in a space defined by the frame 20. Accordingly, the screen provided by the display area AA on a front surface of the portable device 100 can be made available to the user.The belt 30 can be a part for carrying and attaching the portable display device 100. Fig. 3 is a cross-sectional view along line II' in Fig. 1. Fig. 3 schematically shows a subpixel. In the present disclosure, a subpixel is illustrated as an example to facilitate description, but the present disclosure is not limited to this. The subpixel illustrated in Fig. 3 can be arranged on the display area AA. Referring to Fig. 3, the display panel 200 can include a pixel driver circuit comprising a plurality of transistors 220 and 240 arranged on a substrate 201, a light-emitting element 260 and a touch sensor 287. A subpixel can contain the light-emitting element 260 and the pixel driver circuit, which applies a driver current to the light-emitting element 260. The pixel driver circuit can be arranged on the substrate 201, and the light-emitting element 260 can be arranged on the pixel driver circuit. The pixel driver circuit can contain a plurality of transistors 220 and 240 and a storage capacitor 230. In one example, the plurality of transistors 220 and 240 can include a first transistor 220 and a second transistor 240. The substrate 201 can be a flexible plastic substrate. If the substrate 201 is a plastic film, it can contain several layers of an insulating material. For example, the substrate 201 can contain a first base layer 202, a second base layer 203, and a support layer 204. The first base layer 202 and the second base layer 203 can be arranged so that they are spaced apart from each other in a vertical direction, and the support layer 204 can be placed between them. A multi-layer buffer 207 can be arranged on the substrate 201. The multi-layer buffer 207 can be a structure in which a first buffer layer 205 and a second buffer layer 206 are arranged in the vertical direction. The first buffer layer 205 and the second buffer layer 206 can cover a surface of the substrate 201. The first buffer layer 205 and the second buffer layer 206 can reduce or prevent the penetration of moisture, oxygen, or contaminants through the substrate 201. The first buffer layer 205 and the second buffer layer 206 can consist of a single layer or multiple layers made of an inorganic insulating material such as silicon dioxide (SiOx) or silicon nitride (SiNx). A light-shielding layer 209 can be arranged on the multi-buffer layer 207. The light-shielding layer 209 prevents external light from reaching the transistor. For this purpose, the light-shielding layer 209 can contain an opaque metallic material. A first metal structure 209a can be arranged on the multi-buffer layer 207, spaced apart from the light-shielding layer 209. The first metal structure 209a can be made of the same material as the light-shielding layer 209 and formed using the same process. A third buffer layer 212 can be arranged on top of the light-shielding layer 209. The third buffer layer 212 can protect the transistor from moisture, oxygen, or impurities. The third buffer layer 212 can consist of a single layer or multiple layers made of, but is not limited to, an inorganic insulating material such as silicon dioxide (SiOx) or silicon nitride (SiNx). The third buffer layer 212 can cover the light-shielding layer 209 and the first metal structure 209a. The first transistor 220 can be located on the third buffer layer 212. The first transistor 220 can include a first semiconductor layer 221, a first gate insulating layer 222, a first gate electrode 223, and first source / drain electrodes 224. In one example, the first transistor 220 can be a switching transistor. The first semiconductor layer 221 can include a channel region and source / drain regions. A region of the first semiconductor layer 221 that overlaps the first gate electrode 223 in the vertical direction can be the channel region. The source / drain regions can be located on either side of the channel region. For example, a region located on one side of the channel region beneath the source / drain regions can be the source region, and a region located on the other side of the channel region can be the drain region. The first semiconductor layer 221 can consist of a polysilicon semiconductor layer and a low-temperature polysilicon semiconductor layer, or a combination thereof. The first semiconductor layer 221 can be arranged to overlap the light-shielding layer 209 in the vertical direction. The light-shielding layer 209 can prevent external light from falling on the first semiconductor layer 221. For this purpose, the light-shielding layer 209 can have a width that is at least equal to or greater than that of the first semiconductor layer 221. The first gate insulating layer 222 can be positioned between the first semiconductor layer 221 and the first gate electrode 223. The first gate insulating layer 222 can extend outwards while covering the first semiconductor layer 221. The first gate insulating layer 222 can consist of a single layer or multiple layers made of an inorganic insulating material such as silicon dioxide (SiOx) or silicon nitride (SiNx). The first gate electrode 223 can be located on the first gate insulating layer 222. The first source / drain electrodes 224 can be electrically connected to the first semiconductor layer 221 of the first transistor 220. In one example, the first source / drain electrodes 224 can be referred to as the first input / output electrodes. The first source / drain electrodes 224 can be located on either side, with the first gate electrode 223 positioned between them, and can each be in contact with the source region and the drain region of the first semiconductor layer 221. For example, one of the first source / drain electrodes 224 can be a source electrode in contact with the source region of the first semiconductor layer 221. For example, the other of the first source / drain electrodes 224 can be a drain electrode in contact with the drain region of the first semiconductor layer 221.If the first transistor 220 is the switching transistor, the source electrode can be an input electrode into which the data signals provided by the data lines DL (see Fig. 1) are input. The drain electrode can transmit the data signals to the second transistor 240. The drain electrode can be an output electrode that transmits the data signals. A second metal structure 223a can be arranged on the first gate insulating layer 222, spaced apart from the first gate electrode 223. The second metal structure 223a can be made of the same material as the first gate electrode 223 and formed using the same process. The second metal structure 223a can be arranged to overlap the first metal structure 209a in the vertical direction.A section of the second metal structure 223a can extend through the first gate insulating layer 222 and the third buffer layer 212 and be in direct contact with the first metal structure 209a. A lower interlayer insulating structure 215 can be arranged on the first gate electrode 223. The lower interlayer insulating structure 215 can include a first interlayer insulating layer 213 and a second interlayer insulating layer 214 arranged on top of the first interlayer insulating layer 213. The first interlayer insulating layer 213 can cover the first gate electrode 223. The first interlayer insulating layer 213 and the second interlayer insulating layer 214 can consist of a single layer or multiple layers made of an inorganic insulating material such as silicon dioxide (SiOx) or silicon nitride (SiNx). A third interlayer insulating layer 216 can be arranged on top of the second interlayer insulating layer 214. A third metal structure 225 can be arranged at a different position, spaced apart from the first transistor 220. The third metal structure 225 can be arranged between the second interlayer insulating layer 214 and the third interlayer insulating layer 216. The third metal structure 225 can contain a transition metal material with hydrogen-friendly properties and a hydrogen-trapping effect. For example, the third metal structure 225 can contain titanium (Ti). This will be described later. A fourth buffer layer 217 can be arranged on the third intermediate insulating layer 216. The fourth buffer layer 217 can protect the transistor from moisture, oxygen, or impurities. The fourth buffer layer 217 can consist of a single layer or multiple layers made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx). The second transistor 240 can be arranged on the fourth buffer layer 217 at a different position, spaced apart from the first transistor 220. The second transistor 240 can be electrically connected to the first transistor 220. For example, the second transistor 240 can include a second semiconductor layer 241, a second gate insulating layer 242, a second gate electrode 243, and second source / drain electrodes 245. In one example, the second transistor 240 can be a driver transistor electrically connected to the light-emitting element 260. However, Fig. 3 illustrates the connection relationships or the like to describe an example of a method for supplying the driver current to the light-emitting element 260, and the present disclosure is not limited thereto.For example, another switching transistor or another light-emitting transistor can be arranged between the light-emitting element 260 and the second transistor 240. The second semiconductor layer 241 can include a channel region and source / drain regions. A region of the second semiconductor layer 241 that overlaps the second gate electrode 243 in the vertical direction can be the channel region. The source / drain regions can be arranged on either side of the channel region. The second semiconductor layer 241 can be constructed as an oxide semiconductor layer. For example, it can contain at least one oxide semiconductor material such as indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO). In one example, the second semiconductor layer 241 can be arranged to at least partially overlap the first metal structure 209a and the second metal structure 223a in the vertical direction. Accordingly, the metal structures 209a and 223a can prevent external light from outside the substrate 201 from reaching the second semiconductor layer 241.Accordingly, it can be prevented that the properties of the second transistor 240 are changed by external light. Additionally, the second semiconductor layer 241 can be arranged to overlap the third metal structure 225 in the vertical direction. Since the third metal structure 225 contains a transition metal material that can trap hydrogen, the introduction of hydrogen into the second semiconductor layer 241, including the oxide semiconductor material, can be prevented. For this purpose, it is preferred that the third metal structure 225 be configured to have a size greater than the width of the second semiconductor layer 241. The second gate insulating layer 242 can be arranged between the second semiconductor layer 241 and the second gate electrode 243. The second gate insulating layer 242 can consist of a single layer or multiple layers made of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx). The first gate electrode 223 or the second gate electrode 243 can consist of a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu), or an alloy thereof. However, it is not limited to such materials. An upper interlayer structure 218 and 219 can be arranged on the second gate electrode 243. The upper interlayer structure 218 and 219 can include a fourth interlayer insulating layer 218 and a fifth interlayer insulating layer 219. The fourth interlayer insulating layer 218 and the fifth interlayer insulating layer 219 can consist of a single layer or multiple layers made of an inorganic insulating material such as silicon dioxide (SiOx) and silicon nitride (SiNx). The fourth intermediate insulating layer 218 can cover the second gate electrode 243. The storage capacitor 230 can contain a first storage electrode 231 and a second storage electrode 233. For example, the first storage electrode 231 can be located on the same layer as the second gate electrode 243. For example, the first storage electrode 231 can be made of the same material as the second gate electrode 243. The first storage electrode 231 can be located on the second gate insulating layer 242 at a different position, spaced apart from the second gate electrode 243. The second storage electrode 233 can be arranged on the fourth intermediate insulating layer 218 such that it overlaps the first storage electrode 231 in the vertical direction. The first storage electrode 231 and the second storage electrode 233 can consist of a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu), or an alloy thereof. However, the present disclosure is not limited to such materials. The second storage electrode 233 can be covered with the fifth intermediate insulating layer 219. The first source / drain electrodes 224 and the second source / drain electrodes 245 can be arranged on the fifth interlayer insulating layer 219. The first source / drain electrodes 224 can be in direct contact with the source / drain regions of the first semiconductor layer 221 or connected to them by extending through the upper interlayer structure 218 and 219, the fourth buffer layer 217, the third interlayer insulating layer 216, a lower interlayer structure 215, and the first gate insulating layer 222. The first source / drain electrodes 224 can be arranged on both opposite sides, with the first gate electrode 223 positioned between them. The second source / drain electrodes 245 can be in direct contact with and connected to the source / drain regions of the second semiconductor layer 241 by extending through the upper interlayer structure 218 and 219. A section of the second source / drain electrodes 245 of the second transistor 240 can be electrically connected to the third metal structure 225. For example, the section of the second source / drain electrodes 245 can be in direct contact with and connected to the third metal structure 225 by extending through the upper interlayer structure 218 and 219, the second gate insulating layer 242, the fourth buffer layer 217, and the third interlayer insulating layer 216. In this example, the second source / drain electrodes 245 can be referred to as the second input / output electrodes.The second source / drain electrodes 245 can be arranged on either opposite side, with the second gate electrode 243 positioned between them, and can each be in contact with the source region and the drain region of the second semiconductor layer 241. For example, one of the second source / drain electrodes 245 can be a source electrode in contact with the source region of the second semiconductor layer 241. Similarly, the other of the second source / drain electrodes 245 can be a drain electrode in contact with the drain region of the second semiconductor layer 241. If the second transistor 240 is the driver transistor, the source electrode can be an input electrode into which the data signals provided by the data lines DL (see Fig. 1) are input. The drain electrode can transfer the driver current to the light-emitting element 260.The drain electrode can be an output electrode from which the driver current is emitted. The first source / drain electrodes 224 or the second source / drain electrodes 245 may consist of a single layer or multiple layers made of molybdenum (Mo), aluminium (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) or copper (Cu) or an alloy thereof, but may not be limited to these. A passivation layer 247 can be arranged on the first source / drain electrodes 224 or the second source / drain electrodes 245. The passivation layer 247 can consist of a single layer or multiple layers containing an inorganic insulating material such as silicon oxide, silicon nitride, and silicon oxynitride. The passivation layer 247 can protect the pixel driver circuitry located below it. A planarization layer 250 can be arranged on top of the passivation layer 247. The planarization layer 250 can planarize a stage caused by the underlying pixel driver circuitry. The planarization layer 250 can be arranged in a structure in which multiple planarization layers are stacked from bottom to top. For example, the drawing illustrates the planarization layer 250 in a structure in which a first planarization layer 251 and a second planarization layer 252 are stacked vertically, but it is not limited to this. For example, a multilayer structure can be included in which a third planarization layer (not shown) is deposited on top of the second planarization layer 252. For example, the planarization layer 250 can contain an organic insulating material such as polyimide or acrylic resin. A pixel contact electrode 255 can be arranged on the first planarization layer 250. The pixel contact electrode 255 can extend through the first planarization layer 250 and the passivation layer 247 and be in direct contact with the second source / drain electrodes 245 of the second transistor 240. The light-emitting element 260 can be formed on the planarization layer 250. For example, the light-emitting element 260 can be arranged on the second planarization layer 252. The light-emitting element 260 can comprise a first electrode 261, a light-emitting layer 263, a second electrode 265, and a cover layer 267. The light-emitting element 260 can be electrically connected to the pixel driver circuit via the first electrode 261. For example, the first electrode 261 can extend through the second planarization layer 252 and be in direct contact with the pixel contact electrode 255. Accordingly, the first electrode 261 can be electrically connected to the second transistor 240 via the pixel contact electrode 255. However, Fig. 2 serves to describe an example of a method for supplying current to the first electrode, and the present disclosure is not limited to a physical contact between the second transistor 240, which is the driver transistor, and the first electrode 261. In one example, the switching transistor that is electrically connected to the first electrode 261 can be the light-emitting transistor.For example, the light-emitting transistor can control an on and an off state of the light-emitting element 260. The pixel contact electrode 255 can contain a conductive material. For example, the pixel contact electrode 255 can contain a metallic material such as aluminum (Al), chromium (Cr), copper (Cu), titanium (Ti), molybdenum (Mo), and tungsten (W). In one example, the pixel contact electrode 255 can have a multilayer structure of titanium / aluminum / titanium (Ti / Al / Ti). In another example, the pixel contact electrode 255 can be electrically connected to a high-potential supply line (VDD line). The first electrode 261 can contain a transparent conductive film. For example, the first electrode 261 can contain indium tin oxide (ITO) or indium zinc oxide (IZO). Alternatively, the first electrode 261 can contain a single-layer or multi-layer structure incorporating a reflective metal film made of silver (Ag), aluminum (Al), gold (Au), nickel (Ni), or chromium (Cr), or an alloy thereof. The first electrode 261 can also be referred to as the anode electrode or pixel electrode. A bank 262 can be arranged on the first electrode 261. The bank 262 can be arranged to cover an edge of the first electrode 261. A section of the bank 262 can extend onto and along the second planarization layer 252. An upper surface of the first electrode 261 that is not covered by the bank 262 and is exposed can become a light-emitting area. The bank 262 can contain a black material, a light-shielding material, or a light-absorbing material. The bank 262 can contain a material that absorbs light in a specific wavelength range. The bank 262 can be in a structure in which at least two color filters of different colors—a red color filter, a green color filter, and a blue color filter—are stacked. The bank 262 can be made of an organic insulating material.Bank 262 may contain, for example, light-sensitive polyimide, photoacrylic or benzocyclobutene (BCB). The light-emitting layer 263 can be arranged on the first electrode 261. The light-emitting layer 263 can include a hole transport layer (HTL), an organic light-emitting layer (EML), an electron transport layer (ETL), a hole-blocking layer (HBL), a hole injection layer (HIL), an electron-blocking layer (EBL), and an electron injection layer (EIL) as components. The light-emitting layer 263 can have a multi-stack structure in which two or more organic light-emitting layers (EMLs) are stacked. Of the components of the light-emitting layer 263, the electron injection layer (EIL), the electron-blocking layer (EBL), the hole transport layer (HTL), and the hole-blocking layer (HBL) can be arranged as common layers over an entire area of ​​the display area AA and a portion of the non-display area AA.Furthermore, the organic light-emitting layer (EML) may be located only on the pixels in the display area AA. Alternatively, the organic light-emitting layer (EML) may be located as a common layer on both the display area AA and the non-display area AA. The second electrode 265 can be arranged on the light-emitting layer 263. The second electrode 265 can generally be connected to the light-emitting layer 263, which is formed on all pixels. Therefore, the second electrode 265 can also be referred to as the cathode electrode or common electrode. The second electrode 265 can contain a semi-transparent conductive material. For example, the second electrode 265 can be made of a metallic material such as magnesium (Mg), silver (Ag), or an alloy (Ag-Mg) of silver (Ag) and magnesium (Mg). In one example, the second electrode 265 can contain a transparent conductive film made of indium tin oxide (ITO) or indium zinc oxide (IZO). Although not shown in the drawing, the display area AA in one example can contain multiple transmission areas.If the transmission areas are present in the display area AA, the second electrode 265 can be positioned on the display area AA such that it does not overlap the transmission areas. For example, the transmission areas can be areas where no opaque or reflective material is located. A cover layer 267 can be arranged on the second electrode 265. The cover layer 267 can prevent light generated by the light-emitting layer 263 from being lost, thereby improving the light extraction efficiency. An encapsulation stack 270 can be arranged on the light-emitting element 260. The encapsulation stack 270 can protect the light-emitting element 260 from external oxygen or moisture. The encapsulation stack 270 can cover the display area AA and extend into the non-display area NAA, which is located outside the display area AA. The encapsulation stack 270 can contain a multilayer structure in which a first encapsulation layer 271, a second encapsulation layer 273, and a third encapsulation layer 275 are arranged. The second encapsulation layer 273 can be a component arranged between the first encapsulation layer 271 and the third encapsulation layer 275. The first encapsulation layer 271 can be arranged on a cover layer 267. The second encapsulation layer 273 can be arranged on the first encapsulation layer 271. The second encapsulation layer 273 can cover the first encapsulation layer 271 and can have a sufficient thickness to form a flat surface. The second encapsulation layer 273 can prevent foreign substances from penetrating the light-emitting element 260. The third encapsulation layer 275 can be arranged on the second encapsulation layer 273. Each of the first encapsulation layer 271 and the third encapsulation layer 275 can contain an inorganic insulating material, and the second encapsulation layer 273 can contain an organic insulating material. For example, each of the first encapsulation layer 271 and the third encapsulation layer 275 can contain at least one material made of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). The second encapsulation layer 273 can contain at least one material made of epoxy, polyimide, polyethylene, and acrylate. A touch unit can be arranged on the encapsulation stack 270. The touch unit can include a touch buffer layer 277, the touch sensor 287, a touch intermediate layer insulating layer 282, and a touch protection layer 290. The touch buffer layer 277 can be arranged on the third encapsulation layer 275. The touch buffer layer 277 can dissipate stress between the encapsulation stack 270 and the touch sensor 287, thereby preventing damage to the encapsulation stack 270 and the light-emitting element 260. The touch buffer layer 277 can contain an inorganic insulating material. For example, the touch buffer layer 277 can contain silicon nitride (SiNx). The touch sensor 287 can include a plurality of touch electrodes 285 and a bridge electrode 281. The plurality of touch electrodes 285 and the bridge electrode 281 can be arranged in different layers. For example, the bridge electrode 281 can be arranged on the touch buffer layer 277. The plurality of touch electrodes 285 can be arranged on the contact intermediate layer insulating layer 282. The plurality of touch electrodes 285 can include a first touch electrode 283 and a second touch electrode 284. The bridge electrode 281 can electrically connect adjacent first touch electrodes 283. For this purpose, the first touch electrode 283 can extend through the contact intermediate layer insulating layer 282 and be in contact with the bridge electrode 281. The contact intermediate layer insulating layer 282 can contain an inorganic insulating material.For example, the contact interlayer insulating layer can contain silicon nitride (SiNx). The first contact electrode 283, the second contact electrode 284, or the bridge electrode 281 may contain a conductive material. The first contact electrode 283, the second contact electrode 284, or the bridge electrode 281 may contain a single layer or multiple layers made of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), or copper (Cu), or an alloy thereof. The touch buffer layer 277 and the touch intermediate insulating layer 282 can be in contact with each other in the vertical direction to form a touch insulating structure 280. The touch protection layer 290 can be arranged on the touch sensor 287. The touch protection layer 290 can prevent damage to the touch sensor 287 resulting from external impact and moisture. The touch protection layer 290 can contain an organic insulating material. For example, the touch protection layer 290 can contain a photosensitive organic acrylic or polyimide material. In one example, to improve the product characteristics of the display panel 200, which is applied to the portable display device 100, such as the smartwatch phone, the second semiconductor layer 241 of the second transistor 240 in Fig. 3, which is the driver transistor, can contain an oxide semiconductor layer. Since the second semiconductor layer 241 is the oxide semiconductor layer, the second transistor 240 can be an oxide thin-film transistor. If the second transistor, 240, is the oxide thin-film transistor, the hysteresis characteristics of the element can be improved. For example, the oxide thin-film transistor can exhibit smaller hysteresis than a thin-film transistor with a polysilicon semiconductor layer applied to it. If the hysteresis is large, the threshold voltage can shift significantly, which can impair the operational stability of the light-emitting element. On the other hand, if the hysteresis is small, there is almost no change in the threshold voltage shift, allowing the light-emitting element to operate stably, which can increase operational reliability. The oxide semiconductor layer that forms the oxide thin-film transistor is sensitive to hydrogen. Accordingly, when the oxide thin-film transistor is exposed to hydrogen, the threshold voltage shifts in a negative direction, causing a phenomenon where current flows even at a low gate voltage, which can lead to a problem such as a bright spot defect. Figures 4, 5, and 6 are diagrams showing threshold voltage values ​​measured based on positions on a display panel. In Figures 4, 5, and 6, an X-axis can represent the position of a subpixel as measured while moving from the display area AA of the display panel to an edge area EG. A Y-axis can represent a threshold voltage value V. For example, Figure 4 shows a measurement at a lower section of display panel 200, Figure 5 shows a measurement at a left or right section of display panel 200, and Figure 6 shows a measurement at an upper section of display panel 200. Referring to Figures 4, 5 to 6, it can be seen that at all measurement points, such as the upper, lower, left, or right section of the display panel 200, the threshold voltage value V shifts in the negative (-) direction from the reference threshold voltage values ​​Vth_A, Vth_B, and Vth_C to shifted threshold voltage values ​​Vth_A-Δ, Vth_B-Δ, and Vth_C-Δ when the position moves from the display area AA to the edge area EG. The shifted threshold voltage values ​​Vth_A-Δ, Vth_B-Δ, and Vth_C-Δ can be smaller than the reference threshold voltage values ​​Vth_A, Vth_B, and Vth_C. Accordingly, the bright spot defect can occur, in which the subpixel SP, located on the edge area EG of the display panel 200, emits light independently of an operational signal. Therefore, in order to prevent the occurrence of the bright spot defect or the like, and to use the oxide thin-film transistor as the driver transistor, it is important to prevent hydrogen from being introduced from the outside of the display panel 200. The display device according to one embodiment of the present disclosure can include a plurality of barrier structures that can prevent the properties of an oxide semiconductor from being altered by hydrogen ingress into the driver transistor. The plurality of barrier structures can prevent hydrogen from being introduced from the edge region of the display panel 200 to the display area AA. Accordingly, the plurality of barrier structures can prevent the bright spot defect from occurring due to the threshold voltage shift in the negative direction resulting from hydrogen ingress into the driver transistor. The majority of barrier structures can be arranged on the border area that surrounds the outside of the display area AA. For example, the majority of barrier structures can be arranged across an entire area of ​​the border area. For example, the majority of barrier structures can be arranged at locations such as the top, bottom, left, or right section of the display panel 200. Additionally, the majority of barrier structures can be arranged to surround subpixels SP that are located by the subpixels SP on the display area AA at an outermost area adjacent to the border area. The majority of barrier structures can be formed in the same process as the components that form the subpixels SP on the display area AA. For example, the barrier structures can be referred to as dummy subpixels. Fig. 7 is an enlarged view of area 'II' in Fig. 1. Fig. 8 is a cross-sectional view along line VI-VI' in Fig. 7. For example, Fig. 7 may represent an upper corner of the bounding area of ​​the first non-display area NAA1 of display panel 200. Fig. 8 may represent a barrier structure of a first size among the barrier structures. For example, one of the barrier structures of the first size may be designated as a first dummy subpixel DP_1. In Fig. 8, components identical to those in Fig. 5 may be designated with the same reference numerals. Accordingly, redundant descriptions are omitted or brief, and differences are described. Referring to Fig. 7, the majority of subpixels SP can be arranged on the display area AA. The majority of subpixels SP can be those located at the outermost region of the display area AA. Each subpixel SP can have a first length L_P. A subpixel SP located on the display area AA can contain the same components as the subpixel shown in Fig. 3. For example, the second transistor 240, which is the driver transistor, can contain the second semiconductor layer 241, which is the oxide semiconductor. The first non-display area NAA1 can be defined outside the display area AA. The first non-display area NAA1 can contain a first dummy pixel area TS_DPA and a connecting line area 300. A power line or a signal line containing the high-potential supply (VDD) line can be located on the connecting line area 300. The connecting line area 300 can be referred to as the GIP line area. The connecting line area 300 can be a border area surrounding the top, bottom, left, or right section of the display panel 200. The first dummy pixel area TS_DPA can be defined at the top corner of the border area of ​​the first non-display area NAA1. The plurality of first dummy subpixels DP_1 can be located on the first dummy pixel area TS_DPA. Each of the first dummy subpixels DP_1 can have a second length L_DP-1.The second length L_DP-1 of the first dummy subpixel DP_1 can be equal to the first length L_P of the subpixel SP, which is located at the outermost area of ​​the display area AA. The first non-display area NAA1 can contain a first gap area GA1 defined between the display area AA and the link line area 300. A portion of the first gap area GA1 adjacent to the display area AA in the first non-display area NAA1 can be filled by the plurality of first dummy subpixels DP_1 arranged on the first dummy pixel area TS_DPA. For example, at least two rows of the plurality of first dummy subpixels DP_1 can be arranged outside the subpixels SP located at the outermost region of the display area AA. The first dummy subpixel DP_1 can contain a configuration in which the third metal structure, which traps hydrogen, is arranged to overlap the second semiconductor layer 241. This is described below with reference to Fig. 8. Referring to Fig. 7 and Fig. 8, the first dummy subpixel DP_1 can comprise the lower interlayer insulating structure 207, the light-shielding layer 209, and the third buffer layer 212, which are arranged between the first transistor 220 and the substrate 201. The first transistor 220 can include the first semiconductor layer 221, the first gate insulating layer 222, the first gate electrode 223, and the first source / drain electrodes 224. The second transistor 240 and the storage capacitor 230 can be arranged at different locations spaced apart from the first transistor 220. The second transistor 240 can include the second semiconductor layer 241, the second gate insulating layer 242, the second gate electrode 243, and the second source / drain electrodes 245. The second semiconductor layer 241 of the second transistor 240 can be configured as an oxide semiconductor layer. For example, the second semiconductor layer 241 can contain at least one oxide semiconductor material such as indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO). The upper interlayer structure 218 and 219, including the fourth interlayer insulating layer 218 and the fifth interlayer insulating layer 219, can be arranged on the second gate electrode 243 of the second transistor 240. The first source / drain electrodes 224 and the second source / drain electrodes 245 can be arranged on the fifth intermediate insulating layer 219. The first source / drain electrodes 224 can be associated with the source / drain regions of the first semiconductor layer 221 by extending through the insulating layers below. The second source / drain electrodes 245 can be in direct contact with and associated with the source / drain regions of the second semiconductor layer 241 by extending through the upper intermediate layer structure 218 and 219, respectively. Sections of the second source / drain electrodes 245 of the second transistor 240 can be in direct contact with the third metal structure 225 by extending through the insulating layers below. The storage capacitor 230 can contain the first storage electrode 231 and the second storage electrode 233, which overlap each other in the vertical direction, with the fourth interlayer insulating layer 218 of the upper interlayer structure 218 and 219 arranged between them. The passivation layer 247, which contains the inorganic insulating material, can cover the first source / drain electrodes 224 and the second source / drain electrodes 245. The first planarization layer 250 can be arranged on the passivation layer 247. The pixel contact electrode 255 can be arranged on the first planarization layer 251. The pixel contact electrode 255 can be arranged on the second transistor 240. A section of the pixel contact electrode 255 can be in direct contact with one of the second source / drain electrodes 245 by extending through the first planarization layer 251 and the passivation layer 247. In the first dummy subpixel DP_1, the pixel contact electrode 255 is electrically connected to the pixel contact electrode 255 of the display area AA and can therefore be electrically connected to the high-potential supply line (VDD line). For example, the high-potential supply line (VDD line) can be located on the connecting line area 300 of the first non-display area NAA1. The second planarization layer 252 can be arranged on top of the first planarization layer 251 and the pixel contact electrode 255. The pixel contact electrode 255 of the first dummy subpixel DP_1 is covered by the second planarization layer 252. Accordingly, the second transistor 240 of the first dummy subpixel DP_1 can be a dummy transistor that does not function as the driver transistor. The planarization layer 250 can consist of the first planarization layer 251 and the second planarization layer 252. The planarization layer 250 can flatten the step caused by the lower circuit structure. An organic insulating structure 262a can be arranged on the planarization layer 250. The organic insulating structure 262a can be made of the same material as the bank 262 on the display area AA and formed in the same process. The organic insulating structure 262a can cover an entire surface of the second planarization layer 252 in the first dummy subpixel DP_1. In the first dummy subpixel DP_1, the second semiconductor layer 241 of the second transistor 240 can be arranged to overlap the third metal structure 225 in the vertical direction. The third metal structure 225 can contain the transition metal material capable of trapping hydrogen. This prevents hydrogen from being introduced into the second semiconductor layer 241, including the oxide semiconductor material. For example, the third metal structure 225 can contain titanium (Ti). The third metal structure 225 can be configured to be larger than the width of the second semiconductor layer 241 to prevent hydrogen from entering the second semiconductor layer 241. The majority of first dummy subpixels DP_1 can be arranged along the first direction (X) or the second direction (Y) outside the subpixels SP located at the outermost region of the display area AA. Each of the first dummy subpixels DP_1 can form a barrier structure that blocks hydrogen inflow. Additionally, the majority of first dummy subpixels DP_1 can be arranged outside the subpixels SP located at the outermost region. Accordingly, the first dummy subpixels DP_1 can be arranged in a multi-stage structure to block hydrogen inflow. Therefore, the majority of first dummy subpixels DP_1 can prevent hydrogen from being introduced from the outside of an upper distal corner of the display panel 200 to the subpixels SP on the display area AA.Additionally, the majority of first dummy subpixels DP_1 can be located at the first gap area GA1 of the first non-display area NAA1 at the upper corner of the border area. Accordingly, the upper corner of the border area of ​​the first non-display area NAA1 does not require any additional space, even if the barrier structures are arranged in the multi-level structure, thus minimizing the border area. According to one embodiment of the present disclosure, a structure in region 'II', located at the first corner of the display panel 200, may also be present in the fourth corner of the display panel. In this light, the first dummy subpixels DP_1 may be arranged in columns in the X-axis direction from the display area AA to the connecting line area 300, or in the Y-axis direction from the display area AA to the connecting line area 300, such that one or more first dummy subpixels DP_1 can separate the subpixel SP, located at the outermost region of the display area AA, and the connecting line area 300 for each row or column of the first dummy subpixels DP_1. In embodiments of the present disclosure, the number of first dummy subpixels DP_1 in the first dummy pixel area TS_DPA may be the same or may vary from row to row or column to column.In the first dummy pixel area TS_DPA, a step structure can be formed between adjacent rows or columns of the first dummy subpixel DP_1. According to one embodiment of the present disclosure, the organic insulating structure 262a can be arranged on the planarization layer 250 as a film without any recesses on it in the first dummy pixel region TS_DPA. For example, the organic insulating structure 262a does not cover the first electrode 261 in the first dummy pixel region TS_DPA, and the first dummy pixel region TS_DPA can be without the light-emitting element 260. Fig. 9 is an enlarged view of region 'III' in Fig. 1. For example, it may show an upper section of the border region of the first non-display region NAA1 of the display panel 200. Referring to Fig. 9, the majority of subpixels SP may be arranged on the display region AA. The majority of subpixels SP may be those located at the outermost region of the display region AA. Each subpixel SP may have a first length L_P. A subpixel SP located on the display region AA may contain the same components as the subpixel shown in Fig. 3. For example, the second transistor 240, which is the driver transistor, may contain the second semiconductor layer 241, which is the oxide semiconductor. The first non-display area NAA1 can be defined outside the display area AA. The first non-display area NAA1 can contain the first gap area GA1. The first gap area GA can contain a second dummy pixel area TS_DPA1. A plurality of second dummy subpixels DP_2 can be arranged around the second dummy pixel area TS_DPA1. The second dummy subpixel DP_2 can contain the configuration of the first dummy subpixel DP_1 in Fig. 8. For example, the second dummy subpixel DP_2 can contain the same component as the second semiconductor layer 241 (see Fig. 8), which is the oxide semiconductor. Additionally, the second dummy subpixel DP_2 can be arranged such that the third metal structure 225 (see Fig. 8) overlaps the second semiconductor layer 241 for hydrogen trapping. The second dummy subpixels DP_2 can be arranged in at least two columns: a first column adjacent to the subpixels SP located at the outermost part of the display area AA, and a second column outside the first column. For example, the length of a second dummy subpixel DP_2 can be equal to the first length L_P of the subpixel SP in the display area AA. Additionally, the total length of the second dummy subpixels DP_2 arranged in the two columns on the second dummy pixel area TS_DPA1 can be a second length L_DP-2. The second length L_DP-2 can be greater than the first length L_P. A section of the first gap region GA1 adjacent to the display area AA in the first non-display area NAA1 can be filled with a plurality of second dummy subpixels DP_2. For example, the plurality of second dummy subpixels DP_2 can be arranged in at least two columns in the second direction (Y) of the display area AA. Accordingly, the second dummy subpixels DP_2, which can block hydrogen inflow, can be arranged in a multi-level structure. The second dummy subpixel DP_2 can be one of the barrier structures of the first size. Additionally, the second dummy subpixel DP_2 can be referred to as a second barrier structure. Therefore, hydrogen can be prevented from being introduced into the subpixel SP on the display area AA in one direction of an upper distal end 200T_E of the display panel 200.Additionally, the majority of second dummy subpixels DP_2 can be located at the first gap area GA1 of the first non-display area NAAl on the upper part of the border area. Accordingly, even if the second barrier structures arranged in the multi-level structure are located on the upper part of the border area, no additional space is required, thus minimizing the border area. According to one embodiment of the present disclosure, a structure in region 'III', located at the upper section of the display panel 200, can also be present in the right and left side sections of the display panel 200. In this light, the second dummy subpixels DP_2 can be arranged in the Y-axis direction from the display area AA to the upper distal end 200T_E of the display panel 200 at the upper section of the display panel 200, and the second dummy subpixels DP_2 can be arranged in the X-axis direction from the display area AA to the connecting line region 300 when located at the right and left side sections of the display panel 200. Accordingly, one or more second dummy subpixels DP_2 can separate the subpixel SP, located at the outermost region of the display area AA, from the upper distal end 200TE_E and the connecting line region 300. According to one embodiment of the present disclosure, the organic insulating structure 262a can be arranged on the planarization layer 250 as a film without any recesses on it in the second dummy pixel region TS_DPA1. For example, the organic insulating structure 262a does not cover the first electrode 261 in the second dummy pixel region TS_DPA1, since the second dummy pixel region TS_DPA1 can be without the light-emitting element 260. Fig. 10 is an enlarged view of area 'IV' in Fig. 1. Fig. 11 is an enlarged view of area 'V' in Fig. 1. Fig. 12 is a cross-sectional view along line VII-VII' in Fig. 4. In Figs. 10, 11 to 12, the same components as those in Figs. 7 and 8 can be designated with the same reference numerals. Accordingly, redundant descriptions are omitted or brief, and differences are described. For example, Fig. 10 can represent a lower corner facing the lower section of display panel 200. Fig. 11 can represent a lower section of the border area of ​​the first non-display area NAA1 of display panel 200. Referring to Fig. 10, the majority of subpixels SP can be arranged at the outermost region of the display area AA. In Fig. 10, the outermost region of the display area AA can be the region closest to the border area. Each subpixel SP can have a first length L_P. A subpixel SP arranged on the display area AA can contain the same components as the subpixel in Fig. 3. For example, the second semiconductor layer 241, which is the oxide semiconductor, can be contained within the second transistor 240, which is the driver transistor. The first non-display area NAA1 can be located outside the display area AA. The first non-display area NAA1 can contain a third dummy pixel area B_DPA1 and the interconnection line area 300, which is defined outside the display area AA. The power line or signal line containing the high-potential supply (VDD) line can be located on the interconnection line area 300. The interconnection line area 300 can be referred to as the GIP line area. The interconnection line area 300 can be the border area surrounding the top, bottom, left, or right section of the display panel 200. The third dummy pixel area B_DPA1 can be defined at a bottom corner of the border area of ​​the first non-display area NAA1. In one example, the third dummy pixel area B_DPA1 and the interconnection line area 300 can extend to the border area below the display panel 200. A plurality of third dummy subpixels DP_3 can be arranged at a third dummy pixel area B_DPA. Each of the third dummy subpixels DP_3 can have a third length L_DP-3. The third length L_DP-3 of the third dummy subpixel DP_3 can be equal to the first length L_P of the subpixel SP, which is positioned at the outermost part of the display area AA. Additionally, the third dummy subpixel DP_3 can have the same size as the first dummy subpixel DP_1. The first non-display area NAA1 can contain the first gap area GA1, which is defined between the display area AA and the link line area 300. A portion of the first gap area GA1 can be filled by the plurality of third dummy subpixels DP_3, which are arranged on the third dummy pixel area B_DPA1. The plurality of third dummy subpixels DP_3 can be arranged in a multi-level structure outside the subpixels SP, which are located at the outermost region of the display area AA. The third dummy subpixel DP_3 can be one of the barrier structures of the first size. Additionally, the third dummy subpixel DP_3 can be designated as a third barrier structure. The third dummy subpixel DP_3 can have a configuration in which the third metal structure 225 for trapping hydrogen is arranged to overlap the second semiconductor layer 241. The configuration of the third dummy subpixel DP_3 can be the same as that of the first dummy subpixel DP_1 shown in Fig. 8. The majority of dummy subpixels, acting as barrier structures, can be arranged on the bezel area surrounding the outside of display area AA to prevent hydrogen from being introduced from the outside of display panel 200 into the driver transistor on display area AA. For example, the majority of dummy subpixels can be arranged over an entire area of ​​the bezel area. The display panel 200, which is applied to the portable display device 100, such as a smartwatch phone, can have a very narrow bezel area. In one embodiment of the present disclosure, the dummy subpixels DP_1, DP_2, and DP_3 can be arranged at the first gap area GA1 on the bezel area, thereby minimizing sections of the bezel area at the top, left, and right side sections of the display panel 200. In one example, a section of the border area at the bottom of the display panel 200 may be relatively narrower than the sections of the border area at the top, left and right of the display panel 200. According to one embodiment of the present disclosure, a structure in region 'IV', which is the second corner of the display panel 200, can also be present in the third corner of the display panel 200. In this light, the third dummy subpixels DP_3 can be arranged in rows in the X-axis direction from the display area AA to the connecting line area 300, or in columns in the Y-axis direction from the display area AA to the connecting line area 300, such that one or more first dummy subpixels DP_1 can separate the subpixel SP, which is located at the outermost region of the display area AA, and the connecting line area 300 for each row or column of the third dummy subpixels DP_3. In embodiments of the present disclosure, the number of third dummy subpixels DP_3 in the third dummy pixel area B_DPA1 can be the same or different from row to row or column to column.In the third dummy pixel area B_DPA1, a step structure can be formed between adjacent rows or columns of the third dummy subpixel DP_3. In one embodiment of the present disclosure, the plurality of dummy subpixels, which are the barrier structures that prevent the ingress of hydrogen, can also be arranged on the section of the bezel area on the lower section of the display panel 200 that is relatively narrower. Referring to Fig. 11, the majority of subpixels SP can be arranged on the display area AA. The majority of subpixels SP can be those located at the outermost region of the display area AA. Each subpixel SP can have a first length L_P. A subpixel SP located on the display area AA can contain the same components as the subpixel shown in Fig. 3. For example, the second transistor 240, which is the driver transistor, can contain the second semiconductor layer 241, which is the oxide semiconductor. The first non-display area NAA1 can be defined outside the display area AA. The first non-display area NAA1 can also be referred to as the border area. The first non-display area NAA1 can contain a second gap area GA2, which is defined between the display area AA and the bendable area BDA. The second gap area GA2 can be smaller than the first gap area GA1, which is located at the top, left, and right side sections of the display panel 200. The second gap area GA2 can contain the third dummy pixel area B_DPA1 and a fourth dummy pixel area B_DPA2. The third dummy pixel area B_DPA1 can be defined in the border area section at the bottom of the display panel 200. For example, the bottom section of the border area can be located between the display area AA and the bendable area BDA. The third dummy pixel area, B_DPA1, can be located between the display area AA and the bendable area BDA. For example, the third dummy pixel area B_DPA1 can be an area extending from the border area at the bottom corner of display panel 200 in Fig. 10. The fourth dummy pixel area, B_DPA2, can be located between the third dummy pixel area B_DPA1 and the bendable area BDA. For example, the fourth dummy pixel area B_DPA2 can have a smaller area than the third dummy pixel area B_DPA1. The majority of third dummy subpixels DP_3 can be located on the third dummy pixel area B_DPA1. Each third dummy subpixel DP_3 can have the third length L_DP-3. The third length L_DP-3 of the third dummy subpixel DP_3 can be equal to the first length L_P of the subpixel SP located on the display area AA. The third dummy subpixel DP_3 can be one of the first-size barrier structures. Additionally, the third dummy subpixel DP_3 can be referred to as the third barrier structure. A plurality of fourth dummy subpixels DP_4 can be arranged on the fourth dummy pixel area B_DPA2. Each of the fourth dummy subpixels DP_4 can have a fourth length L_DP-4. The fourth dummy subpixel DP_4 can be one of the barrier structures of a second size. Additionally, the fourth dummy subpixel DP_4 can be designated as a fourth barrier structure. The fourth length L_DP-4 of the fourth dummy subpixel DP_4 can be smaller than the third length L_DP-1 of the third dummy subpixel DP_3. The fourth dummy subpixels DP_4 can be smaller than the first dummy subpixels DP_1 or the second dummy subpixels DP_2, which are arranged at the top, left, and right side sections of display panel 200. Accordingly, the third dummy subpixels DP_3, which are the same size as the subpixels SP, are arranged in the narrow lower portion of the bounding area. Then, the fourth dummy subpixels DP_4, which are smaller than the third dummy subpixels DP_3, are arranged, even if only a small space remains. This makes it possible to arrange the multiple dummy subpixels in the lower portion of the bounding area. Additionally, the third dummy subpixels DP_3 and the fourth dummy subpixels DP_4, which have different sizes, can be arranged in the second gap area GA2, which is smaller than the first gap area GA1. Since no additional space is required for arranging the dummy subpixels, the bounding area can be minimized. The fourth dummy subpixel DP_4 is smaller than the other dummy subpixels, while the third metal structure 225, which contains the transition metal material with the hydrogen-trapping effect, can increase the structure density ratio in the fourth dummy subpixel DP_4. For example, the structure density ratio of the third metal structure 225 in the fourth dummy subpixel DP_4, which is smaller than the other dummy subpixels, can be at least 30%. For example, the structure density ratio of the third metal structure 225 can be 31%. Although not shown in the drawing, a dummy subpixel smaller than the fourth dummy subpixel DP_4 can be constructed. In this case, the structure density ratio of the third metal structure 225 in the dummy subpixel smaller than the fourth dummy subpixel DP_4 can be at least 20%. For example, the structure density ratio of the third metal structure 225 can be 24%.The structure density ratios of the third metal structure 225 in the first to third subpixels DP_1, DP_2, and DP_3, which are relatively larger than the fourth dummy subpixel DP_4, can be equal to or less than 9%. Accordingly, the structure density ratio of the third metal structure 225 in the fourth dummy subpixel DP_4 is relatively higher than those in other dummy subpixels. If the structure density ratio of the third metal structure 225 in the dummy subpixel is high, hydrogen introduced from the outside can be more effectively blocked for the same area size. Accordingly, since the multiple dummy subpixels, which have different sizes, are arranged on the narrow rim area and block hydrogen introduced from the outside, it is prevented that elemental properties of the oxide thin-film transistor are degraded or changed. Therefore, the occurrence of the bright spot defect on the outer section of the display panel 200, caused by deterioration or a change in the element properties of the driver transistor, can be prevented. Accordingly, the defect rate of the display device resulting from the bright spot defect or similar issues can be reduced, and thus the energy required for the additional production of the display device can be reduced, which can lower greenhouse gas emissions. Referring to Figures 11 and 12 together, the fourth dummy subpixel DP_4, located on the fourth dummy pixel area B_DPA2, can have the lower intermediate layer insulating structure 207 and the third buffer layer 212 arranged on the substrate 201. The first semiconductor layer 221 can be located on the third buffer layer 212. The first semiconductor layer 221 can be made of the same material as the first semiconductor layer 221 of subpixel SP of display area AA and the second dummy subpixel DP_2, and can be formed using the same process. For example, the first semiconductor layer 221 can be made of a polysilicon semiconductor layer and a low-temperature polysilicon semiconductor layer, or a combination thereof. The first semiconductor layer 221 can be connected to one of the first source / drain electrodes 224. The fourth dummy subpixel DP_4 can have a smaller area than the first dummy subpixel DP_1 and the second dummy subpixel DP_2. Accordingly, unlike in the first dummy subpixel DP_1 and the second dummy subpixel DP_2, only the first semiconductor layer 221 and the first source / drain electrodes 224 may be located beneath the components of the first transistor in the fourth dummy subpixel DP_4. The second transistor 240 and the storage capacitor 230 can be arranged at different locations spaced apart from the first semiconductor layer 221 and the first source / drain electrodes 224. The second transistor 240 can include the second semiconductor layer 241, the second gate insulating layer 242, the second gate electrode 243, and the second source / drain electrodes 245. The second semiconductor layer 241 of the second transistor 240 can be configured as an oxide semiconductor layer. For example, the second semiconductor layer 241 can contain at least one oxide semiconductor material such as indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO). The upper interlayer structure 218 and 219, including the fourth interlayer insulating layer 218 and the fifth interlayer insulating layer 219, can be arranged on the second gate electrode 243 of the second transistor 240. A substructure of the first source / drain electrodes 224 and the second source / drain electrodes 245 can be arranged on the fifth intermediate insulating layer 219. The substructure of the first source / drain electrodes 224 can be connected to the source / drain regions of the first semiconductor layer 221 by extending through the insulating layers below it. The second source / drain electrodes 245 can be in direct contact with the source / drain regions of the second semiconductor layer 241 and connected to them by extending through the upper intermediate layer structure 218 and 219, respectively. A section of the second source / drain electrodes 245 of the second transistor 240 can be in direct contact with the third metal structure 225 by extending through the insulating layers below it. The storage capacitor 230 can contain the first storage electrode 231 and the second storage electrode 233, which overlap each other in the vertical direction, with the fourth interlayer insulating layer 218 of the upper interlayer structure 218 and 219 arranged between them. The passivation layer 247, which contains the inorganic insulating material, can cover a section of the first source / drain electrodes 224 and the second source / drain electrodes 245. The first planarization layer 250 can be arranged on the passivation layer 247. The pixel contact electrode 255 can be arranged on the first planarization layer 251. The pixel contact electrode 255 can be arranged above the second transistor 240. In the fourth dummy subpixel DP_4, the pixel contact electrode 255 is electrically connected to the pixel contact electrode 255 of the display area AA and can therefore be electrically connected to the high-potential supply line (VDD line). For example, the high-potential supply line (VDD line) can be located on the connecting line area 300 of the first non-display area NAA1. The second planarization layer 252 can be arranged on top of the first planarization layer 251 and the pixel contact electrode 255. The pixel contact electrode 255 of the fourth dummy subpixel DP_4 is covered by the second planarization layer 252. Accordingly, the second transistor 240 of the fourth dummy subpixel DP_4 can be the dummy transistor, which does not function as the driver transistor. The planarization layer 250 can consist of the first planarization layer 251 and the second planarization layer 252. The planarization layer 250 can flatten a step caused by the underlying circuit structure. The organic insulating structure 262a can be arranged on the planarization layer 250. The organic insulating structure 262a can be made of the same material as the bank 262 on the display area AA and formed in the same process. The organic insulating structure 262a can cover the entire surface of the second planarization layer 252 in the fourth dummy subpixel DP_4. In the fourth dummy subpixel DP_4, the second semiconductor layer 241 of the second transistor 240 can be arranged to overlap the third metal structure 225 in the vertical direction. Since the third metal structure 225 contains the transition metal material that can trap hydrogen, it can prevent hydrogen from being introduced into the second semiconductor layer 241, including the oxide semiconductor material. For example, the third metal structure 225 can contain titanium (Ti). The third metal structure 225 can be configured to be larger than the width of the second semiconductor layer 241 to prevent the second semiconductor layer 241 from being exposed to hydrogen. The majority of fourth dummy subpixels DP_4 are located outside the third dummy subpixels DP_4, thus blocking hydrogen inflow to each of the fourth dummy subpixels DP_4. Accordingly, barrier structures composed of a multi-stage structure of the majority of third dummy subpixels DP_3 and the fourth dummy subpixel DP_4 can be arranged on the lower portion of the bezel area of ​​the display panel 200. Therefore, these barrier structures prevent hydrogen from being introduced from the outside of a lower distal end of the display panel 200 into the subpixels SP on the display area AA. Consequently, degradation or alteration of the element properties of the driver transistor containing the oxide semiconductor on the display area AA can be prevented, thus improving the operational stability of the display device.Since the multiple dummy subpixels of different sizes are arranged on the narrow border area, no additional space is required, allowing the border area to be minimized. According to one embodiment of the present disclosure, the organic insulating structure 262a can be arranged on the planarization layer 250 as a film without any recesses on it in the third dummy pixel region B_DPA1 and / or the fourth dummy pixel region B_DPA2. For example, the organic insulating structure 262a does not cover the first electrode 261 in the third dummy pixel region B_DPA1 and the fourth dummy pixel region B_DPA2, since the third dummy pixel region B_DPAl and the fourth dummy pixel region B_DPA2 can be without the light-emitting element 260. Additionally, the third dummy pixel area B_DPA1 and / or the fourth dummy pixel area B_DPA2 may be without the first metal structure 209a and / or the second metal structure 223a, and the pixel contact electrode 255 may not be electrically connected to the second transistor 240. According to one embodiment of the present disclosure, the third metal structures 225, which are associated with the first to fourth dummy subpixels DP_1 to DP_4, can be arranged such that they surround the display area AA at the first non-display area NAA1. The display device according to various embodiments of the present disclosure can be described as follows. One aspect of the present disclosure provides a display device comprising: a display panel with a display area and a non-display area surrounding the display area; a plurality of subpixels arranged in the display area; a first area contained in the non-display area and surrounding three sides of the display area of ​​the display device in plan view; a second area contained in the non-display area and arranged in a position different from a position of the first area; a bendable area contained in the non-display area; a barrier structure of a first size arranged in the first area;and a further barrier structure of the first size and a barrier structure of the second size, arranged in the second area and spaced apart from each other, wherein the barrier structure of the first size and the barrier structure of the second size have different sizes in plan view. According to one embodiment, the barrier structure of the second size is smaller than the barrier structure of the first size. According to one embodiment, the first non-display area comprises a first dummy pixel area in an upper corner of the display panel and a second dummy pixel area in an upper, left, and right side section of the display panel in the top view, wherein the second non-display area comprises a third dummy pixel area between a section of the display area in a lower section of the display panel and the bendable area, and a fourth dummy pixel area between the third dummy pixel area and the bendable area in the top view, wherein the first-size barrier structure is arranged in each of the first dummy pixel area and the second dummy pixel area, wherein the further first-size barrier structure is arranged in the third dummy pixel area, and wherein the second-size barrier structure is arranged in the fourth dummy pixel area. According to one embodiment, the barrier structure of first size, which is arranged in the first dummy pixel area, contains a first dummy subpixel, the barrier structure of first size, which is arranged in the second dummy pixel area, contains a second dummy subpixel, the further barrier structure of first size, which is arranged in the third dummy pixel area, contains a third dummy subpixel, and the barrier structure of second size, which is arranged in the fourth dummy pixel area, contains a fourth dummy subpixel, wherein, in the top view, the size of the fourth dummy subpixel is smaller than the size of each of the first dummy subpixel, the second dummy subpixel, and the third dummy subpixel. According to one embodiment, in the top view the first dummy subpixel has the same size as the subpixel of the display area. According to one embodiment, in the top view the third dummy subpixel has the same size as the first dummy subpixel. According to one embodiment, each of the plurality of subpixels comprises: an oxide thin-film transistor comprising: a semiconductor layer; a gate insulating layer arranged on the semiconductor layer; a gate electrode arranged on the gate insulating layer; and source / drain electrodes arranged on both opposite sides of the gate electrode and connected to the semiconductor layer; and a light-emitting element electrically connected to the oxide thin-film transistor, the semiconductor layer comprising an oxide semiconductor material. According to one embodiment, each of the plurality of subpixels further includes a metal structure that overlaps the oxide thin-film transistor in a vertical direction and contains a transition metal material for trapping hydrogen. According to one embodiment, the width of the metal structure is greater than the width of the semiconductor layer of the oxide thin-film transistor. According to one embodiment, the oxide semiconductor material contains indium gallium zinc oxide or indium zinc oxide, and the transition metal material contains titanium. According to one embodiment, the first dummy subpixel comprises: an oxide thin-film transistor comprising: a semiconductor layer containing an oxide semiconductor material; a gate electrode positioned spaced apart from the semiconductor layer; and source / drain electrodes each positioned on opposite sides of the gate electrode; a planarization layer placed on the oxide thin-film transistor; an organic insulating structure covering the planarization layer; and a metal structure overlapping the oxide thin-film transistor in a vertical direction and comprising a transition metal material for trapping hydrogen, wherein a width of the metal structure is greater than a width of the semiconductor layer of the oxide thin-film transistor. According to one embodiment, the fourth dummy subpixel comprises: an oxide thin-film transistor arranged on a substrate on one side thereof, comprising a semiconductor layer containing an oxide semiconductor material, a gate electrode, and source / drain electrodes; a first planarization layer arranged on the oxide thin-film transistor; a second planarization layer arranged on the first planarization layer; an organic insulating structure covering the second planarization layer; and a pixel contact electrode arranged on the first planarization layer, vertically overlapping the source / drain electrodes and spaced above them. According to one embodiment, the fourth dummy subpixel further includes a metal structure that overlaps the oxide thin-film transistor in a vertical direction and contains a transition metal material for trapping hydrogen, wherein a width of the metal structure is greater than a width of the semiconductor layer of the oxide thin-film transistor. According to some embodiments, the pixel contact electrode of the fourth dummy subpixel is electrically connected to a pixel contact electrode of the display area and electrically connected to a high potential current line. One aspect of the present disclosure provides a display device comprising: A display panel with a display area and a non-display area outside the display area; a plurality of subpixels arranged in the display area; a first area contained in the non-display area and located adjacent to the display area in a top view of the display device; a second area contained in the non-display area and arranged in a position different from a position of the first area;and a flexible area contained within the non-display area, wherein the first area comprises an upper section, a right side section, a lower section, and a left side section arranged clockwise in the top view of the display device, each of the upper section, right side section, lower section, and left side section comprising a barrier structure containing a plurality of metal structures configured to trap hydrogen from the display device, and wherein the plurality of metal structures are located along the first area to surround the display area in the top view of the display device. According to one embodiment, the display panel further comprises a first corner, a second corner, a third corner and a fourth corner in a clockwise direction around the display panel in the top view starting from the upper section of the first area. According to one embodiment, the first corner is a transition from the top section to the right side section, the second corner is a transition from the right side section to the bottom section, the third corner is a transition from the bottom section to the left side section, and the fourth corner is a transition from the left side section to the top section in a clockwise direction around a periphery of the display panel. According to one embodiment, the first area of ​​the non-display area includes a first dummy pixel area in at least the first corner of the display panel and a second dummy pixel area in at least one of the upper section, the left side section and the right side section of the display panel in the top view of the display device, and wherein the second area of ​​the non-display area includes a third dummy pixel area between a section of the display area in the lower section of the display panel and the bendable area and a fourth dummy pixel area between the third dummy pixel area and the bendable area in the top view of the display device. According to one embodiment, the first dummy pixel area contains a first dummy subpixel, the second dummy pixel area contains a second dummy subpixel, the third dummy pixel area contains a third dummy subpixel, and the fourth dummy pixel area contains a fourth dummy subpixel, wherein, in the top view of the display device, the size of the fourth dummy subpixel is smaller than the size of each of the first dummy subpixel, the second dummy subpixel, and the third dummy subpixel. According to one embodiment, in the top view of the display device, the first dummy subpixel has the same size as a subpixel of the display area, and the third dummy subpixel has the same size as the first dummy subpixel.

Claims

A display device (100) comprising: a display panel (200) containing a display area (AA) and a non-display area (NAA) surrounding the display area (AA); a plurality of subpixels (SP) arranged in the display area (AA); a first area contained in the non-display area (NAA) surrounding three sides of the display area (AA) in a top view of the display device (100); a second area contained in the non-display area (NAA) arranged at a position different from a position of the first area; a bendable area (BDA) contained in the non-display area (NAA); a barrier structure of the first size arranged in the first area;and a further barrier structure of the first size and a barrier structure of the second size, which are arranged in the second area and spaced apart from each other, wherein the barrier structure of the first size and the barrier structure of the second size have different sizes in plan view. The display device (100) according to claim 1, wherein the barrier structure of the second size is smaller than the barrier structure of the first size. The display device (100) according to claim 1 or 2, wherein the first non-display area (NAA) comprises a first dummy pixel area (TS_DPA) in an upper corner of the display panel (200) and a second dummy pixel area (TS_DPA1) in an upper, left, and right side section of the display panel (200) in the top view, wherein the second non-display area (NAA) comprises a third dummy pixel area (B_DPA1) between a section of the display area (AA) in a lower section of the display panel (200) and the bendable area (BDA), and a fourth dummy pixel area (B_DPA2) between the third dummy pixel area (B_DPA1) and the bendable area (BDA) in the top view, wherein the barrier structure of the first size is located in each of the first dummy pixel area (TS_DPA) and the second The dummy pixel area (TS_DPA1) is arranged, with the further barrier structure of the first size being arranged in the third dummy pixel area (B_DPA1),where the barrier structure of the second size is located in the fourth dummy pixel area (B_DPA2). The display device (100) according to claim 3, wherein the barrier structure of first size, which is arranged in the first dummy pixel area (TS_DPA), contains a first dummy subpixel (DP_1), the barrier structure of first size, which is arranged in the second dummy pixel area (TS_DPA1), contains a second dummy subpixel (DP_2), the further barrier structure of first size, which is arranged in the third dummy pixel area (B_DPA1), contains a third dummy subpixel (DP_3), and the barrier structure of second size, which is arranged in the fourth dummy pixel area (B_DPA2), contains a fourth dummy subpixel (DP_4), wherein, in the top view, the size of the fourth dummy subpixel (DP_4) is smaller than the size of each of the first dummy subpixel (DP_1), the second dummy subpixel (DP_2), and the third dummy subpixel. (DP_3) is. The display device (100) according to claim 4, wherein in the top view the first dummy subpixel (DP_1) has the same size as a size of the subpixel (SP) of the display area (AA). The display device (100) according to claim 4 or 5, wherein in the top view the third dummy subpixel (DP_3) has the same size as the first dummy subpixel (DP_1). The display device (100) according to any one of claims 1 to 6, wherein each of the plurality of subpixels (SP) comprises: an oxide thin-film transistor (240) comprising: a semiconductor layer (241); a gate insulating layer arranged on the semiconductor layer (241); a gate electrode (243) arranged on the gate insulating layer; and source / drain electrodes (245) arranged on both opposite sides of the gate electrode (243) and connected to the semiconductor layer (241); and a light-emitting element (260) electrically connected to the oxide thin-film transistor (240), wherein the semiconductor layer (241) comprises an oxide semiconductor material. The display device (100) according to claim 7, wherein each of the plurality of subpixels (SP) further comprises a metal structure (225) which overlaps the oxide thin-film transistor (240) in a vertical direction and comprises a transition metal material for trapping hydrogen. The display device (100) according to claim 8, wherein a width of the metal structure (225) is greater than a width of the semiconductor layer (241) of the oxide thin-film transistor (240). The display device (100) according to one of claims 7 to 9, wherein the oxide semiconductor material comprises indium gallium zinc oxide or indium zinc oxide, and the transition metal material comprises titanium. The display device (100) according to claim 4, wherein the first dummy subpixel (DP_1) comprises: an oxide thin-film transistor (240) comprising: a semiconductor layer (241) containing an oxide semiconductor material; a gate electrode (243) arranged to be spaced apart from the semiconductor layer (241); and source / drain electrodes (245) each arranged on opposite sides of the gate electrode (243); a planarization layer (250) arranged on the oxide thin-film transistor (240); and an organic insulating structure (262a) covering the planarization layer (250). and a metal structure (225) that overlaps the oxide thin-film transistor (240) in a vertical direction and contains a transition metal material for trapping hydrogen, wherein a width of the metal structure (225) is greater than a width of the semiconductor layer (241) of the oxide thin-film transistor (240). The display device (100) according to claim 4 or 11, wherein the fourth dummy subpixel (DP_4) comprises: an oxide thin-film transistor (240) arranged on a substrate on one side thereof and comprising a semiconductor layer (241) comprising an oxide semiconductor material, a gate electrode (243) and source / drain electrodes (245); a first planarization layer (251) arranged on the oxide thin-film transistor (240); a second planarization layer (252) arranged on the first planarization layer (251); an organic insulating structure (262a) covering the second planarization layer (252); and a pixel contact electrode (255) arranged on the first planarization layer (251) and vertically overlapping the source / drain electrodes (245) and spaced apart from them above. The display device (100) according to claim 12, wherein the fourth dummy subpixel (DP_4) further comprises a metal structure (225) that overlaps the oxide thin-film transistor (240) in a vertical direction and includes a transition metal material for trapping hydrogen, wherein a width of the metal structure (225) is greater than a width of the semiconductor layer (241) of the oxide thin-film transistor (240). The display device (100) according to claim 12 or 13, wherein the pixel contact electrode (255) of the fourth dummy subpixel (DP_4) is electrically connected to a pixel contact electrode (255) of the display area (AA) and is electrically connected to a high potential current line.

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