GATEDIELECTRICS OF NANOSTRUCTURE TRANSISTORS AND MANUFACTURING PROCESSES

Abstract

A method comprises forming multiple first semiconductor nanostructures, each comprising a lower semiconductor nanostructure and a top semiconductor nanostructure above the lower semiconductor nanostructure, forming interface layers contacting the multiple semiconductor nanostructures, and depositing high-k dielectric layers enclosing the interface layers. The top high-k dielectric layer of the high-k dielectric layers enclosing the top semiconductor nanostructure has a top horizontal section overlapping the top semiconductor nanostructure, a lower horizontal section overlapping the top semiconductor nanostructure, and a sidewall section on a sidewall of the top semiconductor nanostructure. The top horizontal section, the lower horizontal section, and the sidewall section each have a first thickness.A second of the uppermost horizontal section, the lower horizontal section and the side wall section has a second thickness that differs from the first thickness.