Doping diffusion process on GaN buffer layers

Abstract

A GaN enrichment transistor comprising: a substrate (31, 41); Transition layers (32, 42) above the substrate (31, 41); a GaN layer (33, 43) containing doping atoms above the transition layers (32, 42); a series of growth interruption layers (39, 49), each comprising a layer with a higher content of dopants followed by a layer with a decreasing lower content of dopants above the GaN layer (33, 43); and a GaN buffer layer (34, 44) with a reduced concentration of doping atoms above the growth interruption layers (39, 49).

Description

Technical field

[0001] The present invention relates to the field of gallium nitride transistors (GaN) and in particular to a method and instrument for trapping excess doping atoms. Background of the invention

[0002] Gallium nitride (GaN) semiconductors are becoming increasingly desirable for use in power semiconductors due to their ability to conduct high currents and handle high voltages. The development of these semiconductors is primarily focused on high-power / high-frequency applications. Semiconductors manufactured for these applications are based on general conductor structures that exhibit high electron mobility and are variously referred to as heterogeneous structure field-effect transistors (HFETs), high electron mobility transistors (HEMTs), or modulation-doped field-effect transistors (MODFETs). These transistor types typically withstand high voltages, such as 100 volts, in high-frequency operation, e.g., 100 kHz to 10 GHz. Light-emitting diodes (LEDs) can also incorporate GaN semiconductors. For example, US 2008 / 0315243A1 describes an LED using GaN semiconductors.

[0003] US 2004 / 0 195 562 A1 describes a superlattice modification of a transistor.

[0004] US 2006 / 0 281 238 A1 describes a method for producing an adaptive AlGaN buffer layer.

[0005] US 2008 / 0 220 555 A1 describes nitride semiconductor structures with interlayer structures and a method for fabricating nitride semiconductor structures with interlayer structures.

[0006] JP 2009 - 21 362 A describes an electronic component made of group III nitride, a laminated wafer for an electronic component made of group III nitride and a method for manufacturing an electronic component made of group III nitride.

[0007] JP 2004 - 311 913 A describes a nitride-based semiconductor epitaxy substrate, a method for its fabrication and substrate for HEMT.

[0008] A GaN HEMT comprises a nitride semiconductor with at least two nitride layers. Due to the different substances forming on the semiconductor or a buffer layer, the semiconductors exhibit different band gaps. The different substances also lead to polarization in the adjacent nitride layers, which enhances the formation of a conductive two-dimensional electron gas region (2DEG) close to the junction between the two layers, especially in the layer with the narrower band gap.

[0009] The nitride layers responsible for polarization are typically an AlGaN junction adjacent to a GaN layer, encompassing the 2DEG, thus charging the flux through the semiconductor. This junction can be doped or undoped. Because the 2DEG region below the gate is powerless, nitride semiconductors are usually in active or depletion mode. If the 2DEG region is depleted, i.e., eliminated, down to below the powerless gate, the semiconductor can be an enhancement transistor. Enhancement FETs are usually disabled and desirable because they provide even greater safety. To conduct current, an enhancement-type transistor typically requires a positive voltage applied to the gate.

[0010] Fig. Figure 1 shows a conventional GaN transistor 100, as also described in US 2006 / 0 006 414 A1. The transistor 100 comprises: a substrate 11 consisting of silicon (Si), silicon carbide (SiC), sapphire, or another material; transition layers 12, typically consisting of aluminum nitride (AlN) and aluminum gallium nitride (AlGaN) with a thickness of about 0.1 to 1.0 µm; a Mg-doped GaN layer 10; a buffer layer 13, typically consisting of GaN with a thickness of about 0.5 to 3 µm; a current-conducting region 14, consisting of GaN or indium gallium nitride (InGaN), typically with a thickness of about 0.01 to 0.5 µm; a contact field 15, typically consisting of AlGaN, Al, and titanium (Ti), possibly with a Si content, with a thickness of about 0.01 to 0.03 µm; and a barrier layer 16, typically consisting of AlGaN with a Al-Ga ratio of approximately 0.1 to 0.5 and a thickness of approximately 0.01 to 0.03 µm, a gate structure 17,consisting of a nickel (Ni) and gold (Au) metal contact as well as ohmic contact metals 18, 19, consisting of Ti and Al with a coating metal, such as Ni and Au.,

[0011] During the growth of the Mg-doped GaN material in a conventional GaN transistor (e.g. Fig. 1) Magnesium (Mg) is added to the growth environment, accumulating on the GaN surface and becoming part of the crystal. The Mg also coats the walls of the growth chamber during this phase. Growing undoped GaN—with the intention of obtaining a Mg-free material—following the growth of the Mg-doped material proves difficult due to the Mg remaining on the GaN surface and chamber walls. The Mg residues will contaminate the crystal for an extended period, as Mg readily disperses within the growth chamber.

[0012] Conventional GaN transistors have many disadvantages. The breakdown voltage is limited by the width of gate 17 (as in Fig. (1 shown) is limited. To achieve high voltages, a wide gate and a large distance between gate 17 and drain contact 18 are required due to the remaining n-doping from oxygen contamination and nitrogen vacancies in the undoped GaN material 13. In addition, conventional GaN transistors with Mg doping in the buffer layer are subject to changes in conductivity caused by the Mg near the junction.

[0013] It is desirable to provide a method and instrument to improve transistor failure using doped buffers while simultaneously reducing power fluctuations caused by doping atoms near the depletion region. To this end, it is desirable to trap excess doping atoms to overcome the previously described disadvantage of the prior art. Description of the drawings Fig. Figure 1 is a cross-sectional view of a conventional GaN transistor. Fig. Figure 2 is a cross-sectional view of a GaN enhancement transistor according to a first embodiment of the present invention. Fig. Figure 3 shows the graph of Mg concentration in a buffer layer for single or multi-row interruptions compared to uninterrupted or standard growth. Fig. Figure 4 shows a cross-sectional view of a GaN enrichment transistor according to a second embodiment of the present invention.

[0014] The present invention relates to a GaN transistor with a Mg growth-disrupting layer for trapping excess or remaining dopants, and to a method for fabricating such a transistor. The present invention promotes the reaction of Mg and nitrogen to obtain, for example, a less volatile material, i.e., magnesium nitride. This material is then coated with either a GaN or AlGaN layer. The coating step can be performed at lower temperatures, thus facilitating the coating process. By lowering the temperature, the reaction between MgN and Al or Ga is reduced. Al and MgN react with each other in such a way that AlN is formed and MgN is reduced to Mg. This reaction is contrary to the desired coating and the trapping of MgN.If it is possible to suppress the reaction by lowering the temperature, Mg is more likely to remain in the MgN form.

[0015] Referring to Fig. Section 2 describes a first implementation with regard to the fabrication of a GaN enhancement transistor. Fig. Figure 2 shows a cross-sectional view of a transistor 200. The transistor 200 comprises (from bottom to top): a substrate 31, transition layers 32, a Mg-doped layer 33, growth interruption layers 39, a buffer layer 34, a barrier layer 35, ohmic contact metals 36, 37, and a gate structure 38. The growth interruption layers (Mg diffusion barrier) 39 can consist of one or more heavily Mg-doped GaN layers. They are formed by interrupting growth and treating the surface with ammonia. In addition to Mg, iron (Fe), nickel (Ni), manganese (Mn), calcium (Ca), vanadium (V), or other transition metals are also suitable as dopants.

[0016] The formation of the structure according to Fig. Section 2 will now be described with reference to Mg as an example of doping. The transition layers 32 are produced by nucleation and growth on the substrate 31. The substrate 31 can consist of silicon (Si), silicon carbide (SiC), sapphire, lithium gallium oxide (LiGaO2), gallium nitride (GaN), or other suitable materials. The transition layers 32 can consist of AlN, AlGaN, InAlGaN, SiO2, SiN, MgO, Al2O3, or combinations of these materials, preferably with a thickness of about 0.1 to 1.0 µm. By default, the transition layers 32 have a thickness of about 100 nm. Subsequently, the Mg-doped layer 33 is grown. The Mg-doped layer 33 can consist of GaN with a thickness of about 0.1 to 1.0 µm and with a Mg concentration between 10 16 atoms per cm3 and 10 19atoms per cm³. Subsequently, the magnesium-inhibiting growth interruption layers 39 grow. The formation of the growth interruption layers 39 according to the invention comprises the growth of GaN without Mg-containing material, the interruption of the addition of Ga-containing materials with the continuous addition of ammonia or another activated nitrogen source (e.g., plasma N₂) to produce a magnesium nitride layer, the re-addition of Ga to enclose the magnesium nitride layer by growing a GaN layer, and the interruption of growth again, with the described sequence being repeated until the target Mg concentration is reached in the last layer. In the next step, buffer layer 34, barrier layer 35, and gate structure 38 are grown, and the gate contacts are produced by processing the material. The buffer layer 34 can consist of GaN, preferably with a thickness of about 0.5 to 3.0 µm.The barrier layer 35 can consist of AlGaN, wherein the Al content is approximately 0.1 to 0.5, preferably with a thickness between 0.01 and 0.03 µm. The Al content refers to the Al content, such that the combined Al and Ga content equals 1. The gate structure 38 can consist of p-GaN with a refractory metal contact, such as tantalum (Ta), titanium (Ti), titanium nitride (TiN), tungsten (W), or tungsten silicide (WSi₂). The gate structure can be a simple metal such as Ni under Au, or a semiconductor with a metal such as GaN under TiN, or a semiconductor under an insulator under a metal such as GaN under SiN under TiN. Other semiconductors can be Si, GaAs, or InAlGaN. Other insulators can be AlGaN, InAlGaN, SiO₂, SiN, MgO, or Al₂O₃. Other metals can include Al, Ni, Au, Pt, etc. Polysilicon could also be used instead of a metal. The thickness of the metal and gate layers is preferably between 0.01 and 1.0 µm.The overall thickness of the gate structure is preferably less than 1 µm. In the next step, the gate structure 38 is etched into the other regions of the transistor, and ohmic contacts 36, 37 are fabricated. The ohmic contact metals 36, 37 can be titanium (Ti) and aluminum (Al) with a coating metal such as nickel (Ni) and gold (Au) or titanium (Ti) and titanium nitride (TiN). An implanted, highly doped region connected to the contact region can also be provided. The primary channel region can be n-doped GaN or undoped or intrinsic InAlGaN.

[0017] According to the procedure described above, the addition of a p-doped GaN layer 33 below the gate, as well as a series of growth interruption layers 39, reduces the Mg content in the GaN buffer layer 34. The Mg doping of layer 33 is shown in Figure 3. Fig. 2. This increases the breakdown voltage of the transistor. The gate length of the transistor can be significantly shortened without reducing the breakdown voltage. The gate capacitance is reduced due to the shortened gate length. The switching speed of the transistor improves due to the lower gate capacitance. The growth interruption layers 39 reduce the Mg concentration within layer 34 and near the junction 35.

[0018] Fig. Figure 3 is a comparative schematic representation of the Mg concentration in a buffer layer without growth interruption layers, a buffer layer with a single growth interruption layer, and a buffer layer with six growth interruption layers. The diagram for multiple growth interruption shows an increased Mg concentration at each interruption point after each growth interruption, followed by a layer with a lower Mg concentration. Each growth interruption layer reduces the Mg concentration, and by using multiple layers, a lower Mg concentration can be achieved over a shorter distance.

[0019] A lower Mg content in layer 34 increases the transistor's conductivity. Furthermore, less Mg in layer 34 allows layer 33 to be placed in close proximity to layer 35 without adversely affecting the transistor's conductivity. Additionally, the close proximity of layers 33 and 35 results in improved transistor failure and lower gate leakage currents. The structure of Fig. However, version 2 has some disadvantages. The production of the growth interruption layers 39 can be very time-consuming, resulting in higher production costs. Furthermore, Mg residues remain in layer 34 due to contaminated reactor components.

[0020] In connection with Fig. Section 4 now describes a second version with reference to the formation of a GaN enrichment transistor. Fig. Figure 4 shows a cross-sectional view of transistor 300, which was fabricated using the method described below. This embodiment of the invention differs from the first embodiment in that the growth interruption layers 39 are made of Fig. 2 are now replaced by AlGaN layers 49. The AlGaN layers (doped diffusion barrier) 49 can consist of one or more AlGaN layers. They are produced by interrupting the growth and treating the GaN surface with ammonia, similar to the first embodiment, followed by the deposition of AlGaN and subsequently GaN. The Al content of the AlGaN layers is between 0.3 and 1. The thickness of the AlGaN layers is preferably about 0.005 to 0.03 µm.

[0021] The formation of the structure according to Fig. 4 is carried out similarly to the procedure described above for the first execution ( Fig. 2) with Mg as an example of doping. The dimensions and compositions of the respective layers are similar to those of the first version. Instead of growth interruption layers 39 ( Fig.2) However, AlGaN layers 49 are produced. The formation of AlGaN layers 49 involves growing GaN without Mg-containing material, interrupting the addition of Ga-containing materials while continuously adding ammonia or another activated nitrogen source (e.g., plasma N2) to produce a magnesium nitride layer, reducing the growth temperature, re-adding Al or Ga to encapsulate the magnesium nitride layer by growing a GaN layer, increasing the temperature for GaN growth back to the initial value and interrupting growth again, and repeating the entire sequence until a target Mg content is reached in the last layer. The step of reducing the growth temperature and subsequently increasing it back to the initial value is optional.

[0022] In accordance with the procedure described above, the addition of a p-GaN layer 43 below the gate, as well as a series of growth-inhibiting and AlGaN layers 49, reduces the Mg content in the GaN buffer layer 44. The second embodiment exhibits the same advantages as the first. In addition, the addition of AlGaN layers to the diffusion barrier 49 improves the effectiveness of the individual growth-inhibiting steps and thus reduces the number of steps required to achieve the desired level of Mg doping in the buffer layer 44.

Claims

[1] A GaN enrichment transistor comprising: a substrate (31, 41); Transition layers (32, 42) above the substrate (31, 41); a GaN layer (33, 43) containing doping atoms above the transition layers (32, 42); a series of growth interruption layers (39, 49), each comprising a layer with a higher content of dopants followed by a layer with a decreasing lower content of dopants above the GaN layer (33, 43); and a GaN buffer layer (34, 44) with a reduced concentration of doping atoms above the growth interruption layers (39, 49). [2] The GaN enrichment transistor according to claim 1, characterized by that the doping atoms are selected from the group Mg, Fe, Ni, Mn, Ca, V and other transition metals. [3] A method for producing a growth interruption layer (39) of a GaN enhancement transistor according to claim 1, comprising: Growth of a GaN material without Mg as doping atoms; Interruption of the addition of Ga-containing materials during the continuous addition of ammonia or another activated nitrogen source, for the production of a magnesium nitride layer; and renewed addition of Ga, to encapsulate the magnesium nitride layer by growth of a GaN layer; and renewed interruption of growth and repeated occurrences the steps. [4] A method for producing a growth interruption layer (39, 49) of a GaN enhancement transistor according to claim 1, comprising: Activation of a flow of doping atoms and Ga-containing gases; Blocking the flow of the gases containing the doping atoms and Ga, with continuous addition of ammonia or an activated nitrogen source, to produce a dopant nitride layer; Lowering the temperature; Reactivation of the flow of Ga-containing gases to enclose the dopant nitride layer by growing a GaN layer; Increasing the temperature, the sequence, comprising flow blockage, temperature reduction, flow reactivation, and temperature increase, is repeated several times. [5] The method according to claim 4, characterized by , that the Ga containing gases are a mixture of at least one of the following gases: trimethylgallium, trimethylaluminium, triethylgallium, triethylaluminium and triethylindium. [6] The method according to claim 4, characterized bythat the doping atoms are selected from the group of Mg, Fe, Ni, Mn, Ca, V and other transition metals.

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