Low-jitter, low-latency, low-power clocking with common reference clock signals for on-package input / output interfaces

Abstract

Device comprising: a filter phase-locked loop circuit (205) in a master device (200) on a first bare chip, die (120), wherein the phase-locked loop (205) provides a clock signal of 2F, a local phase-locked loop circuit (210) in the master device (200) on the first bare chip (120) coupled to the filter phase-locked loop (205), the local phase-locked loop circuit (210) providing a clock signal to one or more functional components of the master device (200) through a local clock divider circuit (215) to provide a clock signal of F to the functional components, and a remote phase-locked loop circuit (255, 260) in a slave device (250) on a second bare die (140) coupled to the filter phase-locked loop (205), the remote phase-locked loop circuit (255, 260) providing a clock signal to one or more functional components of the slave device (250) through a local clock divider circuit (265, 270) to provide a clock signal of F to the functional components.

Description

TECHNICAL FIELD

[0001] Embodiments of the invention relate to input / output architectures and interfaces. In particular, embodiments of the invention relate to high-bandwidth on-package input / output (OPIO) architectures and interfaces. BACKGROUND

[0002] High-bandwidth inter-chip connections using conventional input / output (I / O) interfaces require significant power and chip area. Therefore, these conventional interfaces are not desirable for applications requiring significantly reduced power consumption and / or smaller chip area.

[0003] US 6 185 510 B1 describes a PLL jitter measuring method used for an integrated circuit having a PLL generating an internal clock signal, comprising the steps of extracting jitter information of the internal clock signal of the PLL as an output signal to the outside of the integrated circuit without removing a package of the integrated circuit, and measuring the jitter of the internal clock signal with the extracted output signal.

[0004] US 7 308 065 B2 describes a receiver that can be coupled to a data bus and is configured to receive data in accordance with a receive clock, and comprises a first and a second delay loop (delay-locked loop, DLL). The first delay loop is configured to generate a plurality of phase vectors from a first reference clock, and the second delay loop is coupled to the first delay loop and configured to generate the receive clock from at least one phase vector selected from the plurality of phase vectors and a second reference clock.

[0005] US 6,118,314 A describes a circuit arrangement and a method for synchronizing multiple circuits. A circuit comprises: an oscillator configured to generate a reference clock signal; and a first circuit comprising: a first divider configured to generate a first internal clock signal in response to the reference clock signal; and a reset generation circuit configured to receive an external reset signal and generate a second reset circuit signal synchronized with a predefined position of the first divider, with the reference clock signal, and with the external reset signal.The circuit further comprises a second circuit comprising: a reset detection circuit configured to generate a reset detection signal synchronized with the second reset circuit signal and the reference clock signal, and a second divider configured to be set to a predefined position in response to receiving the reset detection signal and to generate a second internal clock signal synchronized with the first internal clock signal.

[0006] US 2006 / 0 112 205 A1 describes a method and apparatus in a computer system for connecting buses with different clock frequencies. The method comprises receiving a request transmitted from a master to a slave. If the clock frequency of the master is lower than that of the slave, so that the slave sees more requests than the master, redundant cycles of the request signal are masked so that the slave does not receive the request repeatedly. The request is then forwarded to the slave. If the clock frequency of the master is higher than that of the slave, so that the slave cannot receive the request in time, the request signal is extended so that the request signal is synchronized with the clock cycles of the slave. The output data requested by the slave is then transmitted to the master. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the invention are illustrated by way of example and in no way limiting in the figures of the accompanying drawings, in which like reference numerals refer to similar elements. Fig. 1 is a block diagram of one embodiment of a multi-chip package (MCP) having on-package input / output (OPIO) interfaces between at least two chips. Fig. Figure 2 illustrates an embodiment of a clock architecture that can be used, for example, with the OPIO interface of Fig. 1 can be used. Fig. 3 illustrates an embodiment of a circuit for providing a local clock signal. Fig. Figure 4 illustrates an embodiment of an adapted and rasterized receiver clock architecture. Fig. 5 is a block diagram of one embodiment of an electronics. SUMMARY OF THE INVENTION

[0008] The object underlying the invention is to provide accurate clock signals with low jitter and low latency in environments with significantly reduced power consumption and / or a smaller chip area. This object is achieved by the subject matter of the independent claims. Further advantageous embodiments are specified in the subclaims. DETAILED DESCRIPTION

[0009] In the following description, numerous specific details are set forth. However, embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, arrangements, and techniques have not been shown in detail in order not to obscure this description.

[0010] Fig. 1 is a block diagram of one embodiment of a multi-chip module (MCP) having OPIO interfaces between at least two chips. The example of Fig. Figure 1 illustrates two chips with interfaces; however, any number of chips within a module may be interconnected using the techniques described herein.

[0011] Module 100 can be any type of module that can include multiple integrated circuit chips. In the example of Fig. 1, module 100 includes chip 120 and chip 140. These chips can be, for example, processors, memory chips, graphics processors, etc.

[0012] In one embodiment, chip 120 includes OPIO transmitters 125 and OPIO receivers 130. Similarly, chip 140 includes OPIO transmitters 145 and OPIO receivers 150. Transmitters 125 are coupled to receivers 150, and transmitters 145 are coupled to receivers 130. In one embodiment, gap 175 between chip 120 and chip 140 is relatively small. In one embodiment, gap 175 is less than 20 mm. In one embodiment, gap 175 is less than 10 mm. In one embodiment, gap 175 is approximately 1.5 mm. In other embodiments, gap 175 may be less than 1.5 mm. In general, the smaller the gap 175, the greater the bandwidth that can be provided between chips.

[0013] In one embodiment, the interfaces between transmitter 125 and receiver 150 and between transmitter 145 and receiver 130 are relatively high-speed, asymmetric interfaces. In one embodiment, the interfaces are CMOS interfaces between chip 120 and chip 140. In one embodiment, transmitters 125 and 145 are impedance-matched CMOS transmitters, and no termination and equalization are provided. In one embodiment, transmitters 125 and 145 are impedance-matched CMOS transmitters, and very weak termination and no equalization are provided. In one embodiment, a relayed clock signal is transmitted for a cluster of signals. In one embodiment, length-matched routing is provided between the transmitters and the receivers. In one embodiment, minimal ESD protection (as little as 70 volts) is provided for the interfaces between chips 120 and 140.

[0014] In one embodiment, the use of a CMOS transmitter and receiver with no or weak receiver termination and no equalization can reduce I / O power requirements. Simplified clocking with one forwarded clock per cluster of signals and no per-pin deskewing can be achieved due to careful length-matched routing, reducing clock power requirements. Therefore, the architectures described here provide high inter-chip bandwidth with very low power, small area, and low latency.

[0015] The architectures described here can also be extended to achieve discrete modules with full ESD protection for small form-factor cellular applications at lower data rates. Multilevel signaling (e.g., multilevel pulse amplitude modulation, M-PAM) can be used at higher data rates to keep the clock frequency low.

[0016] Fig. Figure 2 illustrates an embodiment of a clock architecture that can be used, for example, with the OPIO interface of Fig. 1 can be used. The clock architecture of Fig. 2 can provide a deterministic, coincident, propagated low-power clock signal with improved performance and lower RTL (round-trip latency) and less inaccuracy, enabling faster I / O rates. Continuous tracking can also support voltage and temperature correction. Filter phase-locked loop (PLL) 205 in processor 200 operates to generate one or more common higher-frequency reference clock signals that can be distributed and matched to processor and / or device PLLs. In one embodiment, filter PLL 205 generates 100 MHz and 200 MHz clock signals; however, any clock signal frequency can be supported.

[0017] In one embodiment, I / O PLL 210 is used within processor 200 to clock both the I / O analog front end (AFE) and the controller. In one embodiment, the generated and distributed clock signal is a single-ended signal adjusted to twice the operating frequency (e.g., 2F, where F represents the frequency). In one embodiment, a local clock macro (LCM) 230 on the AFE converts the single-ended clock signal to a differential signal (SED).

[0018] The signal from filter PLL 205 is provided to OPIO PLL 210 for distribution within processor 200. In one embodiment, filter PLL 205 generates higher frequency common reference clock signals (e.g., 100 MHz and 200 MHz) that are distributed and matched to processor PLL 210 and device PLL 260. In one embodiment, PLL 210 receives a divided clock signal provided by feedback divider 215.

[0019] In one embodiment, PLL 210 in processor 200 provides a clock signal to the I / O analog front end (AFE) and the controller. The clock signals may be provided, for example, by a regional clock buffer (RCB) and / or a local clock buffer (LCB) 220.

[0020] In one embodiment, the generated clock frequency is distributed over an asymmetric network and is adjusted to 2F, where F is the local clock frequency. In one embodiment, a local clock macro (LCM) 230 at the AFE converts the asymmetric clock signal into a differential clock signal (SED). One embodiment of an LCM is described in Fig. 3 shown.

[0021] In one embodiment, the I / O interface at the PISO (parallel input / serial output, not shown) uses the Clock and Clock# signals to serialize data at full data rates. The clock distribution can be customized, and at the end of the distribution network, the clock signal is fed back into the PLL and the duty cycle correction circuit (which may be located at the PLL output) to provide a 50% duty cycle sampled at the end of the distribution.

[0022] The processor controller can locally split the 2F clock signal into an F clock signal (e.g., from 4 GHz to 2 GHz) to drive the control logic. Since the same PLL and clock distribution can be used, no special buffer transition is required on the transfer side between the AFE and the controller.

[0023] For device 250 (e.g., DRAM, eDRAM, WideIO DRAM), multiple PLLs (e.g., 255, 260) may be used to provide clock signals to the functional elements (e.g., memory array) and the AFE, which use the clock signal sent by processor 200 as a reference (e.g., 2F clock signal / or F clock signal). In one embodiment, PLL 255 is dedicated to memory, which has a relatively high clock distribution latency. LCM 230 operates to convert the single-ended clock signal into a differential clock signal.

[0024] Similar to processor 200, in one embodiment, PLL 255 is configured with distribution in the loop with a digital clock (DCC) at the output of PLL 255. In one embodiment, PLL 255 operates at the fundamental frequency (i.e., F). PLL 260 is dedicated to the AFE with a much lower clock distribution latency and is also configured similarly to the other PLL, generating a 2F clock signal. In one embodiment, buffer 290 provides a mechanism for sending and receiving data from another device, e.g., holding data to be stored in memory and holding data read from memory to be transferred to another chip. In one embodiment, PLL 255 receives a divided clock signal provided by feedback divider 270, and PLL 260 receives a divided clock signal provided by feedback divider 265.

[0025] Separating the AFE and memory PLLs enables accurate, low-jitter clock signals for the AFE and also minimizes complexity when the AFE and memory are powered by different supply rails. A low-latency buffer can be used at the chip junction to compensate for PLL and voltage drift.

[0026] Fig. 3 illustrates an embodiment of a circuit for providing a local clock signal. The example of Fig. Figure 3 is an example of a circuit that can be used to convert a single-ended clock signal into a differential clock signal, as described herein. Logic gates 300, transistors 350, and inverters 310, 320, 330, and 240 can be arranged to provide the differential clock signals. Other conversion mechanisms can also be used.

[0027] Fig. Figure 4 illustrates an embodiment of a matched and rasterized receiver clock architecture. At the receiver, the forwarded clock signal (sent with the data from the transmitter) is received by the delay locked loop (DLL). The DLL output is distributed across the data lines (e.g., 16 data lines, but any number can be supported).

[0028] The clock signal can be distributed in an asymmetric, matched manner and converted to a differential signal at the local level using a similar SED structure and used to sample the incoming data. The output is then sent to the SIPO (serial input / parallel output) to parallelize the received data (not shown). The DLL, distribution, and replication feedback provide a total of 180 degrees, 90 in forward delay and 90 in replication, ensuring that data is sampled in the center of the data eye, which continuously provides constant voltage and temperature tracking.

[0029] The effective use of filter PLLs in the processor, with the output at a higher reference clock frequency than a common clock, with a matched reference between two chips (e.g., processor and memory), provides a unique clocking solution for a clock interface. The higher reference clock frequency enables higher PLL bandwidth and thus reduces the PLL jitter measured over multiple cycles (and reduces PLL lock time, further improving energy efficiency).

[0030] A higher reference clock frequency contributes to less skew, which may require buffer compensation, reducing the overall RTL (round-trip latency). Adjusting the reference clocks further minimizes buffer depth. A more efficient clock system can be provided using one or more of the following: asymmetrically distributing clock signals (reducing power consumption) using a flat clock distribution fed from a clean power supply with local single-ended to differential conversion (lower power consumption), integrating the duty cycle at the output of the PLL sampling end of the clock distribution, and locking the PLL to the distribution in the PLL loop, ensuring deterministic interfaces.

[0031] In one embodiment, at the receiver side, a DLL is shared with multiple (e.g., 16, 32) data lines, with the distribution loop being formed by an adjustable delay line, matched clock distribution, and a replica delay line, providing a 180-degree phase shift, of which 90 degrees are in the adjustable delay and distribution.

[0032] In one embodiment, phase detector 425, LCM 450, amplifier 455, and replica feedback branch 440 operate to provide DLL functionality. LCM 445 provides a differential clock signal from the single-ended clock signal received from the DLL. In one embodiment, when one or more PLLs are powered down, DLL 420 remains locked, resulting in more efficient power usage. In one embodiment, the distribution length, which is t1 in Fig. 4 is 90 degrees and the distribution length corresponding to t2 is also 90 degrees.

[0033] Fig. 5 is a block diagram of an embodiment of an electronic system. Fig. The electronics illustrated in Figure 5 are intended to represent a range of electronic systems (either wired or wireless), including, for example, a tablet device, a smartphone, a desktop computer system, a laptop system, a server, etc. Alternative electronic systems may have more, fewer, and / or different components. One or more of the components illustrated in Fig.The components illustrated in Figure 5 may be interconnected using the OPIO architectures described herein. For example, multiprocessor chips, or a processor and cache memory or dynamic random access memory (Dynamic Random Access Memory), etc., may be interconnected. Electronics 500 includes bus 505 or other communication device for communicating information, and processor(s) 510 coupled to bus 505 and capable of processing information. Electronics 500 may include multiple processors and / or coprocessors. Electronics 500 may further include random access memory (RAM) or other dynamic storage device 520 (referred to as memory) coupled to bus 505, and may store information and instructions executable by processor 510.Memory 520 may also be used to store temporary variables or other intermediate information during execution of instructions by processor(s) 510.

[0034] Electronics 500 may also include a read-only memory (ROM) and / or other static storage device 530 coupled to bus 505 and capable of storing static information and instructions for processor 510. Data storage device 540 may be coupled to bus 505 to store information and instructions. Data storage device 540, such as a magnetic disk or an optical disk and a corresponding drive, may be coupled to electronics 500.

[0035] Electronics 500 may also be coupled via bus 505 to display device 550, which may be any type of display device, such as a touchscreen, for displaying information to a user. Input device 560 may be any type of interface and / or device for allowing a user to provide input to electronics 500. The input device may include hard buttons and / or soft buttons and a voice or speaker input for communicating information and command selection to processor(s) 510.

[0036] Electronics 500 may further include sensors 570 that may be used to support the functionality provided by electronics 500. Sensors 570 may include, for example, a gyroscope, a proximity sensor, a light sensor, etc. Any number of sensors and sensor types may be supported.

[0037] Electronics 500 may further include network interface(s) 580 to enable access to a network, such as a local area network. Network interface(s) 580 may include, for example, a wireless network interface having antenna 585, which may represent one or more antennas. Network interface(s) 580 may also include, for example, a wired network interface to communicate with remote devices via network cable 587, which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable.

[0038] In one embodiment, network interface(s) 580 may provide access to a local area network, for example, by conforming to the IEEE 802.11b and / or IEEE 802.11g and / or IEEE 802.11n standards, and / or the wireless network interface may provide access to a personal area network, for example, by conforming to Bluetooth standards. Other wireless network interfaces and / or protocols may also be supported.

[0039] IEEE 802.11b conforms to IEEE Std. 802.11b-1999, "Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Higher-Speed ​​Physical Layer Extension in the 2.4 GHz Band," approved September 16, 1999, and related documents. IEEE 802.11g conforms to IEEE Std. 802.11g-2003, "Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, Amendment 5: Further Higher-Speed ​​Extension in the 2.4 GHz Band," approved June 27, 2003, and related documents. Bluetooth protocols are described in "Bluetooth System Specification: Core, Version 1.1," published on February 22, 2001, by the Bluetooth Special Interest Group, Inc. Related, previous, or subsequent versions of the Bluetooth standard may also be supported.

[0040] In addition to or instead of communicating via wireless LAN standards, network interface(s) 580 may provide wireless communications using, for example, Time Division Multiple Access (TDMA) protocols, Global System for Mobile Communications (GSM) protocols, Code Division Multiple Access (CDMA) protocols, and / or any other type of wireless communication protocol.

[0041] References in the specification to "one embodiment" or "an embodiment" mean that a particular feature, arrangement, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The use of the phrase "in one embodiment" in various places in the specification does not necessarily all refer to the same embodiment.

[0042] Although the invention has been described with reference to several embodiments, those skilled in the art will recognize that the invention is not limited to the described embodiments, but may be practiced with modifications and changes within the spirit and scope of the appended claims. The description is therefore to be considered illustrative rather than restrictive.

Claims

Apparatus comprising: a filter phase-locked loop circuit (205) in a master device (200) on a first bare chip, die (120), wherein the phase-locked loop (205) provides a clock signal of 2F, a local phase-locked loop circuit (210) in the master device (200) on the first bare chip, die (120), coupled to the filter phase-locked loop (205), wherein the local phase-locked loop circuit (210) provides a clock signal to one or more functional components of the master device (200) through a local clock divider circuit (215) to provide a clock signal of F to the functional components, and a remote phase-locked loop circuit (255, 260) in a slave device (250) on a second bare chip, die (140), coupled to the filter phase-locked loop (205), wherein the Remote phase-locked loop circuit (255,260) provides a clock signal to one or more functional components of the slave device (250) through a local clock divider circuit (265, 270) to provide a clock signal of F to the functional components., The apparatus of claim 1, further comprising:a first set of asymmetric transmitter circuits (125) on the first bare die (120) transmitting the clock signal from 2F, wherein the transmitter circuits are impedance matched and have no equalization,a first set of asymmetric receiver circuits (150) on the second bare die (140) coupled to the first set of asymmetric transmitter circuits, wherein the receiver circuits (150) have no termination and no equalization, anda plurality of conductive lines between the first set of transmitter circuits (125) and the first set of receiver circuits (150), wherein the lengths of the plurality of conductive lines are matched. The apparatus of claim 2, further comprising:a second set of asymmetric receiver circuits (130) on the first bare die (120), the receiver circuits (130) having no termination and no equalization,a second set of asymmetric transmitter circuits (145) on the second bare die (140) coupled to the first set of asymmetric receiver circuits (130), the transmitter circuits (145) being impedance matched and having no equalization, anda plurality of conductive lines between the second set of transmitter circuits (145) and the second set of receiver circuits (130), the lengths of the plurality of conductive lines being matched. Apparatus according to claim 1, wherein the adapted clock distribution path is adjustable. The apparatus of claim 2, wherein a propagated clock signal is transmitted with a cluster of N data signals, and a delay locked loop (DLL) circuit having a cluster of N data signal receivers is coupled to the propagated clock signal, the delay locked loop circuit remaining locked to the propagated clock signal to provide a matched distribution path that is at 90 degrees of phase of the clock signal. The apparatus of claim 5, wherein an outgoing clock distribution path provides a 90 degree phase shift and an incoming clock distribution path provides a 90 degree phase shift in the receiver cluster. A tablet computing unit (500), comprising: a touchscreen interface (550), a filter phase-locked loop circuit (205) in a master device (200) on a first bare chip, die (120), wherein the phase-locked loop (205) provides a clock signal of 2F, a local phase-locked loop circuit (210) in the master device (200) on the first bare chip, die (120), coupled to the filter phase-locked loop (210), wherein the local phase-locked loop circuit (210) provides a clock signal to one or more functional components of the master device (200) through a local clock divider circuit (215) to provide a clock signal of F to the functional components, and a remote phase-locked loop circuit (255, 260) in a slave device (250) on a second bare chip, die (140), coupled to the Filter phase-locked loop (205), wherein the remote phase-locked loop circuit (255,260) provides a clock signal to one or more functional components of the slave device (250) through a local clock divider circuit (265, 270) to provide a clock signal of F to the functional components., The tablet (500) of claim 7, further comprising: a first set of asymmetric transmitter circuits (125) on the first bare die (120) that transmit the clock signal from 2F, wherein the transmitter circuits (125) are impedance matched and have no equalization, a first set of asymmetric receiver circuits (150) on a second bare die (140) coupled to the first set of asymmetric transmitter circuits (125), wherein the receiver circuits (150) have no termination and no equalization, and a plurality of conductive lines between the first set of transmitter circuits (125) and the first set of receiver circuits (150), wherein the lengths of the plurality of conductive lines are matched. The tablet of (500) claim 8, further comprising: a second set (130) of asymmetric receiver circuits on the first bare die (120), wherein the receiver circuits (130) have no termination and no equalization, a second set of asymmetric transmitter circuits (145) on the second bare die (140) coupled to the first set of asymmetric receiver circuits (130), wherein the transmitter circuits (145) are impedance matched and have no equalization, and a plurality of conductive lines between the second set of transmitter circuits (145) and the second set of receiver circuits (130), wherein the lengths of the plurality of conductive lines are matched. Tablet (500) according to claim 7, wherein the adapted clock distribution path is adjustable. The tablet (500) of claim 8, wherein a propagated clock signal is transmitted with a cluster of N data signals, and a delay locked loop circuit, DLL circuit, having a cluster of N data signal receivers is coupled to the propagated clock signal, the delay locked loop circuit remaining locked to the propagated clock signal to provide a matched distribution path that is at 90 degrees of phase of the clock signal. The tablet (500) of claim 11, wherein an outgoing clock distribution path provides a 90 degree phase shift and an incoming clock distribution path provides a 90 degree phase shift in the receiver cluster. A system comprising: an omnidirectional antenna, a filter phase-locked loop circuit (205) in a master device (200) on a first bare die (120), the phase-locked loop (205) providing a clock signal of 2F, a local phase-locked loop circuit (210) in the master device (200) on the first bare die (120) coupled to the filter phase-locked loop (205), the local phase-locked loop circuit (210) providing a clock signal to one or more functional components of the master device (200) through a local clock divider circuit (215) to provide a clock signal of F to the functional components, and a remote phase-locked loop circuit (255, 260) in a slave device (250) on a second bare die (140) coupled to the filter phase-locked loop (210), wherein the remote phase-locked loop circuit (255,260) provides a clock signal to one or more functional components of the slave device (250) through a local clock divider circuit to provide a clock signal of F to the functional components., The system of claim 13, further comprising:a first set of asymmetric transmitter circuits (125) on the first bare die (120) that transmit the clock signal from 2F, wherein the transmitter circuits (125) are impedance matched and have no equalization,a first set of asymmetric receiver circuits (150) on a second bare die (140) coupled to the first set of asymmetric transmitter circuits (125), wherein the receiver circuits (150) have no termination and no equalization, anda plurality of conductive lines between the first set of transmitter circuits (125) and the first set of receiver circuits (150), wherein the lengths of the plurality of conductive lines are matched. The system of claim 14, further comprising:a second set of asymmetric receiver circuits (130) on the first bare die (120), the receiver circuits (130) having no termination and no equalization,a second set of asymmetric transmitter circuits (145) on the second bare die (140) coupled to the first set of asymmetric receiver circuits (120), the transmitter circuits (145) being impedance matched and having no equalization, anda plurality of conductive lines between the second set of transmitter circuits (145) and the second set of receiver circuits (130), the lengths of the plurality of conductive lines being matched. The system of claim 13, wherein the adapted clock distribution path is adjustable. The system of claim 14, wherein a propagated clock signal is transmitted with a cluster of N data signals, and a delay locked loop (DLL) circuit having a cluster of N data signal receivers is coupled to the propagated clock signal, the delay locked loop circuit remaining locked to the propagated clock signal to provide a matched distribution path that is at 90 degrees of phase of the clock signal. The system of claim 17, wherein an outgoing clock distribution path provides a 90 degree phase shift and an incoming clock distribution path provides a 90 degree phase shift in the receiver cluster.

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