Semiconductor device and method for its manufacture

Abstract

A method of manufacturing a semiconductor device, comprising: simultaneously forming a soldering portion (4) and a mark (5) by plating on a wiring pattern (2) of an insulating substrate (1), wherein a region between the soldering portion (4) and the mark (5) on the wiring pattern (2) is not plated; Mounting a semiconductor chip (6) on the insulation substrate (1); Detecting a position of the insulation substrate (1) by the marking (5) and bonding a wire (7) to the semiconductor chip (6); Connecting an electrode (8) to the soldering portion (4) by solder (9); and Encapsulating the insulation substrate (1), the semiconductor chip (6), the wire (7) and the electrode (8) in an encapsulation material (13).

Description

Technical FieldThe present invention relates to a semiconductor device used for electric railroad systems, wind power generation, etc., and a method of manufacturing the semiconductor device.Prior ArtIn order to ensure an insulation property of a semiconductor device, an encapsulating material such as silicone gel is injected into the device. Holes for detecting the position of an insulation substrate in a process step, e.g., wire bonding, are provided in a wiring pattern on the insulation substrate (see, for example, Patent Literature 1).EP 2 365 522 A1 discloses a packaged power device including a substrate consisting of a sequence of layers: a first conductive layer followed by a dielectric layer and a second conductive layer, the conductive layers being electrically insulated. A semiconductor chip is mounted on the first conductive layer and the whole is surrounded by a plastic package whose curved back side encloses the undersides of both the plastic package and the substrate.JP 2007-258 374 A discloses a positioning mark area of a wiring board in which a mounting area is defined in which a connection and a mark conductor layer are successively formed by electrolytic plating, and the current is supplied via a metal support plate independently of the conductor pattern. In addition, a mark coating layer is formed on the mark conductor layer by the same method and power source.US 2001 / 0 000 100 A1 discloses that a first marking is formed by thin conductors on a printed circuit board and a second marking is formed by partially coating a region with resist, as a result of which two different regions are identified for the mounting of components.US 7 013 559 B2 discloses a design for making a reference point and an indicator which uses a single solder resist opening in a substrate for chip mounting to fulfil the combined functions of reference points and indicators of the prior art.US 2008 / 0 230 887 A1 discloses a semiconductor package and a method for producing the same. The method comprises the steps of: (a) providing a first substrate; (b) mounting a first die on a surface of the first substrate; (c) forming a plurality of conductive elements on the surface of the first substrate; (d) covering the conductive elements with a mold, the mold having a plurality of cavities receiving the top ends of each of the conductive elements; and (e) forming a first molding compound to encapsulate the surface of the first substrate, the first die, and portions of the conductive elements, wherein the height of the first molding compound is less than the height of each of the conductive elements. In this way, the first molding compound encapsulates the entire surface of the first substrate, such that the mold compliance of the first molding compound does not occur and the stiffness of the first substrate is increased.DE 601 23 736 T2 discloses a method for mounting components, comprising the steps of: detecting a position and orientation of a sucked component; detecting a position and orientation of a secured printed circuit board-shaped substrate; detecting a position and orientation of each of the individual substrates; calculating correction amounts for the position and the orientation of the component to be mounted; and performing necessary correction on the component based on the result of the calculation, and mounting the component at a predetermined position on the individual substrate, wherein a mark provided on the individual substrate for use in detecting the position and orientation of the individual substrate is also used as an error mark to detect a defective individual substrate.Keep ListPatent LiteraturePatent Literature 1: Japanese Patent Laid-Open Publication JP 2002-299 551 ASUMMARY OF THE INVENTIONTechnical ProblemWhen such a position detection hole exists in the vicinity of a soldering portion, there is a possibility that solder flows into the hole by flowing out from the soldering portion. When it flows into the hole, the solder is formed into a spherical or plate-like shape by its surface tension. Therefore, when the diameter of the hole is equal to or less than 3 mm, there is a possibility that the solder covers only an upper portion of the hole without flowing to the bottom of the hole. Failure of the encapsulation material to flow into the hole and therefore the formation of a void may thus result.The dielectric strength of air in the void is about 1 / 10 that of the encapsulating material, e.g., silicone gel. Therefore, there is a problem that partial discharge occurs between the solder and the insulation substrate in the void. There is also a problem that, when the diameter of the position detection hole is increased, it is not possible to reliably ensure the range required for mounting.The present invention has been made to solve the above-described problems, and an object thereof is to provide a semiconductor device and a method for manufacturing the same that can prevent the partial discharge.Means for Solving the ProblemsThe object is achieved by a method according to claim 1 and 2 respectively and by a device according to claim 3 and 4 respectively.Advantageous Effects of the InventionThe present invention makes it possible to prevent the partial discharge.Brief Description of the DrawingsFIG. 1 is a plan view of a semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is a sectional view taken along line I-II in FIG. 1. FIG. 3 is a plan view showing steps for manufacturing the semiconductor device according to Embodiment 1 of the present invention. FIG. 4 is a sectional view of a semiconductor device according to a comparative example. FIG. 5 is a plan view of a semiconductor device according to Embodiment 2 of the present invention. FIG. 6 is a sectional view taken along line I-II in FIG. 5. FIG. 7 is a plan view of a semiconductor device according to Embodiment 3. FIG. 8 is a sectional view taken along line I-II in FIG. 7. FIG. 9 is a plan view of a semiconductor device according to Embodiment 4. FIG. 10 is a plan view of a semiconductor device according to Embodiment 5. FIG. 11 is a sectional view taken along line I-II in FIG. 10. FIG. 12 is a plan view of a semiconductor device according to Embodiment 6. FIG. 13 is a sectional view taken along line I-II in FIG. 12. FIG. 14 is a plan view of a semiconductor device according to Embodiment 7. FIG. 15 is a sectional view taken along line I-II in FIG. 14.DESCRIPTION OF THE EMBODIMENTSA semiconductor device and a method for manufacturing the same according to the embodiments of the present invention will be described with reference to the drawings. The same components are denoted by the same symbols, and their repeated description may be omitted.Embodiment 1FIG. 1 is a plan view of a semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is a sectional view taken along line I-II in FIG. 1. wiring patterns 2 are provided on an upper surface of an insulation substrate 1, while a metal pattern 3 is provided on a lower surface of the insulation substrate 1. Solder portions 4 are provided on the wiring patterns 2. Ni plating marks 5 are provided on the wiring patterns 2. The solder portions 4 and the marks are formed of the same material that is Ni.Semiconductor chips 6 are mounted on the insulation substrate 1. Wires 7 are bonded to the semiconductor chips 6. Electrodes 8 are connected to the solder portions 4 by solder 9. A base plate 10 is connected to the metal pattern 3 by solder 11. All of these components are covered with a package 12, and the insulation substrate 1, the semiconductor chips 6, the wires 7, and the electrodes 8 are encapsulated in an encapsulating material 13.A method of manufacturing the semiconductor device according to the present embodiment will be described below. FIG. 3 is a plan view showing steps for manufacturing the semiconductor device according to Embodiment 1 of the present invention. First, solder portions 4 and Ni plating marks 5 are simultaneously formed on the insulation substrate 1 by plating on the wiring patterns 2. Next, the semiconductor chips 6 are mounted on the insulation substrate 1.Next, the position of the insulation substrate 1 is detected by the Ni plating marks 5, and the wires 7 are bonded to the semiconductor chips 6. Subsequently, the electrodes 8 are connected to the solder portions 4 by solder 9. Subsequently, the base plate 10 is joined to the metal pattern 3 by solder 11. Finally, all of these components are covered with the package 12 and the semiconductor chips 6, the wires 7 and the electrodes 8 are encapsulated in the encapsulation material 13.Advantages of the present embodiment will be described in comparison with a comparative example. FIG. 4 is a sectional view of a semiconductor device according to a comparative example. In the comparative example, a hole 14 for position detection is provided. There is a problem that solder 9 flowing out of the solder portion 4 covers an upper portion of the hole 14; a void is formed thereby; and the partial discharge occurs between the solder 9 and the insulation substrate 1 due to the void.On the other hand, in the present embodiment, no void is formed even if the solder 9 flowing out of the solder portions 4 covers the Ni plating marks 5. The prevention of the partial discharge can thus be achieved. If the diameter of the Ni plating marks 5 is set to be equal to or less than 3 mm, areas required for mounting can be ensured with reliability. When the wiring patterns are Al, the solder portions 4 are usually formed by Ni plating. Therefore, the solder portions 4 and the N plating marks 5 are formed simultaneously with each other by Ni plating. The number of process steps can thus be reduced.Embodiment 2FIG. 5 is a plan view of a semiconductor device according to Embodiment 2 of the present invention. FIG. 6 is a sectional view taken along line I-II in FIG. 5, and in FIG. 5, illustration of the semiconductor chips 6 and wires 7 is omitted.A resist mark 15 formed of solder resist is formed on a wiring pattern 2 in place of the Ni plating marks 5 in the embodiment 1. A protective film 16 formed of the solder resist covers peripheries of the wiring patterns 2, and the protective film 16 and the resist mark 15 are simultaneously formed of the solder resist. The position of the insulation substrate 1 is detected by the resist mark 15, and the wires 7 are bonded to the semiconductor chips 6. The other components and process steps are the same as those in Embodiment 1.The solder 19 flowing out of the solder portion 4 does not adhere to the resist mark 15 formed of the solder resist, so that no void is formed. The occurrence of partial discharge can thus be prevented. When the wiring patterns 2 are Cu, the peripheries of the solder portions 4 are usually covered with the protective film 16 formed of the solder resist. The protective film 16 and the resist mark 15 are therefore formed of the solder resist simultaneously with each other. The number of process steps can thus be reduced.Embodiment 3The following embodiment 3 is for the purpose of explanation only and is not intended to be encompassed by the claims. FIG. 7 is a plan view of a semiconductor device according to Embodiment 3; FIG. 8 is a sectional view taken along line I-II in FIG. 7; in FIG. 7, illustration of the semiconductor chips 6 and the wires 7 is omitted.A protective film 16 formed of a solder resist is provided on the insulation substrate 1. The protective film 16 has openings 17 disposed on the solder portions 4 and openings 18 disposed on portions other than the solder portions 4. Electrodes 8 are connected to the solder portions 4 by solder 9 through the openings 17. The position of the insulation substrate 1 is detected by the openings 18 and the wires 7 are bonded to the semiconductor chips 6. The other components and process steps are the same as those in Embodiment 1.The solder 9 flowing out of the solder portions 4 does not adhere to the protective film 16 formed of the solder resist and does not reach any of the openings 18, so that no void is formed. The occurrence of partial discharge can thus be prevented. When the wiring patterns 2 are Cu, the peripheries of the solder portions 4 are usually covered with the protective film 16 formed of the solder resist. Therefore, the openings 18 that are positioning marks are formed when the protective film 16 is formed. The number of process steps can thus be reduced.Embodiment 4The following embodiment 4 is for the purpose of explanation only and is not intended to be encompassed by the claims.FIG. 9 is a plan view of a semiconductor device according to Embodiment 4; in FIG. 9, illustration of the semiconductor chips 6 and the wires 7 is omitted.Cuts 19 are provided in peripheral portions of a wiring pattern 2 on the insulation substrate 1 in place of the Ni plating mark 5 in the embodiment 1. The position of the insulation substrate 1 is detected by the cuts 19, and the wires 7 are bonded to the semiconductor chips 6. The other components and process steps are the same as those in Embodiment 1.Even if the solder 9 flowing out of the solder portions 4 covers upper portions of the cuts 19, the sealing material 13 enters the voids in the cuts 19 from the sides of the wiring pattern 2, so that no void is formed. The prevention of the partial discharge can thus be achieved. When the cuts 19 are triangular as viewed in plan view, they are widely open at the times of the wiring pattern 2, and the encapsulating material can easily enter the cavities.Embodiment 5The following embodiment 5 is for the purpose of explanation only and is not intended to be encompassed by the claims.FIG. 10 is a plan view of a semiconductor device according to Embodiment 5. FIG. 11 is a sectional view taken along line I-II in FIG. 10.The insulation substrate 1 has wiring patterns 21 and 22 separated from each other by grooves 20. A soldering portion 4 is provided on the wiring pattern 21. Holes 23 for position detection are provided in the wiring patterns 22 instead of the Ni plating marks 5 in Embodiment 1. The position of the insulation substrate 1 is detected by the holes 23, and the wires 7 are bonded to the semiconductor chips 6. The other components and process steps are the same as those in Embodiment 1.The wiring pattern 21 on which the soldering portion 4 is provided and the wiring patterns 22 in which the position detection holes 23 are provided are separated from each other by the grooves 20. Consequently, the solder 9 reaches none of the holes 23, and thus the prevention of the occurrence of the partial discharge can be achieved. Even if the solder 9 covers upper portions of the grooves 20, the sealing material 13 enters the spaces in the grooves from the sides of the wiring patterns 21, 22, so that no void is formed. The prevention of the partial discharge can thus be achieved. When the width of the grooves 20 is set to be equal to or less than 1 mm, regions required for assembly can be ensured with reliability.Embodiment 6The following embodiment 6 is for the purpose of explanation only and is not intended to be encompassed by the claims.FIG. 12 is a plan view of a semiconductor device according to Embodiment 6. FIG. 13 is a sectional view taken along line I-II in FIG. 12.The holes 24 for position detection are provided in a wiring pattern 2 instead of the Ni plating marks 5 in Embodiment 1. The position of the insulation substrate 1 is detected by the holes 24, and the wires 7 are bonded to the semiconductor chips 6. The other components and process steps are the same as those in Embodiment 1.When the distance between the soldering portion 4 and the holes 24 is set to be equal to or larger than 5 mm, the solder 9 flowing out of the soldering portion 4 does not reach the hole 24. Wide areas for wire bonding are also ensured, thereby enabling regions required for mounting to be ensured with reliability.Embodiment 7The following embodiment 7 is for the purpose of explanation only and is not intended to be encompassed by the claims.FIG. 14 is a plan view of a semiconductor device according to Embodiment 7. FIG. 15 is a sectional view taken along line I-II in FIG. 14.The insulation substrate 1 has wiring patterns 21 and 22 separated from each other by a groove 20. A soldering portion 4 is provided on the wiring pattern 21. Holes 23 and 24 for position detection are provided instead of the Ni plating marks 5 in Embodiment 1. The hole 24 is provided in the wiring pattern 21, while the hole 23 is provided in the wiring pattern 22. The position of the insulation substrate 1 is detected by the holes 23 and 24, and the wires 7 are bonded to the semiconductor chips 6. The distance between the soldering portion 4 and the hole 24 is set to be equal to or larger than 5 mm. The other components and process steps are the same as those in Embodiment 1.The wiring pattern 21 on which the soldering portion 4 is provided and the wiring pattern 22 on which the position detection hole 23 is provided are separated from each other by the groove 20. Consequently, the solder 9 does not reach the hole 23. When the distance between the soldering portion 4 and the hole 24 provided on the same wiring pattern 21 is set to be equal to or larger than 5 mm, the solder 9 flowing out of the soldering portion 4 does not reach the hole 24. The degree of freedom of design can thus be improved while preventing the occurrence of partial discharge.In each of Embodiments 5 to 7, any one of the Ni plating marks 5, the resist mark 15, the solder resist holes 18, or the cuts 19 such as those in Embodiments 1 to 4 may be used instead of the position detection holes 23 and 24. The occurrence of partial discharge can thereby be more reliably prevented.Description of Symbols1 Insulation substrate; 2 Wiring pattern; 4 Solder portion; 5 Ni plating mark (mark); 6 Semiconductor chip; 7 Wire; 8 Electrode; 9 Solder; 13 Sealing material; 15 Resist mark (mark); 17 Opening (first opening); 18 Opening (second opening); 19 Cut; 20 Groove; 21 Wiring pattern (first wiring pattern); 22 Wiring pattern (second wiring pattern); 23, 24 Hole (mark).

Claims

A method for manufacturing a semiconductor device, comprising: simultaneously forming a solder portion (4) and a mark (5) by plating on a wiring pattern (2) of an insulation substrate (1) with a region between the solder portion (4) and the mark (5) not being plated on the wiring pattern (2); mounting a semiconductor chip (6) on the insulation substrate (1); recognizing a position of the insulation substrate (1) by the mark (5) and bonding a wire (7) to the semiconductor chip (6); connecting an electrode (8) to the solder portion (4) by solder (9); and encapsulating the insulation substrate (1), the semiconductor chip (6), the wire (7) and the electrode (8) in an encapsulating material (13).A method for manufacturing a semiconductor device, comprising: forming a solder portion (4) on a wiring pattern (2) of an insulation substrate (1); simultaneously forming a protective film (16) covering a periphery of the wiring pattern (2) and a mark (15) formed on the wiring pattern (2) by solder resist; mounting a semiconductor chip (6) on the insulation substrate (1); detecting a position of the insulation substrate (1) by the mark (15) and bonding a wire (7) to the semiconductor chip (6); connecting an electrode (8) to the solder portion (4) by solder (9); and encapsulating the insulation substrate (1), the semiconductor chip (6), the wire (7) and the electrode (8) in an encapsulating material (13).A semiconductor device comprising: an insulation substrate (1) having a wiring pattern (2); a soldering portion (4) formed on the wiring pattern (2); a mark (5) disposed on the wiring pattern (2) and formed of the same material as the soldering portion (4), wherein a region between the soldering portion (4) and the mark (5) is not plated on the wiring pattern (2); a semiconductor chip (6) mounted on the insulation substrate (1); a wire (7) bonded to the semiconductor chip (6); an electrode (8) connected to the soldering portion (4) by solder (9); and an encapsulating material (13) encapsulating the insulation substrate (1), the semiconductor chip (6), the wire (7) and the electrode (8).A semiconductor device comprising: an insulation substrate (1) having a wiring pattern (2); a soldering portion (4) formed on the wiring pattern (2); a protective film (16) covering a periphery of the wiring pattern (2) and formed of a solder resist; a mark (15) disposed on the wiring pattern (2) and formed of a solder resist; a semiconductor chip (6) mounted on the insulation substrate (1); a wire (7) bonded to the semiconductor chip (6); an electrode (8) connected to the soldering portion (4) by solder (9); and an encapsulating material (13) encapsulating the insulation substrate (1), the semiconductor chip (6), the wire (7) and the electrode (8).

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