Non-planar III-N transistors with compositionally graded semiconductor channels

Abstract

Non-planar III-N transistor mounted on a substrate, wherein the transistor has: two wide-bandgap material layers on opposite {0001} faces of a III-N semiconductor channel, which has a compositional gradation along the c-axis between the two wide-bandgap III-N layers; a gate stack comprising a gate dielectric and a gate electrode, wherein the gate stack is arranged over opposing faces of the semiconductor channel spanning a distance between the two wide-bandgap material layers; and a pair of source / drain zones embedded in or coupled to the non-planar III-N semiconductor body on opposite sides of the gate stack.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention relate generally to microelectronic devices and their fabrication, and more particularly to Group III-N transistor architectures. GENERAL STATE OF THE ART

[0002] The mobile computing (e.g., smartphone and tablet) markets benefit from smaller component form factors and lower power consumption. Since current platform solutions for smartphones and tablets rely on multiple packaged integrated circuits (ICs) mounted on a printed circuit board (PCB), further scaling to smaller and more power-efficient form factors is limited. For example, a smartphone has a separate power management IC (PMIC), radio frequency IC (RFIC), and Wi-Fi / Bluetooth / GPS IC in addition to a separate logic processor IC. System-on-a-chip (SoC) architectures offer the advantage of scaling that cannot be achieved through component integration at the PCB level.While the logic processor IC itself can be considered a system on a chip (SoC) that integrates both memory and logic functions, more comprehensive SoC solutions have remained elusive for mobile computing platforms because the PMIC and RFIC operate at two or more of high voltage, high power, and high frequency.

[0003] As such, conventional mobile computing platforms typically use incompatible transistor technologies tailored specifically for the different functions performed by the PMIC and RFIC. For example, laterally diffused silicon MOS (LDMOS) technology is commonly used in the PMIC to manage voltage conversion and power distribution (battery voltage regulation, including boost and / or buck voltage conversion, etc.). Group III-V compound semiconductors, such as GaAs heterojunction bipolar transistors (HBTs), are commonly used in the RFIC to generate sufficient power gain at GHz carrier frequencies. Conventional silicon field-effect transistors implementing CMOS technology then introduce a third transistor technology used for the logic and control functions within the mobile computing platform.In addition to fundamental semiconductor material incompatibilities between the various ICs in the mobile computing platform, the transistor design for DC-DC converter switches in the PMIC was generally incompatible with the transistor design for high-frequency power amplifiers in the RFIC. For example, the relatively low breakdown voltage of silicon requires a source-to-drain isolation in a DC-DC converter switch to be far greater than is permissible for a power amplifier transistor, which requires an Ft that exceeds 20 GHz, possibly up to 500 GHz, depending on the carrier frequency (e.g., WPAN is 60 GHz, and therefore transistors need an Ft that is a multiple of 60 GHz). Such different transistor-level design requirements ensure that the manufacturing processes for the various transistor designs are different and difficult to integrate into a single process.

[0004] While an SoC solution for the mobile computing space that would integrate PMIC and RFIC functions is attractive to improve scalability, reduce costs, and improve platform power efficiency, a barrier to an SoC solution is therefore the lack of a scalable transistor technology that has both sufficient speed (i.e., a sufficiently high cutoff frequency Ft) and a sufficiently high breakdown voltage (BV).

[0005] Group III nitride (III-N) devices offer a promising perspective for integrating PMIC and RFIC functions into CMOS, as both high BV and Ft can be achieved. However, to date, III-N transistors employ a 2D electron gas (2DEG) or layered charge as a transport channel. This 2D layered charge is formed at the abrupt heterointerface, which is created by epitaxially deposing a film with greater spontaneous and piezoelectric polarization, such as AlN, on GaN. Because the polarization fields are highly directional, the 2D layered charge forms only in the upper (0001) wurtzite crystal plane at the heterointerface. This material-based asymmetry poses a challenge for implementing multi-gate transistor architectures, such as the dual-gate and tri-gate designs now practiced in silicon by industry leaders.As such, the footprint of a III-N transistor can be disadvantageously large and subject to various performance limitations related to those that have driven the transition to non-planar silicon devices (e.g., short-channel effects).

[0006] US 2006 / 0 231 860 A1 describes novel GaN / AlGaN metal-semiconductor field-effect transistor (MESFET) structures grown without any impurity doping in the channel. A highly mobile, polarization-induced bulk channel charge is generated by linearly grading the channel region from GaN to Al0.3Ga0.7N over a distance of, for example, 100 nm. A polarization-doped field-effect transistor (PolFET) was fabricated and tested under DC and RF conditions. Under DC conditions, a current density of 850 mA / mm and a transconductance of 93 mS / mm were observed. Small-signal characterization of devices with a 0.7 µm gate length revealed a cutoff frequency of f_tau=19 GHz and a maximum oscillation of f_max=46 GHz. The PolFETs exhibit better performance than comparable MESFETs with impurity-doped channels and are suitable for high microwave power applications.An important advantage of these devices over AlGaN / GaN HEMTs is that the transconductance versus gate voltage profile can be tailored by composition grading to achieve better large-signal linearity.

[0007] WO 2012 / 067687 A2 describes a nanowire comprising a polar semiconductor material whose composition is graded along the nanowire from a first end to a second end to define a polarization doping profile along the nanowire from the first end to the second end. The polar semiconductor material may comprise a Group IH nitride semiconductor, such as an alloy of GaN and AlN or an alloy of GaN and InN. Such nanowires may be formed by nucleating the first ends on a substrate, growing the nanowires by depositing polar semiconductor material on the nucleated first ends on a selected growth surface, and compositionally grading the nanowires during growth to impart the polarization doping.The direction of the compositional gradation can be reversed during nanowire growth to reverse the type of polarization doping imparted. In some embodiments, the reversal creates n / p or p / n junctions in the nanowires.

[0008] The invention is defined in the independent claims. Embodiments of the invention are described in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Embodiments of the present invention are illustrated by way of example and not limitation and may be more fully understood by reference to the following detailed description when considered in conjunction with the figures: Fig. 1A is an isometric illustration of a GaN crystal orientation for a non-planar Group III-N transistor according to one embodiment; the Fig. 1B, Fig. 1C and Fig. 1D are graphical representations of alloy content corresponding to zones of a compositionally graded III-N semiconductor channel shown in cross-section and having the crystal orientation shown in Fig. 1A is illustrated according to one embodiment; Fig. 1E is an isometric illustration of a GaN crystal orientation for a non-planar Group III-N transistor according to one embodiment; the Fig. Figure 1F is a graphical representation of alloy content corresponding to zones of a compositionally graded III-N semiconductor channel shown in cross-section and having the crystal orientation shown in Fig. 1E is illustrated according to one embodiment; Fig. 2A illustrates a cross-section through a channel region of a non-planar tri-gate III-N transistor according to embodiments of the invention; Fig. Figure 2B shows modeled charge within the channel zone, which is Fig. 2A, according to embodiments of the invention; Fig. 2C illustrates a cross-section through a channel region of a non-planar gate wraparound III-N transistor according to embodiments of the invention; Fig. 2D represents modeled charge within the channel zone, which is Fig. 2C, according to embodiments of the invention; Fig. 3 is a flow diagram illustrating a method of fabricating a non-planar high voltage transistor according to an embodiment; the Fig. 4A, Fig. 4B, Fig. 4C and Fig. 4D are isometric illustrations of a non-planar high voltage nanowire transistor constructed in accordance with an embodiment of the Fig. 3; Fig. 5 is a functional diagram of an SoC implementation of a mobile computing platform according to an embodiment of the present invention; and Fig. 6 is a functional diagram of a computing device according to an implementation of the invention. DETAILED DESCRIPTION

[0010] In the following description, numerous details are set forth, but it will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In some instances, well-known methods and devices are shown in block diagram form rather than in detail in order not to obscure embodiments of the present invention. References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, function, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, appearances of the phrase "in one embodiment" in various places in the specification are not necessarily referring to the same embodiment of the invention.Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment wherever the two embodiments are not mutually exclusive.

[0011] The terms "coupled" and "connected," along with their derivatives, may be used herein to describe structural relationships between components. It should be understood that these terms are not synonymous with one another. Rather, in certain embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with one another. "Coupled" may be used to indicate that two or more elements are in either direct or indirect (with other intervening elements in between) physical or electrical contact with one another, and / or that the two or more elements operate or interact with one another (such as in a cause-and-effect relationship).

[0012] As used herein, the terms "over," "under," "between," and "on" refer to a relative location of a layer of material with respect to other layers. As such, for example, a layer disposed over or under another layer may be in direct contact with the other layer, or it may have one or more intermediate layers. Furthermore, a layer disposed between two layers may be in direct contact with the two layers, or it may have one or more intermediate layers. In contrast, a first layer "on" a second layer is in direct contact with that second layer.

[0013] Described herein are embodiments of non-planar III-N transistors having a III-N semiconductor channel compositionally graded in a manner that forms a 3-dimensional electron gas (3DEG) within the III-N semiconductor channel. In practice, the non-planar III-N transistor architectures described herein advantageously provide low base resistance and / or reduce substrate surface area for a given drive current. In embodiments, the graded III-N semiconductor channel has multiple gate areas, enabling reduced short-channel effects and higher drain breakdown voltages (BVDD).

[0014] In embodiments, the high-electron-mobility field-effect transistors (FETs) described herein are used in SoC solutions that integrate an RFIC into a PMIC to implement high-voltage and / or high-power circuits. With the transistor structures described herein, SoC solutions can deliver the product-specific electrical current and power requirements required for a mobile computing platform. The fast-switching, high-voltage transistors are capable of handling high input voltage swings and providing high power efficiencies at RF frequencies. In embodiments, the III-N transistor architectures described herein are monolithically integrated into Group IV transistor architectures such as planar and non-planar silicon CMOS transistor technologies.In specific embodiments, the III-N transistors described herein are used in SoC architectures that integrate high-performance wireless data transmission and / or high-voltage power management functions into low-power CMOS logic data processing. High-frequency operation suitable for broadband wireless data transmission applications is possible, while the use of wide-bandgap III-N materials also provides high BV generation with sufficient RF for wireless data transmission applications. This combination of high Ft / Fmax and high-voltage capability also enables the III-N FET architectures described herein to be used for high-speed switching applications in DC-DC converters that utilize reduced-size inductive elements.Since both power amplification and DC-DC switching applications are essential functional blocks in smartphones, tablets, and other mobile platforms, the structures described here can be used in an SoC solution for such devices. In one example, a first III-N FET is used in a DC-DC circuit of a PMIC, and a second III-N FET is used in an amplifier circuit of an RFIC.

[0015] In embodiments, a III-N semiconductor channel of a III-N FET comprises a ternary or quaternary compositionally graded alloy. In one ternary embodiment, the III-N semiconductor channel comprises indium gallium nitride (InxGa1-xN), where x is varied along the wurtzite crystal c-axis of the semiconductor channel. In another ternary embodiment, the III-N semiconductor channel comprises aluminum gallium nitride (AlxGa1-xN), where x is varied along the c-axis of the semiconductor channel. In one quaternary embodiment, both indium and aluminum are present as an InxAlyGal-x-yN alloy, where x and / or y are varied along the c-axis of the semiconductor channel. Fig. 1A is an isometric illustration of a GaN crystal orientation for a non-planar Group III-N transistor according to one embodiment. Fig. Figure 1B is a cross-sectional view of an InGaN-based compositionally graded III-N semiconductor channel showing the Fig. 1A. A graphical representation of the alloy content corresponding to zones within the III-N semiconductor channel is also shown.

[0016] The Fig. The GaN crystal illustrated in Figure 1A is not centrally symmetric, meaning that the III-N crystal lacks inversion symmetry and, in particular, the {0001} planes are not equivalent. In pure GaN, the (0001) plane is usually referred to as the Ga face (+c polarity, or in the

[0001] direction) and the other (0001) plane is referred to as the N face (-c polarity, or in the

[0001] direction). The alignment in Fig. 1A is therefore Ga-plane or (0001), where the (0001) plane has the lattice constant a on a top side of the III-N semiconductor channel.

[0017] Due to polar bonding and crystal asymmetry, a spontaneous polarization field PSP is present within the III-N semiconductor, and when the III-N semiconductor is subjected to tensile stress in a direction parallel to the (0001) plane (along the y-dimension as in Fig. 1B), a piezoelectric polarization field PPE with PSP is aligned away from the (0001) plane and toward the (0001) plane. Compositional grading within the III-N semiconductor can distribute these polarization fields to provide desired distributional polarization-induced charge carriers (e.g., type n) relative to the particular Ga or N crystal facet. In particular, spontaneous polarization fields in InN and AlN, when deposited on a Ga facet of the GaN, are aligned opposite each other, and therefore embodiments herein achieve a desired distribution of polarization carrier charge within the III-N semiconductor channel volume by grading the In content in a first direction (e.g., increasing In%) relative to either the Ga or N facet, while embodiments grading the Al content do so in the opposite direction (e.g., decreasing Al%).

[0018] In embodiments, the In content is graded to include relatively more pure GaN (e.g., 0% In) at an interface of a wide bandgap material. With such grading, a 3D electron gas may be formed within the graded semiconductor, with no charge carriers present near a substrate region, which may be advantageous for reducing or preventing creepage, as further described elsewhere herein in the context of Fig. 2A to 2B. As described in Fig. As shown in Figure 1B, the grading of the In content is advantageously further symmetrical across a plane centered between the interface of a wide bandgap transition layer 115 and the interface of a wide bandgap III-N polarization layer 125. In embodiments, the In content is graded upward from the respective III-N faces so that they meet at approximately half the c-axis thickness of the graded III-N semiconductor channel 120. Such a grading profile may be advantageous in achieving a specific transport channel geometry with a minimal range of alloy content between the Ga and N faces. Variations in which the In grading is asymmetric across the midplane are also possible.

[0019] In the symmetrically graded version, which is Fig. 1B, the III-N semiconductor channel 120 is graded starting at the interface with the transition layer 115 with increasing indium content over a first distance equal to approximately one-half the thickness of the III-N semiconductor channel 120 (1 / 2 T). Then, the III-N semiconductor channel 120 is further graded with decreasing indium content over a second distance equal to approximately 1 / 2 T to the interface of the polarization layer 125. In the exemplary embodiment, the In content is 0% (i.e., InxGa1-xN with x=0 or pure GaN) at the interface of the semiconductor channel 120 with each of the wide bandgap transition and polarization layers 115, 125. As shown in Fig. 1B by the general location of the charge symbols, with pure GaN at the (0001) face of the III-N semiconductor channel 120, charge carriers are missing at the interface with the wide bandgap transition layer 115.

[0020] In the exemplary embodiment, the maximum In content reaches approximately 10%, although it may be higher in other embodiments (e.g., 15 to 20%). Over this range, the grading is advantageously uniform across the grading pitch to achieve a uniform polarization charge density. In the exemplary embodiment, the grading is linear in directions away from the (0001) face and away from the (0001) face of the III-N semiconductor channel 120 toward the half-thickness or midplane direction. Of course, non-linear gradations (e.g., parabolic across the thickness of the semiconductor channel 120, etc.) are also possible.

[0021] Fig. Figure 1C is a cross-sectional view of an AlxGal-xN-based compositionally graded III-N semiconductor channel 120 with the crystal orientation shown in Fig. 1A, according to one embodiment. Starting at the interface with the transition layer 115, the III-N semiconductor channel 120 is graded with decreasing Al content over a first distance equal to approximately one-half the thickness of the III-N semiconductor channel 120 (1 / 2 T). The III-N semiconductor channel 120 is further graded with increasing Al content over a second distance equal to approximately 1 / 2 T to the interface of the polarization layer 125. In the exemplary embodiment, the Al content is 0% (i.e., pure GaN) at half the thickness or midplane of the semiconductor channel 120 with a maximum Al content (e.g., 30% or more) at the interface of each of the wide bandgap transition and polarization layers 115, 125. As shown in Fig. Figure 1C again illustrates the absence of charge carriers at the interface with the wide bandgap transition layer 115.

[0022] Within the semiconductor channel 120, the Al gradation is advantageously uniform to achieve a uniform polarization charge density. In the exemplary embodiment, the gradation from the (0001) and (0001) surfaces of the III-N semiconductor channel 120 toward the half-thickness or midplane direction is linear. Of course, non-linear gradations (e.g., parabolic across the thickness of the semiconductor channel 120, etc.) are again possible.

[0023] In quaternary embodiments, a grading of Al and / or In is comparable to that used in the Fig. 1B, Fig. 1C, wherein at least one of the Al and In content is varied (e.g., reduced or increased) from the transition layer 115 over a first distance equal to approximately one-half the thickness of the III-N semiconductor channel 120 (1 / 2 T), and then varied (e.g., increased or reduced) symmetrically over a second distance equal to approximately one-half the thickness of the III-N semiconductor channel 120 (1 / 2 T) to the polarization layer 125.

[0024] In other embodiments, the In content is graded such that the highest In content is present at the wide bandgap material interface at the N-face (0001) and the lowest In content is present at the wide bandgap material interface at the Ga-face (0001). This alternative grading profile is shown in Fig. 1D along with a corresponding cross-sectional view of the III-N semiconductor channel 120 and wide bandgap layers 115, 125. As shown, the In content at the interface with the high bandgap transition layer 115 is sufficiently high for charge carriers (electrons) to be present within the III-N semiconductor channel 120 adjacent to the wide bandgap transition layer 115 when a bias voltage above the threshold voltage is applied to a gate electrode. In the exemplary embodiment, the peak In content is 20%, although it can range from 15 to 20%. Again, uniform grading is advantageous, with the exemplary embodiment being a linear grading such that the In content at half the thickness is again approximately 10%, with substantially pure GaN at the interface of the polarization layer 125.In particular, grading the Al content even with an opposite profile than that described for In does not have the same effect, since the GaN band gap is much wider than that for the InGaN embodiments.

[0025] Since the Fig. 1B and Fig. 1C involve grading profiles that are inverted to each other due to the different polarization strengths of the Al and In ternary alloys, the grading profile can be more conveniently expressed as a function of the bandgap. If the bandgap of InGaN is narrower than that of GaN and the bandgap of AlGaN is wider than that of GaN, each of the grading profiles in the Fig. 1B, Fig. 1C and even 1D the band gap over a distance of at least one of the two material layers 115 and 125 with wide band gap (towards a center plane of the semiconductor channel in the Fig. 1B and Fig. 1C and towards the second material layer with wide band gap in Fig. 1D). In other words, the Fig. 1B and Fig. 1C, the bandgap of both of the two material layers 115 and 125 with wide bandgap to the midplane. For the embodiments shown in Fig. In the embodiment illustrated in Figure 1D, the bandgap decreases from the wide bandgap material layer 125 toward the wide bandgap material layer 115.

[0026] In particular, the Fig. 1A to 1D are also applicable to the epitaxial channel layers grown on sidewall surfaces of a substrate, which may be done, for example, for the purpose of providing a (111) or (110) nucleation surface of a substrate (110) or (100). For such embodiments as described in Fig. 1E, a patterned template surface extends from the substrate such that the III-N wurtzite crystal is rotated so that the {0001} faces form sidewalls and one of the {1010} faces forms top and bottom surfaces. Fig. Figure 1F illustrates exemplary In and / or Al gradation profiles for the III-N semiconductor channel 120, which represents the alignment in Fig. 1E.

[0027] Fig. Figure 2A illustrates a cross-section through a channel region of a non-planar tri-gate III-N transistor 201 according to embodiments of the invention. Generally, the transistor 201 utilizes the graded III-N semiconductor channel 120 as described elsewhere herein in the context of Fig. 1A to 1B, and reference numbers are therefore retained for previously described features. The III-N transistor 201 is a gate voltage-controlled device (i.e., a FinFET), and in the exemplary embodiment, it is an n-type FinFET comprising at least one non-planar crystalline semiconductor channel 120 disposed on a substrate layer 205.

[0028] In one embodiment, the substrate layer 205 comprises a buffer layer consisting of a group III-N semiconductor grown on a carrier substrate (not shown) (shown in Fig. 1A). In a particular embodiment, the substrate layer 205 comprises one or more layers of GaN disposed on a silicon support substrate. In the exemplary embodiment, the silicon support substrate is substantially monocrystalline and is (100) silicon (i.e., has a (100) top surface) or (110) silicon (i.e., has a (110) top surface). The support substrate may also be composed of alternative materials that may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, carbon (SiC), and sapphire.

[0029] How to continue in Fig. As shown in Figure 2A, transistor 201 comprises a non-planar III-N semiconductor body separated from substrate layer 205 by junction layer 115. In the exemplary embodiment, junction layer 115 is composed of, and physically positioned with respect to, III-N semiconductor channel 120 to prevent or at least reduce leakage currents from transistor 101 into substrate layer 105 (i.e., subfinal leakage currents). Therefore, junction layer 115 is composed of a wider bandgap material than the III-N semiconductor channel material in direct contact with junction layer 115. Junction layer 115 also allows epitope growth of III-N semiconductor channel 120 and therefore also exhibits wurtzite crystallinity. As such, the transition layer 115 may be one or more III-N materials or crystalline dielectrics, with exemplary III-N materials being AlN, AlGaN (e.g., Al < 0.3 Ga > 0.7 N), or AlInN (e.g.,Al0.83In0.17N) and exemplary crystalline dielectrics include crystalline wurtzite nitrides such as TiN, SiN, AlN, and crystalline wurtzite oxides such as Al2O3, Gd2O3, Sc2O3, Ta2O5, and TiO2. Such dielectric material layers are typically deposited as polycrystalline layers and tend to form crystals suitable as templates for III-N growth when subjected to the high growth temperature of III-N semiconductors.

[0030] The III-N semiconductor channel 120 is arranged on the transition layer 115. According to embodiments, the III-N semiconductor channel 120 has the wurtzite structure and is compositionally graded along the growth direction perpendicular to the {0001} basal plane (i.e., along the c-axis of the III-N semiconductor crystal), as described in the context of Fig. 1A to 1C. In embodiments, the III-N semiconductor channel 120 has a thickness (z-axis in Fig. 2A) between 25 nm and 100 nm. In embodiments, the III-N semiconductor channel 120 has an intrinsic impurity doping level without intentional dopants. As shown in Fig. As shown in Figure 2A, the III-N semiconductor channel 120 includes multiple layers 120A-120N to emphasize compositional grading within a thickness of the III-N semiconductor channel along the c-axis. In the exemplary embodiment, In is graded to the peak concentration at approximately one-half of the semiconductor channel thickness T. In the exemplary embodiment, the III-N semiconductor channel 120 includes InGaN, which has an advantage over AlGaN embodiments because the polarization field of InGaN is oriented opposite that of AlGaN and GaN, and the conduction band offset from the wide bandgap transition layer 115 is larger. This results in relatively better carrier confinement for a given transition layer material and / or relaxes constraints on the transition layer composition (e.g., allowing a lower Al content in an AlGaN transition layer).

[0031] As in Fig. As further illustrated in Figure 2A, a polarization layer 125 is disposed on the (0001) surface of the III-N semiconductor channel 120. The polarization layer 125 functionally serves as a charge inducing layer to controllably provide carriers to the III-N semiconductor channel 120. In embodiments, the thickness of the polarization layer 125 ranges between 1 nm and 20 nm. The polarization layer may further serve as a carrier confinement means where the band gap is sufficiently wide. In embodiments, the polarization layer 125 comprises at least one of AlInGaN, AlGaN, AlInN, or AlN.The polarization layer 125 may also include several compositionally different layers, such as a first charge inducing layer and an overlying upper barrier layer of different composition, to allow transistor threshold voltage tuning while ensuring that a thin (e.g., > 0.5 nm) wide bandgap material is present at the surface of the semiconductor channel layer for reduced alloy scattering and high charge carrier mobility.

[0032] With the compositional grading, as it is in the context of Fig. 1A to 1B, polarization fields (and band gaps) within the graded III-N semiconductor channel 120 are varied to allow the formation of a bulk charge within the III-N semiconductor channel 120, which can then be modulated by the field effect through the gate dielectric 240 as a function of a voltage potential on a gate electrode 250. By selecting a work function for a gate electrode 250, a threshold voltage (Vt) can be set to define on and off states of connectivity between the source and drain ends of the semiconductor channel 120. Since any conventional source / drain architectures can be used for the transistor 201, further details about the source / drain regions are omitted.

[0033] Fig. Figure 2B illustrates modeled charge within the III-N semiconductor channel of transistor 201, which is Fig. 2A, according to embodiments of the invention. The thickness (z-dimension) of the III-N semiconductor channel 120 is modeled as 50 nm and a y-dimension width as 10 nm. As shown, relative to region 220M, higher charge density regions associated with transport channels are present along several surface levels within the III-N semiconductor channel 120 under gate bias conditions above the threshold voltage. Therefore, in addition to a transport channel 220C having a higher charge density near the (0001) upper III-N semiconductor channel surface 110C, there are also the additional transport channels 220A and 220B near the III-N semiconductor channel sidewalls 210A and 210B (i.e., near the {1010} planes). This larger transport channel dimensionality (ie, 3D instead of just 2D) is a result of the type with embodiments described in the context of Fig. 1A to 1B, consistent compositional grading of III-N semiconductor channel 120. In particular, with substantially pure GaN at the interface of junction layer 115, even under gate bias conditions above the threshold voltage, no transport channel is present near junction layer 115. As such, sidewall transport channels 220A, 220B are pinched off at base 220N of non-planar transistor 201, reducing subfin leakage current. Therefore, III-N FinFET 201 exhibits a beneficial multi-side transport channel responsive to the gate stack present at the sidewalls of III-N semiconductor channel 120.

[0034] Fig. Figure 2C illustrates a cross-section through a channel region of a non-planar multi-gate III-N transistor 202 according to embodiments of the invention. Generally, the transistor 202 utilizes the graded III-N semiconductor channel 120 as described elsewhere herein in the context of Fig. 1D, and reference numbers are therefore retained for previously described features. The III-N transistor 202 is a gate voltage-controlled device (i.e., a "gate-wrap" or "nanowire" FET), and in the exemplary embodiment, it is an n-nanowire FET having at least one non-planar crystalline semiconductor channel 120 disposed above the substrate layer 205.

[0035] As in Fig. 2C, the transistor 202 comprises a non-planar III-N semiconductor body separated from the substrate layer 205 by the transition layer 115, as well as the gate dielectric 240 and the gate electrode 250. The III-N semiconductor channel 120 is arranged on the transition layer 115. According to embodiments, the III-N semiconductor channel 120 is compositionally graded along the growth direction perpendicular to the {0001} base plane (i.e., along the c-axis of the III-N semiconductor crystal), as described in the context of Fig. 1D. In embodiments, the III-N semiconductor channel 120 has a thickness (z-axis in Fig. 2C) that is smaller than that for transistor 201, such as less than 30 nm. The y-dimension or width of III-N semiconductor channel 120 is larger than the z-axis thickness (e.g., 50 nm or more) for a "ribbon" geometry. Other dimensions are, of course, possible. Channel doping is optional, and in certain embodiments, III-N semiconductor channel 120 again has an intrinsic impurity doping level without intentional dopants. As shown in Fig. As shown in Figure 2C, the III-N semiconductor channel 120 includes multiple layers 120A through 120N to emphasize compositional grading. In the exemplary embodiment, In is graded from a peak concentration (e.g., ~20%) at the interface of the transition layer 115 to 0% (pure GaN) at the interface of the polarization layer 125.

[0036] Fig. Figure 2D represents modeled charge within the III-N semiconductor channel of transistor 202, which is Fig. 2C, applying a positive potential to the gate electrode 250, according to embodiments of the invention. A charge density associated with transport channels is again present along several surface levels within the III-N semiconductor channel 120 under gate bias conditions above the threshold voltage. In addition to a transport channel 220C near the (0001) surface 110C, there is also the additional transport channel 220D near the (0001) surface of the III-N semiconductor channel 120. This larger transport channel dimensionality (i.e., 3D instead of just 2D) is a result of the in a manner similar to embodiments described in the context of Fig. 1D, consistent compositional grading of III-N semiconductor channel 120. In particular, the transport channel 220D with 20% In content at the interface of the junction layer 115 near the junction layer 115 overlaps the transport channel 220C under gate bias conditions above the threshold voltage, favoring a highest charge carrier concentration toward the center of the nanowire. The top and bottom surfaces of the nanowire semiconductors are therefore both functionally gate-coupled.

[0037] Fig. Figure 3 is a flow diagram illustrating a method 300 for fabricating a non-planar III-N field-effect transistor (FET) according to embodiments of the invention. While method 300 highlights the main operations, each operation may involve many more process steps, and the numbering of the operations or the relative positioning of the operations in Fig. 3 does not imply any order. The method 300 begins with growing a III-N semiconductor stack at operation 301 by a technique such as, but not limited to, MOCVD, MOVPE, or MBE. In particular, operation 301 entails forming a wide bandgap crystalline transition layer, such as any of those described elsewhere herein for the transition layer 115. A ternary or quaternary III-N semiconductor channel layer is then grown over the transition layer, with partial pressures of the alloy bodies appropriately varied to grade the composition of the III-N semiconductor channel layer across a thickness of the channel layer, as described elsewhere herein (e.g., toward a narrower bandgap composition near the polarization layer).

[0038] The grading may further be uniform and symmetrical across half the thickness of the III-N semiconductor channel layer. During epitope growth from the transition layer, for example, the composition of the III-N semiconductor channel layer may be varied from a first lower indium content near the transition layer with monotonically increasing indium content toward the narrowest bandgap composition and with monotonically decreasing indium content to the second wider bandgap composition. Alternatively, in a nanowire embodiment, at operation 301, the composition of the III-N semiconductor channel layer may be varied during growth from a highest indium content near the transition layer with monotonically decreasing indium content toward the narrowest bandgap composition before changing reactor conditions for polarization layer growth.For example, grading In from 0% to 10% or more may be performed during operation 301. As another example, grading Al from 30% or more down to 0% and back to 30% or more may be performed during operation 301. After grading the III-N semiconductor channel, a wide bandgap polarization layer is then epitaxially grown over the III-N semiconductor channel layer near the wider bandgap composition.

[0039] The operation 301 is applicable to either a finFET embodiment or a nanowire embodiment, and selective epitaxial techniques may be used to grow a fin or nanowire structure, or alternatively, a patterning process may be performed at operation 303 to form a fin or nanowire structure from an all-encompassing (non-selective) epitaxial growth. Fig. 4A, Fig. 4B, Fig. 4C, Fig. 4D and Fig. 4E are isometric illustrations of non-planar Group III-N nanowire transistors fabricated according to an embodiment of the method 300. In particular, the fin structure 410 shown in Fig. 4A, the more complex type of finFET, wherein the homogeneous finFET 201 has essentially the same general structure, but with a single III-N semiconductor layer that provides the gradation of the Fig. 1B to 1C. The Fig. 4A to 4E are therefore applicable to the formation of the finFET 201 as well as the nanowire transistor 202.

[0040] Fig. Figure 4A illustrates a vertical stack of nanowires 210A and 210B, each of which has the graded semiconductor channel disposed between the transition and wide bandgap polarization layers, as shown in Fig. 1D. Sacrificial materials 212A, 212B, and 212C with different compositions are arranged between the nanowires 210A, 210B. The layer thicknesses T1 to T4 depend on the desired nanowire dimensions and also on the ability to fill the thicknesses T1, T3 with the gate stack. An insulator layer 407 is formed on both sides of the fin structure 410 above the substrate layer 205, for example, using a shallow trench isolation technique.

[0041] Returning to Fig. 3, at operation 305, a drain contact is formed for wrapping the nanowire 210A and 210B, either partially or completely. At operation 310, a source contact is formed in a similar manner. At operation 315, a gate conductor is coaxially wrapped completely around the graded semiconductor channel within the III-N stacks 210A and 210B. The device is then completed at operation 320, for example, using conventional interconnect techniques.

[0042] Fig. 4B illustrates an embodiment of operations 305, 310, and 315 that involves forming a sacrificial gate 412 disposed on the fin structure 410. Referring to Fig. 4C, the sacrificial gate 412 has been removed, leaving spacers 255 and a portion of the interlayer dielectric (ILD) layer 420. As further shown in Fig. As shown in Figure 4C, the sacrificial semiconductor layers 212A, 212B, and 212C are removed in the channel region, which was originally covered by the sacrificial gate 412. The discrete nanowires 210A and 210B of the first semiconductor material then remain.

[0043] As in Fig. As shown in Figure 4D, the gate stack is then formed by coaxially wrapping the nanowires 210A, 210B within the channel region 245. The gate 250 is formed in the trench in the interlayer dielectric layer 420 after etching the epitaxial stack into the discrete group III-N nanowires. In addition, Fig. 4D illustrates the result of the subsequent removal of the interlayer dielectric layer 420 and the formation of a source / drain contact 421 in the source / drain region 235B (where the region 220 is drawn with the second source / drain end exposed for illustrative purposes).

[0044] Fig. 5 is a functional diagram of an SoC implementation of a mobile computing platform according to an embodiment of the present invention. The mobile computing platform 500 may be any portable device configured for electronic data display, electronic data processing, and wireless electronic data transmission, respectively. For example, the mobile computing platform 500 may be any of a tablet, a smartphone, a laptop, etc., and includes a display 505, which in the exemplary embodiment is a touchscreen (e.g., capacitive, inductive, resistive, etc.) that allows for receiving user input, the SoC 510, and a battery 513.The greater the integration density of the SoC 510, the more of the form factor can be occupied by the battery 513 for the longest operating life between charges, as illustrated within the mobile computing platform 500, or by memory (not shown) such as a solid-state drive for the greatest possible functionality.

[0045] Depending on its applications, the mobile computing platform 500 may include other components, including, but not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, digital signal processor, a secret processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS), a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard disk drive, a compact disc (CD), a digital versatile disc (DVD), etc.).

[0046] The SoC 510 is further illustrated in expanded view 521. Depending on the embodiment, the SoC 510 comprises a portion of a substrate 102 (i.e., a chip) on which two or more of a power management integrated circuit (PMIC) 515, an RF integrated circuit (RFIC) 525 including an RF transmitter and / or receiver, a controller thereof 511, and one or more main processor cores 530, 531 are fabricated. The RFIC 525 can implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols referred to as 3G, 4G, 5G, and beyond. The RFIC 525 can include a variety of communication chips.For example, a first communication chip may be associated with shorter-range wireless communications such as WiFi and Bluetooth, and a second communication chip may be associated with longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0047] It will be apparent to those skilled in the art that, of these functionally different circuit modules, typically only CMOS transistors are used, except in PMIC 515 and RFIC 525. In embodiments of the present invention, PMIC 515 and RFIC 525 employ one or more of the Group III nitride transistors described herein (e.g., Group III nitride transistor 401) employing an embodiment of the horizontal c-axis III-N epitaxial stacks described herein. In further embodiments, PMIC 515 and RFIC 525 employing the Group III nitride transistors described herein are integrated into one or more of controller 511 and processor cores 530, 531, which are provided in silicon CMOS technology and monolithically integrated into PMIC 515 and / or RFIC 525 on (silicon) substrate 102.It will be appreciated that within the PMIC 515 and / or RFIC 525, the high-frequency, high-voltage Group III nitride transistors described herein need not be used to the exclusion of CMOS, but rather, silicon CMOS may be further incorporated within each of the PMIC 515 and RFIC 525.

[0048] The Group III nitride transistors described herein can be used specifically where high voltage fluctuations are present (e.g., 7 to 10 V battery current regulation, DC-DC conversion, etc. within the PMIC 515). As illustrated, in the exemplary embodiment, the PMIC 515 has an input coupled to the battery 513 and an output that provides power to all other functional devices within the SoC 510. In another embodiment, where additional ICs are provided within the mobile computing platform 500 but external to the SoC 510, the output of the PMIC 515 further provides power to all of these additional ICs external to the SoC 510.

[0049] As further illustrated in the exemplary embodiment, the PMIC 515 has an output coupled to an antenna and may further have an input coupled to a communications module on the SoC 510, such as an analog and digital RF baseband module (not shown). Alternatively, such communications components may be provided on an IC off-chip from the SoC 510 and coupled into the SoC 510 for transmission. Depending on the Group III nitride materials used, the Group III nitride transistors described herein (e.g., III-N transistor 401) may further provide the high power efficiency (PAE) required by a power amplifier transistor having an Ft of at least ten times the carrier frequency (e.g., 1.9 GHz in an RFIC 725 designed for 3G or GSM cellular communications).

[0050] Fig.6 illustrates a computing device 600 according to one implementation of the invention. Computing device 600 includes a circuit board 602. Circuit board 602 may include a number of components, including, but not limited to, a processor 604 and at least one communication chip 606. Processor 604 is physically and electrically coupled to circuit board 602. In some implementations, at least one communication chip 606 is also physically and electrically coupled to circuit board 602. In further implementations, communication chip 606 is part of processor 604.

[0051] Depending on its applications, computing device 600 may include other components that may or may not be physically and electrically coupled to circuit board 602. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a secret processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS), a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard disk drive, a compact disc (CD), a digital versatile disc (DVD), etc.).

[0052] The communication chip 606 enables wireless communications for transferring data to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data using modulated electromagnetic radiation through a non-solid medium. The term does not imply that the connected devices do not include wires, although in some embodiments they may not. The communication chip 606 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols referred to as 3G, 4G, 5G, and beyond. Computing device 600 may include a plurality of communication chips 606. For example, a first communication chip 606 may be associated with shorter-range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip 606 may be associated with longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0053] The processor 604 of the computing device 600 includes an integrated circuit (IC) die packaged within the processor 604. In some embodiments of the invention, the processor's IC die comprises one or more devices, such as graded III-N-channel MOS-FETs, formed in accordance with embodiments described elsewhere herein. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memories to transform that electronic data into other electronic data that can be stored in registers and / or memories.

[0054] The communication chip 606 also includes an IC die packaged within the communication chip 606. According to another embodiment of the invention, the IC die of the communication chip comprises one or more devices, such as MOSFETs, having features and / or fabricated according to embodiments described elsewhere herein.

[0055] In further implementations, another component housed within the computing device 600 may include an IC die having one or more devices such as MOS-FETS with features and / or fabricated according to embodiments described elsewhere herein.

[0056] In embodiments, computing device 600 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder.

Claims

[1] Non-planar III-N transistor arranged on a substrate, the transistor comprising: two wide bandgap material layers on opposite {0001} faces of a III-N semiconductor channel having a compositional grading along the c-axis between the two wide bandgap III-N layers; a gate stack comprising a gate dielectric and a gate electrode, the gate stack disposed over opposing surfaces of the semiconductor channel spanning a distance between the two wide bandgap material layers; and a pair of source / drain regions embedded in or coupled to the non-planar III-N semiconductor body on opposite sides of the gate stack. [2] The III-N transistor of claim 1, wherein the III-N semiconductor channel has a bandgap that narrows from at least one of the two wide bandgap material layers to a midplane orthogonal to the c-axis and centered within the III-N semiconductor channel. [3] The III-N transistor of claim 2, wherein the III-N semiconductor channel has a decreasing bandgap from both of the two wide bandgap material layers to the midplane. [4] A III-N transistor according to claim 3, wherein the compositional grading is uniform and symmetric across the midplane. [5] The III-N transistor of claim 2, wherein the compositional grading comprises at least one of a lower In content and a higher Al content near at least one of the two wide bandgap material layers relative to a point distal from at least one of the two wide bandgap material layers. [6] The III-N transistor of claim 5, wherein the In content varies by at least 10% between the at least one wide bandgap material layer and the midplane. [7] The III-N transistor of claim 5, wherein the III-N semiconductor channel is compositionally graded from GaN near each of the wide bandgap material layers to about 10% indium at the midplane. [8] The III-N transistor of claim 5, wherein the III-N semiconductor channel is compositionally graded from GaN near a first of the wide bandgap material layers to the maximum In content at a second of the wide bandgap material layers. [9] The III-N FET of claim 8, wherein the gate stack is completely wrapped around both of the two wide bandgap layers to form a III-N nanowire transistor. [10] The III-N FET of claim 9, wherein the nanowire is disposed within a vertical stack of nanowires, and wherein each of the nanowires includes a channel region having a III-N semiconductor channel compositionally graded along the c-axis between the two wide bandgap III-N layers. [11] A III-N transistor according to claim 2, wherein the III-N semiconductor channel is compositionally graded with a highest Al content near each of the two wide bandgap material layers and decreasing towards the midplane. [12] The III-N transistor of claim 1, wherein the wide bandgap material layer near the (0001) face of the non-planar III-N semiconductor body is selected from the group consisting of: AlN, AlInN, AlGaN, or AlInGaN, and wherein the wide bandgap material layer near the (0001) face of the non-planar III-N semiconductor body is AlN, AlInN, AlGaN, or AlInGaN. [13] Non-planar III-N transistor arranged on a substrate, the transistor comprising: two wide bandgap material layers on opposite sides of a III-N semiconductor channel having a compositional grading along the c-axis between the two crystalline wide bandgap material layers; a gate stack comprising a gate dielectric and a gate electrode, the gate stack disposed over opposing surfaces of the semiconductor channel spanning a distance between the two wide bandgap material layers; and a pair of source / drain regions embedded in or coupled to the non-planar III-N semiconductor body on opposite sides of the gate stack, wherein a transport channel is formed in the III-N semiconductor channel adjacent to both opposing surfaces in response to a bias voltage at a gate electrode exceeding a threshold voltage of the transistor. [14] A III-N transistor according to claim 13, wherein a transport channel adjacent to a first of the wide bandgap crystalline material layers close to the (0001) face of the III-N semiconductor channel forms a continuous transport channel spanning the (0001) face and a plurality of {1010} faces of the semiconductor channel. [15] The III-N transistor of claim 13, wherein the III-N semiconductor channel has a decreasing bandgap from both of the two wide bandgap material layers to a plane through the center of the semiconductor channel. [16] System on a chip (SoC), comprising: a power management integrated circuit (PMIC) comprising at least one of a switching voltage regulator or switching DC-DC converter; and an RF integrated circuit (RFIC) comprising a power amplifier operable to operate at a cutoff frequency Ft and a maximum oscillation frequency Fmax of at least 20 GHz each and to generate a carrier wave frequency of at least 2 GHz, wherein both of the PMIC and RFIC are monolithically integrated onto a same substrate, and wherein at least one of the PMIC and RFIC comprises the III-N transistor of claim 1. [17] SoC according to claim 16, further comprising: a controller of at least one of the PMIC and RFIC integrated on the substrate, the controller comprising CMOS technology fabricated with silicon field effect transistors. [18] A mobile computing device comprising: a touchscreen; a battery; an antenna; a DC-DC converter coupled to the battery; and a wireless transmitter further comprising a power amplifier (PA), wherein at least one of the DC-DC converter and the PA comprises the III-N transistor of claim 1. [19] The mobile computing device of claim 18, wherein the DC-DC converter comprises a first III-N transistor according to claim 1 and the PA employs a second III-N transistor according to claim 1. [20] A method of forming a III-N field effect transistor (FET), the method comprising: forming a wide bandgap crystalline transition layer over a substrate; epitaxially growing a III-N semiconductor channel layer over the transition layer, wherein the growth comprises grading the composition of the III-N semiconductor channel layer across a thickness of the channel layer to a composition having a narrower band gap near the polarization layer; the epitaxial growth of a wide bandgap polarization layer over the III-N semiconductor channel layer; and forming a gate stack over areas of the III-N semiconductor channel layer between the transition layer and the polarization layer. [21] The method of claim 20, wherein epitaxially growing the III-N semiconductor channel layer comprises grading the composition of the III-N semiconductor channel layer symmetrically over half a thickness of the III-N semiconductor channel layer. [22] The method of claim 20, wherein epitaxially growing the III-N semiconductor channel layer comprises grading the composition of the III-N semiconductor channel layer from a first higher indium content and a monotonically decreasing indium content. [23] The method of claim 20, wherein epitaxially growing the III-N semiconductor channel layer comprises grading the composition of the III-N semiconductor channel layer from a first higher aluminum content near the transition layer with monotonically decreasing aluminum content toward the narrowest bandgap composition. [24] The method of claim 23, wherein epitaxially growing the III-N semiconductor channel layer comprises grading the composition of the III-N semiconductor channel layer from AlGaN with at least 30% Al to GaN at the narrowest bandgap composition and then returning to AlGaN with at least 30% Al. [25] The method of claim 20, wherein forming the gate stack further comprises: depositing one or more gate dielectric layers over two or more {1010} faces of the III-N semiconductor channel layer using an atomic layer deposition process; and depositing one or more gate electrode layers over the gate dielectric layer.

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