Method for manufacturing a bipolar transistor with an insulated gate electrode

Abstract

Method for manufacturing a bipolar transistor with an insulated gate electrode (10), comprising a drift layer (3) of a first conductivity type between an emitter side (65) on which a gate electrode (7) and an emitter electrode (8) are arranged, and a collector side (45) opposite the emitter side (65) on which a collector electrode (9) is arranged, wherein the manufacturing method comprises manufacturing steps in the following sequence: - Providing a substrate (1) of a second conductivity type opposite to the first conductivity type, which has a first and a second side opposite to the first side (12, 14) and a doping concentration of 5*10 15 up to 1*10 17 cm -3 exhibits - Generating a first layer (25) of the first conductivity type on the first side (12) by introducing a dopant of the first conductivity type by epitaxial growth or deposition, resulting in the first layer (25) having a first layer thickness (27) between 0.5 and 2 µm, - Generating a drift layer (3) of the first conductivity type, which has a low doping concentration, on the first layer (25), - Diffusion of the dopant, such that a buffer layer (2) with a buffer layer thickness (22) is produced, wherein the buffer layer (2) has a higher doping concentration than the drift layer (3), and such that the buffer layer does not include a region of constant doping concentration in a direction perpendicular to the second side (14), - Generating a base layer (5) of the second conductivity type on the drift layer (3), - Generating an emitter layer (6) of the first conductivity type on the base layer (5), - Thinning (48) of the substrate (1) on the second side (14) so ​​that the remaining part of the substrate forms a collector layer (4) and wherein the buffer layer (2) has the same or a higher maximum doping concentration as / than the collector layer (4).

Description

Technical area

[0001] The invention relates to the field of power electronics and in particular to a method for producing an insulated gate bipolar transistor. BackgroundModes of implementation of the invention

[0002] US 2012 / 0025261 A1 describes a method for manufacturing an insulated-gate bipolar transistor (IGBT). The process begins with a lightly or undoped substrate, which can be n-type or p-type. The doping concentration of this layer is less than 1*10 15 cm -3is at most on the order of the doping concentration of the drift layer, so this layer does not contribute much charge to a p-type collector layer. An n-doped buffer layer with a thickness of 5 to 10 µm is epitaxially grown on this substrate, followed by further epitaxial growth to create an (n-)-doped drift layer. After that, a p-doped base layer is created on the drift layer together with an (n+)-doped emitter layer. A gate electrode is then fabricated on the same side. The substrate is now thinned on the side opposite the first epitaxial layer, leaving a thin, lightly or undoped layer. P-type ions are implanted and diffused on this layer to form the collector layer.

[0003] This process uses a substrate that serves no function in the finished device, so at least one fabrication step is required for each layer. The device is thicker than electrically necessary due to the remaining, lightly doped or undoped portion of the substrate. The collector layer is fabricated at a late stage of fabrication and with the substrate thinned, meaning that the emitter-side layers are exposed to the high temperature used for diffusion of the collector layer, and the thinned substrate must be handled carefully.

[0004] JP 2006-086423 A shows a manufacturing process for an IGBT in which a highly p+-doped substrate with a doping concentration of 1*10 18 cm -3is provided. An n+-doped buffer layer with a thickness of 5 µm is epitaxially grown on the substrate. This layer has a constantly high doping concentration in the depth direction, which is the same doping concentration as in the substrate. The layer thickness and doping of such a purely epitaxial layer are difficult to control. Due to the high doping concentration of the buffer and collector layers, the collector injection efficiency is very high, which leads to a high injection of holes into the drift layer. Turning off the device is slow due to the large amount of stored charge in the drift layer and the low injection of electrons into the collector layer. US 2003 / 42525 A1 shows similar disadvantages of a purely epitaxially grown buffer layer.

[0005] US 5,838,027 shows a process in which a p+ substrate is provided on which a lightly (n-) doped epitaxial layer is grown. An n+ dopant is implanted and diffused into this layer. Subsequently, a lightly doped (n-) drift layer is created on the buffer layer. Such a process requires a complicated procedure with many manufacturing steps to create the buffer layer. Due to the diffusion of the n+ dopant in the (n-) layer, the buffer layer at the transition to the collector layer has a low doping concentration, which increases to its maximum at a greater depth and then decreases again to the doping concentration of the (n-) drift layer, thereby increasing the overall thickness of the semiconductor.

[0006] US 2002 / 0100934 A1 discloses an IGBT with a pass-through structure featuring an n+ buffer layer. It includes a p-type low concentration layer formed between the n+ buffer layer and a p+ drain layer. Due to the low concentration layer, the drain current decreases gradually rather than rapidly to zero when the IGBT is turned off.

[0007] DE 195 44 725 discloses a method comprising vapor deposition of a first epitaxial layer. This layer comprises impurities of a low density first conductivity type and is formed on a silicon substrate. A high density of impurities of the first type is then implanted throughout the first epitaxial layer. A second epitaxial layer is then formed by vapor deposition. This second epitaxial layer has a lower density of impurities of the first type. A heat treatment process is then performed. This sets the gradient of the density increase of the impurities implanted into the first epitaxial layer. The impurities are preferably of the n-type. The method may also comprise forming a thermal oxidation layer on the first epitaxial layer and subsequently removing it in the region where the gate is to be formed, leaving a photoconductive layer structure.The remaining oxidation layer is removed after implantation of the high density of impurities. Disclosure of the invention

[0008] An object of the invention is to provide a method for manufacturing an insulated gate bipolar transistor which avoids the problems of the prior art methods.

[0009] This goal is achieved by providing a method for manufacturing an insulated-gate bipolar transistor comprising a drift layer of a first conductivity type between an emitter side, on which a gate electrode and an emitter electrode are arranged, and a collector side opposite the emitter side, on which a collector electrode is arranged. The manufacturing method comprises manufacturing steps in the following order: - Providing a substrate of a second conductivity type opposite to the first conductivity type, which has a first and a second side opposite to the first side, - producing a first layer of the first conductivity type on the first side by introducing a dopant of the first conductivity type, - creating a drift layer of the first conductivity type on the first layer, which has a low doping concentration, - Diffusing the dopant so that a buffer layer is created, wherein the buffer layer has a higher doping concentration than the drift layer, - Creating a base layer of the second conductivity type on the drift layer, - Creating an emitter layer of the first conductivity type on the base layer and - Thinning the substrate on the second side so that the remaining part of the substrate forms a collector layer.

[0010] Due to the diffusion process used to create the buffer layer, there is better control of the layer thickness and doping concentration due to the distribution of the doped ions by diffusion than with a process that uses only epitaxial growth to create the buffer layer.

[0011] Since no thinning is performed in a patterned doping region of the buffer layer in this process, the thickness and doping concentration of the buffer layer can be well controlled.

[0012] Because the drift layer is formed by epitaxial growth, or the buffer layer by diffusion of a dopant into the epitaxial layer (i.e., the drift layer), the layers are of high quality. For the collector layer, a substrate with less stringent specifications and therefore a lower cost can be used.

[0013] The inventive method can be easily applied to processing large wafer diameters because the entire manufacturing process for the layers, the gate electrode, and the metallization on the emitter side can be performed with a thick substrate, and only the metallization process for the collector electrode (and optionally for the emitter electrode) is performed on the thinned substrate. Not even the collector layer needs to be created on the thinned substrate, so the entire layer creation of the doped layers (emitter- and collector-side layers) can be performed on a thick substrate without the risk of handling a thin substrate.

[0014] Because the collector layer is part of the substrate from the beginning, no high-temperature steps such as diffusion annealing or laser annealing are required for its fabrication after the emitter-side layers and the gate electrode have been introduced. Therefore, this process combines the advantage of handling a thick substrate while eliminating the need for high-temperature steps at a late stage of fabrication.

[0015] The inventive manufacturing method makes it possible to create a soft-on-state device in which the buffer layer has a relatively low doping concentration and a relatively high thickness compared to prior art devices. This device can be produced using an easily controllable process without delicate steps in handling thin wafers. Compared to a buffer formed from a purely epitaxial layer or a deposited layer, the deeply diffused layer provides a gradient profile without a constant doping portion of the buffer. This gradient buffer allows the electric field to extend through the lighter doped region into the buffer regions while ensuring a neutral, highly doped region that the electric field does not reach.The highly doped region closer to the anode is important in controlling the bipolar gain to improve the balance between leakage current and short-circuit capability.

[0016] The collector injection efficiency can be controlled by selecting a collector layer thickness and a substrate with an appropriate doping concentration, independent of the risk posed by high-temperature steps (e.g., laser annealing) at the end of fabrication. This can offer advantages in terms of lower conduction losses in the device. Brief description of the drawings

[0017] The subject matter of the invention is described in more detail in the following text, with reference to the accompanying drawings, in which: Fig. 1 to 9, 11 show different manufacturing steps according to the invention for producing an IGBT; Fig. 10 shows an IGBT manufactured according to the inventive manufacturing method; and Fig. 12 to 18 show the doping profiles during different steps of the manufacturing process.

[0018] The reference symbols used in the figures and their meanings are summarized in the list of reference symbols. In general, identical or identically functioning components are assigned the same reference symbols. The described embodiments are intended as examples and are not intended to limit the invention. Ways of implementing the invention

[0019] To manufacture an inventive insulated gate bipolar transistor (IGBT) 10, the manufacturing steps are carried out in the following order: - Providing a p-doped substrate 1 having a first and a second side 12, 14 opposite to the first side ( Fig. 1), - Producing a first n-type layer 25 by introducing an n-dopant on the first side 12 ( Fig. 2), - Producing an (n-)-doped drift layer 3 on the first layer 25, which has a low doping concentration, for example by means of epitaxial growth ( Fig. 3), - Diffusing the dopant which has been introduced into the layer 25, so that a buffer layer 2 with a buffer layer thickness 22 is produced ( Fig. 4), wherein the buffer layer 2 has a higher doping concentration than the drift layer 3, - Creating a p-doped base layer 5 on the drift layer 3 ( Fig. 6), - Producing an (n+)-doped emitter layer 6 on the base layer 5 ( Fig. 7), - Thinning 48 of the substrate 1 on the second side 14, so that the remaining part of the substrate forms a collector layer 4 ( Fig. 8 shows the thinning and Fig. 9 shows the resulting collector layer 45).

[0020] In any suitable manufacturing step, a gate electrode 7, which is attached to the base layer 5 and the emitter layer 6, and an emitter electrode 8, which contacts the base layer 5 and the emitter layer 6 on an emitter contact surface, are produced. For example, the gate electrode 7 is produced after the formation of the buffer layer 2 and before the formation of the emitter layer 6, the base layer 5, and the thinning 48 of the substrate ( Fig. 5). The gate electrode 7 is formed on the side opposite the second side (ie, on the emitter side 65). A collector electrode 9 is formed on the second side 14. The collector electrode 9, which contacts the collector layer 4, is formed after the thinning of the substrate 1. The emitter electrode 8 is formed after the gate electrode 7 and can be formed before the thinning 48 of the substrate 1 ( Fig. 11) or after thinning 48 of the substrate 1; for example, it is produced together with the collector electrode 9 ( Fig. 10).

[0021] The Fig. Figures 12 to 18 show the doping concentrations of the layers during the manufacturing process. These figures illustrate the manufacturing process for a p-type substrate 1, for example.

[0022] For example, the substrate has a doping concentration of (5*10 15 up to 1*10 17 ) cm -3 on ( Fig. 12). The doping concentration is so high that the collector layer 4, which emerges as the remaining part of the substrate after thinning, can provide controlled injection.

[0023] The substrate thickness is chosen to be thick enough to allow the substrate to be handled in subsequent manufacturing steps without risk of cracking. For example, the substrate thickness is at least 300 µm.

[0024] The first layer 25 can be formed by introducing ions on the first side, e.g. by implanting a dopant ( Fig. 13). For example, the implantation dose (1*10 12 up to 5*10 13 ) cm -2 be.

[0025] Alternatively, the first layer 25 can be produced by epitaxial growth or deposition of the first layer 25, for example with a first layer thickness 27 between 0.5 to 2 µm, for example 0.5 to 1 µm and / or a doping concentration of 1*10 16 up to 5*10 17 cm -3The epitaxial first layer 25 comprises an n-dopant, which is diffused in the later diffusion step, so that the doping concentration steadily decreases without maintaining a constant portion of the doping concentration of the original epitaxial first layer 25. The dopant of the epitaxial layer diffuses into the substrate 1 as well as into the drift layer 3, so that the doping concentration of the buffer layer 2 on its side facing the substrate 1 increases to a maximum value, from which it steadily decreases to the constant doping concentration of the drift layer 3. Therefore, the epitaxial first layer 25 is so thin, and the dopant is diffused in such a way that the finally diffused buffer layer 2 does not comprise any portion of the constantly high doping concentration (i.e., the doping concentration of the original first layer) in a direction perpendicular to the second side 14 (depth direction).This means that the doping concentration of the buffer layer changes constantly without having the same value at different depths.

[0026] In an epitaxial or deposited layer, the dopant of the epitaxial layer can be deeply diffused to at least 5 times the thickness of the epitaxial first layer, for example, to at least 10 times the thickness. The thickness of the layers is measured in the depth direction (ie, as the extent of the layer in the depth direction in a direction perpendicular to the first side 12).

[0027] After the creation of the first layer 25, the drift layer 3 is created by epitaxial growth ( Fig. 14). Thereafter, the buffer layer 2 is created by diffusing the dopant, so that the diffused ions spread in a range of (5 to 30) µm (in the depth direction, ie in a direction perpendicular to the second side 14, which corresponds to the collector side 45). The dopant diffuses into the drift layer 3 ( Fig. 15). The buffer layer thickness 22 is therefore 5 to 30 µm, for example 10 to 30 µm. In the finished IGBT, the drift layer 3 must be the layer with the doping concentration unchanged by the diffusion step, i.e., the doping concentration achieved by the epitaxial growth in the drift layer 3. For example, the drift layer 3 has a constantly low doping concentration. The essentially constant doping concentration of the drift layer 3 means that the doping concentration in the drift layer 3 is essentially homogeneous, without, however, excluding the possibility that fluctuations in the doping concentration on the order of a factor of one to five may exist within the drift layer, e.g., due to fluctuations during the epitaxial growth process. The final drift layer thickness 32 and doping concentration are selected according to the application requirements.An exemplary doping concentration of the drift layer 3 is between 5 * 10. 12 cm -3 and 5 * 10 11 cm -3 .

[0028] Buffer layer 2 corresponds to the region into which the dopant diffuses in drift layer 3. On the side facing the substrate (collector layer 4), buffer layer 2 extends to a region in which the charge of the n-doped dopant overcompensates for the charge of the p-substrate.

[0029] The buffer layer 2 may have the same or a higher maximum doping concentration than the collector layer 4, i.e., the maximum doping concentration of the buffer layer may be at least as high as that of the collector layer 4 (i.e., the p-substrate 1). Alternatively, the maximum doping concentration of the buffer layer 2 is lower than the doping concentration of the collector layer 4 (of the p-substrate 1). Since the substrate 1 / the p-collector layer 4 is uniformly doped, the maximum doping concentration of the p-collector layer 4 / the p-substrate 1 corresponds to the (local) doping concentration, whereas the doping concentration in the buffer layer 2 decreases with increasing depth after the maximum doping concentration, i.e., toward the emitter side 65 of the IGBT.

[0030] The maximum doping concentration of buffer layer 2 can be between 1*10 15 and 5*10 16 cm -3 be.

[0031] A substrate concentration, which corresponds to an integral of the doping concentration (impurity ions) over the depth, is 1*10 12 up to 5*10 13 cm -2 with one implanted layer and 2*10 12 up to 1*10 14 cm -2 for an epitaxial or deposited layer with a thickness in the range of 0.5 to 2 µm or 2*10 12 up to 5*10 13 cm -2 for an epitaxial or deposited layer with a thickness in the range of 0.5 to 1 µm.

[0032] An exemplary collector layer thickness 42 is (3 to 30) µm, and the doping concentration may have a value in a range of (5*10 15 up to 1*10 17 ) cm -3 have.

[0033] Fig. 16 shows the semi-finished device in which the emitter-side processes have been performed and which is shown, for example, as the p-doped base layer 5. Fig. 17 shows the semi-finished device after collector-side thinning of the substrate 1, whereby the collector layer 4 is created. Fig. Figure 18 shows the electric field of the final device stopped within the buffer layer 2.

[0034] The gate electrode 7 is formed either as a planar gate electrode or as a trench gate electrode. The gate electrode 7 is formed using a method well known to those skilled in the art.

[0035] The finished IGBT can have a planar gate electrode (as in Fig.10) comprising an electrically insulating layer 74 on the emitter side 65. An electrically conductive gate layer 72 is arranged on the insulating layer 74 and is therefore insulated from any n- or p-doped layer in the IGBT. Therefore, the insulating layer 74 insulates the gate layer 72 in a region below the gate layer 72 from any n- or p-doped layer in the IGBT that extends to the emitter side 65. The gate layer 72 is, for example, also covered by the insulating layer 74, whereby the gate layer 72 is also insulated from the emitter electrode 8 by the insulating layer 74. Therefore, the gate layer 72 is, for example, completely embedded in the insulating layer 74. The gate layer 72 consists, for example, of a highly doped polysilicon or a metal-like aluminum. The gate layer 72 is arranged on the emitter side 65 laterally of an emitter contact surface.It extends to a region above the base layer 5, the emitter layer 6, and the drift layer 3. The at least one emitter layer 5, the gate layer 72, and the electrically insulating layer 74 are formed such that an opening, which is the emitter contact area, is created above the base layer 5. The emitter contact area is surrounded by the emitter layer 5, the gate layer 72, and the electrically insulating layer 74.

[0036] The emitter electrode 8 is arranged on the emitter side 65 and touches the base layer 5 and the emitter layer 6 at the emitter contact surface. The emitter electrode 8 also covers, for example, the electrically insulating layer 74, but is separated from the gate layer 72 by the electrically insulating layer 74 and is therefore electrically insulated.

[0037] As an alternative to the inventive IGBT with a planar gate electrode, the inventive IGBT may comprise a gate electrode configured as a trench gate electrode. The trench gate electrode is arranged in the same plane as the base layer 5 in a recess in the semiconductor material, adjacent to the emitter layer 6, and separated from each other by an insulating layer 74, which also separates the gate layer 72 from the drift layer 3. The insulating layer 74 is also arranged on the gate layer 72 and therefore insulates the trench gate layer 72 from the emitter electrode 8.

[0038] The IGBT manufactured by the inventive method may also comprise a highly p+-doped contact layer arranged between the emitter contact area and the p-doped base layer 5 in order to have a highly doped intermediate layer at the contact with the emitter electrode 8. The p-contact layer may be limited to the area where a p-doped layer touches the emitter electrode 8, i.e., at the emitter contact area. The contact layer may have a maximum doping concentration between 5×10 18 / cm 3 and 5×10 19 / cm 3The contact layer can also be formed as a diffused layer, i.e., by overlapping the p-doped layers and decreasing the doping concentration of each layer, but with the contact layer disposed to a first depth that is less than the depth / thickness of the base layer (measured from the emitter side 65). The contact layer and the base layer 5 overlap such that there is a discontinuous decrease in doping concentration at the interface. The contact layer is created by introducing p-doped ions (either by implantation or by deposition) and diffusing them into the device to a depth that is less than the depth of the base layer measured from the emitter side 65. It has approximately the thickness of the emitter layer 6.

[0039] In a further embodiment, the conductivity types are reversed, ie all layers of the first conductivity type are p-type (e.g. the drift layer 3), and all layers of the second conductivity type are n-type (e.g. the collector layer 4).

[0040] It should be noted that the term "comprising" does not exclude other elements or steps, and the indefinite article "a," "an," or "another" does not exclude the plural. Likewise, elements described in connection with different embodiments may be combined. It should also be noted that reference signs in the claims should not be interpreted as limiting the scope of the claims.

[0041] Those skilled in the art will recognize that the present invention may be embodied in other specific forms without departing from its spirit or essential characteristics. The presently described embodiments are therefore to be considered in all respects as illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than the foregoing description, and all changes which come within the meaning and range of equivalents thereof are intended to be embraced therein. List of reference numbers 1 substrate 10 IGBT 2 buffer layer 22 Buffer layer thickness 25 first layer 3 Drift layer 32 Drift layer thickness 4 Collector layer 42 Collector layer thickness 45 Collector side 5 Base layer 6 Emitter layer 65 Emitter side 7 Gate electrode 72 Gate layer 74 insulating layer 8 Emitter electrode 9 Collector electrode

Claims

[1] A method for producing an insulated gate bipolar transistor (10) comprising a drift layer (3) of a first conductivity type between an emitter side (65) on which a gate electrode (7) and an emitter electrode (8) are arranged, and a collector side (45) opposite the emitter side (65) on which a collector electrode (9) is arranged, wherein the manufacturing method comprises manufacturing steps in the following order: - Providing a substrate (1) of a second conductivity type opposite to the first conductivity type, which substrate has a first and a second side (12, 14) opposite to the first side and a doping concentration of 5*10 15 up to 1*10 17 cm -3 has, - producing a first layer (25) of the first conductivity type on the first side (12) by introducing a dopant of the first conductivity type by epitaxial growth or deposition, which results in the first layer (25) having a first layer thickness (27) between 0.5 and 2 µm, - producing a drift layer (3) of the first conductivity type, which has a low doping concentration, on the first layer (25), - diffusing the dopant so that a buffer layer (2) with a buffer layer thickness (22) is produced, wherein the buffer layer (2) has a higher doping concentration than the drift layer (3), and so that the buffer layer does not comprise a region of constant doping concentration in a direction perpendicular to the second side (14), - producing a base layer (5) of the second conductivity type on the drift layer (3), - producing an emitter layer (6) of the first conductivity type on the base layer (5), - thinning (48) the substrate (1) on the second side (14) so ​​that the remaining part of the substrate forms a collector layer (4) and wherein the buffer layer (2) has the same or a higher maximum doping concentration as / than the collector layer (4). [2] A method of manufacturing an insulated gate bipolar transistor according to claim 1, characterized by that the substrate (1) has a substrate thickness of at least 300 µm. [3] A method of manufacturing an insulated gate bipolar transistor according to any one of claims 1 or 2, characterized by that the dopant is introduced by implantation, in particular with a dose of 1*10 12 up to 5*10 13 cm -2 . [4] A method of manufacturing an insulated gate bipolar transistor according to any one of claims 1 to 3, characterized by that the first layer (25) comprises at least one a first layer thickness between 0.5 and 1 µm, or a doping concentration of 1*10 16 up to 5*10 17 cm -3 has. [5] A method of manufacturing an insulated gate bipolar transistor according to any one of claims 1 to 4, characterized by that the first layer (25) is diffused to at least 5 times or at least 10 times the first layer thickness. [6] A method of manufacturing an insulated gate bipolar transistor according to any one of claims 1 to 4, characterized by that the buffer layer thickness (22) is 5 to 30 µm. [7] A method of manufacturing an insulated gate bipolar transistor according to claim 6, characterized by that the buffer layer thickness (22) is 10 to 30 µm. [8] A method of manufacturing an insulated gate bipolar transistor according to any one of claims 1 to 7, characterized by that the buffer layer (2) has a maximum doping concentration between 1*10 15 and 5*10 16 cm -3 has. [9] A method of manufacturing an insulated gate bipolar transistor according to any one of claims 1 to 8, characterized by that the collector layer (4) comprises at least one of a collector layer thickness (42) of 3 to 30 µm and a doping concentration of 5*10 15 up to 1*10 17 cm- 3 has. [10] A method of manufacturing an insulated gate bipolar transistor according to any one of claims 1 to 8, characterized by that the drift layer (3) is produced by epitaxial growth. [11] A method for producing an insulated gate bipolar transistor (10) comprising a drift layer (3) of a first conductivity type between an emitter side (65) on which a gate electrode (7) and an emitter electrode (8) are arranged, and a collector side (45) opposite the emitter side (65) on which a collector electrode (9) is arranged, wherein the manufacturing method comprises manufacturing steps in the following order: - Providing a substrate (1) of a second conductivity type opposite to the first conductivity type, which substrate has a first and a second side (12, 14) opposite to the first side and a doping concentration of 5*10 15 up to 1*10 17 cm -3 has, - producing a first layer (25) of the first conductivity type on the first side (12) by introducing a dopant of the first conductivity type by epitaxial growth or deposition, which results in the first layer (25) having a first layer thickness (27) between 0.5 and 2 µm, - producing a drift layer (3) of the first conductivity type, which has a low doping concentration, on the first layer (25), - diffusing the dopant so that a buffer layer (2) with a buffer layer thickness (22) is produced, wherein the buffer layer (2) has a higher doping concentration than the drift layer (3), and so that the buffer layer does not comprise a region of constant doping concentration in a direction perpendicular to the second side (14), - producing a base layer (5) of the second conductivity type on the drift layer (3), - producing an emitter layer (6) of the first conductivity type on the base layer (5), - thinning (48) the substrate (1) on the second side (14) so ​​that the remaining part of the substrate forms a collector layer (4) and wherein the buffer layer (2) has a lower maximum doping concentration than the collector layer (4).

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