Semiconductor equipment and manufacturing process of the semiconductor equipment

Abstract

Semiconductor device (10) with: a semiconductor substrate (100) in which an IGBT region (11) and a diode region (12) are provided; an interlayer insulating layer (135) and a front surface electrode (121) provided on a front surface of the semiconductor substrate (100); and a rear surface electrode (120) provided on a rear surface of the semiconductor substrate (100), wherein the IGBT area (11) exhibits: a collector layer (101) of a first conductivity type; a first drift layer (104 over 11) of a second conductivity type, which is provided on a front surface side of the semiconductor substrate (100) relative to the collector layer (101); a first body layer (105) of the first conductivity type, which is provided on the front surface side of the semiconductor substrate (100) relative to the first drift layer (104 over 11) and is partially located on the outside of the front surface of the semiconductor substrate (100); an emitter layer (107) of the second conductivity type, provided on a front surface of the first body layer (105) and located on the outside of the front surface of the semiconductor substrate (100); and a trench gate (130) that reaches the first drift layer (104 over 11) through the first body layer (105) from the front surface side of the semiconductor substrate (100), wherein the diode region (12) exhibits: a cathode layer (102) of the second conductivity type; a second drift layer (104 over 12) of the second conductivity type, which is provided on the front surface side of the semiconductor substrate (100) relative to the cathode layer (102) and has a lower impurity concentration of the second conductivity type than that of the cathode layer (102); and a second body layer (105) of the first conductivity type, which is provided on the front surface side of the semiconductor substrate (100) relative to the second drift layer (104 over 12); wherein the intermediate layer insulation layer (135) insulates the trench gate (130) from the front surface electrode (121), a lifetime control region (150) containing a peak of a crystal defect density is provided in the first drift layer (104 over 11) and the second drift layer (104 over 12), which are located between a depth of a lower end of the trench gate (130) and surfaces of the first drift layer (104 over 11) and the second drift layer (104 over 12), a silicon nitride layer (143) is further provided above the trench gate (130) and the emitter layer (107) and below the front surface electrode (121) on the front surface side of the semiconductor substrate (100), covers the interlayer insulating layer (135) and has an opening (145a) that is open on a section of the first body layer (109) that is located on the outside of the front surface of the semiconductor substrate (100).

Description

Technical area

[0001] A technology disclosed herein relates to a semiconductor device and a manufacturing method of the semiconductor device. State of the art

[0002] Japanese Patent Laid-Open No. 2011-238872 A discloses a semiconductor device comprising a semiconductor substrate in which an IGBT region and a diode region are provided. This semiconductor device includes a lifetime control region provided over the IGBT region and the diode region. The lifetime control region includes a peak of crystal defect density at a position in a drift layer that is deeper than a lower end of the trench gate provided in the IGBT region. The lifetime control region improves a reverse recovery characteristic of the diode region.

[0003] Relevant prior art can be found, for example, in document US 2009 / 0 242 931 A1, which discloses a semiconductor device with an IGBT and a diode. Furthermore, document US 2005 / 0 255 706 A1 discloses a MOSFET. Summary of the inventionTechnical problem

[0004] To improve the reverse recovery characteristic of the diode region, it is preferable that the lifetime control region be provided at a position in the drift layer that is as close as possible to a boundary between a body layer and the drift layer. Providing the lifetime control region at such a position causes an overlap between a position where the trench gate is provided and the position where the lifetime control region is provided. This results in the formation of an interface state between a gate insulation layer of the trench gate and a portion of the semiconductor substrate that is in contact with the gate insulation layer. Because the interface state traps charge carriers, a plurality of trench gates have different threshold voltages from each other, so there is a greater amount of variation in a threshold voltage for each of the trench gates. Solution to the technical problem

[0005] A first semiconductor device disclosed herein is defined by claim 1.

[0006] It should be noted that a front surface of the first drift layer means an interface between the first drift layer and the first body layer. Further, a front surface of the second drift layer means an interface between the second drift layer and the second body layer. Further, the "peak of a crystal defect density" means the local maximum value of a crystal defect density distribution in a depth direction in the first drift layer or the second drift layer. Further, it is preferable that the "peak of a crystal defect density" is the maximum value in the crystal defect density distribution.

[0007] The first semiconductor device reduces the variations in the threshold voltage of the trench gates because hydrogen atoms are supplied from the silicon nitride layer provided above the trench gate on the front surface side of the semiconductor layer, and an interface state is terminated and reduced by hydrogen. This makes it possible to both reduce the variations in the threshold voltage of the trench gates and improve the reverse repetition characteristic of the diode region.

[0008] In the semiconductor device, the silicon nitride layer may be provided over the emitter layer. Furthermore, the silicon nitride layer may have an opening formed over a portion of the first body layer that is external to the front surface of the semiconductor substrate.

[0009] A second semiconductor device disclosed herein is defined by claim 2.

[0010] The second semiconductor device reduces the variations in the threshold voltage of the trench gates because the interface state is terminated and reduced by the hydrogen atoms supplied from the Al-based electrode layer. Furthermore, the barrier metal layer, by which hydrogen atoms are easily adsorbed, is provided between the portion of the first body layer located relatively far from the trench gate to which hydrogen atoms are supplied and located on the outer surface of the semiconductor substrate, and the Al-based electrode layer, and is not provided between the trench gate to which hydrogen atoms are supplied and the Al-based electrode layer. For this reason, the supply of hydrogen atoms from the Al-based electrode layer to the trench gate is not prevented by the barrier metal layer.The provision of the barrier metal layer makes it possible to supply hydrogen atoms to the trench gate while ensuring effects brought by the provision of the barrier layer, which makes it possible to both reduce the variations in the threshold voltage of the trench gates and improve the reverse recovery characteristic of the diode region.

[0011] Furthermore, a manufacturing method of a semiconductor device according to claim 3 is disclosed herein.

[0012] In the semiconductor device manufacturing method, the lifetime control region is formed on the front surface side of the trench gate in a state where the silicon nitride layer is present. Because the termination of the interface state by hydrogen atoms provided by the silicon nitride layer effectively progresses, especially during annealing, the interface state can be effectively reduced.

[0013] Further disclosed herein is a manufacturing method of a semiconductor device according to claim 4.

[0014] In the manufacturing method of a semiconductor device, the lifetime control region is formed on the front surface side of the trench gate in a state where the barrier metal layer and the Al-based electrode layer are present on the front surface side of the trench gate. Because the termination of the interface state by hydrogen atoms supplied from the Al-based electrode layer effectively progresses, especially during annealing, the interface state can be effectively reduced. Furthermore, because the barrier metal layer, to which hydrogen atoms are easily adsorbed, is opened on the front surface side of the trench gate, to which hydrogen atoms are supplied, the supply of hydrogen atoms from the Al-based electrode layer to the trench gate is not prevented by the barrier metal layer. Short description of the drawings Fig. 1 is a longitudinal cross-sectional view of a semiconductor device according to Embodiment 1; Fig. 2 is a plan view of a semiconductor substrate of the semiconductor device according to Embodiment 1; Fig. 3 is a plan view of the semiconductor device according to Embodiment 1; Fig. 4 is a diagram explaining a manufacturing method of the semiconductor device according to Embodiment 1; Fig. 5 is a diagram explaining a manufacturing method of the semiconductor device according to Embodiment 1; Fig. 6 is a diagram explaining the manufacturing method of the semiconductor device according to Embodiment 1; Fig. 7 is a diagram explaining the manufacturing method of the semiconductor device according to Embodiment 1; Fig. 8 is a diagram explaining the manufacturing method of the semiconductor device according to Embodiment 1; Fig. 9 is a diagram explaining the manufacturing method of the semiconductor device according to Embodiment 1; Fig. 10 is a diagram explaining the manufacturing method of the semiconductor device according to Embodiment 1; Fig. 11 is a longitudinal cross-sectional view of a semiconductor device according to a modification; Fig. 12 is a longitudinal cross-sectional view of a semiconductor device according to Embodiment 2; Fig. 13 is a diagram explaining a manufacturing method of the semiconductor device according to Embodiment 2; Fig. 14 is a diagram explaining the manufacturing method of the semiconductor device according to Embodiment 2; Fig. 15 is a diagram explaining the manufacturing method of the semiconductor device according to Embodiment 2; Fig. 16 is a diagram explaining the manufacturing method of the semiconductor device according to Embodiment 2; Fig. 17 is a diagram explaining the manufacturing method of the semiconductor device according to Embodiment 2; Fig. 18 is a longitudinal cross-sectional view of a semiconductor device according to a modification; Fig. 19 is a diagram explaining a manufacturing method of the semiconductor device according to the modification; Fig. 20 is a longitudinal cross-sectional view of a semiconductor device according to a modification; Fig. 21 is a longitudinal cross-sectional view of a semiconductor device according to a modification; Fig. Fig. 22 is a plan view of a semiconductor substrate of the semiconductor device according to the modification; and Fig. 23 is a plan view of the semiconductor substrate according to the modification. Description of embodimentsExemplary embodiment 1

[0015] As in Fig. As shown in FIGS. 1 to 3, a semiconductor device 10 according to the present embodiment includes: a semiconductor substrate 100 in which an IGBT region and a diode region 12 are provided; interlayer insulation layers 135, a front surface electrode 121, and a silicon nitride layer 143 provided on a front surface of the semiconductor substrate 100; and a back surface electrode 120 provided on a back surface of the semiconductor substrate 100. The front surface electrode 121 is a composite electrode layer in which an Al-Si-based electrode layer, a Ni-based electrode layer, a solder bond layer, and the like are stacked in this order from the semiconductor substrate 100.The back surface electrode 120 is a composite electrode layer in which an Al-based electrode layer, a Ti-based electrode layer, a Ni-based electrode layer, a solder bond layer, and the like are stacked.

[0016] The IGBT region 11 includes: a p-type collector layer 101; an n-type buffer layer 103 in contact with a front surface of the collector layer 101; an n-type drift layer 104 in contact with a front surface of the buffer layer 103; a p-type body layer 105 provided on a front surface side of the semiconductor substrate relative to the drift layer 104; body contact layers 109 provided on a front surface of the body layer 105 and exposed to the front surface of the semiconductor substrate 100; n-type emitter layers 107 provided on the front surface of the body layer 105 and exposed to the front surface of the semiconductor substrate 100. and trench gates 130 that reach the drift layer 104 through the body layer 105 from the front surface side of the semiconductor substrate 100. As shown in Fig. 2 in a top view of the semiconductor substrate 100, the emitter layers 107 have a ladder shape extending along a longitudinal direction of the trench gates 130, and each body contact layer 109 is adjacent to emitter layers 107 in such a way that they fit into spaces in the ladder shape of the emitter layers 107. Each emitter layer 107 has portions 107a extending along the corresponding trench gate 130 and portions 107b extending along a short direction (i.e., a direction perpendicular to the longitudinal direction) of the trench gate 130. Each section 107b is located between two trench gates 130 adjacent to the section 107b in the short direction and connects two sections 107a extending along the respective trench gates 130, and the body contact layer 109 is arranged in regions surrounded by these sections 107a and 107b. It should be noted that Fig. 2 illustrates the front surface of the semiconductor substrate 100 and omits the illustration of the interlayer insulating layers 135, the front surface electrode 121, and the silicon nitride layer 143 provided on the front surface. Each trench gate 130 includes: a trench 131 provided in the semiconductor substrate 100; a gate insulating layer 132 provided on an inner wall of a corresponding trench 131; and a gate electrode 133 that fills the trench 131 while being covered with the gate insulating layer 132. Each interlayer insulating layer 135 covers a front surface of the trench gate 130 and a portion of the emitter layer 107 close to the trench gate 130, so that the gate electrode 133 is insulated from the front surface electrode 121.The front surface electrode 121 is in contact with portions of the emitter layers 107 and the body contact layers 109 that are external to the front surface of the semiconductor substrate 100. As shown in FIG. Fig. 1 and Fig. 3, the silicon nitride layer 143 is provided in a portion of a front surface of the front surface electrode 121 located within the IGBT region 11. The silicon nitride layer 143 is provided above the trench gate 130 and above the emitter layer 107 (note here that the term "above" means a position on the front surface side of the semiconductor substrate 100 along a thickness direction of the semiconductor substrate 100 and in Fig. 1 means "vertically above"), and is not provided above the body contact layer 109. The silicon nitride layer 143 includes openings 145 that are open above the body contact layers 109. The front surface electrode 121 is exposed through the openings 145.

[0017] The diode region 12 includes: an n-type cathode layer 102; an n-type buffer layer 103 in contact with a front surface of the cathode layer 102; an n-type drift layer 104 in contact with a front surface of the buffer layer 103; a p-type body layer 105 provided on the front surface side of the semiconductor substrate relative to the drift layer 104; and anode layers 106 provided on a front surface of the body layer 105 and exposed to the front surface of the semiconductor substrate 100. As shown in Fig. As shown in Figure 2, the anode layers 106 are provided on the front surface of the semiconductor substrate 100 in such a way that they occupy spaces between trench gates adjacent to the anode layers 106 in a longitudinal direction. As with the IGBT region 11, the diode region 12 includes trench gates 130 that reach the drift layer 104 through the body layer 105 from the front surface side of the semiconductor substrate 100. In the diode region 12, as shown in Fig. 1 to 3, the silicon nitride layer 143 is provided only in a portion of the anode layer 106 closest to the IGBT region 11 and whose front surface is covered with the interlayer insulation layer 135. The front surface electrode 121 is in contact with a portion of the anode layer 106 that is exposed to the front surface of the semiconductor substrate 100. It should be noted that an n-type impurity concentration of the drift layer 104 is lower than an n-type impurity concentration of the cathode layer 102. It is preferable that the n-type impurity concentration of the drift layer 104 be lower than 1 × 10 14 atoms / cm 3 is.

[0018] The buffer layer 103 is provided as a buffer layer 103 over both the IGBT region 11 and the diode region 12. The drift layer 104 is provided as a drift layer 104 over both the IGBT region 11 and the diode region 12. The body layer 105 is provided as a body layer 105 over both the IGBT region 11 and the diode region 12. Portions of the buffer layer 103 and the drift layer 104 included in the IGBT region 11 are both examples of the first drift layer, and portions of the buffer layer 103 and the drift layer 104 included in the diode region 12 are both examples of the second drift layer. A portion of the body layer 105 included in the IGBT region and the body contact layers 109 are both examples of the first body layer. A portion of the body layer 105 included in the diode region 12 and the anode layers 106 are both examples of the second body layer.

[0019] A lifetime control region 150 is provided in the drift layer 104 across the IGBT region 11 and the diode region 12. The lifetime control region 150 is a region having a higher crystal defect density than a surrounding area. The lifetime control region 150 includes a peak of a crystal defect density. That is, the lifetime control region 150 is a region in which, when a crystal defect density distribution is measured in a depth direction in the drift layer 104, the local maximum value (preferably the maximum value) of the crystal defect density distribution is present. The lifetime control region 150 is provided in a portion of the drift layer 104 located between a depth of a lower end of the trench gates 130 and a boundary between the drift layer 104 and the body layer 105 (i.e.,a portion of the drift layer 104 located at a position shallower than the depth of the bottom end of the trench gates 130). That is, an average value of the crystal defect densities in the portion of the drift layer 104 located at the position shallower than the depth of the bottom end of the trench gates 130 is higher than an average value of crystal defect densities in a portion of the drift layer 104 located at a position deeper than the depth of the bottom end of the trench gates 130. In the lifetime control region 150, the lifetime of charge carriers is effectively reduced. This allows the diode region 112 to have a favorable reverse recovery characteristic.In the semiconductor device 10, the diode region 12 particularly has a favorable reverse recovery characteristic because the lifetime control region 150 is provided in a portion of the drift layer 104 that is close to the boundary between the body layer 105 and the drift layer 104. Furthermore, in the semiconductor device 10, an interface state is easily formed between the gate insulating layer 132 of each trench gate 130 and a portion of the semiconductor substrate 100 that is in contact with each gate insulating layer 132 because there is a partial overlap between a depth at which each trench gate 130 is provided and a depth at which the lifetime control region 150 is provided. Generally, the formation of such an interface state destabilizes a threshold voltage of a gate of an IGBT, thereby increasing variations in the threshold voltage of mass-produced IGBTs.However, as described in detail below, at the time of manufacturing the semiconductor device, the interface state is terminated and reduced by hydrogen atoms supplied from the silicon nitride layers 143. This reduces the variations in the threshold voltage of the trench gates 130. The semiconductor device 10 makes it possible to both reduce the variations in the threshold voltage of the trench gates 130 and improve the reverse recovery characteristic of the diode region 12.

[0020] The following describes an example of a manufacturing method of a semiconductor device 10. It should be noted that the following omits a detailed description of steps in which a conventional publicly known manufacturing method of a semiconductor device may be used.

[0021] First, as in Fig. 4, a raw material wafer 90 is prepared. For example, a body layer 105, anode layers 106, emitter layers 107, and body contact layers 109 are formed on a front surface side of an n-type silicon wafer using conventional publicly known methods such as ion implantation and annealing. An n-layer 904 is a portion of the n-type silicon wafer into which no ions have been implanted and is a layer serving as a drift layer 104 of the semiconductor layer 10. Thereafter, trench gates 130 and interlayer insulation layers 135 are formed using conventional publicly known methods such as etching, thermal oxidation, and CVD. This makes it possible to form the raw material wafer 90 shown in Fig. 4. It should be noted that in the thermal oxidation step of forming the gate insulation layer 132, the pyrogenic oxidation method in which water vapor is used as an oxidizing species can be suitably used. Therefore, the gate insulation layer can contain a large amount of water when formed using the pyrogenic oxidation method.

[0022] Next, as in Fig. 5, a front surface electrode 121 is formed on a front surface of the raw material wafer 90. The front surface electrode 121 is formed with such a thickness that it further covers a front surface of the interlayer insulation films 135 formed on a front surface of the trench gates 130. Next, as shown in Fig. As shown in FIG. 6, a silicon nitride layer 943 is formed on a front surface of the front surface electrode 121 using a conventional publicly known film formation method such as CVD. The silicon nitride layer 943 is formed to such an extent that it completely covers the front surface electrode 121.

[0023] Next, as in Fig. 7, after the thickness of the raw material wafer 90 is made thin by cutting off a back surface of the raw material wafer 90, ion implantation is performed on the back surface of the raw material wafer 90, whereby a p-type ion implanted layer 901, an n-type ion implanted layer 902, and an n-type ion implanted layer 903 are formed on a back surface side of the raw material wafer 90.

[0024] Next, as in Fig. As shown in Figure 8, crystal defects are formed by irradiating the inner part of the drift layer 104 with charged particles from the back surface side of the raw material wafer 90 in a state where the silicon nitride layer 943 is present on the front surface of the front surface electrode 121. A position of the charged particle irradiation is adjusted so that a peak of a crystal defect density is included in a region located between a depth from the lower ends of the trench gates 130 and a boundary between the drift layer 104 and the body layer 105. Such charged particle irradiation causes some of the charged particles to be implanted into the gate insulating layers 132.For this reason, performing ion implantation facilitates the formation of an interface state between the gate insulating layers 132 and portions of the semiconductor substrate 100 that are in contact with the gate insulating layers 132. Alternatively, crystal defects can be formed by irradiating the inner part of the drift layer with charged particles that have passed through the trench gate from the front surface side.

[0025] Next, as in Fig. 9, a lifetime control region 150 is formed by performing heating to stabilize crystal defects in a state where the silicon nitride layer 934 is present on the front surface of the front surface electrode 121. In this heating step, the p-type ion-implanted layer 901, the n-type ion-implanted layer 902, and the n-type ion-implanted layer 903 are also heated to form a p-type collector layer 101, an n-type cathode layer 102, and an n-type buffer layer 103, respectively. Furthermore, by performing the heating step in a state where the silicon nitride layer 943 is present, hydrogen atoms are supplied from the silicon nitride layer 943 into the semiconductor substrate 100.The hydrogen atoms thus supplied enable the termination of the interface state present at the boundary between the gate insulation layers 132 and the semiconductor substrate 100 to proceed effectively, making it possible to effectively reduce the interface state. Note that in the case where the gate insulation layers 132 are formed using the pyrogenic oxidation method, the interface state is also terminated by hydrogen atoms supplied from the gate insulation layers 132 containing a large amount of water, so the interface state can be more effectively reduced.

[0026] Next, as in Fig. 10, the silicon nitride layer 943 is partially removed by a conventional publicly known method, such as etching. Portions of the silicon nitride layer 943 formed over the anode layers 106 and over the body contact layers 109 are removed, so that the silicon nitride layer 943 forms a silicon nitride layer 143 patterned in the same manner as shown in Fig. 1. Furthermore, the semiconductor device 10 shown in Fig. 1 to 3, by forming a rear surface electrode 120 on the rear surface of the raw material wafer 90 shown in Fig. 10 is shown. (Modification)

[0027] In Embodiment 1, the manufacturing method was described in which the silicon nitride layer 943 is partially removed after heating to stabilize the crystal defects. However, if the silicon nitride layer 943 is completely removed, the effect of reducing the interface state by hydrogen atoms supplied from the silicon nitride layer 943 can also be achieved. In this case, a semiconductor device is manufactured having a configuration in which the silicon nitride layer 143 is removed from the semiconductor device 10 shown in Fig. 1 to 3. Furthermore, although Embodiment 1 was described taking as an example a case where the front surface electrode 121 was a composite electrode not including a barrier metal layer, the present disclosure is not limited to this example. The front surface electrode 121 may be replaced by a composite electrode layer having a barrier metal layer formed entirely or partially on an interface between the composite layer and the semiconductor substrate 100. Even in a case where a barrier metal layer to which hydrogen atoms are easily adsorbed is used, variations in the threshold voltage of the trench gates can be reduced because hydrogen atoms are supplied and replenished from the silicon nitride layer.

[0028] Furthermore, a silicon nitride layer only needs to be provided over the trench gates 130 and over the emitter layer 107, and does not need to be provided over the front surface electrode 121. The advantageous effects of the present disclosure can be obtained even if the silicon nitride layer is arranged under and / or inside the front surface electrode 121. For example, as in a case of a semiconductor device 10a shown in Fig. 11, the silicon nitride layer 143a may be disposed under the front surface electrode 121. The silicon nitride layer 143a is provided over the trench gates 130 and over the emitter layers 107 under the front surface electrode 121, and is not provided over the body contact layers 109. The silicon nitride layer 143a covers front and side surfaces of the interlayer insulating layers 135 provided in the IGBT region 11 and covers portions of the front surfaces of the emitter layers 107 that are not covered with the interlayer insulating layers 135. In the IGBT region 11, the silicon nitride layer 143a is not provided on front surfaces of the body contact layers 109 and has openings 145a opened on front surface sides of the body contact layers 109.In the diode region 12, the silicon nitride layer 143a is provided only in a portion of the anode layer 106 closest to the IGBT region 11, the front surface of which is covered with the interlayer insulation layer 135. The front surface electrode 121 further covers a front surface of the silicon nitride layer 143a and is in contact with the front surfaces of the body contact layers 109 through the openings 145a of the silicon nitride layer 143a. Furthermore, the front surface electrode 121 is in contact with portions of the anode layers 106 that are external to the front surface of the semiconductor substrate 100. The rear surface electrode 120 is in contact with the collector layer 101. Example 2

[0029] A semiconductor device 20 which is in Fig. 12 differs from the semiconductor device 10 in that no silicon nitride layer 143 is provided on the front surface of the semiconductor substrate 100 or on the front surface of the interlayer insulation layers 135, and that a front surface electrode includes an Al-based electrode layer 221 and a barrier metal layer 244. Although not illustrated, a Ni-based electrode layer and a solder bond layer are further stacked on a front surface of the Al-based electrode layer as part of the front surface electrode.

[0030] The Al-based electrode layer 221 is made of an electrode material mainly containing aluminum, such as Al or an Al-Si alloy, which is commonly used in the semiconductor field, and these electrode materials are known to be very capable of supplying hydrogen atoms.

[0031] The barrier metal layer 244 is provided at such a position in the diode region 12 that the front surface of the semiconductor substrate 100 and the front surfaces of the interlayer insulating layers 135 are covered. The barrier metal layer 244 is provided at such a position in the IGBT region 11 that the front surface of the body contact layer 109 is covered, and is not provided at such a position in the IGBT region 11 that the front surfaces of the emitter layers 107 and the front surfaces of the interlayer insulating layers 135 are covered.That is, the barrier metal layer 244 is provided between a portion of the first body layer (a portion of the body layer 105 located within the diode region 12) exposed to the front surface of the semiconductor substrate 100 and the Al-based electrode layer 221, and is not provided between the trench gates 130 and the Al-based electrode layer 221 in the IGBT region 11. The barrier metal layer 244 may be made of any conventional publicly known material used as a barrier metal, such as titanium (Ti), titanium nitride (TiN), or titanium tungsten (TiW). The other components are the same as those of the semiconductor device 10 and, as such, will not be described here.

[0032] In the semiconductor device 20 according to Embodiment 2, the lifetime control region 150 is also provided near the bottom of the trench gates 130. However, as described in detail below, in the process of manufacturing the semiconductor device 20, hydrogen atoms are supplied from the Al-based electrode layer 221 to terminate and reduce the interface state present at the boundary between the gate insulation layers 132 and the semiconductor substrate 100. This reduces the variations in the threshold voltage of the trench gates 130.

[0033] Furthermore, in the IGBT region 11, the barrier metal layer 244, to which hydrogen atoms are easily adsorbed, is provided between portions of the body contact layers 109 exposed to the front surface of the semiconductor substrate 100 and the Al-based electrode layer 221, and is not provided between the trench gates 130 and the Al-based electrode layer 221. That is, the barrier metal layer 244 is provided only at positions relatively far from the trench gates 130 to which the hydrogen atoms provided in the IGBT region 11 are supplied. For this reason, in the IGBT region 11, the supply of hydrogen atoms from the Al-based electrode layer 221 to the trench gate 130 is not prevented by the barrier metal layer 244.

[0034] The semiconductor device 20 makes it possible to supply hydrogen atoms to the trench gate 130 provided in the IGBT region 11 while ensuring effects (such as preventing an Al spike) associated with the provision of the barrier metal layer 244, which makes it possible to reduce the variations in the threshold voltage of the trench gates 130 during operation of the IGBT region 11.

[0035] The following describes an example of a manufacturing method of the semiconductor device 20. It should be noted that the following omits a detailed description of steps in which conventional publicly known manufacturing methods of a semiconductor device can be used.

[0036] First, the raw material wafer 90, which is in Fig. 4, using the same methods as those used in Embodiment 1. As shown in Fig. As shown in Figure 13, a barrier metal layer 244 is formed by sputtering or the like on the raw material wafer 90. The barrier metal layer 244 is patterned to contact the front surface of the anode layers 106 and the front surface of the body contact layers 109 and to be open on the front surface side of the trench gates 130.

[0037] Next, as in Fig. 14, an Al-based electrode layer 221 is further formed on a front surface of the barrier metal layer 244 by sputtering or the like.

[0038] Next, as in Fig. 15, after the thickness of the raw material wafer 90 is made thin by cutting a back surface of the raw material wafer 90, ion implantation is performed on the back surface of the raw material wafer 90, whereby the p-type ion implanted layer 901, the n-type ion implanted layer 902, and the n-type ion implanted layer 903 are formed on a back surface side of the raw material wafer 90.

[0039] Next, as in Fig. As shown in Figure 16, crystal defects are formed by irradiating the inner part of the drift layer 104 with charged particles from the back surface side of the raw material wafer 90 in a state where the barrier metal layer 244 and the Al-based electrode layer 212 are present on the front surface of the raw material wafer 90. The position of the charged particle irradiation is adjusted so that a peak of crystal defect density is included in a region located between a depth from the bottom ends of the trench gates 130 and a boundary between the drift layer 104 and the body layer 105. Such charged particle irradiation causes some of the charged particles to be implanted into the gate insulation layer 132.For this reason, performing ion implantation makes it easy for an interface state to be formed between the gate insulating layers 132 and portions of the semiconductor substrate 100 that are in contact with the gate insulating layers 132.

[0040] Next, as in Fig. As shown in FIG. 17, a lifetime control region 150 is formed by performing heating to stabilize crystal defects in a state where the barrier metal layer 244 and the Al-based electrode layer 221 are present on the front surface of the raw material wafer 90. As in Embodiment 1, in this heating step, a p-type collector layer 101, an n-type cathode layer 102, and an n-type buffer layer 103 are formed. Further, by performing this heating step in a state where the Al-based electrode layer 221 is present, hydrogen atoms are supplied from the Al-based electrode layer 221 into the semiconductor substrate 100.Hydrogen atoms thus supplied allow the termination of the interface state existing at the boundary between the gate insulation layers 132 and the semiconductor substrate 100 to proceed effectively, making it possible to effectively reduce the interface state. Furthermore, because the barrier metal layer 244, to which the hydrogen atoms are easily adsorbed, is open on the front surface side of the trench gates 130 to which the hydrogen atoms are supplied, the supply of hydrogen atoms from the Al-based electrode layer 221 to the trench gates 130 is not prevented by the barrier metal layer 244. (Modification)

[0041] It should be noted that the semiconductor device 20 may further be provided with the silicon nitride layer 143 described in Embodiment 1. The interface state is also terminated by hydrogen atoms supplied from the silicon nitride layer 143, so that the interface layer can be reduced more effectively.

[0042] Alternatively, as in a case of a semiconductor device 20a, which is in Fig. 18, the front surface electrode may include a contact plug layer 254 provided between a barrier metal layer 244a and the Al-based electrode layer 221. The contact plug layers 254 are provided on a front surface side of the barrier metal layer 244a provided in the IGBT region 11, are embedded in recessed portions of the barrier metal layer 244a, and their front surfaces are covered with the Al-based electrode layer 221. The contact plug layers 254 may be suitably made of tungsten or the like.Embedding the contact plug layers 254 in the recessed portions of the barrier metal layer 244a causes the front surfaces of the barrier metal layer 244a, the contact plug layers 254, and the interlayer insulation layer 135 to be flush with each other, making it possible to improve the adhesion of these layers to the Al-based electrode layer 221.

[0043] A semiconductor device 20a can be formed by forming a barrier metal layer 244a through the same step as the step of forming the barrier metal layer 244 in the process of manufacturing the semiconductor device 20, performing the step of forming the contact plug layers 254, and then performing the step of forming the Al-based electrode layer 221 in the process of manufacturing the semiconductor device 20. Specifically, a metal layer (e.g., a tungsten layer) from which the contact plug layers 254 are to be made is formed by sputtering or the like on a front surface of a raw material wafer 90b on which the barrier metal layer 244a has been formed, as shown in Fig. 19. Thereafter, the metal layer is patterned so that a portion of the metal layer, excluding portions embedded in recessed portions of a front surface of the barrier metal layer 244a, is removed. This forms the contact plug layers 254. Next, as shown in Fig. 14, the Al-based electrode layer 221 is formed by sputtering or the like on the front surface of the raw material wafer 90b in a state where the contact plug layers 254 have been formed on the front surface of the barrier metal layer 244a. Thereafter, by performing the same steps as those described in Embodiment 2 with reference to Fig. 15 to 17, the semiconductor device 20a can be manufactured.

[0044] Furthermore, the structures of the IGBT region and the diode region described in the above embodiments and modifications are only examples, and the technology disclosed herein can be applied to a semiconductor device having a structure of an IGBT region and a structure of a diode region different from those described above. For example, as in a case of a semiconductor device 10b shown in Fig. 20, a structure of the front surface side of the drift layer 104 may be the same for both the IGBT region 11 and the diode region 12.

[0045] The diode region 12 of the semiconductor device 10b includes diode emitter layers 157 and diode body contact layers 159. In a top view of the semiconductor substrate 100, the diode emitter layers 157 and the diode contact layers 159 are patterned in the same manner as the emitter layers 107 and the body contact layers 109, respectively. The semiconductor device 10b can be manufactured by a simplified process because the structure of the front surface side of the drift layers 104 is patterned in the same manner for both the IGBT region 11 and the diode region 12. Furthermore, in the semiconductor device 10b, the silicon nitride layer 143 is provided only over the IGBT region 11. However, the silicon nitride layer 143 may also be provided over the trench gates 130 and over the diode emitter layers 157 in the diode region 12 (not illustrated).

[0046] Further, it is possible, for example, to include a semiconductor substrate 100c which, as in a case of a semiconductor device 10c shown in Fig. 21 to 23. In a plan view of the semiconductor substrate 100c, as shown in Fig. As shown in Figure 22, an IGBT region 11 includes emitter layers 167 and body contact layers 169 arranged alternately along the longitudinal direction of the trench gates 130. When the semiconductor device 10c is cut along a direction perpendicular to the longitudinal direction of the trench gates 130, there is a case where only the emitter layers 167 appear between adjacent trench gates 130 in the IGBT region 11, as shown in Fig. 21, and a case (not illustrated) in which only the body contact layers 169 appear between adjacent trench gates 130 in the IGBT region 11, depending on the positions of the cross sections.

[0047] Furthermore, in the semiconductor device 10c, as shown in Fig.23, a silicon nitride layer 143c is provided on a portion of the front surface of the front surface electrode 121 located within the IGBT region 11, and has openings 145c opened near central positions between adjacent trench gates 130. Portions of the emitter layers 167 and portions of the body contact layers 169 are located below the openings 145c. As in the case of the semiconductor device 10c, the silicon nitride layer 143c may not be provided vertically over portions of the emitter layers 167 and may be provided vertically over portions of the body contact layers 169.

Claims

[1] Semiconductor device (10) comprising: a semiconductor substrate (100) in which an IGBT region (11) and a diode region (12) are provided; an interlayer insulation layer (135) and a front surface electrode (121) provided on a front surface of the semiconductor substrate (100); and a rear surface electrode (120) provided on a rear surface of the semiconductor substrate (100), wherein the IGBT area (11) has: a collector layer (101) of a first conductivity type; a first drift layer (104 over 11) of a second conductivity type provided on a front surface side of the semiconductor substrate (100) relative to the collector layer (101); a first body layer (105) of the first conductivity type provided on the front surface side of the semiconductor substrate (100) relative to the first drift layer (104 above 11) and partially exposed to the front surface of the semiconductor substrate (100); an emitter layer (107) of the second conductivity type provided on a front surface of the first body layer (105) and exposed to the front surface of the semiconductor substrate (100); and a trench gate (130) reaching the first drift layer (104 via 11) through the first body layer (105) from the front surface side of the semiconductor substrate (100), wherein the diode region (12) has: a cathode layer (102) of the second conductivity type; a second drift layer (104 over 12) of the second conductivity type provided on the front surface side of the semiconductor substrate (100) relative to the cathode layer (102) and having a lower impurity concentration of the second conductivity type than that of the cathode layer (102); and a second body layer (105) of the first conductivity type provided on the front surface side of the semiconductor substrate (100) relative to the second drift layer (104 above 12); wherein the interlayer insulation layer (135) insulates the trench gate (130) from the front surface electrode (121), a lifetime control region (150) containing a peak of a crystal defect density is provided in the first drift layer (104 over 11) and the second drift layer (104 over 12) located between a depth of a lower end of the trench gate (130) and surfaces of the first drift layer (104 over 11) and the second drift layer (104 over 12), a silicon nitride layer (143) is further provided above the trench gate (130) and the emitter layer (107) and below the front surface electrode (121) on the front surface side of the semiconductor substrate (100), covers the interlayer insulation layer (135) and has an opening (145a) opened at a portion of the first body layer (109) which is external to the front surface of the semiconductor substrate (100). [2] Semiconductor device (20) comprising: a semiconductor substrate (100) in which an IGBT region (11) and a diode region (12) are provided; an interlayer insulation layer (135) and a front surface electrode (121) provided on a front surface of the semiconductor substrate (100); and a rear surface electrode (120) provided on a rear surface of the semiconductor substrate (100), wherein the IGBT area (11) has: a collector layer (101) of a first conductivity type; a first drift layer (104 over 11) of a second conductivity type provided on a front surface side of the semiconductor substrate (100) relative to the collector layer (101); a first body layer (105) of the first conductivity type provided on the front surface side of the semiconductor substrate (100) relative to the first drift layer (104 above 11) and partially exposed to the front surface of the semiconductor substrate (100); an emitter layer (107) of the second conductivity type provided on a front surface of the first body layer (105) and exposed to the front surface of the semiconductor substrate (100); and a trench gate (130) reaching the first drift layer (104 via 11) through the first body layer (105) from the front surface side of the semiconductor substrate (100); wherein the diode region (12) has: a cathode layer (102) of the second conductivity type; a second drift layer (104 over 12) of the second conductivity type provided on the front surface side of the semiconductor substrate (100) relative to the cathode layer (102) and having a lower impurity concentration of the second conductivity type than that of the cathode layer (102); and a second body layer (105) of the first conductivity type provided on the front surface side of the semiconductor substrate (100) relative to the second drift layer (104 above 12), wherein the interlayer insulation layer (135) insulates the trench gate (130) from the front surface electrode (121), a lifetime control region (150) containing a peak of a crystal defect density is provided in the first drift layer (104 over 11) and the second drift layer (104 over 12) located between a depth of a lower end of the trench gate (130) and surfaces of the first drift layer (104 over 11) and the second drift layer (104 over 12), the front surface electrode (121) contains an Al-based electrode layer (221) and a barrier metal layer (244), the barrier metal layer (244) is provided between a portion of the first body layer (109) located on the outside of the front surface of the semiconductor substrate (100) and the Al-based electrode layer (221), the barrier metal layer (244) is not provided between the trench gate (130) and the Al-based electrode layer (221), and the barrier metal layer (244) is not provided between the emitter layer (107) and the Al-based electrode layer (221). [3] A method of manufacturing a semiconductor device (10) comprising: a semiconductor substrate (100) in which an IGBT region (11) and a diode region (12) are provided; an interlayer insulation layer (143) and a front surface electrode (121) provided on a front surface of the semiconductor substrate (100); and a rear surface electrode (120) provided on a rear surface of the semiconductor substrate (100), wherein the IGBT area (11) has: a collector layer (101) of a first conductivity type; a first drift layer (104 over 11) of a second conductivity type provided on a front surface side of the semiconductor substrate (100) relative to the collector layer (101); a first body layer (105) of the first conductivity type provided on the front surface side of the semiconductor substrate (100) relative to the first drift layer (104 above 11) and partially exposed to the front surface of the semiconductor substrate (100); an emitter layer (107) of the second conductivity type provided on a front surface of the first body layer (105) and exposed to the front surface of the semiconductor substrate (100); and a trench gate (130) reaching the first drift layer (104 via 11) through the first body layer (105) from the front surface side of the semiconductor substrate (100), wherein the diode region (12) has: a cathode layer (102) of the second conductivity type; a second drift layer (104 over 12) of the second conductivity type provided on the front surface side of the semiconductor substrate (100) relative to the cathode layer (102) and having a lower impurity concentration of the second conductivity type than that of the cathode layer (102); and a second body layer (105) of the first conductivity type provided on the front surface side of the semiconductor substrate (100) relative to the second drift layer (104 above 12); wherein the interlayer insulation layer (135) insulates the trench gate (130) from the front surface electrode (121), a lifetime control region (150) containing a peak of a crystal defect density is provided in the first drift layer (104 over 11) and the second drift layer (104 over 12) located between a depth of a lower end of the trench gate (130) and surfaces of the first drift layer (104 over 11) and the second drift layer (104 over 12), a silicon nitride layer (143) is further provided above the trench gate (130) and the emitter layer (107) and below the front surface electrode (121) on the front surface side of the semiconductor substrate (100); the method comprising: Forming the trench gate (130) in the semiconductor substrate (100); Forming the silicon nitride layer (143) above the trench gate (100) and the emitter layer (107) covering the interlayer insulation layer (135) and having an opening (145a) opened on a portion of the first body layer (105) exposed on the front surface of the semiconductor substrate (100); Irradiating a region located between a depth of a lower end of the trench gate (130) and surfaces of the first drift layer (104 above 11) and the second drift layer (104 above 12) with charged particles in a state in which the silicon nitride layer (143) is present; and Heating the semiconductor substrate (100) in the state in which the silicon nitride layer (143) is present after irradiating the area with the charged particles. [4] A method of manufacturing a semiconductor device (10) comprising: a semiconductor substrate (100) in which an IGBT region (11) and a diode region (12) are provided; an interlayer insulation layer (143) and a front surface electrode (121) provided on a front surface of the semiconductor substrate (100); and a rear surface electrode (120) provided on a rear surface of the semiconductor substrate (100), wherein the IGBT area (11) has: a collector layer (101) of a first conductivity type; a first drift layer (104 over 11) of a second conductivity type provided on a front surface side of the semiconductor substrate (100) relative to the collector layer (101); a first body layer (105) of the first conductivity type provided on the front surface side of the semiconductor substrate (100) relative to the first drift layer (104 above 11) and partially exposed to the front surface of the semiconductor substrate (100); an emitter layer (107) of the second conductivity type provided on a front surface of the first body layer (105) and exposed to the front surface of the semiconductor substrate (100); and a trench gate (130) reaching the first drift layer (104 via 11) through the first body layer (105) from the front surface side of the semiconductor substrate (100); wherein the diode region (12) has: a cathode layer (102) of the second conductivity type; a second drift layer (104 over 12) of the second conductivity type provided on the front surface side of the semiconductor substrate (100) relative to the cathode layer (102) and having a lower impurity concentration of the second conductivity type than that of the cathode layer (102); and a second body layer (105) of the first conductivity type provided on the front surface side of the semiconductor substrate (100) relative to the second drift layer (104 above 12), wherein the interlayer insulation layer (135) insulates the trench gate (130) from the front surface electrode (121), a lifetime control region (150) containing a peak of a crystal defect density is provided in the first drift layer (104 over 11) and the second drift layer (104 over 12) located between a depth of a lower end of the trench gate (130) and surfaces of the first drift layer (104 over 11) and the second drift layer (104 over 12), wherein the procedure has: Forming the trench gate (130) on the semiconductor substrate (100); Forming a barrier metal layer (244) on the front surface side of the semiconductor substrate (100) provided on at least a portion of the first body layer (109) which is external to the front surface of the semiconductor substrate (100) and is open on a front surface side of the trench gate (130) and the emitter layer (107); Forming an Al-based electrode layer (221) on another front surface side of the barrier metal layer (244); Irradiating a region located between a depth of a lower end of the trench gate (130) and surfaces of the first drift layer (104 above 11) and the second drift layer (104 above 12) with charged particles in a state where the barrier metal layer (244) and the Al-based electrode layer (221) are present; and Heating the semiconductor substrate (100) in the state in which the barrier metal layer (244) and the Al-based electrode layer (221) are present after irradiating the area with the charged particles.

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