Method for manufacturing a semiconductor device

Abstract

Method of manufacturing a semiconductor device comprising the semiconductor device: a semiconductor substrate (1); a p-type layer (2, 13) formed on a surface of the semiconductor substrate (1); and first and second n-type buffer layers (8, 9) formed on a rear surface of the semiconductor substrate (1), wherein the first n-type buffer layer (8) is formed by a plurality of proton implantations at different accelerating voltages and has a plurality of peak concentrations at different depths from the back surface of the semiconductor substrate (1), the second n-type buffer layer (9) is formed by implantation of phosphorus, a position of maximum phosphorus concentration flatter from the back surface of the semiconductor substrate (1) than positions of maximum proton concentrations, the maximum concentration of phosphorus is higher than the maximum concentrations of protons, and at the positions of highest proton concentrations, the concentration of protons is higher than the concentration of phosphorus, whereby the first n-type buffer layer (8) is formed by performing the majority of proton implantations at different accelerating voltages using an ion implanter for semiconductor fabrication, the majority of maximum proton concentrations are located at a depth of 6 µm or more and 30 µm or less from the rear surface of the semiconductor substrate (1), and wherein an implantation scope of a profile with a highest acceleration voltage and an implantation scope of a profile with a next highest acceleration voltage are the same among the majority of proton implantations.

Description

Area

[0001] The present invention relates to a semiconductor device such as a diode or an insulated-gate bipolar transistor (IGBT) and a method for manufacturing the same, and more precisely to a semiconductor device which enables a leakage current to be reduced, an oscillation to be suppressed during a turn-off and during a recovery, and an n-type buffer layer to be formed simply by proton implantation in an ordinary semiconductor fabrication facility, and a method for manufacturing the semiconductor device. State of the art

[0002] From an energy-saving perspective, IGBTs and diodes are used in power modules and similar devices to implement variable speed control of three-phase motors in applications such as multi-purpose inverters, AC servo motors, and the like. For an IGBT or diode to function, a device with low switching losses and low on-voltage is desirable to minimize inverter losses.

[0003] The resistance of a thick n-type base layer, necessary for maintaining a breakdown voltage, accounts for most of an ON voltage, and this resistance is effectively reduced by thinning a wafer. However, in the case of a thinned wafer, a depletion layer reaches a back surface when a voltage is applied to a collector, resulting in a drop in breakdown voltage or an increase in leakage current. Therefore, a flat n-type base layer is generally used. + -Type buffer layer with a higher concentration than a substrate concentration formed by an ion implanter on a rear surface of a substrate.

[0004] Due to the reduction of wafer thickness to near a thickness at which a breakdown voltage can be ensured according to advances in IGBT manufacturing techniques, a flat n +A depletion layer of a type of buffer layer forms when a breakdown voltage determined by a power supply voltage +L*di / dt is applied between a collector and an emitter or between a cathode and anode during a switching operation of an IGBT or diode, and a depletion layer reaches a back surface, a charge carrier is decimated, and voltage and current oscillations occur. The occurrence of these oscillations generates radiation interference signals that adversely affect surrounding electronic devices.

[0005] In contrast, by forming a deep n +A low concentration of a -type buffer layer of approximately 30 µm on a substrate's back surface can gradually halt the depletion of a depletion layer, even when a high voltage is applied to a collector or cathode during switching. As a consequence, by preventing the depletion of a charge carrier on the back surface and ensuring its retention, an abrupt voltage rise can be prevented.

[0006] Fig. Figure 23 is a diagram showing the turn-off waveform of an L-load switching operation performed in a device simulation using an IGBT with a through-voltage of approximately 1200 V. Switching conditions include: n +-Type buffer layers formed from phosphorus at depths of 2 µm and 30 µm; Vce = 900 V; and Ic = 150 A. While the waveform oscillates at a depth of 2 µm, no oscillation occurs at 30 µm.

[0007] Creating a deep n +A type 30 µm thick buffer layer formed by phosphorus diffusion takes 24 hours or more at a general heat treatment temperature such as 1100°C, and its mass energy is low. Other methods involve the use of an accelerator such as a cyclotron or a van de Graaff generator (see, for example, PTL 1). Irradiating a silicon substrate with protons at an accelerating voltage of 8 MeV yields a region of approximately 480 µm and a full width at half maximum (FWHM) of approximately 20 µm. By driving protons through an absorber, rather than directly into the silicon substrate, to adjust the position of a region, the radiation energy can be reduced, and an extended proton peak can be generated close to the silicon surface.Subsequently, protons are activated by performing a heat treatment of 1 to 5 hours at 350°C to 450°C, and an n-type region can be formed. Furthermore, although also dependent on implantation and heat treatment conditions, the proton activation rate is approximately 1%.

[0008] From the subsequently published DE 11 2014 003 712 T5 it is known to provide a plurality of trenches in a strip shape extending in a direction parallel to a front substrate surface to a predetermined depth in a depth direction from the front substrate surface.

[0009] From US 2014 / 0 246 755 A1 it is known to introduce hydrogen atoms and crystal defects into an n-type semiconductor substrate by proton implantation.

[0010] From US 2012 / 0267681A1, it is known that a p-anode layer is located on a main surface of an n -- to form a drift layer. On the other main surface of the n - -Drift layer becomes a n + -Cathode layer formed with a contamination concentration greater than that of the n - -drift layer. An anode electrode is formed on the surface of the p-anode layer. A cathode electrode is formed on the surface of the n- + -cathode layer formed. A broad n-type buffer region exhibiting a net doping concentration greater than the mass impurity concentration of a wafer and less than that of the n + -cathode layer and p-anode layer is, is in the n - A drift layer is formed. The specific resistance ρ0 of the n - The drift layer meets the requirements of 0.12 V0 ≤ ρ0 ≤ 0.25 V0 with respect to a nominal voltage V0. The total net doping concentration of the broad buffer region is equal to or greater than 4.8 × 10⁻⁶. 11 atoms / cm 2and equal to or less than 1.0 × 10 12 atoms / cm 2 .

[0011] From EP 2 793 266 A1 a semiconductor device and a method for manufacturing the semiconductor device are known. List of sources: Patent literature

[0012] [PTL 1] JP 2013- 138 172 A Summary of the invention: Technical problem

[0013] The mechanism by which a proton transforms into an n-type donor is determined by a combination of factors, including implanted hydrogen atoms, crystal defects formed during implantation, and oxygen atoms remaining on a substrate. Activation rates vary depending on the silicon substrate formation process, the concentration of mixed-crystal oxygen, proton implantation conditions, and the like. A variation in the concentration of an n +-Type buffer layer formed by proton implantation causes a variation in leakage currents or an ON voltage, a decrease in short-circuit tolerance, and the like.

[0014] Furthermore, when considering an IGBT or a diode, an extensive back surface must be considered. + To fabricate a -type buffer layer with a depth of approximately 30 µm, protons with an increased half-width are implanted at a high accelerating voltage of about 8 MeV. In contrast, conventionally an accelerator such as a cyclotron or a Van de Graaff generator would be used. However, due to radiation concerns, the main body of these accelerators must be enclosed by a concrete shield 1 to 4 m thick, preventing their simple use within a typical semiconductor fabrication facility.

[0015] The present invention has been made to solve problems such as those described above, and one object of it is to provide a semiconductor device which enables a leakage current to be reduced, an oscillation to be suppressed during a shutdown and during a recovery, and an n-type buffer layer to be formed simply by proton implantation itself in an ordinary semiconductor fabrication facility, and a method for fabricating the semiconductor device. Solution to the problem

[0016] These problems are solved by the features of the independent claims. The dependent claims contain advantageous embodiments of the invention. Advantageous effects of the invention

[0017] According to the present invention, oscillation during the turn-off of an IGBT or during the recovery of a diode can be prevented by the first n-type buffer layer, which is formed by proton implantation and has a low concentration and deep diffusion depth. Furthermore, depletion can be stopped by the second n-type buffer layer, which has high concentration phosphorus implanted, to prevent an increase in leakage currents. Moreover, the first n-type buffer layer can be easily formed by proton implantation itself in a conventional semiconductor fabrication facility, without the need for a cyclotron. Brief description of the drawings Fig. Figure 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention. Fig. Figure 2 is a diagram showing a rear surface profile of a semiconductor device according to the first embodiment of the present invention. Fig. Figure 3 is a sectional view showing a manufacturing process of a semiconductor device according to the first embodiment of the present invention. Fig. Figure 4 is a sectional view showing a manufacturing process of a semiconductor device according to the first embodiment of the present invention. Fig. Figure 5 is a sectional view showing a manufacturing process of a semiconductor device according to the first embodiment of the present invention. Fig. Figure 6 is a sectional view showing a manufacturing process of a semiconductor device according to the first embodiment of the present invention. Fig. Figure 7 is a sectional view showing a manufacturing process of a semiconductor device according to the first embodiment of the present invention. Fig. Figure 8 is a sectional view showing a manufacturing process of a semiconductor device according to the first embodiment of the present invention. Fig. Figure 9 is a sectional view showing a manufacturing process of a semiconductor device according to the first embodiment of the present invention. Fig. Figure 10 is a sectional view showing a manufacturing process of a semiconductor device according to the first embodiment of the present invention. Fig. Figure 11 is a sectional view showing a semiconductor device according to a first comparative example. Fig. Figure 12 is a diagram showing a rear surface profile of the semiconductor device according to the first comparison example. Fig. Figure 13 is a sectional view showing a semiconductor device according to a second embodiment of the present invention. Fig. Figure 14 is a diagram showing a rear surface profile of the semiconductor device according to the second embodiment of the present invention. Fig. Figure 15 is a sectional view showing a manufacturing process of a semiconductor device according to the second embodiment of the present invention. Fig. Figure 16 is a sectional view showing a manufacturing process of a semiconductor device according to the second embodiment of the present invention. Fig. Figure 17 is a sectional view showing a manufacturing process of a semiconductor device according to the second embodiment of the present invention. Fig. Figure 18 is a sectional view showing a manufacturing process of a semiconductor device according to the second embodiment of the present invention. Fig. Figure 19 is a sectional view showing a manufacturing process of a semiconductor device according to the second embodiment of the present invention. Fig. Figure 20 is a sectional view showing a manufacturing process of a semiconductor device according to the second embodiment of the present invention. Fig. Figure 21 is a sectional view showing a semiconductor device according to a second comparative example. Fig. Figure 22 is a diagram showing a rear surface profile of the semiconductor device according to the second comparison example. Fig. Figure 23 is a diagram showing a shutdown waveform of an L-load switching operation performed in a device simulation using an IGBT with a breakdown voltage of approximately 1200 V. Description of the embodiments

[0018] A semiconductor device and a method for manufacturing the same according to the embodiments of the present invention are described with reference to the drawings. The same components are identified by the same reference numerals, and the repeated description thereof may be omitted. First embodiment

[0019] Fig. Figure 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention. This semiconductor device is an IGBT. A p-type base layer 2 is formed on a surface of an n-type silicon substrate 1. An n + -Type emitter layer 3 and a p +-Type contact layer 4 is formed on the p-type base layer 2. A trench gate 5 is formed over a gate insulation layer in a trench that separates the p-type base layer 2 and the n + -Type emitter layer 3 penetrates. An intermediate insulating layer 6 is formed on the trench gate 5. An emitter electrode 7 is formed on the surface of the n-type silicon substrate 1 and is connected to the p + -Type contact layer 4 connected.

[0020] First and second n + -Type buffer layers 8 and 9 are formed on a back surface of the n-type silicon substrate 1. The first n + Type 8 buffer layer is formed by multiple proton implantations at different accelerating voltages. The second n +A -type buffer layer 9 is formed by phosphorus implantation. A p-type collector layer 10 with a depth of approximately 1.0 µm is formed at a shallower position on a rear surface of the n-type silicon substrate 1 than the first and second n + -Type buffer layer 8 and 9. A collector electrode 11 is formed on the back surface of the n-type silicon substrate 1 and is connected to the p-type collector layer 10.

[0021] Fig. Figure 2 is a diagram showing a back-side surface profile of a semiconductor device according to the first embodiment of the present invention. Protons of the first n + -Type buffer layer 8 exhibits a plurality of peak concentrations at different depths from a rear surface of the n-type silicon substrate 1. One position of peak phosphorus concentration of the second n +-Type buffer layer 9 lies less deep from the back surface of the n-type silicon substrate 1 than the positions of the highest proton concentrations of the first n + -Type buffer layer 8. The maximum phosphorus concentration is higher than the maximum proton concentrations. At the positions of the maximum proton concentrations, the maximum proton concentration is higher than the maximum phosphorus concentrations.

[0022] Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9 to Fig. Figure 10 are sectional views showing a manufacturing process of a semiconductor device according to the first embodiment of the present invention. First, as in Fig. Figure 3 shows an IGBT surface structure formed by a conventional surface treatment process. At this point, the wafer thickness is approximately 700 µm, which is about the same as that of a bare wafer.

[0023] Next, as in Fig. As shown in Figure 4, a rear surface of the n-type silicon substrate 1 is polished to a desired thickness using a grinder or wet grinding process. Subsequently, as shown in Figure 4, the following steps are performed: Fig. Figure 5 shows that, using an ordinary ion implanter for semiconductor fabrication, protons were implanted multiple times into the back surface of the n-type silicon substrate 1 at different accelerating voltages of 500 keV or higher and 1.5 MeV or lower. The range of the protons is approximately 6 µm at 500 keV and approximately 30 µm at 1500 keV.

[0024] Next, as in Fig. Figure 6 shows that protons are activated by oven annealing at 350°C to 450°C to form the first n + -Type buffer layer 8 is formed. Subsequently, as in Fig. As shown in Figure 7, phosphorus is implanted into a flat region of the back surface of the n-type silicon substrate 1 at an accelerating voltage of 1 MeV or lower. Next, as shown in Fig. Figure 8 shows that the phosphorus is activated by laser annealing to form the second n + -Type buffer layer 9 to be formed.

[0025] Then, as in Fig. As shown in Figure 9, B is implanted into the back surface of the n-type silicon substrate 1. Next, as shown in Fig. 10 shows a laser annealing process performed to remove the p +The -type contact layer 4 is formed. Subsequently, the collector electrode 11, which is constructed from Al / Ti / Ni / Au, AlSi / Ti / Ni / Au, or the like, is formed on the back surface of the n-type silicon substrate 1 by sputtering. Finally, a heat treatment at 350°C is performed to obtain an ohmic contact between the collector electrode 11 and the n-type silicon substrate 1, thereby reducing the contact resistance. At this point, by performing this heat treatment in the same process as the heat treatment for proton activation, process costs can be reduced, as one heat treatment step can be eliminated.

[0026] Next, an effect of the present embodiment will be described by comparison with a comparative example. Fig. Figure 11 is a sectional view showing a semiconductor device according to a first comparative example. Fig. Figure 12 is a diagram showing a back-side surface profile of the semiconductor device according to the first comparison example. In the first comparison example, a depth n + -Type buffer layer 12 of approximately 30 µm formed by proton implantation using an accelerator such as a cyclotron or a Van de Graaff generator.

[0027] Implanting protons at 1.5 MeV yields a range of approximately 30 µm and allows for the formation of a deep buffer layer, which is expected to suppress oscillations. Even with a conventional ion implanter used for semiconductor fabrication, the accelerating voltage can be increased to around 1.5 MeV. However, since a diffusion layer formed at a low accelerating voltage with a semiconductor ion implanter has a short half-width, it is difficult to create an extended diffusion layer, such as one produced by a cyclotron.

[0028] In view of this, in the present embodiment, by performing a plurality of proton implantations at different acceleration voltages such as 500 keV, 1000 keV and 1500 keV, the first n +-Type buffer layer 8 is formed, which has a relatively extended profile, as in Fig. 2 shown.

[0029] However, as a consequence of performing multiple implantations, the closer the implantation is to the substrate's back surface, the greater the number of internally generated crystal defects. Since proton activation also depends on the number of crystal defects, variations in the concentration of an n-type layer can occur. Considering this, forming a second n + -Type buffer layer 9 of high concentration near the rear surface by phosphorus implantation prevents a depletion layer from reaching a collector side when a voltage is applied, and a drop in breakdown voltage and an increase in leakage currents can be suppressed.

[0030] Furthermore, since phosphorus has an atomic radius larger than that of a proton, a large number of implantation damages occur during implantation due to collisions between atomic nuclei. If a phosphorus implantation profile overlaps with a proton implantation profile, proton-to-donor conversions can be affected. Therefore, in the present embodiment, a maximum position is defined such that at the positions of highest proton concentrations, the proton concentration is higher than the phosphorus concentration. Accordingly, mutual interference can be prevented, and the first n + A desired concentration can be given to the -type buffer layer 8, which is formed by the activation of protons.

[0031] As described above, according to the present embodiment, an oscillation of the IGBT during a shutdown can be prevented by the first n + -Type buffer layer 8, which is formed by proton implantation and has a low concentration and a deep diffusion depth, is prevented. Furthermore, a depletion layer can be formed by the second n + -Type buffer layer 9 of high concentration, which has implanted protons, is stopped to prevent an increase in leakage currents.

[0032] Next, the first n + A type 8 buffer layer is formed by performing multiple proton implantations at different accelerating voltages using a conventional ion implanter for semiconductor fabrication. Accordingly, the first n +-Type buffer layer 8 can be formed in an ordinary semiconductor factory simply by proton implantation, without having to use a cyclotron.

[0033] Furthermore, when the majority of proton implantations are performed, the higher the accelerating voltage, the smaller the implantation area. Accordingly, a profile of the first n + -Type buffer layer 8, which is formed by the majority of proton implantations, can be approximated to a Gaussian distribution.

[0034] Furthermore, the implantation extent of a profile with the highest accelerating voltage and the implantation extent of a profile with the next highest accelerating voltage are the same for the majority of proton implantations. Accordingly, a profile with a very gentle gradient can be formed, and thus a depletion layer that propagates during the turn-off of an IGBT or during the recovery of a diode can be gently halted. As a consequence, the leaching and depletion of charge carriers can be prevented.

[0035] Furthermore, the phosphorus implantation area is set smaller than the proton implantation area. Phosphorus activation is performed by laser annealing, while proton activation is performed by oven annealing at 350°C to 450°C. Laser annealing increases the phosphorus activation rate to approximately 70%, whereas oven annealing achieves an activation rate of approximately 1% for protons. Therefore, even if the phosphorus implantation area is set smaller than the proton implantation area, the maximum phosphorus concentration can be set sufficiently higher than the maximum proton concentration. Consequently, a proton implantation area located near a phosphorus implantation area can be converted into a donor while suppressing the damage caused by phosphorus implantation. Second embodiment

[0036] Fig. Figure 13 is a sectional view showing a semiconductor device according to a second embodiment of the present invention. This semiconductor device is a diode. A p-type anode layer 13 is formed on the surface of an n-type silicon substrate 1. An anode electrode 14 is formed on the surface of the n-type silicon substrate 1 and is connected to the p-type anode layer 13. In a manner similar to the first embodiment, the first and second n + -Type buffer layers 8 and 9 are formed on a rear surface of the n-type silicon substrate 1. A cathode electrode 15 is formed on the rear surface of the n-type silicon substrate 1 and is connected to the second n + -Type buffer layer 9 connected.

[0037] Fig. Figure 14 is a diagram showing a back-side surface profile of the semiconductor device according to the second embodiment of the present invention. In a similar manner to the first embodiment, protons of the first n + -Type buffer layer 8 exhibits a plurality of peak concentrations at different depths from the back surface of the n-type silicon substrate 1. One position of peak phosphorus concentration of the second n + -Type buffer layer 9 is less deep from the back surface of the n-type silicon substrate 1 than the positions of the highest proton concentrations of the first n + -Type buffer layer 8. The maximum phosphorus concentration is higher than the maximum proton concentrations. At the positions of the maximum proton concentrations, the proton concentration is higher than the phosphorus concentration.

[0038] Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19 to Fig. Figure 20 are sectional views showing a manufacturing process of a semiconductor device according to the second embodiment of the present invention. First, as in Fig. Figure 15 shows a diode surface structure formed by a conventional surface treatment process. At this point, the wafer thickness is approximately 700 µm, which is about the same as that of a bare wafer.

[0039] Next, as in Fig. As shown in Figure 16, a rear surface of the n-type silicon substrate 1 is polished to a desired thickness using a grinder or wet grinding process. Subsequently, as shown in Fig. Figure 17 shows that, using an ordinary ion implanter for semiconductor fabrication, protons were implanted multiple times into the back surface of the n-type silicon substrate 1 at different accelerating voltages of 500 keV or higher and 1.5 MeV or lower. The range of the protons is approximately 6 µm at 500 keV and approximately 30 µm at 1500 keV.

[0040] Next, as in Fig. Figure 18 shows that protons are activated by oven annealing at 350°C to 450°C to form the first n + to form a -type buffer layer. Then, as in Fig. As shown in Figure 19, phosphorus is implanted into a flat region of the back surface of the n-type silicon substrate 1 at an accelerating voltage of 1 MeV or lower. Next, as shown in Fig. 20 shows that the phosphorus is activated by laser annealing to produce the second n + -Type buffer layer 9 to be formed.

[0041] The cathode electrode 15, constructed from Al / Ti / Ni / Au, AlSi / Ti / Ni / Au, or the like, is then formed on the back surface of the n-type silicon substrate 1 by sputtering. Finally, a heat treatment at approximately 350°C is performed to create an ohmic contact between the cathode electrode 15 and the n-type silicon substrate 1, thereby reducing the contact resistance. At this point, performing this heat treatment in the same process as the heat treatment for proton activation can reduce process costs, as one heat treatment step can be eliminated.

[0042] Next, an effect of the present embodiment will be described by comparison with a comparative example. Fig. Figure 21 is a sectional view showing a semiconductor device according to a second comparative example. Fig.Figure 22 is a diagram showing a back-side surface profile of the semiconductor device according to the second comparison example. In the second comparison example, a depth n + -Type buffer layer 12 of approximately 30 µm formed by proton implantation using an accelerator such as a cyclotron or a Van de Graaff generator.

[0043] In comparison, in the present embodiment, an oscillation of the diode during a recovery phase can be achieved in a similar manner to the first embodiment. + -Type buffer layer 8, which is formed by proton implantation and has a low concentration and deep diffusion depth, is prevented. Furthermore, a depletion layer can be formed by the second n + -Type buffer layer 9 of high concentration, which has implanted phosphorus, is stopped to prevent an increase in leakage currents. Furthermore, the first n +-Type buffer layer 8 can be formed in an ordinary semiconductor factory simply by proton implantation, without having to use a cyclotron.

[0044] The semiconductor substrate is not limited to silicon and can be a wide-bandgap semiconductor with a bandgap larger than that of silicon. Examples of wide-bandgap semiconductors include silicon carbide, gallium nitride-based materials, and diamond. A power semiconductor device made from such a wide-bandgap semiconductor exhibits a high breakdown voltage and a high allowable current density, and can therefore be miniaturized. A semiconductor module containing this miniaturized semiconductor device can also be miniaturized. Furthermore, heat sink fins can be made smaller, and a water-cooled component can be replaced by an air-cooled one because the semiconductor device has a high thermal resistance.Furthermore, the device exhibits low power loss and high efficiency, and the efficiency of the semiconductor module can therefore be improved. Reference symbol list

[0045] 1 n-type silicon substrate (semiconductor substrate), 2 p-type base layer (p-type layer), 8 first n + -type buffer layer (first n-type buffer layer), 9 second n + -type buffer layer (second n-type buffer layer), 11 Collector electrode (rear electrode), 13 p-type anode layer (p-type layer), 15 Cathode electrode (rear electrode)

Claims

[1] Method of manufacturing a semiconductor device comprising the semiconductor device: a semiconductor substrate (1); a p-type layer (2, 13) formed on a surface of the semiconductor substrate (1); and first and second n-type buffer layers (8, 9) formed on a rear surface of the semiconductor substrate (1), wherein the first n-type buffer layer (8) is formed by a plurality of proton implantations at different accelerating voltages and has a plurality of peak concentrations at different depths from the back surface of the semiconductor substrate (1), the second n-type buffer layer (9) is formed by implantation of phosphorus, a position of maximum phosphorus concentration flatter from the back surface of the semiconductor substrate (1) than positions of maximum proton concentrations, the maximum concentration of phosphorus is higher than the maximum concentrations of protons, and at the positions of highest proton concentrations, the concentration of protons is higher than the concentration of phosphorus, whereby the first n-type buffer layer (8) is formed by performing the majority of proton implantations at different accelerating voltages using an ion implanter for semiconductor fabrication, the majority of maximum proton concentrations are located at a depth of 6 µm or more and 30 µm or less from the rear surface of the semiconductor substrate (1), and wherein an implantation scope of a profile with a highest acceleration voltage and an implantation scope of a profile with a next highest acceleration voltage are the same among the majority of proton implantations. [2] Method of manufacturing a semiconductor device comprising the semiconductor device: a semiconductor substrate (1); a p-type layer (2, 13) formed on a surface of the semiconductor substrate (1); and first and second n-type buffer layers (8, 9) formed on a rear surface of the semiconductor substrate (1), wherein the first n-type buffer layer (8) is formed by a plurality of proton implantations at different accelerating voltages and has a plurality of peak concentrations at different depths from the back surface of the semiconductor substrate (1), the second n-type buffer layer (9) is formed by implantation of phosphorus, a position of maximum phosphorus concentration flatter from the back surface of the semiconductor substrate (1) than positions of maximum proton concentrations, the maximum concentration of phosphorus is higher than the maximum concentrations of protons, and at the positions of highest proton concentrations, the concentration of protons is higher than the concentration of phosphorus, whereby the first n-type buffer layer (8) is formed by performing the majority of proton implantations at different accelerating voltages using an ion implanter for semiconductor fabrication, wherein an accelerating voltage of the protons is 500 keV or higher and 1.5 MeV or lower, and wherein an implantation scope of a profile with a highest acceleration voltage and an implantation scope of a profile with a next highest acceleration voltage are the same among the majority of proton implantations. [3] Method of manufacturing a semiconductor device according to claim 1 or claim 2, wherein the semiconductor device is a diode or a bipolar transistor with an insulated gate. [4] Method of manufacturing a semiconductor device according to one of claims 1 to 3, wherein the implantation extent of the phosphorus is less than the implantation extent of the protons, and the phosphorus is activated by laser annealing. [5] Method of manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the protons are activated by oven annealing at 350°C to 450°C. [6] Method of manufacturing a semiconductor device according to any one of claims 1 to 5, wherein the accelerating voltage of the phosphorus is 1 MeV or lower. [7] Method of manufacturing a semiconductor device according to claim 1, wherein the acceleration voltage of the protons is 500 keV or higher and 1.5 MeV or lower. [8] Method of manufacturing a semiconductor device according to any one of claims 1 to 7, comprising forming a backside electrode (11, 15) on a backside surface of the semiconductor substrate (1); and performing a heat treatment to obtain an ohmic contact between the backside electrode (11, 15) and the semiconductor substrate (1) in the same process as a heat treatment for activating the protons.

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