BUS setup function address space mapping

Abstract

Device comprising: Bridge logic to: to receive a request from a facility, wherein the request refers to an address in a secondary address space, the secondary address space corresponds to a subset of addresses in a system's configuration address space, the secondary address space corresponds to a first view of the configuration address space, addresses in the secondary address space each comprise a corresponding Peripheral Component Interconnect (PCI)-based bus / facility / function number (BDF number), the secondary address space comprises a specific one of a plurality of non-overlapping secondary address spaces, each of the plurality of secondary address spaces maps to a corresponding section of the configuration address space, and a specific BDF number is used in the specific secondary address space and in another of the plurality of secondary address spaces; and to use a mapping table to translate the address of the specified secondary address space into a corresponding address in the configuration address space, wherein addresses of the configuration address space correspond to another second view of the configuration address space, addresses of the configuration address space each include a corresponding PCI-based BDF number, and the mapping table maps BDF numbers in the secondary address space to BDF numbers in the configuration address space.

Description

REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. Patent Application No. 62 / 158,456, filed May 7, 2015, entitled "BUS-DEVICE-FUNCTION ADDRESS SPACE MAPPING," which is incorporated herein by reference in its entirety. AREA

[0002] This disclosure relates to a computing system and, in particular (but not exclusively), to an address space mapping. STATE OF THE ART

[0003] A Peripheral Component Interconnect (PCI) configuration space is used by systems using PCI, PCI-X, and PCI Express (PCIe) to perform configuration tasks for PCI-based devices. PCI-based devices have an address space for device configuration registers called configuration space, and PCI Express introduces an extended device configuration space. Configuration space registers are typically mapped by the host processor to input / output locations mapped in memory. Device drivers, operating systems, and diagnostic software access configuration space and can read and write information to configuration space registers.

[0004] One of the improvements that the PCI Local Bus had over other I / O architectures was its configuration mechanism. In addition to the normal memory-mapped and I / O port spaces, each device function on the bus has a 256-byte configuration space that can be addressed by knowing the eight-bit PCI bus, five-bit device, and three-bit function number for the device (commonly referred to as BDF or B / D / F, an abbreviation of Bus / Device / Function). This allows up to 256 buses, each with up to 32 devices, each supporting eight functions. A single PCI expansion card can respond as one device and can implement at least function number zero. The first 64 bytes of the configuration space are standardized; the remainder are available extensions defined in the specification and / or for vendor-defined purposes.

[0005] To allow more parts of the configuration space to be standardized without conflicting with existing usage, there may be a list of capabilities defined in the first 192 bytes of the Peripheral Component Interface configuration space. Each capability has one byte describing what capability it is and one byte to point to the next capability. The number of additional bytes depends on the capability ID. If capabilities are used, a bit is set in the status register, and a pointer to the first in a linked list of capabilities is provided. Previous versions of PCIe were provided with similar features, such as an extended PCIe capability structure.

[0006] US 2011 / 0219164 A1 relates to an I / O system and an I / O control method that can share an I / O device among a plurality of computers. The I / O system includes a plurality of computers, an I / O device including memory locations and interrupt resources separately allocable to the plurality of computers, and an I / O virtualization device provided between the plurality of computers and the I / O device. The I / O virtualization device forms an address space unique to the I / O device, maps the address space of the I / O device to address spaces of the plurality of computers, and exchanges address spaces of the computers and the address space of the I / O device for packets (I / O packets) used for access between the computers and the I / O device.The I / O virtualization device includes an exchange unit that exchanges addresses of the I / O packets between the address space of the I / O device and the address spaces of the plurality of computers, a holding unit that holds exchange information about relationships between the address space of the I / O device and the address spaces of the plurality of computers, an address space formation unit that forms the address space unique to the I / O device, and an acquisition unit that acquires spaces required to map the address space of the I / O device to the address spaces of the computers during a configuration cycle of the computers.

[0007] US 9 015 351 B1 relates to the virtualization of computer resources. A described method comprises: receiving a first address for one of a plurality of resources, wherein the first address relates to a first address space and wherein each of the resources is associated with i) a respective first aperture in the first address space and ii) a respective second aperture in a second address space, and translating the first address into a second address, wherein the second address relates to the second address space. Translating comprises swapping a first sequence of bits in the first address with a second sequence of bits in the first address. A number of bits in the second sequence is determined according to a number of the resources, and a number of bits in the first sequence is determined according to a difference between a size of the first aperture and a size of the second aperture.

[0008] US 2011 / 0320759 A1 concerns the provision of address spaces within system memory and the provision of address translation tables that can be used when accessing system memory. For example, an adapter is assigned a plurality of address spaces. To select a specific address space for the adapter, a request identifier and an address space identifier are used, which are provided by the adapter in a request. Each address space is assigned a different address translation mechanism.

[0009] US 2015 / 0067229 A1 relates to methods and devices implemented in multi-node computing platforms, such as those using a NUMA (Non-Uniform Memory Access) architecture. SUMMARY

[0010] The present invention is defined by the subject matter of main claim 1 and the subordinate claims 16 and 22. The dependent claims define further embodiments of the device or system according to the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates one embodiment of a computing system including an interconnect architecture. Fig. Figure 2 illustrates one embodiment of an interconnect architecture including a layered stack. Fig. Figure 3 illustrates one embodiment of a request or packet to be generated or received in an interconnect architecture. Fig. Figure 4 illustrates one embodiment of a transmitter and receiver pair for an interconnect architecture. Fig. Figure 5 illustrates a representation of system buses. Fig. Figure 6 illustrates a representation of an enumeration of bus identifiers in a system. Fig. Figure 7 illustrates an embodiment of a mapping portal bridge (MPB). Fig. Figure 8 illustrates a representation of an enumeration of bus identifiers in a system and corresponding address mappings. Fig. 9 illustrates a representation of at least a portion of an exemplary capability register. Fig. 10 illustrates one embodiment of a block diagram for a computing system including a multi-core processor. Fig. 11 illustrates another embodiment of a block diagram for a computing system. DETAILED DESCRIPTION

[0011] In the following description, numerous specific details are set forth, such as examples of specific types of processors and system configurations, specific hardware structures, specific architectural and microarchitectural details, specific register configurations, specific instruction types, specific system components, specific dimensions / heights, specific processor pipeline stages and operations, etc., to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that these specific details need not be used to practice the present invention.In other instances, well-known components or methods, such as specific and alternative processor architectures, specific logic circuits / specific code for described algorithms, specific firmware code, specific interconnect operation, specific logic configurations, specific manufacturing techniques and materials, specific compiler implementations, specific expression of algorithms in code, specific shutdown and startup techniques / logic, and other specific operating details of the computer system have not been described in detail to avoid unnecessarily obscuring the present invention.

[0012] Although the following embodiments may be described with reference to power conservation and energy efficiency in specific integrated circuits, such as computing platforms or microprocessors, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments described herein may be applied to other types of circuits or semiconductor devices that may also benefit from improved power efficiency and energy conservation. For example, the disclosed embodiments are not limited to desktop computer systems or Ultrabooks™ and may also be used in other devices such as wearable devices, tablets, other thin notebooks, system-on-chip (SOC) devices, and embedded applications.Some examples of portable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (PDAs), and portable PCs. Embedded applications typically include a microcontroller, a digital signal processor (DSP), a system on a chip, network computers (NetPCs), set-top boxes, network hubs, wide area network (WAN) switches, or any other systems capable of performing the functions and operations taught below. Furthermore, the apparatus, methods, and systems described herein are not limited to physical computing devices but may also pertain to software optimizations for power conservation and efficiency.

[0013] As computing systems evolve, their components become more complex. Consequently, the interconnect architecture for coupling and communicating between components also increases in complexity to ensure bandwidth requirements are met for optimal component operation. Furthermore, different market segments require different aspects of interconnect architectures to meet market needs. For example, servers require higher performance, while the mobile ecosystem may sometimes sacrifice overall performance for power savings. However, the sole purpose of most architectures is to provide the highest possible performance with maximum power savings. A number of interconnects that would potentially benefit from aspects of the invention described herein are discussed below.

[0014] One interconnect fabric architecture includes the Peripheral Component Interconnect (PCI) Express (PCIe) architecture. A primary goal of PCIe is to enable components and devices from different vendors to interoperate in an open architecture spanning multiple market segments: clients (desktops and mobile devices), servers (standard and enterprise), and embedded and communications devices. PCI Express is a high-performance, general-purpose I / O interconnect defined for a wide variety of future computing and communications platforms. Some PCI attributes, such as its usage model, load-store architecture, and software interfaces, have been maintained throughout its revisions, whereas previous parallel bus implementations have been replaced by a highly scalable, fully serial interface.The newer versions of PCI Express leverage point-to-point connections, switch-based technology, and a packetized protocol to deliver new levels of performance and new features. Power management, quality of service (QoS), hot-swap and hot-swap support, data integrity, and error handling are among the advanced features supported by PCI Express.

[0015] With reference to Fig. 1 illustrates one embodiment of a fabric consisting of point-to-point links connecting a set of components. A system 100 includes a processor 105 and system memory 110 coupled to a control node 115. The processor 105 includes any processing element, such as a microprocessor, a host processor, an embedded processor, a coprocessor, or another processor. The processor 105 is coupled to the control node 115 by a front side bus (FSB) 106. In one embodiment, the FSB 106 is a serial point-to-point connection as described below. In another embodiment, the link 106 includes a serial, differential interconnect architecture compliant with various interconnect standards.

[0016] System memory 110 includes any memory device, such as random access memory (RAM), non-volatile (NV) memory, or other memory accessible by devices in system 100. System memory 110 is coupled to control node 115 by a memory interface 116. Examples of a memory interface include a double data rate (DDR) memory interface, a dual-channel DDR memory interface, and a dynamic random access memory (DRAM) memory interface.

[0017] In one embodiment, control node 115 is a root node, a root complex, or a root controller in a Peripheral Component Interconnect Express (PCIe or PCIE) interconnect hierarchy. Examples of control nodes 115 include a chipset, a memory control node (MCH), a northbridge, an interconnect control node (ICH), a southbridge, and a root controller / root node. Often, the term chipset refers to two physically separable control nodes, i.e., a memory control node (MCH) coupled to an interconnect control node (ICH). Note that current systems often include the MCH integrated with processor 105, while controller 115 communicates with I / O devices in a manner similar to that described above. In some embodiments, peer-to-peer routing is optionally supported by root complex 115.

[0018] Here, control node 115 is coupled to a switch / bridge 120 through a serial link 119. Input / output modules 117 and 121, which may also be referred to as interfaces / ports 117 and 121, contain / implement a layered protocol stack to provide communication between control node 115 and switch 120. In one embodiment, multiple devices may be coupled to switch 120.

[0019] The switch / bridge 120 forwards packets / messages from a device 125 upstream, ie, upstream in a hierarchy to a root complex, to the control node 115 and downstream, ie, downstream in a hierarchy away from a root controller, from the processor 105 or system memory 110 to the device 125. The switch 120, in one embodiment, is referred to as a logical assembly of multiple virtual PCI-to-PCI bridge devices.Device 125 includes any internal or external device or component to be coupled to an electronic system, such as an I / O device, a network interface controller (NIC), an add-in card, an audio processor, a network processor, a hard disk, a storage device, a CD / DVD-ROM, a monitor, a printer, a mouse, a keyboard, a router, a portable storage device, a FireWire device, a Universal Serial Bus (USB) device, a scanner, and other input / output devices. Such a device is often referred to in PCIe jargon as an endpoint. Although not specifically shown, device 125 may include a PCIe-to-PCI / PCI-X bridge to support older PCI devices or PCI devices of a different version. Endpoint devices in PCIe are often classified as legacy, PCIe, or root-complex integrated endpoints.

[0020] Additionally, a graphics accelerator 130 is coupled to the control node 115 through a serial link 132. In one embodiment, the graphics accelerator 130 is coupled to an MCH, which is coupled to an ICH. The switch 120, and accordingly, the I / O device 125, is then coupled to the ICH. I / O modules 131 and 118 are also intended to implement a layered protocol stack to communicate between the graphics accelerator 130 and the control node 115. Similar to the discussion of the MCH above, a graphics controller or the graphics accelerator 130 itself may be integrated into the processor 105.

[0021] On Fig. 2, one embodiment of a layered protocol stack is illustrated. The layered protocol stack 200 includes any form of layered communication stack, such as a QuickPath Interconnect (QPI) stack, a PCIe stack, a next-generation high-performance computing interconnect stack, or another layered stack. Although the immediately following discussion with respect to Fig. 1-4 in conjunction with a PCIe stack, the same concepts can be applied to other interconnect stacks. In one embodiment, protocol stack 200 is a PCIe protocol stack that includes a transaction layer 205, a link layer 210, and a physical layer 220. An interface, such as interfaces 117, 118, 121, 122, 126, and 131 in Fig. 1, can be represented as a communication protocol stack 200. A communication protocol stack representation can also be referred to as a module or interface that implements / contains a protocol stack.

[0022] PCI Express uses packets to communicate information between components. Packets are formed in the transaction layer 205 and the data link layer 210 to carry the information from the sending component to the receiving component. As the sent packets flow through the other layers, they are augmented with additional information necessary to handle packets at those layers. On the receiving side, the reverse process occurs, and packets are transformed from their physical layer 220 representation to their data link layer 210 representation, and finally (for transaction layer packets) to the form that can be processed by the transaction layer 205 of the receiving device. Transaction layer

[0023] In one embodiment, the transaction layer 205 provides an interface between a processing core of a device and the interconnect architecture, such as the data link layer 210 and the physical layer 220. In this regard, a primary task of the transaction layer 205 is the assembly and disassembly of packets (i.e., transaction layer packets or TLPs). The translation layer 205 typically manages credit-based flow control for TLPs. PCIe implements split transactions, i.e., transactions with time-separated requests and responses, allowing a link to carry other traffic while the destination device gathers data for the response.

[0024] In addition, PCIe employs credit-based flow control. In this scheme, a device announces an initial amount of credit for each of the receive buffers in the transaction layer 205. An external device at the opposite end of the link, such as the control node 115 in Fig. 1, counts the number of credits consumed by each TLP. A transaction can be sent if the transaction does not exceed a credit limit. After receiving a response, a credit amount is restored. One advantage of a credit scheme is that the latency of credit return does not affect performance, provided the credit limit is not touched.

[0025] In one embodiment, a four-transaction address space includes a configuration address space, a memory address space, an input / output address space, and a message address space. Transactions in the memory space include one or more read requests and write requests to transfer data to / from a memory-mapped location. In one embodiment, transactions in the memory space can use two different address formats, such as a short address format, such as a 32-bit address, or a long address format, such as a 64-bit address. Transactions in the configuration space are used to access the configuration space of PCIe devices. Transactions to the configuration space include read requests and write requests. Message transactions are defined to support in-band communication between PCIe arbiters.

[0026] Therefore, in one embodiment, the transaction layer 205 assembles a packet header / payload 156. The format for current packet headers / payloads can be found in the PCIe specification on the PCIe specification website.

[0027] Quickly on Fig. Referring to Figure 3, one embodiment of a PCIe transaction descriptor is illustrated. In one embodiment, transaction descriptor 300 is a mechanism for carrying transaction information. In this regard, transaction descriptor 300 supports identification of transactions within a system. Other possible uses include tracking modifications to a standard transaction order and mapping transactions to channels.

[0028] The transaction descriptor 300 includes a global identifier field 302, an attribute field 304, and a channel identifier field 306. In the illustrated example, a global identifier field 302 is shown, which includes a local transaction identifier field 308 and a source identifier field 310. In one embodiment, the global transaction identifier 302 is unique for all outstanding requests.

[0029] According to one implementation, the local transaction identifier field 308 is a field generated by a requesting agent and is unique for all outstanding requests requiring fulfillment for that requesting agent. Furthermore, the source identifier field 310 uniquely identifies the request agent within a PCIe hierarchy. Accordingly, the local transaction identifier field 308, together with the source ID 310, provides global identification of a transaction within a hierarchy domain.

[0030] The attribute field 304 specifies properties and relationships of the transaction. In this regard, the attribute field 304 may be used to provide additional information that enables modification of the default transaction handling. In one embodiment, the attribute field 304 includes a priority field 312, a reserved field 314, an ordering field 316, and a no-snoop field 318. Here, the priority subfield 312 may be modified by an initiator to assign a priority to the transaction. The reserved attribute field 314 is reserved for future use or for a provider-defined use. Possible usage models that utilize priority or security attributes may be implemented using the reserved attribute field.

[0031] In this example, the ordering attribute field 316 is used to provide optional information conveying the type of ordering that can modify default ordering rules. According to one implementation example, an ordering attribute of "0" indicates that default ordering rules apply, while an ordering attribute of "1" indicates a relaxed ordering, where writes can pass other writes in the same direction and read completions can pass writes in the same direction. The snoop attribute field 318 is used to determine whether transactions are snooped. As shown, the channel ID field 306 identifies a channel with which a transaction is associated. connection layer

[0032] The link layer 210, also referred to as the data link layer 210, acts as an intermediate layer between the transaction layer 205 and the physical layer 220. In one embodiment, the function of the data link layer 210 is to provide a reliable mechanism for exchanging transaction layer packets (TLPs) between two components of a connection. One side of the data link layer 210 accepts TLPs assembled by the transaction layer 205, applies a packet sequence identifier 211, i.e., an identification number or packet number, calculates and applies an error detection code, i.e., CRC 212, and passes the modified TLPs to the physical layer 220 for transmission over a physical to an external device. Physical layer

[0033] In one embodiment, physical layer 220 includes a logical sub-block 221 and an electrical sub-block 222 for physically transmitting a packet to an external device. Logical sub-block 221 is responsible for the "digital" functions of physical layer 221. In this regard, the logical sub-block includes a transmit section for preparing outgoing information for transmission by physical sub-block 222 and a receive section for identifying and preparing received information before it is transmitted to link layer 210.

[0034] The physical block 222 includes a transmitter and a receiver. The transmitter is supplied with symbols from the logical sub-block 221, which the transmitter serializes and sends to an external device. The receiver is supplied with serialized symbols from an external device and converts the received signals into a bit stream. The bit stream is deserialized and provided to the logical sub-block 221. In one embodiment, an 8b / 10b transmit code is used, in which ten-bit symbols are transmitted / received. Special symbols are used to frame a packet with frames 223. In one example, the receiver also provides a symbol clock determined from the incoming serial stream.

[0035] As stated above, although the transaction layer 205, the link layer 210, and the physical layer 220 were discussed with reference to a specific embodiment of a PCIe protocol stack, a layered protocol stack is not so limited. Rather, any layered protocol may be included / implemented. As an example, a port / interface represented as a layered protocol includes: (1) a first layer for assembling packets, i.e., a transaction layer; a second layer for sequencing packets, i.e., a link layer; and a third layer for transmitting the packets, i.e., a physical layer. As a specific example, a layered Common Standard Interface (CSI) protocol is employed.

[0036] Next, with reference to Fig. 4 illustrates one embodiment of a PCIe point-to-point serial fabric. Although one embodiment of a PCIe point-to-point serial link is illustrated, a point-to-point serial link is not so limited, as it includes any transmit path for transmitting serial data. In the illustrated embodiment, a basic PCIe link includes two differentially operated low-voltage signal pairs: a transmit pair 406 / 411 and a receive pair 412 / 407. Accordingly, a device 405 includes transmit logic 406 for transmitting data to a device 410, and receive logic 407 for receiving data from the device 410. In other words, two transmit paths, i.e., paths 416 and 417, and two receive paths, i.e., paths 418 and 419, are incorporated into a PCIe link.

[0037] A transmit path refers to any path for sending data, such as a broadcast wire, a copper wire, an optical wire, a wireless communication channel, an infrared communication link, or any other communication path. A connection between two devices, such as device 405 and device 410, is referred to as a link, such as link 415. A link can support one lane—each lane represents a set of differential signal pairs (one pair for transmitting, one pair for receiving). For bandwidth scaling, a link can aggregate multiple lanes denoted by xN, where N is any supported link width, such as 1, 2, 4, 8, 12, 16, 32, 64, or wider.

[0038] A differential pair refers to two transmit paths, such as lines 416 and 417, for transmitting differential signals. For example, when line 416 transitions from a low voltage level to a high voltage level, i.e., a rising edge, line 417 transitions from a high logic level to a low logic level, i.e., a falling edge. Differential signals may exhibit better electrical characteristics, such as better signal integrity, i.e., crosstalk, voltage overshoot / undershoot, oscillation, etc. This allows for a better timing window, enabling faster transmit frequencies.

[0039] New and growing deployment models, such as PCIe-based storage arrays and Thunderbolt, are driving a significant increase in the depth and breadth of the PCIe hierarchy. The PCI Express (PCIe) architecture was built on PCI, which provided a "conf iguration space" in which system firmware and / or software discover functions and enable / disable / control them. Addressing in this space is based on a 16-bit address (often referred to as the "BDF" or Bus Facility Function Number), which consists of an 8-bit bus number, a 5-bit facility number, and a 3-bit function number.

[0040] PCI allows systems to provide multiple independent BDF spaces, called "segments." Each segment can have specific resource requirements, such as a mechanism for generating PCI / PCIe configuration requests, including the Extended Configuration Access Mechanism (ECAM) defined in the PCIe specification. Additionally, input / output (I / O) memory management units (IOMMUs) (such as Intel VT-d) can use the BDF space as an index, but may not be configured to directly understand segments. Accordingly, in some cases, a separate ECAM and IOMMU must be duplicated for each segment defined in a system. Fig. Figure 5 illustrates an example of a system containing multiple segments (e.g., 505a-c). For example, in this example, one segment is defined for each of three switches 510, 515, 520 connected to a root complex 525. A separate IOMMU and a separate ECAM (e.g., 530a-c) may be implemented at the root complex 525 to enable each of the segments (e.g., 505a-c). Furthermore, in this example, a variety of endpoints (EPs) are connected to different buses in each segment. In some cases, a segment's configuration space may reserve multiple bus addresses for possible hot-plug events, limiting the total number of bus addresses available in each segment. Further, bus number allocation in one or more of the segments may be performed according to an algorithm that pays little attention to dense address populating and compact use of the available bus address space.This may in some cases result in wasted configuration address space (ie BDF space).

[0041] Conventional PCIe systems are configured to allocate address space in a manner that, when applied to modern and emerging use cases, inefficiently uses BDF space, and especially bus numbers. While relatively few implementations can actually involve a single system consuming all 64K of the unique BDF values ​​(e.g., those defined under PCIe), deep hierarchies, such as those found in deep hierarchies of PCIe switches, can consume the available bus numbers very quickly. Additionally, in applications that support hot-plugging, large portions of the BDF space can typically be reserved for possible future use (i.e., when a future device is hot-plugged into the system), removing additional swaths of bus numbers from the inventory that can be immediately used by a system.While segment mechanisms can be applied to address this problem, the segments themselves scale poorly because, as noted above, additional hardware resources (e.g., IOMMUs) must be incorporated into the CPU, the Platform Control Node (PCH), the System on Chip (SoC), the root complex, etc., to support each segment. Therefore, using segments to address deep hierarchies results in scaling the system to meet a worst-case system requirement, which is typically much more than needed for most systems, resulting in significant waste of platform resources. Furthermore, it can be difficult (and in some cases, virtually impossible) to create segments outside of a system's root complex.

[0042] In some implementations, a system may be provided to enable more efficient use of BDF space and address at least some of the exemplary problems above. This may enable the extension of PCIe, Thunderbolt, single-chip system fabrics (e.g., Intel On-Chip System Fabric (IOSF) and others), and other interconnects to very large topologies without requiring dedicated resources in the root complex, as would be the case with solutions relying exclusively on segments or other alternatives. Fig. Figure 6 illustrates an example assignment of bus numbers to buses within the system following an example PCIe BDF assignment. In this example, a system with two directly connected devices 605, 610 directly connected to a root complex 615 and two switch-based hierarchies (corresponding to switches 620, 625) is numbered with approximately the densest possible bus number assignments (as marked by circular labels, e.g., 650a-d, etc.). In deep hierarchies, the available bus numbers in a single BDF space can be quickly consumed. Furthermore, real systems allocate bus numbers much less efficiently, resulting in a sparse (or "wasted") allocation of the BDF space.

[0043] Another issue with use cases that support hot add / remove, such as Thunderbolt and, in some cases, PCIe-based storage, is that bus number assignments in the BDF space are "shuffled" to account for changes in hardware topology that occur in a running system. However, shuffling can be very difficult for system software to perform, as in typical cases, all PCI functions are then forced into a quiesced state in conjunction with shuffling to allow the BDF space to be renumbered by the system, followed by the re-enabling of PCI functions. However, this process can be quite slow and typically results in a system freeze, in the worst case for very long periods of time (e.g., long enough to be disruptive to running applications and easily visible to the end user).An improved system can also be provided to reduce the time required to apply a redesigned BDF space, so that the switching process can be performed in a span of hundredths of a millisecond or faster, and without explicitly placing PCI functions in quiesced states.

[0044] Finally, very large systems or systems with (proprietary) mechanisms for supporting multiple root complexes can be defined, requiring the use of segments. An improved system can also be applied in such use cases to provide facility management with a minimum of changes relative to what would be implemented using a single-root system. More specifically, an improved system can provide a mapping portal bridge (MPB), implemented using hardware (and / or software) logic from one or more facilities in a system to provide multiple views of a BDF space and remapping tables to create a "bridge" (which is the logical view of a root or switch port) to translate one view of one BDF space into another, in both directions across the bridge, effectively creating a virtual segment.

[0045] A mapping portal bridge (MPB) may be provided in some implementations at a port of a root node or switch to enable translation between primary and secondary BDF space. An MPB can be implemented in root ports and / or switch ports, with a consistent software model, and can be implemented recursively within a given topology, enabling a high degree of scalability. Furthermore, an MPB does not need to be tied to a specific usage model (e.g., it can be used alternatively in either or both Thunderbolt (TBT) and normal PCIe use cases). Furthermore, MPB implementations can support implementation flexibility and design price / performance tradeoffs. Furthermore, persistence within an existing PCIe system software stack can be maintained, among other exemplary benefits.

[0046] The MPB employs a mapping mechanism that allows the MPB to map all PCIe packets flowing between a primary BDF space and a secondary BDF space across the MPB. The primary BDF space refers to the view of the configuration address space seen on the primary side of the bridge (i.e., the side closer to the host CPU (e.g., the root complex)). The secondary BDF space may refer to the view of the configuration address space created and maintained for devices on the secondary side of the bridge (i.e., the side closer to the devices). In PCIe, the same BDF mappings used for device configuration can also be used to identify the source (and sometimes destination) of packets, report errors, and perform other functions.

[0047] Fig. 7 illustrates a block diagram 700 representing an implementation example of an MPB 705. The MPB 705 may include a pointer to and / or a (full or partial) local copy of two mapping tables, one for mapping the secondary address space to the primary address space (BDFsec→BDFpri) and another for mapping the primary address space to the secondary address space (BDFpri→BDFsec). In one example, the mapping tables may be stored in system memory 710, in which case the MPB 705 may read the tables from system memory (at 715) and / or maintain local copies (720, 725) of at least a portion of each mapping table (i.e., BDFsec→BDFpri and BDFpri→BDFsec) (e.g., to improve performance). In still other examples, the mapping tables BDFsec→BDFpri and BDFpri→BDFsec may be stored directly in the MPB 705 without maintaining copies in the system memory 710.The MPB 705 may further perform and manage translations between the primary BDF space and one or more BDFsec spaces. In the case of multiple BDFsec spaces, a single mapping table may be used, containing a column to map not only the BDFsec address but also the specific one of the BDFsec spaces to a BDFpri address. In other cases, separate mapping tables may be maintained for each BDFsec space. The MPB may be implemented in hardware of a switch, a node, or a port, such as a port of a root complex. The MPB 705 may also include control logic 730 to enable / disable the mapping functionality (e.g., to selectively configure the MPB 705 as an option on various ports of a switch or root complex, among other examples).

[0048] An MPB 705 may, in some cases, be configured to flexibly operate (e.g., using control logic 730) as either an MPB 705 (employing the primary / secondary BDF space mapping mechanism) or a conventional bridge (e.g., employing conventional PCIe BDF addressing). If system software wishes to enable an MPB 705, it may configure the MPB to provide a unique one-to-one mapping between primary (BDFpri) and secondary (BDFsec) BDF addresses. In other words, a single BDF on the primary side may correspond to a single BDF on the secondary side. Among other exemplary benefits, this constraint may ensure that the MPB does not track outstanding requests, as such tracking would add significant overhead to the MPB. In some implementations, multiple MPBs may be deployed in a system.For example, a separate MPB 705 may be provided for each BDFsec space. In such cases, the BDFsec assignments behind these multiple different MPBs may be allowed to reuse the same BDF values ​​(in their respective second BDF spaces) (which they likely will), provided these are mapped to unique values ​​in the BDFpri space.

[0049] System software can individually number the BDFsec space using any suitable or conventional algorithm. In some cases, before a specific BDF can be initially checked on the secondary side, the numberer configures the MPB to assign a "key" in BDFpri. This key can be used to generate and remap the configuration requirements to that specific BDF. The numberer must "understand" the BDFpri:BDFsec mapping during this initial numbering and can provide services to all modules using the BDF to perform this mapping during system operation.

[0050] Fig. Figure 8 is a simplified block diagram showing the example of Fig. 6, which has been modified by using MPB(s), allowing a BDFpri-space / BDFsec-space dichotomy. Fig. For example, Figure 8 shows how the BDFsec spaces can be assigned in a system with two MPBs (a first MPB used to implement a virtual segment (vSEG) A (805a) and a second MPB used to implement vSEG B (805b)). In this example, bus numbers 1 and 2 (at 806, 808) of the root complex 625 can be maintained in the BDFpri space (810) and assigned to the two directly connected devices 605, 610. Hierarchies of connections from buses 3-n can be handled in this example by BDFsec spaces (corresponding to vSEG A (805a) and vSEG B (805b)) and one or more corresponding MPBs. For example, buses 3-6 can be numbered to a BDFsec space vSEG A (805a), providing a virtual segment to the buses and devices connected to the root complex by buses 3-6.A second virtual segment may be provided by defining a second BDFsec space vSEG B (805b) that encompasses buses and devices connected to the root complex by buses 7-n. Each BDFsec space may be assigned BDF addresses (and bus numbering) within the respective second space according to any suitable scheme, including schemes that assign these addresses inefficiently. Indeed, different BDFsec spaces may assign addresses differently based on the endpoint types or routing devices connected to the corresponding buses. Unlike the BDFsec spaces, the BDFpri space (i.e., the root complex's view of the configuration space) can be optimized to enable and control a compact and efficient allocation of bus addresses within the space (as in the example of . Fig. 6 illustrated).

[0051] Each BDFsec address in vSEG A and vSEG B can map to exactly one BDF address in the BDFpri space (e.g. according to the Fig. ). As an example, a first device in vSEG A can be assigned the BDF “1:0:0” in the vSEG A BDFsec space, which is mapped to the primary BDF “4:0:0” (as in the Fig. shown), among other examples. Different devices in other BDFsec spaces of the system (e.g., vSEG B) can assign the same BDFsec values ​​as those assigned in other BDFsec spaces (e.g., vSEG A). For example, a second device in vSEG B can also be assigned BDF "1:0:0", but in the BDFsec of vSEG B. However, the second device will be mapped to a different BDF in the system's BDFpri (i.e., BDF "7:0:1", as in the Fig. shown) and so on.

[0052] As noted above, in some implementations, the mapping(s) between BDFpri and BDFsec spaces may be achieved through mapping tables residing in system memory. Different packet types may be mapped differently (i.e., to mediate between BDFsec and BDFpri spaces). For requests in either direction, for example, the appropriate requestor ID may be remapped (e.g., according to the appropriate mapping table). Message requests forwarded by configuration and ID may be forwarded through ID bus / facility / function number fields. Completions in either direction may be forwarded by the requestor and completer IDs, among other examples.

[0053] The MPB's mapping hardware can access map tables located in system memory, with optional caching within the MPB. In some implementations, a single map table may be used for traffic in both directions, with the MPB having logic to determine the mapping in the forward (e.g., downstream) and reverse (e.g., upstream) directions (e.g., through reverse lookups). In other implementations, it may be more efficient to provide two separate map tables per MPB, one for the forward direction and the other for the reverse direction. This may, in some cases, be less expensive than providing MPB hardware to perform a reverse lookup in one of the two directions.

[0054] An MPB on the primary side (e.g., the port closest to the root complex) may be responsible for mapping a subset of the bus numbers in the BDFpri space to a corresponding BDFsec space. Accordingly, the range of bus numbers in the BDFpri space assigned to the MPB may be restricted to the range indicated by [secondary bus number to child bus number], since in the BDFpri space, only packets in this range are routed to that particular MPB. Therefore, the BDFsec:BDFpri mapping table may involve a translation table large enough to cover the secondary to child range of bus numbers, but not necessarily larger. In some embodiments, a default table with 64K entries may be provided for simplicity in implementation.Indeed, to map BDFpri to BDFsec, a translation table with 64K entries can be provided to make the full BDF space available on the secondary side, but this may be restricted in some alternatives to reduce hardware / memory requirements.

[0055] Mapping tables can be maintained by system software that directs data communication on PCIe (or other interconnects that implement these functions). For example, in implementations that employ two separate upstream and downstream tables, the two tables can be maintained by system software. The system software can ensure consistency between the tables so that a mapping from BDFx → BDFy → BDFx' always yields the result x = x', among other exemplary considerations.

[0056] In some implementations, an MPB may implement a cache to store at least a portion of the mapping tables locally at the MPB. System software may assume that MPBs cache translations based on the mapping tables and may support cache management by providing the necessary cache management information to the hardware. It may be desirable to provide mechanisms for system software to ensure that the MPB cache is only updated under system software control. Furthermore, a mechanism may be defined, such as a specific register(s) in the MPB memory-mapped space (MMIO space) to provide pointers to the mapping tables in system memory.Registers can also be used for cache management, allowing system software to enable / disable caching, invalidate the MPB cache, etc. Alternatively, in some implementations, the tables can be implemented directly in the MPB without maintaining copies in system memory. In this case, the system software directly updates the tables at the MPB as needed.

[0057] An additional advantage of the MPB mapping table mechanism is that system software can update the mapping tables atomically, for example, by creating new mapping tables and then "immediately" invalidating the MPB cache and redirecting the MPBs from the old to the new tables. This can be achieved by defining the control register mechanism so that the MPB hardware must sample the register settings when indicated by the system software and then continue to operate with the sampled settings until instructed to sample again. This re-sampling can be performed by MPB hardware in such a way that the transition from the old to the new sampling takes effect atomically. By also providing a mechanism for system software to temporarily block traffic through the MPB (e.g.,to "pause" traffic at the MPB to allow changes to the mapping tables), it becomes much more attractive to allow the system software to modify ("shuffle") the bus number assignments in a running system, since the amount of time required to switch mapping tables can be kept very short. Alternatively, if the mapping tables are maintained directly in the MPB, a mechanism such as double buffering can be employed that allows the MPB to operate using a copy of the tables while an alternative set is updated by the system software, and thereafter, the MPB transitions to operating with the updated tables (e.g., while replacing local tables with the updated versions) under the direction of the system software.

[0058] Now on Fig. 9, a representation of one embodiment of the register fields and bits for use in implementing the hardware / software interface for an example MPB is shown. More specifically, in this particular example, an extended PCIe discovery / management capability may be defined in an MPB system. The extended capability may include fields such as: an outstanding request (OR) field, which reflects the MPB count of unposted (NP) requests in both directions (although the unposted requests would not be tracked accurately or individually); an MPB enable bit (E) to indicate whether MPB functionality is enabled on a bridge supporting MPB (where the address registers are to be scanned by the MPB when the E bit is set (0 → 1)); and a trigger map table update (TR) field, among other examples.In some cases, additional fields can be used in conjunction with a window mechanism to generate "sniff" configRequests behind the MPB, such as a status bit so that the system software can understand when ConfigWrites are complete. In some cases, the window mechanism may only support one ConfigRequest at a time (e.g., no requests in the pipeline). In still further examples, the capability structure may provide values ​​to describe the type of local translation tables maintained at an MPB (e.g., to indicate the size of the table if they are not at full size, etc.), among other examples.

[0059] The primary / secondary BDF mapping and MPBs can be used in conjunction with segments in some implementations. As noted above, MPBs can be used to implement virtual segments (vSEGs) to at least partially replace and reduce the number of segments in a system design. In cases where segments are to be accommodated, or when building a system with multiple roots (e.g., using a proprietary load / store fabric), MPBs can be extended to support mapping between different segments and between parts of a hierarchy that do not support segments. For example, in a system where BDFpri is extended to support segments, this effectively becomes the BDFpri space of a segment (SBDFpri space), since the segment acts as a "prefix" to increase the number of available bus numbers.In such a system, a mechanism such as a TLP prefix could be used to identify specific segments. However, since many devices do not yet support a segment marking mechanism, the MPB mapping mechanism can be used with extensions to support a mapping of a BDFsec space that does not support segment marking to an SBDFpri space that does, among other examples.

[0060] Sampling may be incorporated by MPBs in some implementations. Here, "sampling" may refer to reading the first data word (DW) of a function's configuration space to see if there is a valid vendor / device ID. However, using the in-memory tables during scanning may involve repeated updates, which may be particularly problematic if the scanning occurs at runtime due to repeated updating of the mapping tables. To avoid this, a mechanism may be provided to generate configuration requests through the MPB for scanning. This mechanism may not be intended for use as the normal configuration generation path, but may instead be configured for scanning (and in some cases, as a "failsafe"). In some examples, the mechanism may include a windowing mechanism in the extended MPB capability (e.g.,Based on the CFC / CF8 configuration access mechanism defined for PCI, extended with support for a 4K configuration space. System software can use this mechanism to discover a function, for example, by scanning. After discovering a function, the system software can then update the mapping tables to provide a translation for the function and proceed with further numbering / configuration through the MPB's table-based translation mechanism, among other example functions.

[0061] It should be noted that the devices, methods, and systems described above can be implemented in any electronic device or system as mentioned above. As specific illustrations, the figures below provide exemplary systems for implementing the invention as described herein. While the systems are described in more detail below, a number of different interconnections are disclosed, described, and reconsidered from the above discussion. And, as will be appreciated, the advances described above can be applied to any of these interconnections, structures, or architectures.

[0062] Now on Fig. Referring to Figure 10, one embodiment of a block diagram for a computing system including a multi-core processor is shown. A processor 1000 includes any processor or processing device, such as a microprocessor, an embedded processor, a digital signal processor (DSP), a network processor, a portable processor, an application processor, a coprocessor, a system on chip (SOC), or other device to execute code. The processor 1000, in one embodiment, includes at least two cores—cores 1001 and 1002—which may include asymmetric cores or symmetric cores (the illustrated embodiment). However, the processor 1000 may include any number of processing elements, which may be symmetric or asymmetric.

[0063] In one embodiment, a processing element refers to hardware or logic to support a software thread. Examples of hardware processing elements include: a thread unit, a thread slot, a thread, a process unit, a context, a context unit, a logical processor, a hardware thread, a core, and / or any other element that can maintain state for a processor, such as execution state or architectural state. In other words, in one embodiment, a processing element refers to any hardware that can be independently associated with code, such as a software thread, an operating system, an application, or other code. A physical processor (or processor socket) typically refers to an integrated circuit, which may contain any number of other processing elements, such as cores or hardware threads.

[0064] A core often refers to logic residing on an integrated circuit capable of maintaining independent architectural state, where each independently maintained architectural state is associated with at least some dedicated execution resources. In contrast to cores, a hardware thread typically refers to any logic residing on an integrated circuit capable of maintaining independent architectural state, where the independently maintained architectural states share access to execution resources. As can be seen, the boundary between the nomenclature of a hardware thread and a core overlaps when certain resources are shared and others are assigned to an architectural state.However, a core and a hardware thread are often viewed by an operating system as individual logical processors, and the operating system can schedule operations on each logical processor individually.

[0065] The physical processor 1000, as in Fig. 10, includes two cores—cores 1001 and 1002. Here, cores 1001 and 1002 are considered symmetric cores, that is, cores with the same configurations, functional units, and / or logic. In another embodiment, core 1001 includes an out-of-order processor core, while core 1002 includes an in-order processor core. However, cores 1001 and 1002 may be individually selected from any core type, such as a native core, a software-managed core, a core adapted to execute a native instruction set architecture (ISA), a core adapted to execute a translated instruction set architecture (ISA), a co-designed core, or any other known core. In a heterogeneous core environment (i.e., asymmetric cores), a form of translation, such as binary translation, can be used to schedule or execute code on one or both cores.To continue the discussion, the functional units illustrated in core 1001 are discussed in more detail below, since the units operate in a similar manner in core 1002 in the illustrated embodiment.

[0066] As shown, core 1001 includes two hardware threads 1001a and 1001b, which may also be referred to as hardware thread slots 1001a and 1001b. Therefore, in one embodiment, software entities such as an operating system may view processor 1000 as four separate processors, i.e., four logical processors or processing elements capable of executing four software threads simultaneously. As mentioned above, a first thread is associated with architectural state registers 1001a, a second thread is associated with architectural state registers 1001b, a third thread may be associated with architectural state registers 1002a, and a fourth thread may be associated with architectural state registers 1002b. Here, each of the architectural state registers (1001a, 1001b, 1002a, and 1002b) may be referred to as processing elements, thread slots, or thread units, as described above.As illustrated, the architectural state register 1001a is replicated in the architectural state register 1001b, so individual architectural states / contexts can be stored for the logical processor 1001a and the logical processor 1001b. In the core 1001, other minor resources, such as instruction pointers and renaming logic in the allocation and renaming block 1030, can also be replicated for the threads 1001a and 1001b. Some resources, such as reorder buffers in a reorder / retirement unit 1035, ILTB 1020, load / store buffers, and queues, can be shared through partitioning. Other resources such as internal general purpose registers, page table base register(s), low level data cache and data TLB 1015, execution unit(s) 1040, and portions of out-of-order unit 1035 may be fully shared.

[0067] The processor 1000 often contains other resources that are fully shared, shared by partitioning, or dedicated by / to processing elements. In Fig. 10 illustrates one embodiment of a purely exemplary processor with illustrative logic units / resources of a processor. It should be noted that a processor may include or omit any of these functional units, as well as include any other functional units, logic, or firmware not shown. As illustrated, core 1001 includes a simplified, representative out-of-order (OOO) processor core. However, in other embodiments, an in-order processor may be employed. The OOO core includes a branch target buffer 1020 to predict branches to be executed / taken and an instruction translation buffer (I-TLB) 1020 to store address translation entries for instructions.

[0068] Core 1001 further includes decode module 1025 coupled to fetch unit 1020 to decode fetched elements. Fetch logic, in one embodiment, includes individual schedulers associated with thread slots 1001a and 1001b, respectively. Typically, core 1001 is associated with a first ISA that defines / specifies instructions executable on processor 1000. Often, machine code instructions that are part of the first ISA include a portion of the instruction (referred to as an opcode) that references / specifies an instruction or operation to be performed. Decode logic 1025 includes circuitry that recognizes these instructions from their opcodes and forwards the decoded instructions down the pipeline for processing as defined by the first ISA.As discussed in more detail below, in one embodiment, decoders 1025 include logic constructed or adapted to recognize specific instructions, such as transactional instructions. As a result of the recognition by decoders 1025, architecture or core 1001 takes certain predefined actions to perform tasks associated with the respective instruction. It should be noted that any of the tasks, blocks, operations, and methods described herein may be performed in response to a single or multiple instructions; some of which may be new or old instructions. Note that in one embodiment, decoders 1026 recognize the same ISA (or a subset thereof). Alternatively, in a heterogeneous core environment, decoders 1026 recognize a second ISA (either a subset of the first ISA or a different ISA).

[0069] In one example, allocation and renaming block 1030 includes an allocation unit to reserve resources, such as register files, to store instruction processing results. However, threads 1001a and 1001b may be capable of out-of-order execution, with allocation and renaming block 1030 also reserving other resources, such as reorder buffers, to track instruction results. Unit 1030 may also include a register renaming unit to rename program / instruction reference registers to other registers internal to processor 1000. Reorder / retire unit 1035 includes components, such as the aforementioned reorder buffers, load buffers, and store buffers, to support out-of-order execution and later in-order retirement of instructions that are executed out of order.

[0070] In one embodiment, the scheduling and execution unit(s) 1040 includes a scheduling unit for scheduling instructions / operations onto execution units. For example, a floating-point instruction is scheduled at a port of an execution unit that has an available floating-point execution unit. Register files associated with these execution units are also included to store the results of information instruction processing. Example execution units include a floating-point execution unit, an integer execution unit, a jump execution unit, a load execution unit, a store execution unit, and other known execution units.

[0071] A low-level data cache and a data translation buffer (D-TLB) 1050 are coupled to the execution unit(s) 1040. The data cache is to store recently used / operated elements, such as data operands, which may be held in memory coherence states. The D-TLB is to store new virtual / linear-to-physical address translations. As a specific example, a processor may include a page table structure to partition physical memory into a plurality of virtual pages.

[0072] Here, cores 1001 and 1002 share access to a higher-level or more outlying cache, such as a second-level cache associated with on-chip interface 1010. Note that the term higher-level or more outlying refers to increasing cache levels or levels located farther away from the execution unit(s). In one embodiment, a higher-level cache is a last-level data cache—the last cache in the memory hierarchy on processor 1000—such as a second- or third-level data cache. However, a higher-level cache is not so limited, as it may be associated with or include an instruction cache.A trace cache—a type of instruction cache—may instead be coupled after decoder 1025 to store recently decoded traces. Here, an instruction may refer to a macroinstruction (i.e., a general instruction recognized by the decoders) that can be decoded into a number of microinstructions (microoperations).

[0073] In the configuration shown, the processor 1000 also includes an on-chip interface module 1010. Historically, a memory controller, described in more detail below, was included in a computing system external to the processor 1000. In this scenario, the on-chip interface 1010 has to communicate with devices external to the processor 1000, such as the system memory 1075, a chipset (which often includes a memory controller node to interface with the memory 1075 and an I / O controller node to interface with peripherals), a memory controller node, a northbridge, or another integrated circuit. And in this scenario, the bus 1005 can be any known connection, such as a multi-drop bus, a point-to-point connection, a serial connection, a parallel bus, a coherent (e.g.,with cache coherent) bus, a layered protocol architecture, a differential bus and a GTL bus.

[0074] Memory 1075 may be dedicated to processor 1000 or shared with other devices in a system. Common examples of memory 1075 types include DRAM, SRAM, non-volatile memory (NV RAM), and other known memory devices. Note that device 1080 may include a graphics accelerator, a processor or card coupled to a memory control node, a data store coupled to an I / O control node, a wireless transceiver, a flash device, an audio controller, a network controller, or other known device.

[0075] Recently, however, each of these devices may be included on processor 1000 as more logic and devices are integrated onto a single chip, such as a SOC. For example, in one embodiment, a memory control node is located on the same package and / or chip with processor 1000. Here, a portion of the core (an in-core portion) 1010 includes one or more controllers for interfacing with other devices, such as memory 1075 or a graphics device 1080. The configuration including interconnect and controllers for interfacing with such devices is often referred to as an in-core (or coreless) configuration. As one example, on-chip interface 1010 includes a ring interconnect for on-chip communication and a high-speed point-to-point serial link 1005 for off-chip communication.In the SOC environment, even more devices, such as the network interface, coprocessors, memory 1075, graphics processor 1080, and any other known computing devices / interfaces may be integrated onto a single chip or integrated circuit to provide a small form factor with high functionality and low power consumption.

[0076] In one embodiment, processor 1000 is capable of executing compiler, optimization, and / or translation code 1077 to compile, translate, and / or optimize application code 1076 to support or interface with the apparatus and methods described herein. A compiler often includes a program or set of programs to translate source code into target code. Typically, compilation of program / application code with a compiler is performed in multiple phases and passes to convert high-level programming language code into low-level machine or assembly language code. However, single-pass compilers may still be used for simple compilation.A compiler can use any known compilation techniques and perform any known compiler operations, such as lexical analysis, preprocessing, parsing, semantic analysis, code generation, code transformation, and code optimization.

[0077] Larger compilers often contain multiple phases, but most commonly these phases are contained in two general phases: (1) a front-end, i.e., generally where syntactic processing, semantic processing, and some transformation / optimization operations may take place, and (2) a back-end, i.e., generally where analysis, transformations, optimizations, and code generation take place. Some compilers refer to a middle, illustrating a blurring of the line between a front-end and a back-end of a compiler. As a result, a reference to an insertion, association, generation, or other operation of a compiler may take place in any of the aforementioned phases or passes, as well as in any other known phases or passes of a compiler. As an illustrative example, a compiler might insert operations, calls, functions, etc.in one or more compilation phases, such as inserting calls / operations in a front-end compilation phase and subsequently transforming the calls / operations into lower-level code during a transformation phase. It should be noted that during dynamic compilation, compiler code or dynamic optimization code can insert such operations / calls as well as optimize the code for execution at runtime. As a specific illustrative example, binary code (already compiled code) can be dynamically optimized at runtime. Here, the program code can include the dynamic optimization code, the binary code, or a combination thereof.

[0078] Similar to a compiler, a translation unit, such as a binary translation unit, translates code either statically or dynamically to optimize and / or translate code. Therefore, a reference to an execution of code, application code, program code, or other software environment may mean: (1) either dynamic or static execution of a compiler program orof compiler programs, an optimizing code optimizer, or a translation unit to compile program code, to maintain software structures, to perform other operations to optimize code, or to translate code; (2) an execution of main program code that contains operations / calls such as application code that have been optimized / compiled; (3) an execution of other program code, such as libraries, associated with the main program code to maintain software structures, to perform other software-related operations, or to optimize code; or (4) a combination thereof.

[0079] Now on Fig. Referring to Figure 11, a block diagram of a second system 1100 according to an embodiment of the present invention is shown. As shown in Fig. As shown in Figure 11, the multiprocessor system 1100 is a point-to-point interconnect system and includes a first processor 1170 and a second processor 1180 coupled via a point-to-point interconnect 1150. Each of the processors 1170 and 1180 may be a version of a processor. In one embodiment, 1152 and 1154 are part of a serial coherent point-to-point interconnect fabric, such as Intel's Quick Path Interconnect (QPI) architecture. As a result, the invention may be implemented in the QPI architecture.

[0080] While it is shown with only two processors 1170, 1180, it should be understood that the scope of the present invention is not so limited. In other embodiments, one or more additional processors may be present in a given processor.

[0081] Processors 1170 and 1180 are shown as including integrated memory control units 1172 and 1182, respectively. Processor 1170 also includes point-to-point (PP) interfaces 1176 and 1178 as part of its bus control units; similarly, the second processor 1180 includes PP interfaces 1186 and 1188. Processors 1170, 1180 may exchange information via a point-to-point (PP) interface 1150 using PP interface circuits 1178, 1188. As shown in Fig. 11, the IMCs 1172 and 1182 couple the processors to respective memories, namely a memory 1132 and a memory 1134, which may be parts of a main memory locally attached to the respective processors.

[0082] The processors 1170, 1180 each exchange information with a chipset 1190 via individual PP interfaces 1152, 1154 using point-to-point interface circuits 1176, 1194, 1186, 1198. The chipset 1190 also exchanges information with a high-performance graphics circuit 1138 via an interface circuit 1192 along a high-performance graphics interconnect 1139.

[0083] A shared cache (not shown) may be included in either processor or external to both processors but connected to the processors via a PP interconnect so that the local cache information of either or both processors can be stored in the shared cache when one processor is placed in a low power mode.

[0084] Chipset 1190 may be coupled to a first bus 1116 via an interface 1196. In one embodiment, first bus 1116 may be a Peripheral Component Interconnect (PCI) bus or a bus such as a PCI Express bus or other third-generation I / O interconnect bus, although the scope of the present invention is not limited thereby.

[0085] As in Fig. 11, various I / O devices 1114 are coupled to the first bus 1116 along with a bus bridge 1118 that couples the first bus 1116 to a second bus 1120. In one embodiment, the second bus 1120 includes a low-pin count (LPC) bus. Various devices are coupled to a second bus 1120, including, for example, a keyboard and / or mouse 1122, communication devices 1127, and a storage unit 1128, such as a disk drive or other mass storage device, which in one embodiment often includes instructions / code and data 1130. Additionally, an audio I / O 1124 is shown coupled to the second bus 1120. It should be noted that other architectures are possible, with the included components and interconnect architectures varying. For example, instead of the point-to-point architecture of Fig. 11 implement a multipoint bus or other such architecture.

[0086] While the present invention has been described with reference to a limited number of embodiments, numerous modifications and variations thereof will be apparent to those skilled in the art. It is intended that the appended claims cover all such modifications and variations that fall within the true spirit and scope of this invention.

[0087] A design can go through several stages, from conception to simulation to manufacturing. Data representing a design can represent the design in a number of ways. First, the hardware can be represented using a hardware description language or other functional description language, as is useful in simulations. Additionally, a circuit-level model with logic and / or transistor gates can be created at some stage of the design process. Furthermore, most designs reach a level of data representing the physical placement of various devices in the hardware model at some stage.In the case where conventional semiconductor manufacturing techniques are used, the data representing the hardware model may be the data indicating the presence or absence of various features on various mask layers for masks used to fabricate the integrated circuit. In any representation of the design, the data may be stored in any form of machine-readable medium. A random access memory or a magnetic or optical storage such as a disk may be the machine-readable medium for storing information sent via an optical or electrical wave that is modulated or otherwise generated to transmit such information. When an electrical carrier wave is transmitted displaying or carrying the code or design, to the extent that any copying, buffering, or retransmission of the electrical signal is performed, a new copy is made.Therefore, a communications provider or a network provider may store an item, such as information encoded into a carrier wave and embodying techniques of embodiments of the present invention, at least temporarily on a tangible, machine-readable medium.

[0088] A module, as used herein, refers to any combination of hardware, software, and / or firmware. As an example, a module includes hardware, such as a microcontroller, associated with a non-transitory medium to store code adapted to be executed by the microcontroller. Therefore, in one embodiment, reference to a module refers to the hardware specifically configured to recognize and / or execute the code to be held on a non-transitory medium. Further, in another embodiment, use of a module refers to the non-transitory medium containing the code specifically adapted to be executed by the microcontroller to perform predetermined operations.And, as can be inferred, in yet another embodiment, the term module (in this example) may refer to the combination of the microcontroller and the non-transitory medium. Often, module boundaries illustrated as separate vary widely and may overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while possibly retaining some independent hardware, software, or firmware. In one embodiment, the use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.

[0089] The use of the phrase "to" or "configured to," in one embodiment, refers to arranging, assembling, manufacturing, offering for sale, importing, and / or constructing a device, hardware, logic, or element to perform an intended or predetermined task. In this example, a device or element thereof that is not operating is nevertheless "configured" to perform an intended task if it is constructed, coupled, and / or connected to perform that intended task. As a purely illustrative example, a logic gate may provide a 0 or a 1 during operation. However, a logic gate "configured" to provide an enable signal to a clock does not include every possible logic gate that can provide a 1 or a 0.Instead, the logic gate is one that is coupled in some way so that during operation, the 1 or 0 output is intended to activate the clock. It should be noted again that the use of the term "configured to" does not require any operation, but instead focuses on the latent state of a device, hardware, and / or element, where the device, hardware, and / or element is designed to perform a specific task in the latent state when the device, hardware, and / or element is operating.

[0090] Furthermore, the use of the terms "capable of" and / or "operative to" in one embodiment refers to a device, logic, hardware, and / or element that is constructed to enable use of the device, logic, hardware, and / or element in a predetermined manner. As above, it should be noted that the use of "to," "capable of," or "operative to" in one embodiment refers to the latent state of a device, logic, hardware, and / or element, where the device, logic, hardware, and / or element is not operational but is constructed to enable use of a device in a predetermined manner.

[0091] A value, as used herein, includes any known representation of a digit, a state, a logical state, or a binary logical state. Often, the use of logic levels, logic values, or logical values ​​is also referred to as 1s and 0s, which simply represent binary logical states. For example, a 1 denotes a high logic level and a 0 denotes a low logic level. In one embodiment, a memory cell, such as a transistor or a flash cell, may be capable of holding a single logical value or multiple logical values. However, other representations of values ​​in computer systems have been used. For example, the decimal number ten can also be represented as a binary value of 1010 and a hexadecimal letter A. Therefore, a value includes any representation of information that can be held in a computer system.

[0092] Furthermore, states can be represented by values ​​or portions of values. For example, a first value, such as a logical one, can represent a default or initial state, while a second value, such as a logical zero, can represent a non-default state. Furthermore, in one embodiment, the terms reset and set refer to a default and an updated value, respectively. For example, a default value may include a high logical value, i.e., reset, while an updated value may include a low logical value, i.e., set. It should be noted that any combination of values ​​can be employed to represent any number of states.

[0093] The embodiments of methods, hardware, software, firmware, or code set forth above may be implemented via instructions or code stored on a machine-accessible, machine-readable, computer-accessible, or computer-readable medium and executable by a processing element. A non-transitory machine-accessible / readable medium includes any mechanism that provides (i.e., stores and / or transmits) information in a form readable by a machine, such as a computer or electronic system.A non-transitory machine-accessible medium includes, for example, random access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; a magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustic storage devices; other forms of storage devices for holding information received from transitory (relayed) signals (e.g., carrier waves, infrared signals, digital signals); etc., which are to be distinguished from the non-transitory media that can receive information therefrom.

[0094] Instructions used to perform embodiments of the invention may be stored in a memory within the system, such as DRAM, cache, flash memory, or other memory. Furthermore, the instructions may be distributed over a network or by other computer-readable media. Therefore, a machine-readable medium may include any mechanism for storing or transmitting information in a format supported by a machine (e.g., a hard disk).a computer) readable form, but is not limited to floppy disks, optical disks, read-only compact discs (CD-ROMs) and magneto-optical disks, read-only random access memory (ROMs), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory, or any tangible machine-readable memory used in the transmission of information over the Internet via electrical, optical, acoustic, or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, the computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form suitable for being read or understood by a machine (e.g.,a computer).

[0095] The following examples relate to embodiments consistent with this description. One or more embodiments may provide a method, system, machine-readable storage medium, and apparatus including bridge logic to receive a request from a device, wherein the request references an address of a secondary address space, the secondary address space corresponds to a subset of addresses in a configuration address space of a system, and the secondary address space corresponds to a first view of the configuration address space. The bridge logic may further use a mapping table to translate the address to a corresponding address in the configuration address space, where addresses of the configuration address space correspond to a different second view of the configuration address space.

[0096] In one example, the second view of the configuration address space contains a view of a root complex of the configuration address space.

[0097] In one example, the first view of the configuration address space contains a view of the configuration address space setup.

[0098] In one example, the second address space includes a particular one of a plurality of non-overlapping secondary address spaces, each mapping to a corresponding portion of the configuration address space.

[0099] In one example, a particular address is contained in two or more of the plurality of secondary address spaces.

[0100] In one example, the configuration address space contains a Peripheral Component Interconnect (PCI)-based configuration address space.

[0101] In one example, an address in the configuration address space contains each of a set of bus / device / function numbers.

[0102] In one example, each address in the secondary address space maps to exactly one respective address in the configuration address space.

[0103] In one example, the configuration address space also contains a subset of addresses reserved for hot-swapping.

[0104] In one example, addresses in the configuration address space are individually numbered to maximize the use of available bus addresses within the configuration address space.

[0105] In one example, addresses in the configuration address space are individually numbered using a first technique and addresses in the secondary address space are individually numbered using a different second technique.

[0106] In one example, the second technique is agnostic with respect to maximizing available bus addresses within the second address space.

[0107] In one example, the mapping table contains two mapping tables, one for upstream translations and the second for downstream translations.

[0108] In one example, the mapping table is stored in system memory, a pointer in local memory points to the mapping table, and the bridge logic accesses the mapping table using the pointer.

[0109] In one example, memory may be provided (e.g., at the device) to store at least a portion of the mapping table locally for access by the bridge logic.

[0110] In one example, the bridge logic is further to identify an update to the mapping table, invalidate a local copy of at least a portion of the mapping table, and replace the local copy with a new copy of at least a portion of the updated mapping table.

[0111] One or more embodiments may provide a method, system, apparatus, and machine-readable storage medium storing instructions executable to manage mapping tables for access by a mapping portal bridge to translate configuration address space addresses between a primary address domain and a secondary address domain for a system. The primary address domain may include a view of the configuration address space as seen upstream of the mapping portal bridge, and the secondary address domain may be a view of the configuration address space as seen downstream of the mapping portal bridge. Changes to the system may be detected, and the mapping tables updated based on the change.

[0112] In one example, mapping tables may be accessed by a different second mapping portal bridge, and mapping tables for the second mapping portal bridge may define a mapping between the primary address domain and a secondary address domain.

[0113] In one example, the first secondary address domain corresponds to a first Peripheral Component Interconnect Express (PCIe) virtual segment and the second secondary address domain corresponds to a second PCIe virtual segment.

[0114] In one example, a read request is received by the mapping portal bridge for a particular request, and a response to the read request may be returned to the mapping portal bridge.

[0115] One or more embodiments may provide a system including a root complex and a mapping portal bridge coupled to a device and receiving data exchanged between the device and the root complex. The mapping portal bridge may receive a request from a device referencing an address of a secondary address space corresponding to a subset of addresses in a configuration address space of a system and corresponding to a first view of the configuration address space. The mapping portal bridge may use a mapping table to translate the address into a corresponding address in the configuration address space, where addresses of the configuration address space correspond to another second view of the configuration address space.

[0116] In one example, the second view is a view of the root complex.

[0117] In one example, the system further includes system memory to store the mapping table, wherein the mapping portal bridge is to access the system memory to use the mapping table.

[0118] In one example, the system further includes system software to manage updates to the mapping table.

[0119] In one example, the system further includes the facility.

[0120] In one example, the data is exchanged via either a PCIe or a Thunderbolt compatible link.

[0121] If you Fig. 17B, ​​a device (e.g., 1705) may, in some cases, instead of determining the coupling state of another endpoint device (as in Fig. 17A), use remote receive detection logic to detect and determine the coupling used by a link extender 1715 between two endpoints (e.g., 1705, 1710). Link extenders 1715 may include such examples as repeaters, retimers, redrivers, and the link. In the particular example of Fig. 17B, ​​for example, a redriver 1715 may be coupled to an endpoint 1710, and the endpoint 1710 may detect whether the redriver 1715 employs a DC or AC coupling. As in previous examples, the endpoint (e.g., 1710 (and / or 1705)) may configure its transmitter and receiver to operate with the detected coupling used by the redriver 1715 (i.e., AC or DC) based on detecting the coupling state of the redriver 1715.

[0122] Reference throughout this specification to "a single embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least one embodiment of the present invention. Therefore, the appearances of the phrases "in a single embodiment" or "in an embodiment" in various places throughout this specification do not necessarily all refer to the same embodiment. Further, the individual features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0123] In the foregoing specification, a detailed description has been given with reference to specific exemplary embodiments. However, it will be apparent that various modifications and changes may be made therein without departing from the general spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be considered in an illustrative rather than a restrictive sense. Furthermore, the foregoing use of an embodiment and other exemplary language does not necessarily refer to the same embodiment or example, but may refer to different and various embodiments, and possibly the same embodiment.

Claims

[1] Device comprising: Bridge logic to: to receive a request from a device, wherein the request refers to an address of a secondary address space, the secondary address space corresponds to a subset of addresses in a configuration address space of a system, the secondary address space corresponds to a first view of the configuration address space, addresses in the secondary address space each comprise a corresponding Peripheral Component Interconnect (PCI)-based Bus / Device / Function (BDF) number, the secondary address space comprises a particular one of a plurality of non-overlapping secondary address spaces, each of the plurality of secondary address spaces maps to a corresponding portion of the configuration address space, and a particular BDF number is used in the particular secondary address space and in another one of the plurality of secondary address spaces; and to use a mapping table to translate the address of the particular secondary address space into a corresponding address in the configuration address space, wherein addresses of the configuration address space correspond to a different second view of the configuration address space, addresses of the configuration address space each comprise a corresponding PCI-based BDF number, and the mapping table maps BDF numbers in the secondary address space to BDF numbers in the configuration address space. [2] The apparatus of claim 1, wherein the second view of the configuration address space comprises a view of a root complex of the configuration address space. [3] The apparatus of claim 2, wherein the first view of the configuration address space comprises a view of the device of the configuration address space. [4] The apparatus of claim 1, wherein the configuration address space comprises a Peripheral Component Interconnect (PCI)-based configuration address space. [5] The apparatus of claim 1, wherein each address in the secondary address space maps to exactly one respective address in the configuration address space. [6] The apparatus of claim 1, wherein the configuration address space further comprises a subset of addresses reserved for hot installation. [7] The apparatus of claim 1, wherein addresses in the configuration address space are individually numbered to maximize utilization of available bus addresses within the configuration address space. [8] The apparatus of claim 7, wherein addresses in the configuration address space are individually numbered using a first technique and addresses in the secondary address space are individually numbered using a different second technique. [9] The apparatus of claim 8, wherein the second technique is agnostic to maximizing available bus addresses within the second address space. [10] The apparatus of claim 1, wherein the mapping table comprises two mapping tables, one for upstream translations, the second for downstream translations. [11] The apparatus of claim 1, wherein the mapping table is stored in system memory, a pointer in local memory points to the mapping table, and the bridge logic accesses the mapping table using the pointer. [12] The apparatus of claim 1, further comprising memory to store at least a portion of the mapping table locally for access by the bridge logic. [13] The apparatus of claim 1, wherein the bridge logic further comprises: has to identify an update of the mapping table; invalidate a local copy of at least one section of the mapping table; and the local copy must be replaced with a new copy of at least one section of the updated mapping table. [14] The apparatus of claim 13, wherein the local copy is replaced by the new copy during a runtime of the system. [15] The apparatus of claim 1, further comprising an extended capability structure comprising a table update field, a pending request field, a mapping enable field, one or more fields for use in test configuration requests, and a mapping table base address field. [16] System comprising: a root complex; a mapping portal bridge coupled to a device and receiving data exchanged between the device and the root complex, the mapping portal bridge comprising logic to: to receive a request from a device, the request referencing an address of a secondary address space, the secondary address space corresponding to a subset of addresses in a configuration address space of a system, the secondary address space corresponding to a first view of the configuration address space, addresses in the secondary address space each comprising a corresponding Peripheral Component Interconnect (PCI)-based Bus / Device / Function (BDF) number, the secondary address space comprising a particular one of a plurality of non-overlapping secondary address spaces, each of the plurality of secondary address spaces mapping to a corresponding portion of the configuration address space, and a particular BDF number being used in the particular secondary address space and in another one of the plurality of secondary address spaces; and to use a mapping table to translate the address of the particular secondary address space into a corresponding address in the configuration address space, wherein addresses of the configuration address space correspond to a different second view of the configuration address space, addresses of the configuration address space each comprise a corresponding PCI-based BDF number, and the mapping table maps BDF numbers in the secondary address space to BDF numbers in the configuration address space. [17] The system of claim 16, wherein the second view comprises a view of the root complex. [18] The system of claim 16, further comprising system memory to store the mapping table, wherein the mapping portal bridge is to access the system memory to use the mapping table. [19] The system of claim 16, further comprising system software to manage updates to the mapping table. [20] The system of claim 16, further comprising the device. [21] The system of claim 16, wherein the data is exchanged via either a PCIe or a Thunderbolt compatible link. [22] System comprising: Means for receiving a request from a device, the request referencing an address of a secondary address space, the secondary address space corresponding to a subset of addresses in a configuration address space of a system, the secondary address space corresponding to a first view of the configuration address space, addresses in the secondary address space each comprising a corresponding Peripheral Component Interconnect (PCI)-based Bus / Device / Function (BDF) number, the secondary address space comprising a particular one of a plurality of non-overlapping secondary address spaces, each of the plurality of secondary address spaces mapping to a corresponding portion of the configuration address space, and a particular BDF number being used in the particular secondary address space and in another one of the plurality of secondary address spaces; Means for using a mapping table to translate the address of the determined secondary address space into a corresponding address in the configuration address space, wherein addresses of the configuration address space correspond to another second view of the configuration address space, addresses of the configuration address space each comprise a corresponding PCI-based BDF number, and the mapping table maps BDF numbers in the secondary address space to BDF numbers in the configuration address space.

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