Method for manufacturing a semiconductor device

Abstract

Method for manufacturing a semiconductor device, comprehensive the steps: - forming a layer of a second conductivity type (p) on the side of an upper surface of a substrate (1) of a first conductivity type (n); and - forming a buffer layer (10) by performing a plurality of ion implantation steps, where: - each of the ion implantation steps implants ions of an impurity of a first conductivity type (n) on the side of a lower surface of the substrate (1) at an ion implantation angle which is fixed with respect to the lower surface of the substrate (1), - the ion implantation angle of a subsequent ion implantation step is smaller than that of the previous ion implantation step and - during the step of forming the buffer layer (10) the acceleration energy is not changed.

Description

Technical area

[0001] This invention relates to a method of manufacturing a semiconductor device which can be used, for example, to control a large current. background

[0002] Currently, for discrete high-performance semiconductor devices such as punch-through IGBTs (Insulated Gate Bipolar Transistors), low-cost single-crystal silicon substrates manufactured by the FZ (Float Zone) process, the MCZ (Magnetic Field Applied Czochralski) process, and the like can be used to reduce costs.

[0003] A method for manufacturing a punch-through IGBT based on an N-type single-crystal silicon substrate is briefly described. First, an N+ diffusion layer (emitter layer), a P+ diffusion layer (base layer), a gate insulating layer, a gate electrode, a metal interconnection (emitter electrode), and the like are formed on the upper surface side of the substrate. Then, the substrate is ground on the lower surface side until the thickness of the substrate becomes, for example, 100 μm. After that, an impurity is introduced into the substrate from the lower surface of the substrate by ion implantation, and the impurity is activated by an electric furnace, laser annealing, or the like, thereby forming an N+ buffer layer and a P+ collector layer on the lower surface side of the substrate.

[0004] In conventional processes, an N+ buffer layer is formed by implanting ions, such as phosphorus, at an energy of approximately 500 keV to 8 MeV. Accordingly, the position where the impurity concentration has a local maximum is at a depth of approximately 5 µm or less from the bottom surface of the substrate.

[0005] Furthermore, a P+ collector layer is formed by implanting ions, for example, boron, at a low energy of approximately 5 to 100 keV. Accordingly, the boron impurity lies at a depth of approximately 0.1 to 1.0 µm from the bottom surface of the substrate.

[0006] Generally, for a semiconductor device with an impurity distribution on the bottom surface of the substrate, it is desirable to thin the semiconductor substrate to reduce loss. The loss reduction achieved by thinning the substrate comes at the expense of deterioration of the breakdown voltage characteristics and oscillations caused by surges during turn-off.

[0007] Patent Literature 1 discloses a method for forming an N+ buffer layer (field stop layer) by performing a plurality of cycles of proton irradiation. When a defect (a near-amorphous state with a high crystal defect density) is formed in the substrate by proton irradiation, a leakage current may increase, or a loss may increase due to a reduction in carrier mobility. Accordingly, the invention of Patent Literature 1 performs a plurality of proton irradiation cycles. Specifically, a subsequent cycle of proton irradiation is directed to the position where a defect remains after a previous cycle of proton irradiation.

[0008] Patent Literature 2 discloses a method that forms an N+ buffer layer with a broad distribution by oxygen introduction into a semiconductor substrate followed by proton irradiation. State of the artPatent literature Patent literature 1: International patent application WO 2013 / 089 256 A1 Patent Literature 2: Japanese Patent Application JP 2007- 266 233 A

[0009] The document DE 10 2006 040 491 A1 teaches a method for producing an implantation zone in a semiconductor substrate, wherein in a step of irradiating the semiconductor substrate with a particle beam, the implantation zone is formed at a predetermined penetration depth, starting from a main surface of the semiconductor substrate, wherein by a coordinated increase in the radiation energy of the particle beam and an increase in the irradiated path length up to a main implantation peak, an implantation zone which is undisturbed at the predetermined penetration depth is produced, which is significantly broadened in the depth direction of the semiconductor substrate compared to an implantation zone produced at the same penetration depth with non-increased radiation energy and path length.

[0010] The document EP 2 793 268 A1 shows a semiconductor component in which a p +-collector layer, which serves as an n-drift layer. In a deeper region than the p-type layer formed on the back + -collector layer is a n + -field stop layer. A collector electrode contacts the p + -collector layer. During the formation of the p + -collector layer and the n +To form the field-stop layer, impurity ions are implanted into the back of the semiconductor substrate. A first annealing process is then performed to activate the impurity ions, thus forming the p+ collector layer. The back of the semiconductor substrate is then irradiated with a proton. A second annealing process is then performed to convert the proton into a donor, thus forming the field-stop layer. The first annealing process is performed at a higher annealing temperature than the second. A collector electrode is then formed on the back of the semiconductor substrate. This can prevent deterioration of the electrical properties.

[0011] US Pat. No. 6,229,148 B1 discloses a method and apparatus for performing multiple implantations into a semiconductor wafer to set variable implantation waveforms. An implanter enables the setting of variable waveforms according to energy, beam current, and angle of implantation. At least one ramp voltage, a ramp beam current source, and a programmable motor mechanically connected to a wafer stage are used to generate the variable waveforms. The implanter and the method of the invention generate detailed doping profiles with only a single implantation. Such detailed doping profiles are used to produce high-degree retrograde wells as well as transistors with punch-through suppression implants and channel implants with controlled doping gradients. Technical problem

[0012] Preferably, a thick buffer layer is formed while reducing noise. However, the method disclosed in Patent Literature 1 performs a subsequent cycle of proton irradiation after changing the acceleration energy of the previous cycle of proton irradiation, and thus has the problem of requiring a long time for beam adjustment, thereby reducing manufacturing efficiency. Furthermore, the method disclosed in Patent Literature 2 performs proton irradiation after introducing oxygen, and therefore causes an increase in the number of manufacturing steps and a problem that the distribution of the N+ buffer layer cannot be precisely controlled.

[0013] The present invention has been developed to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device which can form a thick buffer layer with less noise while efficiently reducing fluctuations. Means to solve the problems

[0014] The object underlying the invention is achieved in a method for producing a semiconductor device according to the invention with the features of claim 1. Advantageous further developments are the subject of the respective dependent claims.

[0015] According to the present invention, a method for manufacturing a semiconductor device comprises the steps of forming a layer of a second conductivity type on an upper surface side of a substrate of a first conductivity type, and forming a buffer layer by performing a plurality of ion implantation steps, wherein each of the ion implantation steps implants ions of an impurity of a first conductivity type on the lower surface side of the substrate at an ion implantation angle which is fixed with respect to the lower surface of the substrate, the ion implantation angle of a subsequent ion implantation step is smaller than that of the previous ion implantation step, wherein the acceleration energy is not changed during the buffer layer formation step.

[0016] Other features of the present invention will become apparent from the following description. Advantageous effects of the invention

[0017] According to this invention, an impurity is injected sequentially from a deeper position of the substrate during a plurality of ion implantation steps, each having different ion implantation angles and the same acceleration energy for each implantation. Accordingly, a thick buffer layer with less impurity can be formed while efficiently reducing fluctuations. Short description of the drawings Fig. 1 is a cross-sectional view of a semiconductor device in a state where the structures have been formed on the upper surface side of the substrate. Fig. Figure 2 is a view showing boron implantation. Fig. 3 is a view showing the execution of the process of the first ion implantation step. Fig. 4 is a view showing a scanning direction of the ion beam and a moving direction of the plate. Fig. 5 is a view showing the execution of the process of the second ion implantation step. Fig. 6 is a view showing the execution of the process of the third ion implantation step. Fig. 7 is a cross-sectional view of the semiconductor device after the heat treatment step. Fig. 8 is a cross-sectional view of the semiconductor device in which a collector electrode has been formed. Fig. Figure 9 is a diagram showing the distribution of impurities along the line IX-IX' in Fig. 8 shows. Fig. 10 is a diagram showing the distribution of impurities of the buffer layer according to Embodiment 2. Fig. 11 is a cross-sectional view of a semiconductor device formed by a method for manufacturing a semiconductor device according to Embodiment 3. Fig. Figure 12 is a diagram showing the distribution of impurities along the line XII-XII' in Fig. 11 shows. Fig. 13 is a view showing the impurity distribution of the semiconductor device according to the modification. Description of the embodiments

[0018] The methods for manufacturing a semiconductor device according to embodiments of the present invention will be described with reference to the drawings. Identical or corresponding components are denoted by the same reference numerals, and repetition of their explanations may be omitted. Embodiment 1.

[0019] Fig. 1 to 8 are views showing a method for manufacturing a semiconductor device according to Embodiment 1 of the present invention. To manufacture a semiconductor device according to Embodiment 1, first, a pattern is formed on the upper surface side of the substrate. Fig. 1 is a cross-sectional view of a semiconductor device in the course of manufacturing, in a state where the structures have been formed on the upper surface side of the substrate. A substrate 1 is made of N-type single-crystal silicon. An emitter layer 2 made of an N+ diffusion layer, a base layer 3 made of a P+ diffusion layer, a gate insulating layer 4, a gate electrode 5, an emitter electrode 6 which is a metal interconnection, and the like are formed on the upper surface side of the substrate 1 by a well-known method. Note that a passivation layer may be formed on these structures.

[0020] Subsequently, the thickness of the substrate 1 is reduced to, for example, approximately 100 µm by grinding the substrate 1 from the lower surface side of the substrate 1. Preferably, a protective adhesive tape is applied to the upper surface side of the substrate 1 to protect the structures on the upper surface side of the substrate 1 during grinding. Generally, the protective adhesive tape has a heat resistance of up to approximately 100°C, and the protective adhesive tape must be removed before a step in which the temperature of the upper surface side of the substrate to which a protective adhesive tape is applied is 100°C or higher.

[0021] Subsequently, ions of a P-type impurity are implanted, which forms a collector layer. Fig. Figure 2 is a cross-sectional view showing a state in which a P-type impurity has been implanted, forming a P+ collector layer. Using an intermediate-current ion implanter, a P-type impurity (boron 7) is implanted into the lower surface side of the substrate 1. The implantation energy for boron is set to a low energy, for example, 100 keV or less, thereby implanting the boron 7 in a near-surface region starting from the lower surface of the substrate 1.

[0022] Subsequently, an activation heat treatment is performed on the substrate 1 using a laser heat treatment device or an electric furnace to activate the implanted impurities. This activates the aforementioned boron 7 and forms a collector layer.

[0023] A first ion implantation step is then carried out. Fig. 3 is a view showing the process of the first ion implantation step. In the first ion implantation step, an impurity (protons 12) is implanted from the lower surface side of the substrate 1 by using, for example, a high-energy ion implanter. At this time, the acceleration energy is unchanged. Furthermore, the ion implantation angle θ with respect to the lower surface of the substrate 1 is 90° to 83°. In other words, ions are implanted at an angle of approximately 0° to 7° when the direction perpendicular to the lower surface of the substrate 1 is considered 0°. The first ion implantation step is a step in which the protons 12 are implanted into the entire lower surface of the substrate 1 at a fixed acceleration energy and ion implantation angle.

[0024] To ensure the uniformity of the amount of impurities introduced within the substrate surface in the first ion implantation step, an ion beam or a plate holding the substrate 1 is moved vertically and horizontally. Alternatively, the plate can be moved vertically during a horizontal scan by the ion beam, thereby implanting ions into the entire lower surface of the substrate 1. Fig. Figure 4 is a view showing a state where the plate is moved vertically while the ion beam is scanned horizontally. To ensure the uniformity of the implanted impurities within the substrate surface, it is preferable to set a lower limit on the number of scans of the ion beam or plate.

[0025] If the ion implantation angle is changed during the first ion implantation step, the uniformity within the substrate surface decreases and the implantation depth cannot be controlled. Accordingly, the ion implantation angle is fixed in the first ion implantation step.

[0026] A second ion implantation step is then carried out. Fig. Figure 5 is a view showing the process of the second ion implantation step. In the second ion implantation step, an impurity (protons 14) is implanted from the lower surface side of the substrate 1 using, for example, a high-energy ion implanter. The acceleration energy is set to the same acceleration energy as in the first ion implantation step. Furthermore, the ion implantation angle θ with respect to the lower surface of the substrate 1 is 50°. In other words, ions are implanted at an angle of approximately 40° when the direction perpendicular to the lower surface of the substrate is considered to be 0°.

[0027] The ion implantation angle in the second ion implantation step is smaller than the ion implantation angle in the first ion implantation step. Accordingly, the protons 14 are located at a lower depth from the surface of the substrate 1 than the positions of the protons 12.

[0028] A third ion implantation step is then carried out. Fig. Figure 6 is a view showing the process of the third ion implantation step. In the third ion implantation step, an impurity (protons 16) is implanted from the lower surface side of the substrate 1 by using, for example, a high-energy ion implanter. The acceleration energy is set to the same acceleration energy as in the first ion implantation step. Furthermore, the ion implantation angle θ with respect to the lower surface of the substrate 1 is 30°. In other words, ions are implanted at an angle of approximately 60° when the direction perpendicular to the lower surface of the substrate is considered 0°. Note that in the second ion implantation step, as in the first ion implantation step, the ion beam and / or the plate are moved to ensure the uniformity of the implanted impurity within the substrate surface.

[0029] The ion implantation angle in the third ion implantation step is smaller than the ion implantation angle in the second ion implantation step. Accordingly, the protons 16 are located at a shallower position from the surface of the substrate 1 than the positions of the protons 14. The first to third ion implantation steps are collectively referred to as the buffer layer formation step.

[0030] Following the buffer layer formation step, a heat treatment step (activation heat treatment) is performed. In the heat treatment step, a heat treatment is performed on the substrate 1 at, for example, approximately 400°C. Fig. 7 is a cross-sectional view of the semiconductor device after the heat treatment step. The heat treatment step forms a buffer layer 10 (field stop layer), which is an N+ region. The collector layer 8 was formed by the heat treatment before the buffer layer formation step. However, the heat treatment for forming the collector layer 8 and the heat treatment for forming the buffer layer 10 may be combined into a single step. In particular, the activation heat treatment for forming the collector layer 8 before the buffer layer formation step may be omitted.

[0031] Finally, the lower surface side of the substrate 1 is cleaned and then a collector electrode is formed. Fig. 8 is a cross-sectional view of the semiconductor device in which a collector electrode 9 contacting the collector layer 8 has been formed. The collector electrode 9 is formed by forming a metal layer.

[0032] Fig. Figure 9 is a diagram showing the distribution of the impurities of the collector layer 8 and the buffer layer 10 along the line IX-IX' in Fig. 8. The buffer layer 10 is a layer having three peak concentrations of impurities and formed in a deep position of the substrate.

[0033] In the buffer layer formation step, a plurality of ion implantation steps are performed to implant n-type impurities into the lower surface side of the substrate 1 at a fixed ion implantation angle with respect to the lower surface of the substrate 1 such that the ion implantation angle in a subsequent ion implantation step becomes smaller than that of the previous implantation step. In other words, ions are first implanted into deep positions of the substrate 1, and a later ion implantation step implants ions into less deep positions of the substrate 1. In the first ion implantation step, in which the amount of impurities in the substrate is small, an impurity is implanted into a deep position of the substrate. Accordingly, the impurity can be formed to reach a deep position in the substrate without being affected by impurities.Accordingly, a thick buffer layer can be formed.

[0034] When the ion implantation step that causes an impurity to reach a deepest position of the substrate among a plurality of ion implantation steps is performed as a second or subsequent implantation step, a perturbation introduced by a previous ion implantation step reduces the ion reach. Accordingly, an impurity cannot be implanted to an intended depth. To avoid this problem, in Embodiment 1, ions are first implanted into deep positions of the substrate, and a later ion implantation step implants ions into less deep positions of the substrate.

[0035] The method for manufacturing a semiconductor device according to Embodiment 1 of the present invention can form a thick (wide) buffer layer. By forming the thick buffer layer 10, the peak concentration of the buffer layer 10 can be reduced and turn-off oscillations can be reduced. Furthermore, the substrate can be thinned to reduce loss because the impurity distribution along the depth of the substrate can be designed as desired.

[0036] The turn-off process of the semiconductor device will be briefly described. When the positive voltage at the gate electrode 5 is reduced in the on-state of the semiconductor device, a channel formed near the gate insulating layer 4 disappears, and the injection of electrons from the emitter layer 2 into the substrate 1 stops. At this time, the potential of the buffer layer 10 increases, electric charges (holes) injected from the collector layer 8 into the substrate 1 decrease, and charge carriers (electrons, holes) accumulated in the substrate 1 disappear in pairs within the substrate 1. Alternatively, electrons in the substrate 1 flow toward the collector electrode 9 to recombine with holes and disappear, and holes in the substrate 1 flow from the base layer 3 to the emitter electrode 6 to recombine with electrons and disappear.As soon as all accumulated charge carriers in substrate 1 have disappeared, substrate 1 is in a high-resistance blocking state.

[0037] According to Embodiment 1 of the present invention, ions are first implanted into deeper positions of the substrate, and in a later ion implantation step, ions are implanted into shallower positions of the substrate. This allows subsequent proton implantation to provide (compensate) protons to a disturbed region created by a previous proton implantation. To enable this compensation, the ion implantation angle is determined by considering the bottom surface of the substrate. The ion implantation angle is a parameter that determines the depth of the peak concentration of the impurity. Accordingly, in addition to optimizing the ion implantation angle, by optimizing the implantation amount so that a necessary amount of protons can be supplied to a depth where the disturbance is formed, disturbance can be reduced.By reducing a problematic disturbance using proton implantation, the breakdown voltage characteristics can be improved, oscillations during turn-off can be reduced, and leakage current and loss can be reduced.

[0038] Thereby, the method for manufacturing a semiconductor device according to Embodiment 1 of the present invention can form a thicker buffer layer with less noise.

[0039] If the acceleration energy is changed after a previous ion implantation step and a subsequent ion implantation step is performed, a long time is required for beam adjustment, and the manufacturing efficiency is very low. However, in the method for manufacturing a semiconductor device according to Embodiment 1 of the present invention, a plurality of ion implantation steps are performed at a fixed acceleration energy in the buffer layer formation step. In other words, the acceleration energy is not changed during the buffer layer formation step. Accordingly, the semiconductor device can be manufactured efficiently.

[0040] Furthermore, the method for manufacturing a semiconductor device according to Embodiment 1 of the present invention changes the ion implantation depth by changing the ion implantation angle with respect to the bottom surface of the substrate 1, and therefore does not require oxygen introduction as disclosed in Patent Literature 2. Accordingly, an increase in the number of manufacturing steps and variations in the thickness of the buffer layer can be reduced.

[0041] Between the preceding and subsequent ion implantation steps, the acceleration energy remains unchanged, and only the ion implantation angle is altered. Thus, multiple ion implantation steps can be performed continuously.

[0042] The method for manufacturing a semiconductor device according to Embodiment 1 of the present invention can be modified in various ways. For example, in the buffer layer formation step, light ions such as helium ions can be implanted instead of protons. The implantation of light ions allows the introduction of impurities to a depth of approximately 30 μm from the bottom surface of the substrate. This improves the breakdown voltage characteristics and reduces turn-off oscillations. This allows the substrate to be thinned to reduce loss. More than one ion implantation step (cycles) must be performed, but the number is not limited to three.

[0043] The conductivity types of the layers formed by the method for manufacturing a semiconductor device according to Embodiment 1 can be inverted. Each of the layers is formed to be of a first conductivity type (an N type or a P type) and a second conductivity type (the other of an N type or a P type).

[0044] In Embodiment 1 of the present invention, a planar IGBT is manufactured in the form of a semiconductor device. However, the manufacturing method of the present invention can be widely applied to discrete high-performance semiconductor devices such as trench IGBTs and diodes. In the case of manufacturing a diode, first, an impurity forming a P-type anode layer is implanted into the upper surface side of an N-type substrate. Subsequently, an impurity forming an N+ cathode layer is implanted into the lower surface side of the substrate. After that, ion implantation is performed on the lower surface side of the substrate, which is equivalent to the buffer layer formation step described above.Specifically, a plurality of ion implantation steps are performed such that the ion implantation angle of a subsequent ion implantation step is smaller than that of the previous ion implantation step, with each of the ion implantation steps implanting ions of an N-type impurity on the lower surface side of the substrate at a fixed ion implantation angle relative to the lower surface of the substrate. Subsequently, by performing a heat treatment step, a thick buffer layer with fewer impurities can be formed between the substrate and the cathode layer.

[0045] The structures formed on the upper surface side of the substrate are an N+ type (first conductivity type) emitter layer 2, a P+ type (second conductivity type) base layer 3, and the like in the case of an IGBT, or a P-type (second conductivity type) anode layer in the case of a diode. In each case, a P-type (second conductivity type) layer is formed on the upper surface side of the N-type (first conductivity type) substrate.

[0046] In the case where the bottom surface of the substrate has irregularities, the substrate is preferably rotated in the buffer layer formation step to avoid shadowing. In the case where ions are implanted perpendicular to the bottom surface of the substrate in the first ion implantation step (first ion implantation step), the substrate is rotated in the second and subsequent ion implantation steps. The substrate may be continuously rotated in the buffer layer formation step, but the substrate may be regularly moved in one rotational direction. For example, a step method may be employed in which the substrate is regularly rotated by 45°. In the case where the substrate is regularly rotated, the disk can be driven more easily than in the case where the substrate is continuously rotated.

[0047] These modifications can also be applied to the methods for manufacturing a semiconductor device according to the embodiments below. The methods for manufacturing a semiconductor device according to the embodiments below have many similarities with the method for manufacturing a semiconductor device according to Embodiment 1, and therefore, the differences from Embodiment 1 will be primarily described. Embodiment 2.

[0048] In Embodiment 2 of the present invention, the buffer layer formed in the buffer layer formation step is activated by a heat treatment step as in Embodiment 1. The buffer layer after the heat treatment step has only a local peak of impurity concentration along the depth. Fig. 10 is a diagram showing the impurity distribution of the buffer layer 10 according to Embodiment 2. Fig. Figure 10 shows the impurity concentration, with the depth increasing from left to right, starting from the bottom surface of the substrate. The maximum concentrations of the respective implantation steps are connected to form a broad distribution, and the buffer layer 10 has a smooth impurity profile. Consequently, the impurity concentration of the buffer layer 10 has a local peak.

[0049] The Fig. The impurity distribution of the buffer layer 10 shown in Figure 10 can be realized by adjusting the implantation amounts by performing, for example, four ion implantation steps. Specifically, the ion implantation angle of the first ion implantation step is set to 7°, the ion implantation angle of the second ion implantation step is set to 30°, the ion implantation angle of the third ion implantation step is set to 45°, the ion implantation angle of the fourth ion implantation step is set to 60°, and a heat treatment step is performed by heat treatment at approximately 400°C, thereby adjusting the impurity distribution in Fig. 10 is realized.

[0050] Forming the buffer layer 10 in such a way that it has only one local peak of the impurity concentration along the depth means that each region of the buffer layer has a relatively high impurity concentration. In the case where the sum of the impurities of the buffer layer 10 in Fig. 9 and the sum of the defects of the buffer layer in Fig. 10 (the present embodiment), the peak concentration of the present embodiment can be reduced. By reducing the peak concentration, the function of facilitating the supply of electric charges (holes) during a shutdown operation can be enhanced. This can reduce oscillations.

[0051] To ensure that the relatively thick buffer layer has only a local peak in the impurity concentration, it is important to increase the number of ion implantation steps. Typically, approximately four ion implantation steps are required, but the number of ion implantation steps is not limited to four and can be set to any desired number. Embodiment 3.

[0052] Fig. 11 is a cross-sectional view of a semiconductor device formed by a method for manufacturing a semiconductor device according to Embodiment 3. An intermediate buffer layer 20 into which P is implanted is formed between the collector layer 8 and the buffer layer 10. Fig. Figure 12 is a diagram showing the distribution of impurities along the line XII-XII' in Fig. 11 shows. The peak concentration of impurities in the intermediate buffer layer 20 is higher than the peak concentration of impurities in the buffer layer 10.

[0053] To form the intermediate buffer layer 20, for example, phosphorus (P) is first implanted from the lower surface side of the substrate 1 at an implantation energy of approximately 500 keV to 8 MeV. This step is referred to as the intermediate buffer layer formation step. A heat treatment step is then performed to activate P. The implantation of P ions may be performed before the buffer layer formation step or may be performed after the buffer layer formation step. Preferably, the activation of all the implanted ions for forming the buffer layer 10, the implanted ions for forming the intermediate buffer layer 20, and the implanted ions for forming the collector layer 8 is performed at once through a single heat treatment step. In the heat treatment step, the substrate is heated to approximately 400°C.

[0054] As in Fig. As shown in Figure 12, the peak impurity concentration of the intermediate buffer layer 20 after the heat treatment step is located between the peak impurity concentration position of the buffer layer 10 and the peak impurity concentration position of the collector layer 8. A feature of the method for manufacturing a semiconductor device according to Embodiment 3 is that the intermediate buffer layer 20, which has a peak impurity concentration higher than that of the buffer layer 10, is disposed between the buffer layer 10 and the collector layer 8. This intermediate buffer layer 20 enables the breakdown voltage characteristic to be ensured. Accordingly, the peak concentration and amount of impurities of the buffer layer 10 can be reduced, and an oscillation reducing effect during a turn-off operation can be enhanced.

[0055] It should be noted that the features of the methods for manufacturing a semiconductor device according to the above-described embodiments can be appropriately combined to enhance advantageous effects of the present invention. For example, as shown in Fig. As shown in Fig. 13, the intermediate buffer layer 20 having a local maximum value may be provided between the buffer layer 10 and the collector layer 8. List of reference symbols 1 substrate 2 Emitter layer 3 Base layer 4 Gate insulation layer 5 Gate electrode 6 Emitter electrode 7 Bor 8 collector layer 9 Collector electrode 10 Buffer layer 12, 14, 16 protons 20 intermediate buffer layer

Claims

[1] Method for manufacturing a semiconductor device, comprehensive the steps: - forming a layer of a second conductivity type (p) on the side of an upper surface of a substrate (1) of a first conductivity type (n); and - forming a buffer layer (10) by performing a plurality of ion implantation steps, where: - each of the ion implantation steps implants ions of an impurity of a first conductivity type (n) on the side of a lower surface of the substrate (1) at an ion implantation angle which is fixed with respect to the lower surface of the substrate (1), - the ion implantation angle of a subsequent ion implantation step is smaller than that of the previous ion implantation step and - during the step of forming the buffer layer (10) the acceleration energy is not changed. [2] The method according to claim 1, wherein the substrate (1) is rotated in the step of forming the buffer layer (10). [3] The method according to claim 1, wherein - ions are implanted perpendicular to the lower surface of the substrate (1) in a first of the ion implantation steps, and - the substrate (1) is rotated in a second and subsequent ion implantation steps. [4] The method according to claim 1, wherein the substrate (1) is periodically moved in a rotational direction in the step of forming the buffer layer (10). [5] Method according to one of claims 1 to 4, wherein in the step of forming the buffer layer (10) protons or helium ions are implanted. [6] Method according to one of claims 1 to 5, - further comprising the step of carrying out a heat treatment after the step of forming the buffer layer (10), - wherein the heat treatment step results in the buffer layer (10) formed in the buffer layer (10) forming step having only a local peak of impurity concentration along its depth. [7] The method of claim 1, further comprising the steps of: - forming a collector layer (8) of the second conductivity type on the side of the lower surface of the substrate (1); and - Forming a collector electrode (9) which is in contact with the collector layer (8). [8] Method according to claim 7, further comprising the steps: - carrying out a heat treatment after the step of forming the buffer layer (10) and - forming an intermediate buffer layer (20) before the heat treatment step by means of P implantation into the lower surface of the substrate (1), where: - after the heat treatment step, a peak concentration of impurities of the intermediate buffer layer (20) is located between a position of a peak concentration of impurities of the buffer layer (10) formed in the step of forming the buffer layer (10) and a position of a peak concentration of impurities of the collector layer (8), and - the peak concentration of the impurities of the intermediate buffer layer (20) is higher than the peak concentration of the impurities of the buffer layer (10). [9] The method according to claim 8, wherein the heat treatment step results in the buffer layer (10) formed in the buffer layer (10) forming step having only a local peak of impurity concentration along its depth.

Images