Semiconductor device

Abstract

Semiconductor device (100) comprising: a semiconductor substrate (10) comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, arranged on a front main surface of the first semiconductor layer, and a third semiconductor layer, which is of the second conductivity type and is arranged on a rear main surface of the first semiconductor layer, where the first semiconductor layer in an FS layer has several impurity concentration peaks that are positioned differently in a first direction extending towards the rear main surface, an integrated concentration obtained by integrating an impurity concentration value of the first semiconductor layer in the first direction to the rear main surface equal to or lower than a critical integrated concentration n c is: nc = E c ( ε r ε 0 / q ) where E c the critical electric field strength, ε r ε₀ denotes the relative permittivity of a semiconductor, ε₀ the permittivity of free space, and q the elementary charge. a defect concentration at a first defect concentration peak of the multiple defect concentration peaks, which is furthest from the rear main surface of the first semiconductor layer, is higher than a defect concentration at a second defect concentration peak of the multiple defect concentration peaks, which is the second furthest from the rear main surface of the first semiconductor layer.

Description

BACKGROUND 1. Technical field

[0001] The present invention relates to a semiconductor device.

[0002] In the conventional art, a device having an insulated gate bipolar transistor (IGBT device) has a region doped with hydrogen ions and the like, which can serve as a field stop layer (FS layer) (see, for example, Patent Documents 1 and 2).

[0003] Further prior art is also known from patent documents 3 and 4. State of the art documentPatent documents Patent document 1: JP 2010 - 541 266 A Patent document 2: JP 2014 - 99 643 A Patent document 3: US 2014 / 0 187 005 A1 Patent document 4: US 7,538,412 B2

[0004] In IGBTs, the FS layer is typically located near the collector electrode. However, if the FS layer is positioned closer than usual to the emitter electrode, it becomes possible to reduce the oscillation that may occur at the time of switching and the leakage current that may occur between the collector and emitter when the gate voltage is zero, and also to improve the reverse bias safe operating area (RBSOA). The effect of reducing the oscillation that may occur at the time of switching and the like is particularly enhanced as the concentration of the FS layer increases. On the other hand, if the FS layer is positioned close to the collector electrode, the drift layer has a greater thickness than if the FS layer is positioned closer than usual to the emitter electrode. This improves the resistance to large-current-induced short circuits and the breakdown voltage.The effect of improving resistance to large-current-induced short circuits and the like is particularly enhanced as the concentration of the FS layer decreases. As discussed above, it is difficult to achieve both the effects of reducing the oscillation that may occur during switching and the like and the effects of improving resistance to large-current-induced short circuits and the like, because they require contradictory properties for the FS layer.

[0005] Here, the large-current-induced short-circuit resistance is defined as the amount of current flowing when the IGBT breaks down as a result of gradually increasing the gate voltage. The large-current-induced short-circuit resistance is measured as follows. The duration of the on-time period is fixed, and the IGBT is turned on and off repeatedly, and the gate voltage input to the IGBT is progressively increased each time the IGBT is turned on. In this way, large currents are supplied to the IGBT. If the FS layer is positioned closer than normal to the emitter electrode and has a higher than normal concentration, this reduces the holes moving from the collector side. As a result, the proportion of electrons becomes higher than that of holes in the current components flowing through the IGBT, and the electric fields on the collector side increase.If the electric fields on the collector side increase too much, the IGBT will eventually break down. Summary

[0006] A first aspect of the present innovations provides a semiconductor device according to claim 1

[0007] An integrated concentration obtained by integrating the impurity concentration value of the first semiconductor layer in the first direction toward the back main surface up to a boundary between the second impurity concentration peak and a third impurity concentration peak among the plurality of impurity concentration peaks that is third closest to the front main surface may be equal to or lower than the critical integrated concentration.

[0008] An integrated concentration obtained by integrating the impurity concentration value of the first semiconductor layer in the first direction toward the back main surface up to a boundary between the third impurity concentration peak and the impurity concentration peak for the impurities may be equal to or lower than the critical integrated concentration.

[0009] An integrated concentration obtained by integrating the impurity concentration value in the first direction from the first surface to the third impurity concentration peak may be equal to or lower than the critical integrated concentration.

[0010] The first semiconductor layer having the first conductivity type may have, between the back main surface and the impurity concentration peak for the impurities, an impurity concentration peak for the impurities of the second conductivity type at which an impurity concentration is higher than the impurity concentration peak for the impurities.

[0011] A percentage of (i) a length from a front side of the second semiconductor layer having the second conductivity type positioned opposite a junction interface to a position of the first impurity concentration peak with respect to (ii) a length in the first direction of the first semiconductor layer and the second semiconductor layer may fall within a range higher than 85% and lower than 89%. A percentage of (i) a length from the front side to a position of the second impurity concentration peak with respect to (ii) the length in the first direction of the first semiconductor layer and the second semiconductor layer may fall within a range higher than 89% and lower than 91%.A percentage of (i) a length from the front side to a position of the third impurity concentration peak with respect to (ii) the length in the first direction of the first semiconductor layer and the second semiconductor layer of the second conductivity type may fall within a range higher than 96% and lower than 98%. A percentage of (i) a length from the front side to a position of the impurity concentration peak for the impurities with respect to (ii) the length in the first direction of the first semiconductor layer and the second semiconductor layer may fall within a range higher than 98% and lower than 100%.

[0012] The first impurity concentration peak may be positioned at a distance in a range greater than 94 µm and less than 97 µm from a front side of the second semiconductor layer positioned opposite the junction interface. The second impurity concentration peak may be positioned at a distance in a range greater than 97 µm and less than 100 µm from the front side. The third impurity concentration peak may be positioned at a distance in a range greater than 105 µm and less than 108 µm from the front side. The impurity concentration peak for the impurities may be positioned at a distance in a range greater than 108 µm and less than 110 µm from the front side.

[0013] A percentage of (i) a length from a front side of the second semiconductor layer positioned opposite the junction interface to a position of the first impurity concentration peak with respect to (ii) a length in the first direction of the first semiconductor layer and the second semiconductor layer may fall in a range higher than 77% and lower than 81%. A percentage of (i) a length from the front side to a position of the second impurity concentration peak with respect to (ii) the length in the first direction of the first semiconductor layer and the second semiconductor layer may fall in a range higher than 81% and lower than 86%.A percentage of (i) a length from the front side to a position of the third impurity concentration peak with respect to (ii) the length in the first direction of the first semiconductor layer and the second semiconductor layer may fall within a range higher than 93% and lower than 97%. A percentage of (i) a length from the front side to a position of the impurity concentration peak for the impurities with respect to (ii) the length in the first direction of the first semiconductor layer and the second semiconductor layer may fall within a range higher than 97% and lower than 100%.

[0014] The first impurity concentration peak may be positioned at a distance in a range greater than 54 µm and less than 57 µm away from the front side of the second semiconductor layer positioned opposite the junction interface. The second impurity concentration peak may be positioned at a distance in a range greater than 57 µm and less than 60 µm away from the front side. The third impurity concentration peak may be positioned at a distance in a range greater than 65 µm and less than 68 µm away from the front side. The impurity concentration peak for the impurities may be positioned at a distance in a range greater than 68 µm and less than 70 µm away from the front side.

[0015] The semiconductor device may further include a gate insulating film and a gate electrode. The gate insulating film may be formed as a trench in at least a portion of the second semiconductor layer. The gate electrode may be in contact with the gate insulating film.

[0016] Donors at each of the first to third impurity concentration peaks can contain donor complexes of hydrogen, vacancies, and oxygen.

[0017] The summary section does not necessarily describe all necessary features of the embodiments of the present invention. The present invention may also be a partial combination of the features described above. Brief description of the drawings Fig. 1 shows the cross section of an IGBT 100 relating to an embodiment of the present invention. Fig. Figures 2A to 2D show the manufacturing process of the IGBT 100. Fig. 3 shows the impurity concentration peaks (P x ) and limits (V y ) between the impurity concentration peaks in the region between A1 and A2 in a first embodiment. Fig. Figure 4 is an enlarged view showing the area from a position of 80 µm to a position of 110 µm shown in Fig. 3 are shown. Fig. Figure 5 shows the relationship between the impurity concentration peaks (P x ) and a critical integrated concentration in the area between A1 and A2 in the first embodiment. Fig. Figure 6 is an enlarged view showing the area from a position of 80 µm to a position of 110 µm shown in Fig. 5 are shown. Fig. Figure 7 shows the impurity concentration peaks (P x ) and limits (V y) between the impurity concentration peaks in the region between A1 and A2 in a second embodiment. Fig. Figure 8 is an enlarged view showing the area from a position of 40 µm to a position of 70 µm shown in Fig. 7 are shown. Fig. Figure 9 shows the relationship between the impurity concentration peaks (P x ) and a critical integrated concentration in the area between A1 and A2 in the second embodiment. Fig. Figure 10 shows the relationship between a critical electric field strength E c and a donor concentration and the relationship between a critical integrated concentration n c and the donor concentration. Description of the exemplary embodiments

[0018] Some embodiments of the present invention are described below. The embodiments do not limit the invention according to the claims, and all combinations of features described in the embodiments are not necessarily essential to the means provided by aspects of the invention.

[0019] As used herein, the letters "n" and "p," respectively, indicate that electrons and holes are the majority charge carriers. Additionally, the letters "n" and "p" may be accompanied by superscripts "+" and "-," which indicate a higher charge carrier concentration than if they were not added, and a lower charge carrier concentration than if they were not added, respectively. In the examples described herein, a first conductivity type indicates n-type, and a second conductivity type indicates p-type. However, in other examples, the first conductivity type may indicate p-type, and the second conductivity type may indicate n-type.

[0020] Fig. Figure 1 shows the cross-section of an IGBT 100 relating to an embodiment of the present invention. The IGBT 100, shown as an exemplary semiconductor device, includes a semiconductor substrate 10, an emitter electrode 52 and an interlayer dielectric film 36 provided on and in contact with a front side 19 of the semiconductor substrate 10, and a collector electrode 54 provided on and in contact with the back side of the semiconductor substrate 10.

[0021] The semiconductor substrate 10 includes an n-type drift layer 12, shown as an exemplary semiconductor layer of the first conductivity type, and a p-type base layer 18, shown as an exemplary semiconductor layer of the second conductivity type. The drift layer 12 has a first surface 14 and a second surface 16. The first surface 14 is also referred to as a pn junction interface between the drift layer 12 and the base layer 18. The second surface 16 is positioned opposite the first surface 14 and is also referred to as the backside of the aforementioned semiconductor substrate 10. The base layer 18 is provided on and in contact with the first surface 14. The base layer 18 has a front side 19 positioned opposite the first surface 14 (the junction interface). As shown in Fig. As shown in Figure 1, a contact region 42 and an emitter region 44 are provided in the base layer 18 on the side of the front side 19. The front side 19 is also the front side of the semiconductor substrate 10.

[0022] The drift layer 12 has a semiconductor layer 20 on the second surface 16 side. The semiconductor layer 20 is formed by implanting impurities through the second surface 16 of the drift layer 12. The semiconductor layer 20 has a plurality of impurity concentration peaks therein, which are differently positioned in a first direction. As used herein, the term "peak" means the peak of the concentration of impurities of the first or second conductivity type. The semiconductor layer 20 includes an FS layer 22 of the first conductivity type, a buffer layer 24 of the first conductivity type, and a collector layer 26 of the second conductivity type. The FS layer 22, the buffer layer 24, and the collector layer 26 are arranged in the named order in the first direction. The first direction is directed from the first surface 14 to the second surface 16.In other words, the first direction can be considered to be the thickness direction of the semiconductor substrate 10, which is directed from the emitter electrode 52 to the collector electrode 54.

[0023] The FS layer 22 of the first conductivity type has three impurity concentration peaks therein, which are differently positioned in the first direction. In the present example, the FS layer 22 is capable of preventing the depletion layer from further expanding. Specifically, the FS layer 22 is capable of preventing the depletion layer, which begins to expand near the first surface 14, from reaching the second surface 16. In the present example, the FS layer 22 is a region filled with protons (H + ) and has three impurity concentration peaks resulting from the implantation of protons (H +) and which are differently positioned in the first direction. The donors that form the impurity concentration peaks resulting from the implantation of protons include junction defects of hydrogen (H), which is introduced as a result of the implantation of protons, vacancies (V), which are crystal defects formed during the same implantation, and oxygen (O), which is originally present in the semiconductor substrate 10—in other words, donor complexes generated by the VOH defects. The donor complexes generated by the VOH defects are also referred to as hydrogen-related donors.

[0024] The first conductivity type buffer layer 24 is a layer having a higher concentration of impurities producing the first conductivity type than the FS layer 22. In other words, in the present example, the FS layer 22 is n-type, and the buffer layer 24 is n-type. + -type. The buffer layer 24 may also be capable of preventing the depletion layer from expanding further, like the FS layer 22. In the present example, the buffer layer 24 has a peak in the concentration of impurities of the first conductivity type other than protons. In the present example, the buffer layer 24 is a region doped with phosphorus (P). However, the buffer layer 24 may alternatively be a layer doped with protons (H + ) instead of phosphorus (P) to achieve a higher impurity concentration than the FS layer 22.

[0025] The second conductivity type collector layer 26 is capable of supplying holes from the semiconductor substrate 10. The impurity concentration peak in the collector layer 26 is higher than the impurity concentration peak in the buffer layer 24. In the present example, the collector layer 26 is a region doped with boron (B).

[0026] The semiconductor substrate 10 further includes a trench-type gate electrode 32, a gate insulating film 34, an emitter region 44 of the first conductivity type, and a contact region 42 of the second conductivity type. The gate insulating film 34 is provided as a trench in at least a portion of the base layer 18. The gate electrode 32 is provided on and in contact with the gate insulating film 34.

[0027] Note that in other examples, the IGBT 100 may include a planar-type gate electrode and gate insulating film. When trench gate technology is employed, more electrons are introduced from emitter electrode 52 into collector electrode 54 than when planar gate technology is used. Therefore, the semiconductor layer 20 of the present example, which is configured to reduce the concentration of electric fields on the collector electrode 54 side by supplying holes from collector layer 26, produces stronger effects when trench gate technology is employed than when planar gate technology is employed.

[0028] The gate electrode 32 is electrically separated from the emitter electrode 52 by an interlayer dielectric film 36 provided on and in contact with the front side 19. A voltage is applied to a plurality of gate electrodes 32 via a gate terminal 50. An emitter terminal 51 is electrically connected to the emitter electrode 52, and a collector terminal 53 is electrically connected to the collector electrode 54.

[0029] When the gate electrode 32 is turned on, a channel region is formed in the base layer 18 and near the gate electrode 32. Here, when a suitable potential difference is formed between the emitter electrode 52 and the collector electrode 54, currents flow from the collector electrode 54 to the emitter electrode 52. The emitter region 44 is configured to provide a current path connected to the channel formation region.

[0030] Contact region 42 is configured to provide a low contact resistance between emitter electrode 52 and semiconductor substrate 10. When currents flow through IGBT 10, the currents flow from collector electrode 54 to emitter electrode 52 through emitter region 44 and contact region 42.

[0031] The Fig. Figures 2A to 2D show the manufacturing process of the IGBT 100. Fig. 2A shows a step of forming the base layer 18 on the front surface 19 of the semiconductor substrate 10, which includes the drift layer 12. The semiconductor substrate 10 may be an n-type single-crystal substrate formed by a fused-zone (FZ) technique, a single-crystal substrate formed by the Czochralski (Cz) technique, or a single-crystal substrate formed by the Czochralski applied magnetic field (MCZ) technique. The semiconductor substrate 10 may have a thickness of 100 μm or more and a resistivity of 50 Ωcm or more. In the present example, the semiconductor substrate 10 has a thickness of 110 μm and a resistivity of 70 Ωcm or more.

[0032] Fig. 2B shows a step of forming the gate electrode 32, the gate insulating film 34, the contact region 42, and the emitter region 44, and subsequently forming the interlayer dielectric film 36 and the emitter electrode 52 on the front side 19 of the semiconductor substrate 10. The gate electrode 32 may be made of polysilicon, and the gate insulating film 34 may be made of silicon oxide. The contact region 42 may be a region doped with the second conductivity type impurities such as boron (B). The emitter region 44 may be a region doped with the first conductivity type impurities such as arsenic (As) or phosphorus (P). The interlayer dielectric film 36 may be made of silicon oxide, and the emitter electrode 52 may be made of an alloy of aluminum and silicon (Al-Si).

[0033] Fig. 2C shows a step of forming the FS layer 22, the buffer layer 24 and the collector layer 26 by implanting impurities through the second surface 16 of the drift layer 12. According to the present example, in the Fig. 2C, first protons (H + ) is implanted to form the FS layer 22, which has three peaks differently positioned in the first direction. The positions of the impurity concentration peaks can be controlled by regulating the accelerating voltage for the protons.

[0034] In this example, the protons (H + ) with the dose calculated on 1.0E13 cm -2 and with the accelerating voltage set to 1.00 MeV, to form a first tip at a position 15 µm away from the second surface 16. In addition, the protons (H +) with the dose calculated at 7.0E12 cm -2 and with the accelerating voltage set to 0.80 MeV, to form a second tip at a position 10 µm away from the second surface 16. In addition, the protons (H + ) with the dose calculated on 1.0E13 cm -2 and implanted with the accelerating voltage set to 0.40 MeV to form a third tip at a position 4.2 µm from the second surface 16. Note that the positions where the tips are actually formed after activation annealing differ slightly from the originally assigned positions described above. Here, the letter "E" represents powers of 10, and 1.0E13, for example, means 1.0 × 10 13 .

[0035] After the FS layer 22 has been formed, phosphorus (P) is implanted to form the buffer layer 24. In the present example, phosphorus (P) is implanted with the dose set to 1.7E12 cm -2 and with the accelerating voltage set to 640 keV, to form a tip at a position 0.7 µm away from the second surface 16. After the buffer layer 24 has been formed, boron (B) is injected at a dose of 2.0E13 cm -2 implanted to form the collector layer 26.

[0036] Fig. Figure 2D shows a step for forming the collector electrode 54, which is in contact with the second surface 16. The collector electrode 54 can be formed by stacking titanium (Ti), nickel (Ni), and gold (Au) in the order mentioned. Next, the gate terminal 50, the emitter terminal 51, and the collector terminal 53 are provided. In this way, the IGBT 100 is completed.

[0037] Fig. 3 shows the impurity concentration peaks (P x ) and limits (V y ) between the impurity concentration peaks in the region between A1 and A2 in a first embodiment. As used herein, P x (x = 1 to 5) the impurity concentration peak. At the peak P x the impurity concentration assumes a local maximum value. The position and height of the peak P x can be controlled by varying the acceleration voltage for the impurities to be implanted and the impurity concentration. Here, V y (y = 1 to 4) the boundary between two peaks P x . At the Border V y the impurity concentration takes a minimum value between two peaks P x to.

[0038] In Fig. 3 the vertical axis represents the impurity concentration [ / cm 3], in particular the net impurity concentration (net doping), which is obtained by adding the impurity concentrations of the first and second conductivity types. Fig. Figure 3 shows the impurity concentration observed between A1 and A2, which is Fig. 1. The horizontal axis represents the position in the semiconductor substrate 10, defined in the first direction. A position of 0 µm denotes the front surface 19, and a position of 110 µm denotes the second surface 16. The first surface 14 of the drift layer 12 is positioned between the 0 µm position and the 10 µm position.

[0039] The present example shows the impurity doping pattern in the IGBT 100, which has a breakdown voltage of 1200 V. In the present example, A1-A2 denotes the region extending in the first direction from the front surface 19 to the second surface 16.

[0040] As used herein, a first peak P1 denotes a first of a plurality of impurity concentration peaks that is closest to the first surface 14. Similarly, a second peak P2, a third peak P3, and a fourth peak P4 denote the second, third, and fourth closest impurity concentration peaks to the first surface 14, respectively. Furthermore, a fifth peak P5 denotes the peak that is closest to the second surface 16. In the present example, peaks P1 to P3 are the proton concentration peaks (H + Concentration peaks) in the concentration distribution. The fourth peak P4, which is positioned closer to the second surface 16 than the third peak P3, is a concentration peak of impurities other than protons. The fifth peak P5 is positioned between the second surface 16 and the fourth peak P4 and has a higher impurity concentration than the fourth peak P4.

[0041] A boundary V1 is positioned between the vertex P1 and the vertex P2. Similarly, a boundary V2 is positioned between the vertex P2 and the vertex P3, a boundary V3 is positioned between the vertex P3 and the vertex P4, and a boundary V4 is positioned between the vertex P4 and the vertex P5.

[0042] In the present example, the first to fourth doping patterns are observed, numbered in ascending order of the impurity concentration at the P3 peak. Note that the integrated concentration, which will be described later, decreases in the order from the first to the fourth doping patterns. Although they have different impurity concentrations at the P3 peak, the first to fourth doping patterns all have the P3 peak at the same position.

[0043] Fig. Figure 3 shows four different doping pattern types in a single diagram. The multiple doping pattern types correspond to different IGBTs 100. A single completed IGBT 100 has a single doping pattern type. While the total dose for the first doping pattern is represented as 1, the second, third, and fourth doping patterns are represented as 1.4, 2.6, and 4.5, respectively. The difference in total dose is particularly evident at the third peak and near the third boundary.

[0044] The four different types of the first to fourth doping patterns have different impurity concentrations at the third peaks P 3-1 , P 3-2 , P 3-3 and P 3-4 and near the third borders V 3-1 , V 3-2 , V 3-3 and V 3-4However, the four different types of doping patterns coincide with each other in the remaining regions. For example, in the region from the 0 µm position to the 100 µm position, the four different types of doping patterns coincide with each other. For example, the first to fourth doping patterns coincide with each other at the peak P4, the boundary V4, and the peak P5. The impurity concentrations at the third peaks decrease in the order of the third peaks P 3-1 , P 3-2 , P 3-3 and P 3-4 increases, and the impurity concentrations at the third boundaries increase in the order of the third boundaries V 3-1 , V 3-2 , V 3-3 and V 3-4 to.

[0045] Fig. Figure 4 is an enlarged view showing the area from a position 80 µm to a position 110 µm shown in Fig. 3. As can be seen from Fig. 4, the four different types of doping patterns coincide perfectly with each other in the region excluding the region from the second boundary V2 to the fourth peak P4.

[0046] Between the second border V2 and the third peak P 3-1 of the first doping pattern, local maximum and minimum values ​​of the impurity concentration are observed, which are lower than the impurity concentration of the third peak P 3-1 . The local maximum and minimum values ​​of the impurity concentration between the second boundary V2 and the third peak V 3-1 However, they are not intentionally formed by regulating the acceleration voltage for the impurities to be implanted and the impurity concentration. Therefore, they are not considered here as a peak P and a boundary V.

[0047] In the present example, the position of peak P1 falls within the range of greater than 94 µm and less than 97 µm. The position of peak P2 falls within the range of greater than 97 µm and less than 100 µm. The position of peak P3 falls within the range of greater than 105 µm and less than 108 µm. The position of peak P4 falls within the range of greater than 108 µm and less than 110 µm.

[0048] In the present example, the above-mentioned ranges can also be expressed in the following manner, where L denotes the substrate length or the length of the drift layer 12 and the base layer 18 in the first direction. The percentage of the length from the position 0 µm to the position of the peak P1 with respect to the substrate length L falls in the range of more than 85% and less than 89%. The percentage of the length from the position 0 µm to the position of the peak P2 with respect to the substrate length L falls in the range of more than 89% and less than 91%. The percentage of the length from the position 0 µm to the position of the peak P3 with respect to the substrate length L falls in the range of more than 96% and less than 98%. The percentage of the length from the position 0 µm to the position of the tip P4 with respect to the substrate length L falls in the range of more than 98% and less than 100%.

[0049] Fig. Figure 5 shows the relationship between the impurity concentration peaks (P x ) and the critical integrated concentration in the area between A1 and A2 in the first embodiment. The vertical axis represents the integrated concentration [ / cm 2 ], and the horizontal axis represents the position in the semiconductor substrate 10 defined with respect to the first direction, as shown in the Fig. 3 and Fig. 4. In the present example, the graph showing the values ​​near the position of 110 µm is omitted for scaling reasons.

[0050] As used herein, the term "integrated concentration" refers to the value obtained by integrating the impurity concentration value in the first direction from the first surface 14, which is the junction interface between the drift layer 12 and the base layer 18, to a specific position in the drift layer 12. Moreover, as used herein, if a forward bias voltage is applied between the collector electrode 54 and the emitter electrode 52, the integrated impurity concentration value reaches a critical integrated concentration at the specific position, the maximum value of the electric field strength reaches the critical electric field strength, avalanche breakdown occurs, and depletion occurs in the region extending in the first direction from the first surface 14 to the specific position in the drift layer 12.Applying the forward bias between the collector electrode 54 and the emitter electrode 52 in the IGBT 100 means that the potential of the collector electrode 54 is higher than the potential of the emitter electrode 52.

[0051] Applying the forward bias causes depletion to occur in the drift layer 12 down to the specific position where the critical integrated concentration is reached, but depletion does not occur in the region beyond the specific position in the first direction. In the present example, the position in the drift layer 12 where the critical integrated concentration is reached can be controlled by regulating the positions of the peaks in the FS layer 22 (peaks P1 to P3) of the four doping patterns. The critical integrated concentration can be set in the range of 1.2E12 / cm 2 up to 2.0E12 / cm 2In the present example, the critical integrated concentration is approximately 1.4E12 / cm 2 .

[0052] In the present example, the integrated concentration obtained by integrating the impurity concentration value in the first direction from the first surface 14 to the boundary V1 is equal to or lower than the critical integrated concentration in the first to fourth doping patterns. In addition, the integrated concentration obtained by integrating the impurity concentration value in the first direction from the first surface 14 to the boundary V2 is equal to or lower than the critical integrated concentration in the first to fourth doping patterns.

[0053] In the present example, the integrated concentration obtained by integrating the impurity concentration value in the first direction from the first surface 14 to the boundary V 3-1is equal to or lower than the critical integrated concentration in the first doping pattern. In addition, the integrated concentration obtained by integrating the impurity concentration value in the first direction from the first surface 14 to the boundary V 3-2 is equal to or lower than the critical integrated concentration in the second doping pattern. However, in the third and fourth doping patterns, the integrated concentration obtained by integrating the impurity concentration value in the first direction from the first surface 14 to the boundary V 3-3 or V 3-4 is the critical integrated concentration. In the second doping pattern, the integrated concentration obtained by integrating the impurity concentration value in the first direction from the first surface 14 to the tip P 3-2obtained is equal to or lower than the critical integrated concentration.

[0054] Fig. Figure 6 is an enlarged view showing the area from a position of 80 µm to a position of 110 µm shown in Fig. 5. In the present example, the three peaks P1, P2, and P3 are present in the FS layer 22. At the first peak P1 in the FS layer 22, the critical integrated concentration is not reached. Thus, the FS layer 22 can be positioned relatively closer to the emitter electrode 52 and have a relatively higher concentration. This can contribute to the reduction of oscillation that may occur at the time of switching. In the present example, the critical integrated concentration is reached in the FS layer 22 or buffer layer 24. Thus, the FS layer 22 or buffer layer 24 can prevent the depletion layer from expanding further.

[0055] Furthermore, in the present example, the buffer layer 24 (the peak P4) has a higher concentration than the FS layer 22, and the collector layer 26 (the peak P5) has a higher concentration than the buffer layer 24. While the FS layer 22 has an impurity concentration of 1.0E14 to 1.0E16, the impurity concentration at the peak P4 is 1.0E16 to 1.0E17, and the impurity concentration at the peak P5 is 1.0E17 to 1.0E18. Thus, the peaks P4 and P5 are in Fig. 6 is not specified. In the present example, the buffer layer 24 and the collector layer 26 can be configured to control the carrier implantation characteristics. For example, the collector layer 26 can contribute to improving the hole implantation characteristics into the drift layer 12. This allows the carriers to be injected into the depletion layer while the IGBT 100 is turned off, thus reducing the increase in the electric field on the collector side. In this way, the resistance to large current-induced short circuits can be improved.As described above, the structure of the present example can achieve both the object of reducing the oscillation that may occur at the time of switching and the like and the object of improving the resistance to large current-induced short circuit and the like without requiring a compromise therebetween.

[0056] In the present example, a test was conducted to investigate the resistance to large current-induced short circuit under conditions such that the collector voltage Vcc = 680 V, the gate on-resistance Rgon = 4.1 Ω, the gate off-resistance Rgoff = 20 Ω, the gate input pulse duration = 2 μs, the chip junction temperature Tj = 25 °C, and the gate-emitter potential Vge was gradually increased from 15 V. The IGBT 100 of the present example did not break down even when the collector-emitter current Ic = 4300 A / cm 2Due to the limitations of the device, the currents were blocked from flowing when Ic = 4300 A / cm 2 was. The collector voltage Vcc indicates the voltage applied to the collector terminal 53. The gate-emitter potential Vge indicates the potential difference between the gate terminal 50 and the emitter terminal 51. The collector-emitter current Ic indicates the current flowing between the collector terminal 53 and the emitter terminal 51.

[0057] In addition, in the present example, a test was conducted to investigate the cut-off current surge under such conditions that the collector voltage Vcc = 870 V, the collector-emitter current Ice = 300 A / cm 2, the gate on-resistance Rgon = 1 Ω, the gate off-resistance Rgoff = 1 Ω, the floating inductance Ls = 70 [nH], the chip junction temperature Tj = 25 °C, and the gate-emitter potential Vge was turned off by lowering the potential from 15 V to 0 V. As for the IGBT 100 of the present example, the collector-emitter voltage Vce peaked at 1125 V when the gate was turned off. This indicates that the voltage overshoot that can occur when the gate is turned off is lower than usual. In addition, the oscillation that can occur when the gate is turned off is also lower than usual.

[0058] Fig. Figure 7 shows the impurity concentration peaks (P x ) and the limits (V y ) between the impurity concentration peaks in the region between A1 and A2 in a second embodiment. The vertical and horizontal axes represent the same parameters as in Fig. 3. In the present example, the second surface 16 is equivalent to the position of 70 µm. In the IGBT 100 of the present example, the drift layer 12 has a smaller thickness than in the first embodiment and a breakdown voltage of 600 V. In the present example, the peaks P x positioned differently than in the first embodiment. Apart from that, the second embodiment may be the same as the first embodiment. In the present example, one type of doping pattern is shown.

[0059] Fig. Figure 8 is an enlarged view showing the area from a position of 40 µm to a position of 70 µm shown in Fig. 7. In the present example, the position of peak P1 falls in the range of greater than 54 µm and less than 57 µm. The position of peak P2 falls in the range of greater than 57 µm and less than 60 µm. The position of peak P3 falls in the range of greater than 65 µm and less than 68 µm. The position of peak P4 falls in the range of greater than 68 µm and less than 70 µm.

[0060] In the present example, the above-mentioned ranges can also be expressed in the following manner, where L denotes the substrate length or the length of the drift layer 12 and the base layer 18 in the first direction. The percentage of the length from the position of 0 µm to the position of the peak P1 with respect to the substrate length L falls in the range of more than 77% and less than 81%. The percentage of the length from the position of 0 µm to the position of the peak P2 with respect to the substrate length L falls in the range of more than 81% and less than 86%. The percentage of the length from the position of 0 µm to the position of the peak P3 with respect to the substrate length L falls in the range of more than 93% and less than 97%. The percentage of the length from the position of 0 µm to the position of the tip P4 with respect to the substrate length L falls in the range of more than 97% and less than 100%.

[0061] Fig. Figure 9 shows the relationship between the impurity concentration peaks (P x) and the critical integrated concentration in the region between A1 and A2 in the second embodiment. In the present example, the integrated concentration obtained by integrating the impurity concentration value in the first direction from the first surface 14 to the boundary V1 is equal to or lower than the critical integrated concentration. The integrated concentration obtained by integrating the impurity concentration value in the first direction from the first surface 14 to the peak P2 is equal to or lower than the critical integrated concentration. In addition, the integrated concentration obtained by integrating the impurity concentration value in the first direction from the first surface 14 to the boundary V2 is equal to or lower than the critical integrated concentration.However, the integrated concentration obtained by integrating the impurity concentration value in the first direction from the first surface 14 to the tip P3 exceeds the critical integrated concentration.

[0062] The manufacturing process of the IGBT 100 relating to the second embodiment is substantially the same as that in the first embodiment. The following lists the differences. In the second embodiment, the semiconductor substrate 10 may have a thickness of less than 100 μm and a resistivity of less than 50 Ω. In the present example, the semiconductor substrate 10 has a thickness of 70 μm and a resistivity of 30 Ωcm. When the FS layer 22 is formed, protons are injected at a dose limited to 1.0E14 cm -2and with the accelerating voltage set to 0.40 MeV, to form the third tip at a position 4.2 µm away from the second surface 16. Apart from this, the second embodiment is similar to the first embodiment. The present example can produce the same effects as the first embodiment.

[0063] In the present example, a test was conducted to investigate the resistance to large current-induced short circuit under conditions such that the collector voltage Vcc = 360 V, the gate on-resistance Rgon = 1 Ω, the gate off-resistance Rgoff = 90 Ω, the gate input pulse duration = 2 μs, the chip junction temperature Tj = 40 °C, and the gate-emitter potential Vge was gradually increased from 15 V. The IGBT 100 of the present example did not break down even when the collector-emitter current Ic = 4300 A / cm 2Due to the limitations of the test equipment, the currents were blocked from flowing when Ic = 4300 A / cm 2 was.

[0064] In addition, in the present example, a test was conducted to investigate the cut-off current surge under such conditions that the collector voltage Vcc = 410 V, the collector-emitter current Ice = 310 A / cm 2, the gate on-resistance Rgon = 3.9 Ω, the gate off-resistance Rgoff = 3.9 Ω, the floating inductance Ls = 70 nH, the chip junction temperature Tj = 175 °C, and the gate-emitter potential Vge was turned off by lowering the potential from 15 V to 0 V. As for the IGBT 100 of the present example, the collector-emitter voltage Vce peaked at approximately 700 V when the gate was turned off. The voltage overshoot that can occur when the gate is turned off is lower than usual. In addition, the oscillation that can occur when the gate is turned off is also lower than usual.

[0065] In addition, in the present example, a test was conducted to investigate the cut-off current surge under such conditions that the collector voltage Vcc = 350 V, the collector-emitter current Ice = 490 A / cm 2and the other parameters were set in the same manner as in the turn-off current surge test described above. As for the IGBT 100 of the present example, the collector-emitter voltage Vce peaked at approximately 750 V when the gate was turned off. The voltage overshoot that can occur when the gate is turned off is lower than usual. In addition, the oscillation that can occur when the gate is turned off is also lower than usual.

[0066] Fig. Figure 10 shows the relationship between the critical electric field strength E c and the donor concentration and the relationship between the critical integrated concentration n c and the donor concentration. The horizontal axis represents the donor concentration (the n-type impurity concentration) [ / cm 3 ], the left vertical axis represents the critical electric field strength E c[V / cm], and the right vertical axis represents the critical integrated concentration n c [ / cm 2 ]. The following describes that a correlation exists between the critical electric field strength E c and the critical integrated concentration n c in connection with the donor concentration.

[0067] Here, a planar pn junction is considered. Specifically, a one-sided abrupt junction is discussed, where the concentration of the p-type layer is several orders of magnitude higher than the concentration of the n-type layer. In the case of a one-sided abrupt junction, applying a reverse bias to the pn junction can be considered to limit the expansion of the depletion layer to only the n-type layer. As a result of applying the reverse bias, the depletion layer expands, and the electric field strength assumes its maximum value near the pn junction. If the maximum electric field strength reaches a predetermined value, impact ionization causes avalanche breakdown.

[0068] In the first and second embodiments, the drift layer 12 is considered to be the n-type layer, and the base layer 18 is considered to be the p-type layer. Additionally, applying the reverse bias to the pn junction corresponds to applying a forward bias to the IGBT 100 in such a way that the potential of the collector electrode 54 is higher than the potential of the emitter electrode 52.

[0069] The critical electric field strength indicates the value of the electric field strength that causes avalanche breakdown to occur. The avalanche breakdown depends on the elemental composition of the semiconductors, the impurities implanted in the semiconductors, and the concentrations of the impurities. If N D and E crepresent the donor concentration and the critical electric field strength, respectively, and the impact ionization coefficient of silicon (Si) is used to calculate the ionization integral, the critical field strength E c represented by expression 1. Ec=4010⋅(ND_)1 / 8

[0070] As can be seen from expression 1, the critical electric field strength E c fixed as soon as the donor concentration N D is fixed. The Poisson equation can be expressed by Expression 2 if only the one-dimensional direction (assumed to be the x-direction) is considered. dE / dx=(q / εrεo)(p−n+ND−NA)

[0071] In the expression, q denotes the elementary charge (1.062 ×10 15 C), ε0 denotes the dielectric constant of the vacuum or 8.854 × 10 -14 F / cm and ε rrefers to the relative dielectric constant of the substance. Silicon has a relative dielectric constant ε r = 11.9. In addition, p denotes the hole concentration, n denotes the electron concentration and N A denotes the acceptor concentration. Since only the p-type layer of the one-sided abrupt junction is considered, no acceptors are present (N A = 0). Additionally, a perfectly depleted layer is assumed in which no holes or electrons are present (n = p = 0). In this case, Expression 3 is obtained by integrating Expression 2 over the depth x. E=(q / εrεo)∫NDdx

[0072] The position of the pn junction is expressed as the origin 0, and the position of the end of the depletion layer in the n-type layer positioned opposite the pn junction is expressed as x0. Here, if the entire depletion layer is integrated from 0 to x0, E in Expression 3 takes the maximum value in the electric field strength distribution. The maximum value in the electric field strength distribution is expressed as E m which is expressed by Expression 4. Em=(q / εrεo)∫0x0NDdx

[0073] If the maximum value E m in the electric field strength distribution the critical electric field strength E c is reached, expression 4 is transformed into expression 5. Ec=(εrεo / q)∫0x0NDdx

[0074] Both sides of expression 5 give constant values. The right-hand side of expression 5 denotes the perfectly depleted region in the n-type layer and is thus the critical integrated concentration n c in accordance with the definition described here. Thus, the following expression 6 is obtained. Expression 6 shows that the critical integrated concentration n c with the critical electric field strength E c As explained here, the critical integrated concentration n c a constant value that corresponds to the critical electric field strength E c correlated. Ec(εrεo / q)=nc

[0075] In Fig. 10 it is assumed that the donor concentration N D has a uniform concentration distribution in the x-direction in the n-type layer. Since the critical electric field strength E c on the donor concentration ND of the layer depends on the n-type (see expression 5), the critical integrated concentration n c also depends on the donor concentration N D of the n-type layer. If the donor concentration N D in the range of 1 × 10 13 up to 1 × 10 15 / cm 3 decreases, the critical integrated concentration n c in the range of 1.1 × 10 12 up to 2.0 × 10 12 / cm 2 . Judging from the fact that the donor concentration is in the range of several orders of magnitude, the critical integrated concentration n c essentially be considered as a constant value.

[0076] In an exemplary case where the IGBT 100 has a breakdown voltage of 1200 V as in the first embodiment, the critical integrated concentration n c be rated to be approximately 1.4 × 10 12 / cm2 is, based on Expression 6, when the donor concentration N D the drift layer 12 is equal to 6.1 × 10 13 / cm 3 is (see Fig. 3 and Fig. 4). In another exemplary case where the IGBT 100 has a breakdown voltage of 600 V as in the second embodiment, the critical integrated concentration n c be rated to be approximately 1.55 × 100 / cm 2 is, based on Expression 6, when the donor concentration N D the drift layer 12 is equal to 1.4 × 10 14 / cm 3 is (see Fig. 7 and Fig. 8).

[0077] In the first and second embodiments, the position at which the critical integrated concentration n c is achieved by regulating the positions of the peaks P x controlled. Since the critical integrated concentration n cat the peak P1 in the FS layer 22 is not achieved, the FS layer 22 can be positioned relatively closer to the emitter electrode 52 and formed to have a relatively higher concentration. This can contribute to reducing the oscillation that may occur at the time of switching. This can also reduce the leakage currents and improve the RBSOA. In addition, by controlling the properties for implanting the holes using the collector layer 26, which has a higher impurity concentration than the FS layer 22, the critical electric field strength E c at the position where the critical integrated concentration n cis achieved. As a result, the resistance to large current-induced short circuits can be improved without requiring the FS layer 22 to be positioned closer to the collector electrode 54 than usual and the FS layer 22 to have a lower concentration than usual. Furthermore, the breakdown voltage can also be improved. As described above, the above examples do not require a compromise therebetween and can achieve both the objective of reducing the oscillation that may occur at the time of switching and the like and the objective of improving the resistance to large current-induced short circuits.

[0078] It should be noted that when the IGBT 100 includes the FS layer 22 having multiple impurity concentration peaks therein, as described herein, the drift layer 12 does not have a uniform donor concentration N Din the FS layer 22. The critical integrated concentration n c However, denotes the integral in the first direction in which the depletion layer expands. Thus, the fluctuations in the impurity concentration in the FS layer 22 are included in the integral.

[0079] Furthermore, the constraints on the critical total impurity quantity described above can be applied not only to silicon, but also to wide band-gap semiconductors such as silicon carbide (SiC), gallium nitride (GaN), diamond, and gallium oxide (Ga2O3). Specifically, the impact ionization coefficient of each substance can be used to derive Expression 1, and the relative dielectric constant of the substance used is substituted into Expression 2.

[0080] The operations, procedures, steps, and stages of each process performed by an apparatus, system, program, and method shown in the claims, embodiments, or diagrams may be performed in any order as long as it is not indicated by "before," "previous," or the like, and as long as the output from a previous process is not used in a later process. EXPLANATION OF REFERENCE SYMBOLS

[0081] 10 Semiconductor substrate, 12 Drift layer, 14 First surface, 16 Second surface, 18 Base layer, 19 Front side, 20 Semiconductor layer, 22 FS layer, 24 Buffer layer, 26 Collector layer, 32 Gate electrode, 34 Gate insulating film, 36 Interlayer dielectric film, 42 Contact region, 44 Emitter region, 50 Gate terminal, 51 Emitter terminal, 52 Emitter electrode, 53 Collector terminal, 54 Collector electrode, 100 IGBT

Claims

[1] A semiconductor device (100) comprising: a semiconductor substrate (10) comprising a first semiconductor layer which is of a first conductivity type, a second semiconductor layer which is of a second conductivity type and which is arranged on a front main surface of the first semiconductor layer, and a third semiconductor layer which is of the second conductivity type and which is arranged on a rear main surface of the first semiconductor layer, where the first semiconductor layer in an FS layer has a plurality of impurity concentration peaks which are differently positioned in a first direction extending towards the rear main surface, an integrated concentration obtained by integrating an impurity concentration value of the first semiconductor layer in the first direction toward the back main surface equal to or lower than a critical integrated concentration n c is: nc=Ec(εrε0 / q) where E c the critical electric field strength, ε r is the relative dielectric constant of a semiconductor, ε0 is the dielectric constant of the vacuum and q is the elementary charge, and an impurity concentration at a first impurity concentration peak of the plurality of impurity concentration peaks that is farthest from the back main surface of the first semiconductor layer is higher than an impurity concentration at a second impurity concentration peak of the plurality of impurity concentration peaks that is second farthest from the back main surface of the first semiconductor layer. [2] The semiconductor device (100) according to claim 1, wherein an integrated concentration obtained by integrating the impurity concentration value of the first semiconductor layer in the first direction toward the back main surface up to a boundary between the second impurity concentration peak and a third impurity concentration peak among the plurality of impurity concentration peaks that is third closest to the front main surface is equal to or lower than the critical integrated concentration. [3] The semiconductor device (100) according to claim 2, wherein an integrated concentration obtained by integrating the impurity concentration value of the first semiconductor layer in the first direction toward the back main surface up to a boundary between the third impurity concentration peak and the impurity concentration peak for the impurities is equal to or lower than the critical integrated concentration. [4] The semiconductor device (100) according to claim 2, wherein an integrated concentration obtained by integrating the impurity concentration value in the first direction from the first surface (14) to the third impurity concentration peak is equal to or lower than the critical integrated concentration. [5] The semiconductor device (100) according to claim 2, wherein the first semiconductor layer has, between the back main surface and the impurity concentration peak for the impurities, an impurity concentration peak for the second conductivity type impurity at which an impurity concentration is higher than the impurity concentration peak for the impurities. [6] A semiconductor device (100) according to claim 2, wherein a percentage of (i) a length from a front side (19) of the second semiconductor layer positioned opposite a junction interface to a position of the first impurity concentration peak with respect to (ii) a length in the first direction of the first semiconductor layer and the second semiconductor layer falls within a range higher than 85% and lower than 89%, a percentage of (i) a length from the front side (19) to a position of the second impurity concentration peak with respect to (ii) the length in the first direction of the first semiconductor layer and the second semiconductor layer falls within a range higher than 89% and lower than 91%, a percentage of (i) a length from the front side (19) to a position of the third impurity concentration peak with respect to (ii) the length in the first direction of the first semiconductor layer and the second semiconductor layer falls within a range higher than 96% and lower than 98%, and a percentage of (i) a length from the front side (19) to a position of the impurity concentration peak for the impurities with respect to (ii) the length in the first direction of the first semiconductor layer and the second semiconductor layer falls within a range higher than 98% and lower than 100%. [7] A semiconductor device (100) according to claim 2, wherein the first impurity concentration peak is positioned at a distance in a range greater than 94 µm and less than 97 µm away from a front side (19) of the second semiconductor layer, which is positioned opposite a junction interface, the second impurity concentration peak is positioned at a distance in a range greater than 97 µm and less than 100 µm from the front side (19), the third impurity concentration peak is positioned at a distance in a range greater than 105 µm and less than 108 µm from the front side (19), and the impurity concentration peak for the impurities is positioned at a distance in a range greater than 108 µm and less than 110 µm away from the front side (19). [8] A semiconductor device (100) according to claim 2, wherein a percentage of (i) a length from a front side (19) of the second semiconductor layer positioned opposite a junction interface to a position of the first impurity concentration peak with respect to (ii) a length in the first direction of the first semiconductor layer and the second semiconductor layer falls within a range higher than 77% and lower than 81%, a percentage of (i) a length from the front side (19) to a position of the second impurity concentration peak with respect to (ii) the length in the first direction of the first semiconductor layer and the second semiconductor layer falls within a range higher than 81% and lower than 86%, a percentage of (i) a length from the front side (19) to a position of the third impurity concentration peak with respect to (ii) the length in the first direction of the first semiconductor layer and the second semiconductor layer falls within a range higher than 93% and lower than 97%, and a percentage of (i) a length from the front side (19) to a position of the impurity concentration peak for the impurities with respect to (ii) the length in the first direction of the first semiconductor layer and the second semiconductor layer falls within a range higher than 97% and lower than 100%. [9] A semiconductor device (100) according to claim 2, wherein the first impurity concentration peak is positioned at a distance in a range greater than 54 µm and less than 57 µm away from a front side (19) of the second semiconductor layer positioned opposite the junction interface, the second impurity concentration peak is positioned at a distance in a range greater than 57 µm and less than 60 µm away from the front side (19), the third impurity concentration peak is positioned at a distance in a range greater than 65 µm and less than 68 µm away from the front side (19), and the impurity concentration peak for the impurities is positioned at a distance in a range greater than 68 µm and less than 70 µm away from the front side (19). [10] The semiconductor device (100) of claim 1, further comprising: a gate insulating film (34) formed as a trench in at least a part of the second semiconductor layer; and a gate electrode (32) in contact with the gate insulating film (34). [11] The semiconductor device (100) according to claim 2, wherein donors at each of the first to third impurity concentration peaks include donor complexes of hydrogen, vacancies, and oxygen. [12] The semiconductor device (100) according to any one of claims 1 to 11, wherein the integrated concentration reaches a critical integrated concentration at a position closer to the back main surface than a boundary between the second impurity concentration peak and a third impurity concentration peak among the plurality of impurity concentration peaks which is third closest to the front main surface. [13] A semiconductor device (100) comprising: a first semiconductor layer which is of a first conductivity type and which has a first surface (14) and a second surface (16) positioned opposite the first surface (14); and a second semiconductor layer which is of a second conductivity type and which is in contact with the first surface (14) of the first semiconductor layer, wherein the first semiconductor layer has a plurality of impurity concentration peaks which are differently positioned in a first direction extending from the first surface (14) to the second surface (16), the first semiconductor layer further comprises a plurality of third impurity concentration peaks positioned between (i) a first impurity concentration peak from the plurality of impurity concentration peaks closest to the first surface (14) and (ii) a second impurity concentration peak from the plurality of impurity concentration peaks closest to the second surface (16), the plurality of third impurity concentration peaks have lower impurity concentrations than the first impurity concentration peak and the second impurity concentration peak, the plurality of third impurity concentration peaks having a third impurity concentration peak that is third closest to the first surface (14), and the second impurity concentration peak is an impurity concentration peak for impurities other than protons at a position closer to the second surface (16) than the third impurity concentration peak of the plurality of third impurity concentration peaks.

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