Semiconductor device and method for manufacturing a semiconductor device

Abstract

Semiconductor device (10) comprising the following: a transistor region in which a field-effect transistor is provided; and a connection area in which a metal layer (32, 33) that is electrically connected to the field-effect transistor is provided, the area of ​​connection includes the following: several insulating layers (80, 83, 84, 85) provided between the metal layer (32, 33) and a substrate (53); and a layer with low permittivity (72, 73) provided in the insulating layer (85) under the metal layer (32, 33) and in each further insulating layer (80, 83, 84) and having a lower permittivity than the insulating layer (80, 83, 84, 85); wherein the layer with low permittivity (72,73) is arranged such that it reaches the substrate (53) in a side view.

Description

Technical area

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing a semiconductor device. State of the art

[0002] For example, a field-effect transistor (FET) is used as a switching element in a radio-frequency device. A radio-frequency switch (RF SW) is a switch that turns the transmission and reception of a radio frequency (RF) signal ON or OFF and is primarily used for the front end of a mobile communication terminal, such as a mobile phone.

[0003] In a case where a field-effect transistor is used for a high-frequency switch, it is required that the field-effect transistor reduces the loss of a passing high-frequency signal and does not generate a signal other than the passing high-frequency signal (that is, does not cause distortion of the signal).

[0004] For example, Patent Literature 1 below discloses a technology in which a cavity is formed around a gate electrode of a field-effect transistor, thereby reducing the parasitic capacitance between the gate electrode and a contact plug and reducing the loss of a high-frequency signal passing therethrough.

[0005] Citation list: Patent Literature 1: JP 2002-359369A Patent literature 2: US 2012 / 0 037 962 A1 Patent Literature 3: JP 2009-21269 A Patent literature 4: US 2006 / 0 071 304 A1 Patent literature 5: US 2010 / 0 314 768 A1 Patent literature 6: DE 11 2012 003 959 T5 Disclosure of the inventionTechnical problem

[0006] However, in the technology disclosed in Patent Literature 1, it has been difficult to suppress the generation of a signal other than an input or output signal (that is, distortion of a signal) in a signal that has passed through the field effect transistor.

[0007] Patent Literature 2 describes a semiconductor structure having an air-filled gap at the contact level within the dielectric interlayers above a semiconductor device to minimize parasitic capacitances.

[0008] Patent Literature 3 describes a semiconductor device and a manufacturing method thereof capable of reducing the capacitance between a gate electrode and a contact and the edge capacitance. A field-effect transistor is structured by forming a gate insulating layer and the gate electrode on a semiconductor substrate having a channel formation region, forming a source-drain region on both sides of the gate electrode on the semiconductor substrate, coating the transistor with a first insulating layer, opening contact holes to the source-drain region, embedding contact pins in the holes, and forming an air gap between the gate electrode and the contact pin.

[0009] Patent Literature 4 describes a structure, device, and method for a FET primary cell surrounded by a conductor. The surrounding conductor includes a substrate contact located close to a source of the FET. This contact can act as a ring substrate contact within the FET substrate, electrically connecting to the elongated sources of the FET and serving as a collection source for noise such as stray currents without the need for external contacts.

[0010] Patent Literature 5 describes an interconnect structure within a microelectronic device and a method for fabricating this interconnect structure, which utilize a developable bottom anti-reflection coating layer and at least one imageable interlayer dielectric layer over a substrate comprising a base layer and a first conductor layer embedded therein. By employing the developable bottom anti-reflection coating layer and the imageable interlayer dielectric layer, an opening, such as a dual damascene opening, can be formed through these layers to expose a terminal layer located on the first conductor layer without using a dry plasma etching method when forming the interconnect structure within the microelectronic device.

[0011] Patent Literature 6 describes a semiconductor device comprising an insulator and layers on the insulator. Each of the layers includes a first metal conductor and a second metal conductor positioned adjacent to the first metal conductor. The first metal conductors include a first vertically stacked structure, and the second metal conductors include a second vertically stacked structure. At least one air gap is positioned between the first vertically stacked structure and the second vertically stacked structure.

[0012] Thus, the present disclosure proposes a new and improved semiconductor device capable of suppressing generation of a signal other than an input or output signal, and a method of manufacturing the semiconductor device. Solution to the problem

[0013] According to a first aspect, the present disclosure provides a semiconductor device according to the subject matter of independent claim 1. According to a second aspect, the present disclosure provides a method for manufacturing a semiconductor device according to the subject matter of independent claim 11. Further aspects emerge from the dependent claims, the description and the accompanying figures.

[0014] According to the present disclosure, a semiconductor device is provided, including: a transistor region in which a field-effect transistor is provided; and an interconnection region in which a metal layer electrically connected to the field-effect transistor is provided. The interconnection region includes an insulating layer provided between the metal layer and a substrate, and a low-permittivity layer provided in the insulating layer under the metal layer and having a lower permittivity than the insulating layer.

[0015] In addition, according to the present disclosure, there is provided a method of manufacturing a semiconductor device, including: a step of forming a field-effect transistor in a transistor region; a step of filling, with an insulating layer, a connection region in which a metal layer to be electrically connected to the field-effect transistor is to be provided, and the transistor region; a step of forming, in the insulating layer, a low-permittivity layer having a lower permittivity than the insulating layer; and a step of forming the metal layer on the low-permittivity layer.

[0016] According to the present disclosure, the nonlinear parasitic capacitance generated between a junction and / or an electrode and a substrate in a semiconductor device can be reduced. This can reduce the nonlinearity in an input or output signal of the semiconductor device. Advantageous effects of the invention

[0017] As described above, according to the present disclosure, it is possible to suppress the generation of a signal other than an input or output signal.

[0018] It should be noted that the effects described above are not necessarily limiting. With or instead of the above effects, any of the effects described in this specification or other effects obtainable from this specification may be achieved. Short description of the drawings [ Fig. 1] Fig. 1 is a conceptual diagram illustrating a configuration of a high-frequency switch including a semiconductor device according to an embodiment of the present disclosure. [ Fig. 2] Fig. 2 is a conceptual diagram illustrating a configuration of a high-frequency switch including a semiconductor device according to an embodiment of the present disclosure. [ Fig. 3] Fig. 3 is a circuit diagram of an equivalent circuit of a Fig. 2 shown SPST switch. [ Fig. 4] Fig. Figure 4 is a circuit diagram of an equivalent circuit when the SPST switch is ON. [ Fig. 5] Fig. Figure 5 is a circuit diagram of an equivalent circuit when the SPST switch is OFF. [ Fig. 6] Fig. Figure 6 is an explanatory diagram describing harmonic distortion and intermodulation distortion. [ Fig. 7] Fig. Figure 7 is a conceptual diagram describing a multi-band adapted switching element adapted for both a 3G standard and a 2G standard. [ Fig. 8] Fig. 8 is a plan view illustrating an overall configuration of a semiconductor device according to an embodiment of the present disclosure. [ Fig. 9] Fig. 9 is a cross-sectional view in a stacking direction illustrating a cross-sectional structure of the semiconductor device according to the embodiment. [ Fig. 10] Fig. 10 is an explanatory diagram describing nonlinear capacitances in a semiconductor device. [ Fig. 11] Fig. 11 is a cross-sectional view in a stacking direction of a semiconductor device according to a first structural example. [ Fig. 12A] Fig. 12A is a plan view illustrating an example of a planar arrangement of low permittivity layers of the first structural example. [ Fig. 12B] Fig. 12B is a plan view illustrating an example of a planar arrangement of low permittivity layers of the first structural example. [ Fig. 13] Fig. 13 is a cross-sectional view in a stacking direction of a semiconductor device 10 according to a second structural example. [ Fig. 14A] Fig. 14A is a plan view illustrating an example of an arrangement of low permittivity layers of the second structural example. [ Fig. 14B] Fig. 14B is a plan view illustrating an example of an arrangement of low permittivity layers of the second structural example. [ Fig. 15] Fig. 15 is a cross-sectional view in a stacking direction of a semiconductor device according to a third structural example. [ Fig. 16] Fig. 16 is a cross-sectional view in a stacking direction of a semiconductor device according to a fourth structural example. [ Fig. 17] Fig. 17 is a cross-sectional view in a stacking direction of a semiconductor device according to a fifth structural example. [ Fig. 18] Fig. 18 is a cross-sectional view in a stacking direction of a semiconductor device according to a sixth structural example. [ Fig. 19] Fig. 19 is a cross-sectional view in a stacking direction illustrating a manufacturing process of a semiconductor device according to the embodiment. [ Fig. 20] Fig. 20 is a cross-sectional view in a stacking direction illustrating a manufacturing process of a semiconductor device according to the embodiment. [ Fig. 21] Fig. 21 is a cross-sectional view in a stacking direction illustrating a manufacturing process of a semiconductor device according to the embodiment. [ Fig. 22] Fig. 22 is a cross-sectional view in a stacking direction illustrating a manufacturing process of a semiconductor device according to the embodiment. [ Fig. 23] Fig. 23 is a cross-sectional view in a stacking direction illustrating a manufacturing process of a semiconductor device according to the embodiment. [ Fig. 24] Fig. 24 is a cross-sectional view in a stacking direction illustrating a manufacturing process of a semiconductor device according to the embodiment. [ Fig. 25] Fig. 25 is a cross-sectional view in a stacking direction illustrating a manufacturing process of a semiconductor device according to the embodiment. [ Fig. 26] Fig. 26 is a cross-sectional view in a stacking direction illustrating a manufacturing process of a semiconductor device according to the embodiment. [ Fig. 27] Fig. 27 is a cross-sectional view in a stacking direction illustrating a manufacturing process of a semiconductor device according to the embodiment. [ Fig. 28] Fig. 28 is a cross-sectional view in a stacking direction illustrating a manufacturing process of a semiconductor device according to the embodiment. [ Fig. 29] Fig. 29 is a cross-sectional view in a stacking direction illustrating a manufacturing process of a semiconductor device according to the embodiment. [ Fig. 30] Fig. 30 is a cross-sectional view in a stacking direction illustrating a manufacturing process of a semiconductor device according to the embodiment. [ Fig. 31] Fig. 31 is a block diagram illustrating an example of a wireless communication device that is a use example of a semiconductor device according to the embodiment. Mode(s) of carrying out the invention

[0019] Hereinafter, preferred embodiment(s) of the present disclosure will be described in detail with reference to the attached drawings. Note that in this description and the attached drawings, structural elements having substantially the same function and structure are denoted by the same reference numerals, and repeated explanation of these structural elements will be omitted.

[0020] Please note that the description is given in the following order. 0. Technical background 1. Configuration of the semiconductor device 1.1 First structural example 1.2. Second structural example 1.3 Third structural example 1.4 Fourth structural example 1.5 Fifth structural example 1.6 Sixth structural example 2. Method for manufacturing a semiconductor device 3. Example of use <0. Technical background>

[0021] First, the technical background of the present disclosure will be described with reference to Fig. 1 to Fig. 7 described. Fig. 1 and Fig. 2 are conceptual diagrams illustrating the configurations of high-frequency switches, each of which includes a semiconductor device according to an embodiment of the present disclosure.

[0022] Anyone who Fig. 1 and Fig. The high-frequency switch shown in Figure 2 is used for a front end of a personal digital assistant, such as a mobile phone. High-frequency switches are categorized into various configurations, such as SPST (single-pole single-through), SPDT (single-pole double-through), SP3T, and SPNT (where N is a natural number), based on the number of input or output terminals.

[0023] Fig. 1 shows a configuration example of an SP10T (Single-Pole Ten-Through) switch. As shown in Fig. As shown in Figure 1, an SP10T switch 1 includes a pole connected to an antenna ANT and ten contacts. Fig. 2 shows a configuration example of a SPST (Single-Pole Single-Through) switch. As in Fig. As shown in Figure 2, an SPST switch 1A includes a pole connected to an antenna ANT and a contact that can be switched ON or OFF.

[0024] Fig. 3 is a circuit diagram of an equivalent circuit of the Fig. 2 shown SPST switch 1A. As shown in Fig. For example, as shown in Figure 3, the SPST switch 1A includes a first terminal Port1 connected to the antenna ANT, a second terminal Port2, a first switching element FET1, and a second switching element FET2. Note that the first switching element FET1 is provided between the first terminal Port1 and ground, and the second switching element FET2 is provided between the first terminal Port1 and the second terminal Port2.

[0025] The ON and OFF of the SPST switch 1A are controlled by control voltages Vc1 and Vc2, which are applied via resistors to the gates of the first switching element FET1 and the second switching element FET2, respectively.

[0026] An equivalent circuit when SPST switch 1 is ON or OFF can be as Fig. 4 and Fig. 5, using the resistance value R on (Ω·mm) of the field-effect transistor per unit length, the capacitance value C off (fF / mm) of the field effect transistor per unit length and the gate widths W g1 and W g2 (mm). Fig. 4 is a circuit diagram of an equivalent circuit when the SPST switch 1A is ON, and Fig. Figure 5 is a circuit diagram of an equivalent circuit when the SPST switch is 1AOFF.

[0027] That is, in a case where the SPST switch 1A is in the ON state, as in Fig. 4, the second switching element FET2 is in a conduction state and the first switching element FET1 is in a non-conduction state. On the other hand, in a case where the SPST switch 1A is in the OFF state, as shown in Fig. 5, the first switching element FET1 is in a conduction state and the second switching element FET2 is in a non-conduction state.

[0028] With reference to Fig. 4 and Fig. 5, the ON resistances of the first switching element FET1 and the second switching element FET2 can be defined as R on / W g1 or R on / W g2 Furthermore, the OFF capacitances of the first switching element FET1 and the second switching element FET2 can be expressed as C off *W g1 or C off *W g2 This means that the ON resistance is inversely proportional to the gate widths W g1 and W g2and the OFF capacitance is proportional to the gate widths W g1 and W g2.

[0029] Here, in the high-frequency switch, it is required that no signal other than a passing high-frequency signal be generated (i.e., no signal distortion is caused). In particular, it is required that signal distortions known as harmonic distortion and intermodulation distortion be suppressed.

[0030] Harmonic distortion and intermodulation distortion are now discussed with reference to Fig. 6 described. Fig. Figure 6 is an explanatory diagram describing harmonic distortion and intermodulation distortion.

[0031] In an ideal high-frequency switch, an output signal with a frequency of f1 is output for an input signal with the frequency of f1. However, in an actual high-frequency switch, the ON resistance and OFF capacitance of the field-effect transistor exhibit nonlinearity, therefore, as shown in (A) of Fig. 6, distortions of a signal, such as f2 and f3, are generated in an output signal.

[0032] More precisely, as in (A) of Fig. 6, in a case where a signal with a specific frequency f1 has passed through a non-linear circuit, an N-th harmonic distortion with an N-fold frequency f n(= Nf1) (where N is a natural number greater than or equal to 2) in addition to a fundamental signal with the frequency of f1 are included in an output signal. Specifically, among harmonic distortions, it is required that second harmonic distortion with twice the frequency f2 (= 2f1) and third harmonic distortion with three times the frequency f3 (= 3f1) be suppressed, as they have a significant impact on the transmission and reception signals of communication devices.

[0033] Furthermore, as in (B) of Fig. As shown in Figure 6, in a case where two input signals with frequencies of f1 and f2 pass through a nonlinear circuit and two second harmonics with frequencies of 2f1 and 2f2 are generated, third-order intermodulation distortions (IM3) with frequencies of 2f1 - f2 and 2f2 - f1 are generated due to intermodulation between the second harmonics and the input waves. Similarly, fifth-order intermodulation distortions (IM5) with frequencies of 3f1 - 2f2 and 3f2 - 2f1 are generated due to intermodulation between the third harmonics and the second harmonics.

[0034] The generation of intermodulation distortion is described in more detail using mathematical formulas. An output signal from a nonlinear circuit can be expressed by a Taylor expansion, as shown, for example, in Formula 1 below, as the sum of zeroth-order and first-order terms, which are linear terms, and second- and subsequent-order terms, which are nonlinear terms. V0=f(Vi)=a0+a1Vi+a2Vi2+a3Vi3+⋯

[0035] Here, if two input signals V1 and V2 represented by formula 2 below are substituted for V0, formula 3 below is given. V1=E1cosω1t V2=E2cosω2t V0=a0+a1⋅E1⋅cosω1t+a2⋅E2⋅cosω2t+a22(E12+E22)+a22(E12⋅cos2ω1t+E22⋅cos2ω2t)+a2⋅E1⋅E2{cos(ω1−ω2)t+cos(ω1+ω2)t}+a3(34E13+32E1⋅E22)⋅cosω1t+a3(34E23+32E12⋅E2)⋅cosω2t−a34E13⋅cos3ω1t−a34E23⋅cos3ω2t+34a3⋅E12⋅E2{cos(2ω1−ω2)t−cos(2ω1+ω2)t}+34a3⋅E1⋅E22{cos(2ω2−ω1)t−cos(2ω2+ω1)t}+…

[0036] As shown in Formula 3, it can be seen that signals with frequencies of 2ω1 - ω2 and 2ω2 - ω1, which are not contained in the input signal V1 or V2, are contained in the output signal V0 from the nonlinear circuit. That is, these signals with frequencies of 2ω1 - ω2 and 2ω2 - ω1 correspond to the third-order intermodulation distortions described above. Similarly, fifth-order intermodulation distortions are also assumed to be generated from harmonic distortions of the input signals. Therefore, it can be seen that, in a nonlinear circuit, a signal with a frequency not originally contained in an output signal is generated inside the circuit.

[0037] To suppress the influence of such harmonic distortion and intermodulation distortion generated from a nonlinear circuit, one proposed approach is to use a filter (e.g., a bandpass filter or the like) that attenuates frequencies other than the output signal frequency. However, such a method has been difficult to adequately suppress the influence of harmonic distortion and intermodulation distortion on the output signal.

[0038] The above will now be discussed with reference to Fig. 7 specifically described. Fig. Figure 7 is a conceptual diagram describing a multi-band adapted switching element adapted for both the 3G standard and the 2G standard.

[0039] As in Fig. As shown in Figure 7, a switching element 1B switches between a circuit of the 3G standard (for example, W-CDMA, Wideband Code-Division Multiple Access, or the like) that receives a received signal Rx1 and transmits a transmitted signal Tx1, and a circuit of the 2G standard (for example, GSM, Global System for Mobile Communications, or the like) that receives a received signal Rx2 and transmits a transmitted signal Tx2. In the circuit of the 2G standard, the transmitted and received signals are sorted by another switching element 7, and in the circuit of the 3G standard, the transmitted and received signals are sorted by a duplexer 5, which allows only the frequency bands of the transmitted and received signals to pass through.

[0040] For example, consider a case where duplexer 5 allows 1950 MHz to pass through as the transmission signal frequency and 2140 MHz to pass through as the reception signal frequency. Here, in a case where a transmission signal of 1950 MHz and an interference signal of 1760 MHz simultaneously enter switching element 1B, a signal with a frequency of 2140 MHz (= 2 × 1950 - 1760), which is close to the reception signal, is generated as third-order intermodulation distortion. Such third-order intermodulation distortion passes through duplexer 5 and thus becomes a noise source for the reception signal.

[0041] In particular, the 3G standard circuit is always in the ON state, unlike the 2G standard circuit, whose ON and OFF are switched by the switching element 7. Therefore, in a case where intermodulation distortion is generated at a frequency similar to the frequency of the transmission or reception signal, the generated intermodulation distortion passes through the duplexer 5 in the 3G standard circuit and flows into a transmission or reception circuit.

[0042] Therefore, even when using a filter that attenuates signals with frequencies outside a specified frequency band, it has been difficult to sufficiently suppress the influence of harmonic distortion and intermodulation distortion. Therefore, a switching element with low nonlinearity has been desired, in which harmonic distortion and intermodulation distortion are less likely to be generated.

[0043] A semiconductor device according to an embodiment of the present disclosure can reduce nonlinearity in the semiconductor device by reducing the nonlinear parasitic capacitance generated between an interconnection and / or an electrode and a substrate. Therefore, the semiconductor device according to the present embodiment can suppress the generation of harmonic distortion and intermodulation distortion in an output signal. <1. Configuration of the semiconductor device>

[0044] Next, the structure of a semiconductor device according to the present embodiment will be described with reference to Fig. 8 and Fig. 9 described. Fig. 8 is a plan view illustrating the overall configuration of a semiconductor device according to the present embodiment.

[0045] As in Fig. As shown in FIG. 8, a semiconductor device 10 according to the present embodiment includes, for example, a field-effect transistor for a high-frequency device included in the first or second switching element FET1 or FET2 in the SPST switch 1A. Furthermore, the field-effect transistor included in the semiconductor device 10 includes a gate electrode 20, a source electrode 30S, and a drain electrode 30D.

[0046] The gate electrode 20 includes a plurality of finger portions 201 extending in the same direction (for example, a Y direction) and a linking portion 202 that links the plurality of finger portions 201, and has a so-called multi-finger structure. The gate width W gThe gate electrode 20 can be set as large as approximately several hundred micrometers to several millimeters for a field-effect transistor used for a logic circuit or the like to reduce the loss of the field-effect transistor, and the length (finger length) L21 of the finger portion 201 can be several dozen micrometers. Furthermore, the link portion 202 is connected to a gate contact (not illustrated).

[0047] Note that, in the following, a description will be given by assuming the direction in which the finger portion 201 of the gate electrode 20 extends as a Y direction, the longitudinal direction of the interconnection portion 202 as an X direction, and the direction (stacking direction) orthogonal to both directions as a Z direction.

[0048] The source electrode 30S includes, similar to the gate electrode 20, a plurality of finger portions 301S extending in the same direction (e.g., the Y direction), and a link portion 302S connecting the plurality of finger portions 301S. Furthermore, the link portion 302S is connected to a source contact (not illustrated).

[0049] The drain electrode 30D includes, similar to the gate electrode 20, a plurality of finger portions 301D extending in the same direction (e.g., the Y direction), and a link portion 302D connecting the plurality of finger portions 301D. Furthermore, the link portion 302D is connected to a drain contact (not illustrated).

[0050] Here, the finger portion 201 of the gate electrode 20, the finger portion 301S of the source electrode 30S, and the finger portion 301D of the drain electrode 30D are arranged within an active region AA. Furthermore, the finger portion 301S of the source electrode 30S and the finger portion 301D of the drain electrode 30D are alternately arranged between the finger portions 201 of the gate electrode 20. On the other hand, the connecting portion 202 of the gate electrode 20, the connecting portion 302S of the source electrode 30S, and the connecting portion 302D of the drain electrode 30D are arranged in an element isolation region outside the active region AA.

[0051] Fig. 9 is a cross-sectional view in the stacking direction illustrating a cross-sectional structure of the semiconductor device according to the present embodiment. As shown in Fig. As shown in Figure 9, the semiconductor device 10 according to the present embodiment includes, for example, a field-effect transistor and a metal layer electrically connected to a gate electrode, a source electrode, and / or a drain electrode of the field-effect transistor. Specifically, the semiconductor device 10 includes the gate electrode 20, a semiconductor layer 50, contact plugs 60S and 60D, the source electrode 30S, the drain electrode 30D, metal layers 32 and 33, and low-permittivity layers 71, 72, and 73.

[0052] The gate electrode 20 is provided on the semiconductor layer 50 via a gate oxide film 23. The gate electrode 20 has a thickness of, for example, 150 nm to 200 nm and may include polysilicon or the like. The gate oxide film 23 has a thickness of, for example, 5 nm to 10 nm and may include silicon oxide (SiO2).

[0053] The semiconductor layer 50 may contain, for example, silicon (Si). A source region 50S and a drain region 50D containing n-type (n+) silicon are formed in the semiconductor layer 50 on both sides of the gate electrode 20.

[0054] Furthermore, low-resistance regions 51S and 51D containing high-concentration n-type (n++) silicon or silicide are formed on the surfaces of the source region 50S and the drain region 50D in contact with the contact plugs 60S and 60D for connection to the contact plugs 60S and 60D. Furthermore, extension regions 52S and 52D containing low-concentration n-type (n-) silicon are formed in the semiconductor layer 50 between the source region 50S and the gate electrode 20 and between the drain region 50D and the gate electrode 20.

[0055] Furthermore, an element isolation layer 56 is formed in the semiconductor layer 50 outside the source region 50S and the drain region 50D. The element isolation layer 56 may contain, for example, silicon oxide (SiO2) or the like.

[0056] The semiconductor layer 50 is formed, for example, via an embedded oxide film 54 on a support substrate 53. The support substrate 53, the embedded oxide film 54, and the semiconductor layer 50 may form a silicon-on-insulator (SOI) substrate 55. The support substrate 53 may be, for example, a low-resistance silicon substrate, and the embedded oxide film 54 may contain, for example, SiO2.

[0057] The contact plugs 60S and 60D are connected to the low-resistance regions 51S and 51D formed in the source region 50S and the drain region 50D. Each of the contact plugs 60S and 60D may, for example, include a stacked structure (not illustrated) of a titanium (Ti) layer, a titanium nitride (TiN) layer, and a tungsten (W) layer from the low-resistance regions 51S and 51D side. The titanium layer may reduce the contact resistance between the contact plugs 60S and 60D and the underlying low-resistance regions 51S and 51D, and the titanium nitride layer may suppress the diffusion of the tungsten layer provided on the upper side of the titanium nitride layer to the silicon.

[0058] The source electrode 30S and the drain electrode 30D are formed to be stacked on the contact plug 60S and the contact plug 60D. Note that the source electrode 30S and the drain electrode 30D may be referred to as a first metal M1. Both the source electrode 30S and the drain electrode 30D (the first metal M1) have a thickness of, for example, 500 nm to 1000 nm and may contain aluminum (Al).

[0059] A first insulating layer 81, a second insulating layer 82, a third insulating layer 83, a fourth insulating layer 84, a fifth insulating layer 85, a sixth insulating layer 86, and a seventh insulating layer 87 protect the respective configurations of the semiconductor device 10 and ensure insulation between respective ones of the configurations. The first insulating layer 81, the third insulating layer 83, the fourth insulating layer 84, the fifth insulating layer 85, the sixth insulating layer 86, and the seventh insulating layer 87 may contain, for example, SiO2. Note that hereinafter, the third insulating layer 83 and the fourth insulating layer 84 may be collectively referred to as an interlayer insulating layer 80.

[0060] Here, the second insulating layer 82 contains a material having a different etching rate than the third insulating layer 83 and the fourth insulating layer 84. This is to prevent excessive etching progress when the later-described layers 71, 72, and 73 are formed. For example, in a case where the third insulating layer 83 and the fourth insulating layer 84 contain SiO2, the second insulating layer 82 may contain silicon nitride (Si3N4 or the like).

[0061] Each of the low-permittivity layers 71, 72, and 73 is a layer having a lower permittivity than the third insulating layer 83, the fourth insulating layer 84, and the fifth insulating layer 85. More specifically, each of the low-permittivity layers 71, 72, and 73 may be a cavity. Furthermore, each of the low-permittivity layers 71, 72, and 73 may be a layer containing a material having a lower permittivity than the third insulating layer 83, the fourth insulating layer 84, and the fifth insulating layer 85. The low-permittivity layer 71 is formed in a region between the source electrode 30S and the drain electrode 30D in the XY direction in the plane of the semiconductor layer 50. Furthermore, the low permittivity layers 72 and 73 are formed in regions under the metal layers 32 and 33, respectively, in the Z direction (stacking direction).Thereby, the semiconductor device 10 can reduce the nonlinear parasitic capacitance and can therefore reduce the nonlinearity of the semiconductor device 10.

[0062] In a case where the third insulating layer 83, the fourth insulating layer 84, and the fifth insulating layer 85 contain SiO2 (where the relative permittivity is 4.1), examples of the material that can form the low-permittivity layers 71, 72, and 73 include SiOC (where the relative permittivity is, for example, 2.5) in which Si-CH3 is introduced into a SiO2-based material, inorganic or organic spin-on glass (SOG) (where the relative permittivity is, for example, less than or equal to 3), and the like.

[0063] Each of the metal layers 32 and 33 is, for example, a connection layer and / or a pad electrode electrically connected to the gate electrode 20, the source electrode 30S, or the drain electrode 30D of the field-effect transistor. The metal layers 32 and 33 may be referred to as a second metal and a third metal from the bottom, depending on the positions where they are formed. Fig. 9, metal layer 32 corresponds to the second metal, and metal layer 33 corresponds to the third metal. Metal layers 32 and 33 may contain, for example, aluminum (Al).

[0064] It should be noted that although the above describes a case where the support substrate 53 of the SOI substrate 55 of the semiconductor device 10 is a high-resistance silicon substrate, the technology according to the present disclosure is not limited to the above. In the semiconductor device 10, for example, the support substrate 53 may be formed on a substrate containing sapphire (a so-called silicon-on-sapphire (SOS) substrate). Since a sapphire substrate has insulating properties, a field-effect transistor formed on an SOS substrate can obtain characteristics close to those of a field-effect transistor based on a compound such as GaAs. Furthermore, the semiconductor device 10 according to the present embodiment may be formed on a bulk substrate other than an SOI substrate or an SOS substrate.

[0065] The reduction in the nonlinearity of the semiconductor device 10 described above will now be described with reference to Fig. 10 described. Fig. 10 is an explanatory diagram describing nonlinear capacitances in the semiconductor device 10.

[0066] As in Fig. As shown in Figure 10, in the semiconductor device 10, the interface between the support substrate 53 and the embedded oxide film 54 included in the SOI substrate 55 is positively charged due to defects in the embedded oxide film 54. Therefore, electrons in the support substrate 53 are attracted to the interface between the support substrate 53 and the embedded oxide film 54, and some electrons are trapped in defects in the embedded oxide film 54.

[0067] Here, in a case where an RF signal has passed through each of the metal layers 32 and 33 located on the upper side of the SOI substrate 55, defects in the embedded oxide film 54 repeat the capture and release of trapped electrons. In this case, the parasitic capacitances between the support substrate 53 and the metal layers 32 and 33 fluctuate, and therefore, nonlinearity in the capacitance occurs.

[0068] One possible measure to reduce such nonlinearity is to reduce the parasitic capacitances between the support substrate 53 and the metal layers 32 and 33, thus reducing the absolute values ​​of the nonlinear capacitances. In the semiconductor device 10 according to the present embodiment, portions of the insulating layers located between the support substrate 53 and the metal layers 32 and 33 (i.e., the interlayer insulating layer 80 and the fifth insulating layer 85) are replaced with low-permittivity layers 72 and 73 having a lower permittivity; thereby, the absolute values ​​of the parasitic capacitances between the support substrate 53 and the metal layers 32 and 33 are reduced, and the nonlinearity is reduced.

[0069] Hereinafter, specific arrangements of the low permittivity layers 72 and 73 in the semiconductor device 10 according to the present embodiment will be described with reference to Fig. 11 to Fig. 18, with an individual description for a first to sixth structural example. (1.1 First structural example)

[0070] First, a first structural example of the semiconductor device 10 according to the present embodiment will be described with reference to Fig. 11 to Fig. 12B. Fig. 11 is a cross-sectional view in the stacking direction of the semiconductor device 10 according to the first structural example, and Fig. 12A and Fig. 12B are plan views illustrating examples of a planar arrangement of low permittivity layers of the first structural example.

[0071] As in Fig. 11, a plurality of low-permittivity layers 72 may be formed under the metal layer 32. For example, in a case where a low-permittivity layer 72 is formed in the entire projection area of ​​the metal layer 32 when a plan view of the support substrate 53 is viewed, the strength of the semiconductor device 10 may be reduced. In particular, in a case where the low-permittivity layer 72 is a void, the strength of the semiconductor device 10 is very likely to be reduced. Therefore, by separately forming a plurality of low-permittivity layers 72 under the metal layer 32, the metal layer 32 can be supported by the interlayer insulating layer 80 between adjacent ones of the low-permittivity layers 72.This allows the capacitance between the metal layer 32 and the support substrate 53 to be reduced while maintaining the strength of the semiconductor device 10.

[0072] Here, as in Fig. 12A, the planar arrangement of low-permittivity layers 72 may be striped. Note that the direction in which the low-permittivity layer 72 extends may be a direction parallel to the connection direction of the metal layer 32 or a direction perpendicular to the connection direction of the metal layer 32. However, in order to improve the strength of the semiconductor device 10, the length by which the low-permittivity layer 72 is extended is preferably shorter. Therefore, the direction in which the low-permittivity layer 72 extends is preferably a direction perpendicular to the connection direction of the metal layer 32.

[0073] Furthermore, as in Fig. As shown in Figure 12B, the planar arrangement of low-permittivity layers 72 may be staggered or zigzag. In such a case, the length by which the low-permittivity layer 72 is extended is shortened, and low-permittivity layers 72 are sparsely arranged throughout the metal layer 32; thus, the strength of the semiconductor device 10 can be improved while maintaining the volume of formed low-permittivity layers 72. Furthermore, by shortening the length by which the low-permittivity layer 72 is extended, electric fields can be prevented from traveling around the low-permittivity layer 72. (1.2 Second structural example)

[0074] Next, a second structural example of the semiconductor device 10 according to the present embodiment will be described with reference to Fig. 13 to Fig. 14B. Fig. 13 is a cross-sectional view in the stacking direction of the semiconductor device 10 according to the second structural example, and Fig. 14A and Fig. 14B are plan views illustrating examples of an arrangement of low permittivity layers of the second structural example.

[0075] As in Fig. 13, a plurality of low-permittivity layers 72A and 72B may be formed separately. Specifically, a first insulating layer 81, a second insulating layer 82A, an interlayer insulating layer 80A, and a fifth insulating layer 85A are formed on the element insulating layer 56, and the low-permittivity layers 72A are formed in the interlayer insulating layer 80A and the fifth insulating layer 85A. Further, a second insulating layer 82B, an interlayer insulating layer 80B, and a fifth insulating layer 85B are formed on the fifth insulating layer 85A, and the low-permittivity layers 72B are formed in the interlayer insulating layer 80B and the fifth insulating layer 85B. Further, a metal layer 32 is formed on the fifth insulating layer 85B.

[0076] This allows the distance between the metal layer 32 and the support substrate 53 to be lengthened, and thereby further reduces the parasitic capacitance between the metal layer 32 and the support substrate 53. Furthermore, in such a case, it is preferable that the low-permittivity layer 72A and the low-permittivity layer 72B be arranged such that their positions do not overlap when viewed from a top view of the support substrate 53. This is because the strength of the semiconductor device 10 may be locally reduced at a location where the low-permittivity layer 72A and the low-permittivity layer 72B overlap.

[0077] Here, as in Fig. 14A, the planar arrangement of the low-permittivity layers 72A and 72B may be striped. As described above, the direction in which the low-permittivity layers 72A and 72B extend may be a direction parallel to the connection direction of the metal layer 32 or may be a direction perpendicular to the connection direction of the metal layer 32. However, in order to improve the strength of the semiconductor device 10, the direction in which the low-permittivity layers 72A and 72B extend is preferably a direction perpendicular to the connection direction of the metal layer 32. Furthermore, when a plan view of the support substrate 53 is viewed, it is preferable that the low-permittivity layers 72A and 72B are arranged such that a low-permittivity layer 72B is located between low-permittivity layers 72A.

[0078] Furthermore, as in Fig. 14B, the planar arrangement of the low-permittivity layers 72A and 72B may be staggered. In such a case, the length by which the low-permittivity layers 72A and 72B are extended is shortened, and low-permittivity layers 72 are sparsely arranged throughout the metal layer 32; thus, the strength of the semiconductor device 10 can be improved while maintaining the volume of formed low-permittivity layers 72A and 72B. Furthermore, in a case where the length by which the low-permittivity layers 72A and 72B are extended is short, electric fields can be prevented from circulating around the low-permittivity layer 72. Further, it is preferable that each of the low-permittivity layers 72A and 72B be arranged at the same interval.In such a case, the formation of the low permittivity layers 72A and 72B can be easily performed. (1.3 Third structural example)

[0079] Next, a third structural example of the semiconductor device 10 according to the present embodiment will be described with reference to Fig. 15 described. Fig. 15 is a cross-sectional view in the stacking direction of the semiconductor device 10 according to the third structural example.

[0080] As in Fig. As shown in Figure 15, the low-permittivity layer 72 may be formed to pierce up to the support substrate 53. More specifically, the low-permittivity layer 72 is formed to pierce through the fifth insulating layer 85, the interlayer insulating layer 80, the second insulating layer 82, the first insulating layer 81, the element insulating layer 56, and the embedded oxide film 54, and reach the support substrate 53.

[0081] In such a case, the volume of the low-permittivity layer 72 can be increased, thereby reducing the average permittivity between the metal layer 32 and the support substrate 53; thereby further reducing the parasitic capacitance between the metal layer 32 and the support substrate 53. Furthermore, the interface area between the support substrate 53 and the embedded oxide film 54 can be reduced, thereby reducing the amount of positive charge carried in the embedded oxide film 54.

[0082] It should be noted that the planar arrangement of the low permittivity layers 72 in the third structural example may be any arrangement and may be striped or staggered as shown in the first structural example. (1.4 Fourth structural example)

[0083] Next, a fourth structural example of the semiconductor device 10 according to the present embodiment will be described with reference to Fig. 16 described. Fig. 16 is a cross-sectional view in the stacking direction of the semiconductor device 10 according to the fourth structural example.

[0084] As in Fig. 16, the low-permittivity layer 73 may be further formed between the metal layer 33 and the metal layer 32 in the semiconductor device 10. More specifically, the seventh insulating layer 87 is formed on the metal layer 32 (corresponding to the second metal) using a material (silicon nitride or the like) similar to the material of the second insulating layer 82. Further, an eighth insulating layer 88 and a ninth insulating layer 89 using silicon oxide or the like are formed on the seventh insulating layer 87, and the low-permittivity layer 73 is formed in the eighth insulating layer 88 and the ninth insulating layer 89. Further, the metal layer 33 (corresponding to the third metal) is formed on the ninth insulating layer 89, and the metal layer 33 is embedded in a tenth insulating layer 90 containing silicon oxide or the like.

[0085] In such a case, by reducing the average permittivity between the metal layer 32 and the metal layer 33, the low-permittivity layer 73 can reduce the parasitic capacitance between the metal layer 32 and the metal layer 33. The parasitic capacitance between the metal layer 32 and the metal layer 33 does not exhibit nonlinearity, but causes a loss of a signal passing through the metal layer 32 or the metal layer 33. Thus, the loss of the semiconductor device 10 can be further reduced by reducing the parasitic capacitance between the metal layer 32 and the metal layer 33. (1.5 Fifth structural example)

[0086] Next, a fifth structural example of the semiconductor device 10 according to the present embodiment will be described with reference to Fig. 17 described. Fig. 17 is a cross-sectional view in the stacking direction of the semiconductor device 10 according to the fifth structural example.

[0087] As in Fig. As shown in Figure 17, the low-permittivity layers 72 and 73 are formed at least in the projection regions of the metal layers 32 and 33 when viewed from a top view of the support substrate 53. Furthermore, the low-permittivity layer 72 may be formed in the adjacent interlayer insulating layer 80, including immediately below the metal layer 32, and the low-permittivity layer 73 may be formed in the adjacent eighth insulating layer 88, including immediately below the metal layer 33.

[0088] This is because the parasitic capacitance between the metal layer 32 and the support substrate 53 is influenced not only by the interlayer insulating layer 80 of the region immediately below the metal layer 32 (that is, the projection region of the metal layer 33 when a plan view of the support substrate 53 is viewed), but also by the permittivity of the adjacent interlayer insulating layer 80. Furthermore, this is because a parasitic capacitance is generated between the metal layer 32 and the metal layer 33 even in a case where the metal layer 32 is present in a region near the region immediately below the metal layer 33.

[0089] In a case where the low-permittivity layer 72 is formed in the adjacent interlayer insulating layer 80 including immediately below the metal layer 32, the parasitic capacitance having nonlinearity between the metal layer 32 and the support substrate 53 can be reduced. Furthermore, in a case where the low-permittivity layer 73 is formed in the adjacent eighth insulating layer 88 including immediately below the metal layer 33, the parasitic capacitance between the metal layer 32 and the metal layer 33 can be reduced. Note that the planar arrangement of the low-permittivity layers 72 and 73 in the fifth structural example may be any arrangement, and may be arranged in a stripe-like manner or staggered as shown in the second structural example. (1.6 Sixth structural example)

[0090] Next, a sixth structural example of the semiconductor device 10 according to the present embodiment will be described with reference to Fig. 18 described. Fig. 18 is a cross-sectional view in the stacking direction of the semiconductor device 10 according to the sixth structural example.

[0091] As in Fig. 18, low-permittivity layers 72 and 74 may be formed between a metal layer 34, which is a pad electrode, and the support substrate 53. More specifically, the low-permittivity layer 72 is formed in the interlayer insulating layer 80, on the second insulating layer 82, and in the fifth insulating layer 85. Furthermore, the low-permittivity layer 74 is formed in the eighth insulating layer 88, on the seventh insulating layer 87, and in the ninth insulating layer 89. Furthermore, the metal layer 34, which is a pad electrode, is formed on the ninth insulating layer 89, and the metal layer 34 is embedded in the tenth insulating layer 90.

[0092] In such a case, the low-permittivity layers 72 and 74 can reduce the parasitic capacitance exhibiting nonlinearity between the metal layer 34, which is a pad electrode, and the support substrate 53. This can reduce the nonlinear capacitance of the semiconductor device 10. Note that the planar arrangement of the low-permittivity layers 72 and 74 in the sixth structural example can be any arrangement and can be arranged in a stripe-like manner or in a staggered manner, as shown in the third structural example. <2. Method for manufacturing a semiconductor device>

[0093] Next, a method of manufacturing the semiconductor device 10 according to the present embodiment will be described with reference to Fig. 19 to Fig. 30 described. Fig. 19 to Fig. 30 are cross-sectional views in the stacking direction illustrating the manufacturing process of the semiconductor device 10 according to the present embodiment.

[0094] First, as in Fig. As shown in Figure 19, the SOI substrate 55, in which the embedded oxide film 54 and the semiconductor layer 50 are formed on the support substrate 53, is prepared. In the semiconductor layer 50 of the SOI substrate 55, the element isolation layer 56 is formed by, for example, the STI method or the LOCOS method, and a transistor region separated by the element isolation layer 56 is formed.

[0095] Next, for example, an implantation via film (not illustrated) of a silicon oxide film is formed by the thermal oxidation method or the like, and well implantation and channel implantation are performed on the transistor region where the silicon oxide film is formed. Note that the implantation via film is removed after the well implantation and channel implantation are performed.

[0096] Then, as in Fig. As shown in Fig. 20, the gate oxide film 23 containing silicon oxide is formed to a thickness of, for example, 5 nm to 10 nm by the thermal oxidation method or the like. Thereafter, a gate electrode material film (not illustrated) containing polysilicon is formed to a thickness of, for example, 150 nm to 200 nm by the chemical vapor deposition (CVD) method or the like. Further, the gate electrode material film is processed by photolithography and etching, and thereby the gate electrode 20 is formed on the semiconductor layer 50 via the gate oxide film 23.

[0097] Next, as in Fig. 21, using the gate electrode 20 and an offset spacer (not illustrated) as a mask, an implantation IMPL of arsenic (As) or phosphorus (P) is performed, and the extension regions 52S and 52D are formed on both sides of the gate electrode 20. Further, a sidewall (not illustrated) is formed on the side surface of the gate electrode 20, and then an implantation of arsenic (As) or phosphorus (P) is performed. Thereby, the source region 50S and the drain region 50D are formed in the semiconductor layer 50 on both sides of the gate electrode 20. The sidewall is removed after the source region 50S and the drain region 50D are formed.

[0098] Then, as in Fig. 22, after the source region 50S and the drain region 50D are formed, the first insulating layer 81 containing silicon oxide is formed to a thickness of, for example, 10 nm to 30 nm on the gate electrode 20 and the semiconductor layer 50 by the CVD method or the like.

[0099] Next, as in Fig. As shown in Figure 23, the second insulating layer 82 containing silicon nitride (Si3N4 or the like) is formed to a thickness of, for example, 5 nm to 30 nm on the first insulating layer 81 by the CVD method or the like. Note that silicon nitride has a different etching rate than silicon oxide and can therefore prevent excessive etching progress during the etching of the third insulating layer 83 and the fourth insulating layer 84, which will be described later.

[0100] Then, as in Fig. 24, the third insulating layer 83 containing silicon oxide is formed to a thickness of, for example, 500 nm to 1000 nm on the second insulating layer 82 by the CVD method or the like.

[0101] Next, as in Fig. As shown in Figure 25, after the third insulating layer 83 is formed, portions of the third insulating layer 83, the second insulating layer 82, and the first insulating layer 81 are removed by photolithography and etching, and a contact hole (not illustrated) is formed on each of the source region 50S and the drain region 50D. After the contact holes are formed, an implantation IMPL with high concentration arsenic (As) or phosphorus (P) is performed over the contact holes, thereby forming the low-resistance regions 51S and 51D.

[0102] After the low-resistance regions 51S and 51D are formed, contact plugs 60S and 60D, each comprising a stacked structure of a titanium layer, a titanium nitride layer, and a tungsten layer, are formed in the contact holes. Note that the contact plugs 60S and 60D are formed on the source region 50S and the drain region 50D.

[0103] Then, as in Fig. As shown in Fig. 26, the source electrode 30S and the drain electrode 30D containing aluminum (Al) (corresponding to the first metal M1) are formed on the contact plugs 60S and 60D. Further, after the source electrode 30S and the drain electrode 30D are formed, the fourth insulating layer 84 containing silicon oxide is formed on the third insulating layer 83, the source electrode 30S, and the drain electrode 30D by the CVD method or the like.

[0104] Next, as in Fig. As shown in Figure 27, after the fourth insulating layer 84 is formed, openings P1, P2, and P3 are formed by photolithography and dry etching. The opening P1 is formed in a region of the semiconductor layer 50 between the source electrode 30S and the drain electrode 30D. Furthermore, the openings P2 and P3 are formed in regions where the metal layers 32 and 33 will be formed in subsequent processes. Note that the width of each of the openings P1, P2, and P3 can be, for example, 100 nm to 1000 nm.

[0105] In this case, the second insulating layer 82 acts as an etching stopper; thus, the etching of the openings P1, P2, and P3 proceeds to pierce the fourth insulating layer 84 and the third insulating layer 83 containing silicon oxide and stops at the upper surface of the second insulating layer 82.

[0106] Then, as in Fig. As shown in Fig. 28, the fifth insulating layer 85 containing silicon oxide is formed on the fourth insulating layer 84 by the CVD method or the like. The fifth insulating layer 85 is deposited to cover the upper sides of the openings P1, P2, and P3. Thus, before the openings P1, P2, and P3 are filled with the fifth insulating layer 85, the upper sides of the openings P1, P2, and P3 are sealed, and the low-permittivity layers 71, 72, and 73, which are spaces, are formed in the interiors of the openings P1, P2, and P3. Note that the side surface and the bottom surface of each of the openings P1, P2, and P3 may be covered with the fifth insulating layer 85.

[0107] Therefore, in a case where the low-permittivity layers 71, 72, and 73 are formed simultaneously, at least the upper ends or the lower ends of the low-permittivity layers 71, 72, and 73 are provided in the same layer. In the case where the low-permittivity layers 71, 72, and 73 are formed simultaneously, the manufacturing process of the semiconductor device 10 can be simplified.

[0108] Each of the low-permittivity layers 71, 72, and 73 is, for example, a cavity and therefore has a lower permittivity than the third insulating layer 83, the fourth insulating layer 84, and the fifth insulating layer 85 (e.g., silicon oxide). Note that air may be present in each of the low-permittivity layers 71, 72, and 73, or each of them may be a vacuum.

[0109] Furthermore, the low-permittivity layers 71, 72, and 73 can also be formed by filling the interiors of the openings P1, P2, and P3 with a material (e.g., SiOC, inorganic SOG, organic SOG, and the like) that has a lower permittivity than the third insulating layer 83, the fourth insulating layer 84, and the fifth insulating layer 85 (e.g., silicon oxide). For example, the low-permittivity layers 71, 72, and 73 can be formed by filling the openings P1, P2, and P3 with SiOC by the CVD method or the like. Furthermore, the low-permittivity layers 71, 72, and 73 can be formed by filling the openings P1, P2, and P3 with inorganic or organic SOG by the spin-coating method or the like.

[0110] Next, as in Fig. As shown in Figure 29, the metal layer 32 containing aluminum (Al) is formed in a region on the fifth insulating layer 85 and above the area where the low-permittivity layer 72 is formed. The metal layer 32 is an interconnection layer to be connected to any of the various electrodes of field-effect transistors and corresponds to the second metal. Furthermore, the sixth insulating layer 86 containing silicon oxide is formed on the metal layer 32 and the fifth insulating layer 85 by the CVD method or the like.

[0111] Then, as in Fig. As shown in Figure 30, the metal layer 33 containing aluminum (Al) is formed in a region on the sixth insulating layer 86 and above the region where the low-permittivity layer 73 is formed. The metal layer 33 is an interconnection layer, a pad electrode, or the like to be connected to any of the various electrodes of field-effect transistors and corresponds to the third metal. Furthermore, the seventh insulating layer 87 containing silicon oxide is formed on the metal layer 33 and the sixth insulating layer 86 by the CVD method or the like.

[0112] Through the above process, the semiconductor device 10 according to the present embodiment can be manufactured. The semiconductor device 10 according to the present embodiment can reduce the capacitances having nonlinearity between the metal layers 32 and 33, each of which is an interconnection and / or an electrode, and the support substrate 53. This reduces the nonlinearity in the semiconductor device 10 according to the present embodiment; therefore, in a circuit using the semiconductor device 10, the generation of a signal other than an input or output signal (i.e., distortion of a signal) can be suppressed.

[0113] It should be noted that the shape, material, thickness, film forming method, etc. of each of the layers described in the above embodiment are not limited to the above examples, and it is a matter of course that other shapes, materials, thicknesses, and film forming methods may be used. <3. Example of use>

[0114] Further, a usage example of the semiconductor device 10 according to the present embodiment will be described with reference to Fig. 31 described. Fig. 31 is a block diagram illustrating an example of a wireless communication device that is a usage example of the semiconductor device 10 according to the present embodiment.

[0115] As in Fig. As shown in Figure 31, a wireless communication device 3 is, for example, a mobile phone system that has functions such as voice and data communication and local area network (LAN) connection. The wireless communication device 3 includes, for example, an antenna ANT, the high-frequency switch 1, a high-power amplifier HPA, a high-frequency integrated circuit HFIC, a baseband section BB, a voice output section MIC, a data output section DT, and an external interface section I / F (for example, a wireless LAN, Bluetooth (registered trademark), or the like).

[0116] The high frequency switch 1 includes, for example, the high frequency switch which can be used in any of the Fig. 1, Fig. 2 and Fig. 7. Furthermore, the integrated radio frequency circuit HFIC and the baseband section BB are connected to each other by an internal interface.

[0117] In a case where a transmission signal is output from a transmission system in the wireless communication device 3 to the antenna ANT, the transmission signal output from the baseband section BB is output to the antenna ANT via the high-frequency integrated circuit HFIC, the high-power amplifier HPA, and the high-frequency switch 1.

[0118] Furthermore, in a case where a reception signal is input to a reception system in the wireless communication device 3, the reception signal received by the antenna ANT is input to the baseband section BB via the high-frequency switch 1 and the high-frequency integrated circuit HFIC. The reception signal processed by the baseband section BB is output from output sections such as the voice output section MIC, the data output section DT, and the external interface section I / F.

[0119] Note that although the semiconductor device 10 according to the present embodiment is described above as being used for the high-frequency switch 1 of the wireless communication device 3, the technology according to the present disclosure is not limited to the above. For example, the semiconductor device 10 according to the present embodiment can also be used for high-frequency devices other than a high-frequency switch (RF SW), such as an amplifier (power amplifier PA).

[0120] The preferred embodiment(s) of the present disclosure have been described above with reference to the accompanying drawings, although the present disclosure is not limited to the above examples.

[0121] Furthermore, the effects described in this specification are merely illustrative or exemplary effects and are not limiting. That is, the technology according to the present disclosure may achieve other effects with or instead of the above effects, which will be apparent to those skilled in the art from the description of this specification. List of reference symbols 1 high-frequency switch 10 semiconductor device 20 Gate electrode 23 Gate oxide film 30D drain electrode 30S source electrode 32, 33, 34 metal layer 50 semiconductor layer 50D Drain Area 50S Source Area 51D, 51S Low resistance area 52D, 52S expansion area 53 Carrier substrate 54 embedded oxide film 56 Element insulation layer 60D, 60S contact plugs 71, 72, 73 Low permittivity layer 81 first insulation layer 82 second insulation layer 83 third insulation layer 84 fourth insulation layer 85 fifth insulation layer 86 sixth insulating layer 87 seventh insulating layer

Claims

[1] A semiconductor device (10) comprising: a transistor region in which a field-effect transistor is provided; and a connection region in which a metal layer (32, 33) electrically connected to the field effect transistor is provided, where the connection area includes: a plurality of insulating layers (80, 83, 84, 85) provided between the metal layer (32, 33) and a substrate (53); and a low permittivity layer (72, 73) provided in the insulating layer (85) under the metal layer (32, 33) and in each further one of the insulating layers (80, 83, 84) and having a lower permittivity than the insulating layer (80, 83, 84, 85); wherein the low permittivity layer (72,73) is arranged such that it reaches the substrate (53) in a side view. [2] Semiconductor device (10) according to claim 1, wherein several of the low permittivity layers (72,73) are provided and the layers with low permittivity (72,73) are arranged in stripes. [3] Semiconductor device (10) according to claim 1, wherein several of the low permittivity layers (72,73) are provided and the low permittivity layers (72,73) are staggered. [4] The semiconductor device (10) according to claim 1, wherein the low permittivity layers (72, 73) provided in the insulating layers (85) are arranged so as not to overlap when a plan view of the substrate (53) is viewed. [5] A semiconductor device (10) according to claim 4, wherein the low permittivity layers (72,73) provided in the insulating layers (85) are staggered when viewing a plan view of the substrate (53). [6] Semiconductor device (10) according to claim 1, wherein a top metal layer (33) is further provided over an inter-metal insulating layer (86, 87) on the metal layer (32) and a low-permittivity inter-metal layer (73) having a lower permittivity than the inter-metal insulating layer (86, 87) is provided in the inter-metal insulating layer (86, 87) between the metal layer (32) and the top-side metal layer (33). [7] The semiconductor device (10) according to claim 1, wherein the low permittivity layer (72, 73) is provided at least in a projection region of the metal layer (32, 33) when a plan view of the substrate (53) is viewed. [8] A semiconductor device (10) according to claim 1, wherein the metal layer (32, 33) is a connection or an electrode electrically connected to the field effect transistor. [9] Semiconductor device (10) according to claim 1, wherein several of the low permittivity layers (72,73) are provided and at least the upper ends or the lower ends of the low permittivity layers (72,73) are provided in the same layer. [10] A semiconductor device (10) according to claim 1, wherein the field effect transistor is a field effect transistor for a high frequency device. [11] A method of manufacturing a semiconductor device (10), comprising: a step of forming a field effect transistor in a transistor region; a step of filling, with a plurality of insulating layers (80, 83, 84, 85), a connection region in which a metal layer (32, 33) to be electrically connected to the field effect transistor is to be provided, and the transistor region; a step of forming, in the insulating layers (80, 83, 84, 85), a low-permittivity layer (72, 73) having a lower permittivity than the insulating layer (80, 83, 84, 85), such that the low-permittivity layer (72, 73) is arranged to reach the substrate (53) in a side view; and a step of forming the metal layer (32, 33) on the low permittivity layer (72, 73).

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