Semiconductor device and method for producing the same

Abstract

Semiconductor unit (101 to 105) comprising: - an insulating substrate (13, 14) comprising an insulating plate (6), a first conductive plate (5) arranged on one surface of the insulating plate, and a second conductive plate (7) arranged on the other surface of the insulating plate; - a sintered metal (22); - a semiconductor element (11) arranged on the first conductive plate through the sintered metal, the semiconductor element (11) having a crack propagation rate in depth of 30% or less, the crack propagation rate defining a ratio of a depth (d) of a crack (K) to the chip thickness (L) on a percentage basis, and having a thickness of 0.05 mm or more and 0.1 mm or less; - a connecting material (23); and - a cooling device (12) connected to the second conductive plate by the connecting material, wherein the semiconductor element (11) is adapted to absorb thermal stresses resulting from a difference between thermal expansion coefficients between the semiconductor element (11) and the cooling device (12), wherein the semiconductor element (11) has a degree of flexural strength of 700 MPa or more, wherein the sintered metal (22) has a thickness of 3 µm or more and 100 µm or less, and wherein the semiconductor element (11) has a semiconductor base (11a) made of SiC.

Description

TECHNICAL FIELD

[0001] The present invention relates to semiconductor devices and methods for producing the same. STATE OF THE ART

[0002] Semiconductor units used as power modules use semiconductor elements made of materials such as silicon (Si) or silicon carbide (SiC). Heat from such an element, whose temperature must be maintained at or below a specified temperature, should be efficiently dissipated.

[0003] With regard to heat dissipation, a power module has been conventionally proposed that includes a cooling device connected to the semiconductor element, with an insulating substrate interposed therebetween. The insulating substrate has a one-piece structure consisting of an insulating ceramic plate with high thermal conductivity and conductive plates made of a metal with high thermal conductivity arranged on both surfaces of the insulating ceramic plate.

[0004] The insulating ceramic plate is made of, for example, silicon nitride, aluminum nitride, or aluminum oxide. The conductive plate is made of, for example, aluminum (including an aluminum alloy or the like) or copper (including a copper alloy or the like).

[0005] The semiconductor element is bonded to one surface of the insulating substrate, with a sintered metal, such as sintered Ag, interposed between them. The cooling device is directly or indirectly bonded to the other surface of the insulating substrate, with a bonding material, such as solder, interposed between them.

[0006] Meanwhile, semiconductor elements have been proposed for reducing the deformation of a resin sealing the semiconductor device. This deformation results, for example, from temperature changes in the external environment. For example, a semiconductor element with a bending strength of 100 MPa or more and 1000 MPa or less is provided as a stress relief device.

[0007] A stress relief device according to Patent Document 1 is composed of a semiconductor element disposed on a main surface of an insulating substrate and having a degree of bending strength of 100 MPa or more and 1000 MPa or less.

[0008] Patent Document 2 relates to a power module including a power module substrate on which a circuit layer is disposed.

[0009] Patent Document 3 describes a semiconductor substrate having a first surface and a second surface, wherein a support substrate is attached to the first surface of the semiconductor substrate.

[0010] Patent Document 4 teaches a method to improve the quality of wafer dicing to reduce cracking and chipping. PRIOR ART DOCUMENTPatent document Patent document 1: JP 2015- 15 412 A Patent document 2: US 2011 / 0 074 010 A1 Patent document 3: US 2015 / 0 243 592 A1 Patent document 4: US 2006 / 0 172 509 A1 BRIEF DESCRIPTIONProblem to be solved by the invention

[0011] The above-mentioned configuration may not be able to maintain sufficient heat dissipation performance over a required lifetime, even if it has been designed with heat dissipation in mind. Such a malfunction is caused by thermal stresses induced by a difference between the thermal expansion coefficients of the semiconductor element and the cooling device under certain operating conditions, and is caused by cracking in the semiconductor element or the bonding material between the semiconductor element and the cooling device due to the resulting thermal stresses.

[0012] For example, Patent Document 1 discloses a semiconductor device including a stress relief device. Such a semiconductor device has a problem in a direct cooling module, which includes a cooling device and an insulating substrate directly connected to each other with solder. The insulating substrate is provided with a sintered Ag region that is connected to the semiconductor element (e.g., a SiC chip).

[0013] Typically, SiC is desirably insensitive to a transition temperature higher than that of Si. Heating cycles with repeated high and low temperatures result in a temperature of 175°C or higher at the time of the high temperature. The sintered Ag region may exhibit cracking when operated in such heating cycles.

[0014] In order to solve this problem, the object of the present invention is to provide a semiconductor device having a high thermal conductivity and a high productivity, and to provide a method for producing such a semiconductor device. Means of solving the problem

[0015] The present object is achieved by a semiconductor unit according to claim 1 and by a method according to claim 5. Advantageous developments of the semiconductor unit according to the invention are specified in dependent claims 2 to 4. An advantageous development of the method according to the invention is specified in dependent claim 6. Effects of the invention

[0016] The semiconductor device according to the present invention absorbs thermal stresses in the semiconductor element resulting from a difference between the linear thermal expansion coefficient of the semiconductor element and the thermal expansion coefficient of the cooling device. This relieves stresses induced in the bonding material and achieves high productivity while maintaining high thermal conductivity. The method for manufacturing a semiconductor device according to the present invention contributes to the manufacture of the semiconductor device according to the present invention.

[0017] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The figures show: Fig. 1 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment; Fig. 2 to 5 are cross-sectional views of respective successive steps for manufacturing a semiconductor element; Fig. 6 is a cross-sectional view of a step after the semiconductor element is manufactured and before the semiconductor unit is formed; Fig. 7 graphs showing relations between the lifetime of a substrate bonding material and linear expansion coefficients of an insulating substrate; Fig. 8 is a SAT image showing delamination in the substrate bonding material; Fig. 9 is a cross-sectional view of a semiconductor element 11 after dicing as viewed through a microscope; Fig. 10 is a cross-sectional view of the semiconductor element 11 after chip separation as viewed through a microscope; Fig. 11 graphs showing relations between cumulative failure rates and degrees of flexural strength of the semiconductor element; Fig. 12 are graphs showing degrees of voltage applied to the semiconductor element in the semiconductor device; Fig. 13 graphs showing relationships between chip singulation states and crack propagation rates into depth; Fig. 14 is a cross-sectional view showing the structure of a semiconductor device according to a second embodiment; Fig. 15 is a cross-sectional view of one of successive steps for manufacturing the semiconductor device according to the second embodiment; Fig. 16 is a cross-sectional view of another of successive steps for manufacturing the semiconductor device according to the second embodiment; Fig. 17 is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment; Fig. 18 is a cross-sectional view showing the structure of another semiconductor unit according to the third embodiment; Fig. 19 is a cross-sectional view showing the structure of a semiconductor unit according to a fourth embodiment; Fig. 20 to 22 are cross-sectional views of respective successive steps for manufacturing the semiconductor device according to the fourth embodiment. DESCRIPTION OF AN EMBODIMENT(S)First Embodiment

[0019] Fig. 1 is a cross-sectional view of the structure of a semiconductor device 101 according to a first embodiment. The semiconductor device 101 includes a semiconductor element 11, a substrate bonding material 22, an insulating substrate 13, a connecting material 23, and a cooling device 12.

[0020] The semiconductor element 11 is bonded to one surface of the insulating substrate 13 by the substrate bonding material 22. The cooling device 12 is bonded to the other surface of the insulating substrate 13 by the bonding material 23. The insulating substrate 13 includes an insulating ceramic 6 acting as an insulating plate, a conductive plate 5 disposed on one surface of the insulating ceramic 6, and a conductive plate 7 disposed on the other surface of the insulating ceramic 6.

[0021] In other words, the insulating substrate 13 includes the conductive plates 5 and 7, and the insulating ceramic 6 sandwiched between the conductive plate 5 and the conductive plate 7. These components are preliminarily integrated with a material such as wax to form the insulating substrate 13.

[0022] The conductive plate 5 is in contact with the substrate bonding material 22. Thus, the semiconductor element 11 is arranged on the conductive plate 5 by the substrate bonding material 22 and is specifically connected to the conductive plate 5. Note that the semiconductor element 11 can be connected to the insulating substrate 13 by a direct bonding process, such as solid-phase Cu diffusion bonding or ultrasonic bonding, without the substrate bonding material 22. The conductive plate 7 faces the cooling device 12 and is connected to the cooling device 12 by the bonding material 23.

[0023] The semiconductor element 11 includes a semiconductor base 11a and a wiring electrode 11b electrically connected to the semiconductor base 11a. The semiconductor element 11 further includes an external output electrode 11c on the back surface of the semiconductor element 11 (hereinafter referred to as a "second main surface") that is opposite to a surface (hereinafter referred to as a "first main surface") provided with the wiring electrode 11b (in the drawing, the second surface is located at the bottom).

[0024] The semiconductor base 11a is made of SiC, for example. SiC is a so-called wide-bandgap semiconductor. Using a wide-bandgap semiconductor, which has a wider bandgap than Si, as the semiconductor base 11a is advantageous for increasing the electric field strength of the semiconductor element 11 against dielectric breakdown and for operating the semiconductor element 11 at a high temperature of 175°C or higher. The following describes a case where the semiconductor base 11a is made of SiC.

[0025] The wiring electrode 11b is formed, for example, from a metal layer containing one of Cu, Al, AlSi, Ni, and Au, or a combination of these metal layers. In the present embodiment, the external output electrode 11c on the rear side is formed, for example, from a metal layer containing one of Al, AlSi, Ni, and Au, or a combination of these metal layers.

[0026] The substrate bonding material 22 can be made, for example, from a low-temperature sintered material containing silver nanoparticles, from a liquid-phase diffusion bonding material (such as Cu-Sn or Ag-Sn), or from a bonding material that is a good electrical conductor and a good thermal conductor, such as solder. The following describes a case where the substrate bonding material 22 is made of a sintered metal. An example of the sintered metal is sintered Ag.

[0027] The semiconductor element 11 absorbs thermal stresses caused during a heating cycle test by a difference in the thermal expansion coefficients between the semiconductor element 11 and the cooling device 12. If the semiconductor device 101 as a whole warps or buckles, the substrate bonding material 22 also warps or buckles and thus exhibits stresses. The substrate bonding material 22 must be insensitive to these stresses.

[0028] If the substrate bonding material 22 has a thickness of less than 3 µm, it is not resistant to the stresses induced during the heating cycle test, resulting in cracking. Thus, the substrate bonding material 22 with a thickness of less than 3 µm lacks sufficient strength. If the substrate bonding material 22 has a thickness of more than 100 µm, cracking may occur during its manufacturing processes.

[0029] Accordingly, the substrate bonding material 22 desirably has a thickness of 3 µm or more to have sufficient strength, and desirably has a thickness of 100 µm or less to avoid cracking during its manufacturing processes.

[0030] The conductive plates 5 and 7 can each be formed, for example, from a conductor such as copper or aluminum. If the conductive plates 5 and 7 are made of copper, they each have a thickness of 0.2 to 1.0 mm and a linear expansion coefficient of 17 ppm, for example.

[0031] The insulating ceramic 6 can be formed from a ceramic, for example, silicon nitride, aluminum nitride, or aluminum oxide, which are electrical insulators and good thermal conductors. When the insulating ceramic 6 is made of silicon nitride, for example, it has a thickness of 0.1 mm to 1.00 mm and a linear expansion coefficient of 2.5 ppm. The insulating substrate 13 as a whole, which includes the conductive plates 5 and 7, is believed to have a linear expansion coefficient of 5.7 ppm to 8.9 ppm, for example.

[0032] The bonding material 23 may be made, for example, of a low-temperature sintered material containing silver nanoparticles, a liquid-phase diffusion bonding material (such as Cu-Sn or Ag-Sn), or a bonding material that is a good thermal conductor, such as solder. For a solder bond, the yield strength of a solder material is desirably considered, and a high-strength solder, such as Sn-Cu-Sb, is preferably used.

[0033] The cooling device 12 is made of a metal material with good thermal conductivity, such as copper or aluminum.

[0034] Such a configuration provides low thermal resistance from the semiconductor element 11 to the cooling device 12. Thus, the heat generated by the semiconductor element 11 is transferred to the cooling device 12 thanks to high heat transfer performance. Furthermore, plastic deformation of the semiconductor element 11 absorbs most of the thermal stress resulting from the difference in thermal expansion coefficients between the semiconductor element 11 and the cooling device 12. This sufficiently improves the reliability of a connection between the insulating substrate 13 and the cooling device 12.

[0035] With reference to the Fig. 2 to 5, steps for manufacturing the semiconductor element 11 and, in particular, steps for manufacturing the semiconductor element 11 with a thickness t of 100 µm or less are described below in a simple manner. Fig. 2 to 5 are cross-sectional views of successive steps for manufacturing the semiconductor element 11. First, a device surface is formed on the first main surface. The device surface is, for example, a source surface in a MOSFET. In this step (see Fig. 2) the wiring electrode 11b is formed.

[0036] Next, the second main surface is subjected to grinding so that the semiconductor base 11a has a thickness of, for example, 50 µm or more and 100 µm or less. The grinding is performed, for example, by means of a grinding device using a grindstone containing vitrified bonded diamond abrasive grains. During grinding, the first main surface of the semiconductor base 11a is subjected to the application of a protective strip to protect the device surface from grinding. Alternatively, the first main surface may be subjected to the application of wax or other types of application, followed by the application of a support substrate to protect the device surface.

[0037] After grinding, a metal layer 11d is deposited on the second main surface to form a silicide. The metal layer 11d is made of Ni, for example. Next, the metal layer 11d undergoes a reaction with the semiconductor base 11a to form a silicide layer, and a contact electrode is formed. This reaction is performed by irradiating the metal layer 11d with laser light.

[0038] Next, a surface of the contact electrode is subjected to an etching process to remove an oxide layer and other deposits on the surface. The etching is performed, for example, by dry etching with Ar. + -ions. It is possible that part of the metal layer 11d remains unreacted.

[0039] After removing the oxide layer on the surface, the external output electrode 11c is formed on the back surface of the contact electrode ( Fig. 5) For simplicity, the contact electrode is omitted from the drawing. The way in which the external output electrode 11c is formed on the backside significantly affects its adhesion. In the present embodiment, the external output electrode 11c is formed on the backside by DC sputtering. The electric current used in this process results in a deposition temperature of 100°C or higher.

[0040] Typically, a plurality of semiconductor elements 11 are fabricated on the same semiconductor wafer. Fig. 2 to 5 illustrate steps for manufacturing one of the plurality of semiconductor elements 11, which are manufactured in parallel. The semiconductor wafer serves as the semiconductor base 11a of the plurality of semiconductor elements 11. Immediately after manufacturing, the plurality of semiconductor elements 11 are coupled together with the semiconductor base 11a interposed therebetween. Accordingly, the coupled semiconductor elements 11 are subjected to chip dicing into individual pieces.

[0041] Fig. 6 is a cross-sectional view of a step after the manufacture of each semiconductor element 11 and before the completion of the semiconductor unit 101. The insulating substrate 13 is prepared, which, as mentioned above, is formed from the conductive plates 5 and 7 and the insulating ceramic 6 as they were previously integrated with each other. Then, the semiconductor element 11 is bonded to the conductive plate 5 on the second main surface by the substrate bonding material 22. The cooling device 12 is bonded to the conductive plate 7 by the bonding material 23. As mentioned above, the semiconductor unit 101 is manufactured ( Fig. 1). That is, these manufacturing steps contribute to the manufacture of the semiconductor device 101.

[0042] During a heating cycle test, a difference in the linear expansion coefficients between the cooling device 12, which is a good thermal conductor, and the insulating substrate 13 and the semiconductor element 11 typically causes warping or buckling in the semiconductor device 101. Accordingly, greater warping or buckling causes greater stresses to be induced in the substrate bonding material 22.

[0043] In a direct cooling module structure in the present embodiment, the cooling device 12 is directly bonded to the bonding material 23, an example of which is solder. Furthermore, the cooling device 12 is bonded to the insulating substrate 13, which includes the semiconductor element 11, through the bonding material 23 as a substrate bond. Therefore, the difference in the linear expansion coefficients between the cooling device 12 and the insulating substrate 13 and the semiconductor element 11 is likely to cause warping or distortion.

[0044] In a typical module structure, a copper base plate (not shown) is bonded to the cooling device 12 by grease. The base plate is further bonded to the insulating substrate 13, which includes the semiconductor element 11, by a bonding material such as solder. Thus, the grease and the base plate reduce the warping or distortion resulting from the difference in the linear expansion coefficient between the cooling device 12 and the insulating substrate 13 and the semiconductor element 11, thereby reducing the warping or distortion compared to a direct cooling module structure. In other words, the substrate bonding material 22 has low stresses.

[0045] A calculation is described below to obtain a linear expansion coefficient for the insulating substrate 13 that is desirable for reduced stresses in the substrate bonding material 22.

[0046] Fig. 7 illustrates graphs showing relationships between the lifetime of the substrate bonding material 22 and the linear expansion coefficient of the insulating substrate 13 as a whole, which is bonded to the semiconductor element 11 by the substrate bonding material 22. The graphs employ the thickness t of the semiconductor element 11 as a parameter in the relationships and provide cases where its values ​​are equal to 100 µm, 200 µm, and 300 µm.

[0047] Note that these graphs are the results of an analysis performed using computer-aided engineering (CAE). Sintered Ag is used as the substrate bonding material 22. The insulating substrate 13 is bonded to the semiconductor element 11 by the substrate bonding material 22. The cooling device 12 is bonded to the insulating substrate 13 by the bonding material 23.

[0048] The horizontal axis in Fig. 7 denotes the linear expansion coefficient of the insulating substrate 13 as a whole (in the drawing, only "linear expansion coefficient of the insulating substrate 13" is formulated) in the unit ppm. The vertical axis in Fig. 7 denotes the lifetime of the substrate bonding material 22, that is, the number of cycles performed until the substrate bonding material 22 malfunctions during a heating cycle test. The heating cycle test is a temperature cycle test in which the temperature of the external environment of the semiconductor device 101 changes from -(minus)40°C to 175°C to -(minus)40°C again.

[0049] In the following description, the cooling device 12 used in the direct cooling module structure is made of Al and has a linear expansion coefficient of 23 ppm; further, the semiconductor element 11 is made of SiC and has a linear expansion coefficient of 4.6 ppm.

[0050] The larger the linear expansion coefficient of the insulating substrate 13, the smaller the difference in the linear expansion coefficients between the insulating substrate 13 and the cooling device 12. Thus, the bonding material 23 located between the insulating substrate 13 and the cooling device 12 exhibits lower stresses. However, the larger the linear expansion coefficient of the insulating substrate 13, the greater the difference in the linear expansion coefficients between the insulating substrate 13 and the semiconductor element 11.

[0051] Thus, the substrate bonding material 22 exhibits greater stresses resulting from warping or buckling in the insulating substrate 13. Consequently, the larger the coefficient of linear expansion of the insulating substrate 13, the shorter the lifetime of the substrate bonding material 22.

[0052] Conversely, the smaller the linear expansion coefficient of the insulating substrate 13, the greater the stresses of the bonding material 23 due to warping or buckling in the cooling device 12 and the lower the stresses of the substrate bonding material 22. Thus, the substrate bonding material 22 has a longer service life.

[0053] As far as improving the lifetime of the substrate bonding material 22 is concerned, the semiconductor element 11, when it contains, for example, SiC, has a linear expansion coefficient of 4.6 ppm, and the insulating substrate 13 advantageously has a linear expansion coefficient closer to 4.6 ppm. Note that the cooling device 12, when it contains, for example, Al, has a linear expansion coefficient of 23 ppm.

[0054] Accordingly, when the insulating substrate 13 has a linear expansion coefficient closer to that of the semiconductor element 11, it causes a larger difference in the linear expansion coefficients between the insulating substrate 13 and the cooling device 12, and thus the connecting material 23 has larger stresses due to warping or buckling in the cooling device 12.

[0055] As in Fig. 7, a test calculation within a range that does not affect the bonding material 23 revealed that the difference in the linear expansion coefficients of the insulating substrate 13 has little effect on the heating cycle life of the substrate bonding material 22.

[0056] The graphs showed that a reduction in the thickness t of the semiconductor element 11 increases the lifetime of the substrate bonding material 22 at the respective Fig. 7 is improved. This is because the thinner the semiconductor element 11 is, the more the semiconductor element 11 is likely to follow the warping or buckling in the cooling device 12, thus relieving the stresses induced in the substrate bonding material 22. Accordingly, the thickness of the semiconductor element 11 in the semiconductor device 101 is desirably reduced to improve the durability of the substrate bonding material 22.

[0057] Fig. 8 is a scanning acoustic tomography (SAT) image showing delamination occurring in the substrate bonding material 22. This delamination is caused by a heating cycle test. In this SAT image, the semiconductor device 101 is viewed from the first main surface of the semiconductor element 11. Regions 11g at the corners of the semiconductor element 11 have white areas indicative of a delamination state.

[0058] The depth position of the SAT image is predetermined by the position of the substrate bonding material 22. Accordingly, these white areas reflect the state of delamination of the substrate bonding material 22. The thickness t of the semiconductor element 11 is desirably reduced to increase the number of heating cycles before such delamination occurs in the substrate bonding material 22.

[0059] As from Fig. As can be seen from Figure 7, the heating cycle life is approximately 3,000 to 7,000 cycles when the thickness t is 100 µm; when the thickness t is 200 µm, it is approximately 400 to 600 cycles; and when the thickness t is 300 µm, it is approximately 200 to 300 cycles. That is, the heating cycle life of the substrate bonding material 22 improves by an order of magnitude of one digit when the thickness t is 100 µm compared to the thicknesses t of 200 µm and 300 µm. In contrast, the heating cycle life of the substrate bonding material 22 at a thickness t of 200 µm improves only by a factor of 2 compared to a thickness t of 300 µm.

[0060] Thus, the semiconductor element 11 desirably has a thickness t of 100 µm or less in order to significantly improve the heating cycle life.

[0061] On the other hand, in view of yield in manufacturing processes, the semiconductor element 11 desirably has a thickness t of 50 µm or more. Accordingly, a desirable range of the thickness t of the semiconductor element 11 is 50 µm or more and 100 µm or less (ie, 0.05 mm or more and 0.1 mm or less).

[0062] To accommodate warping or distortion in the cooling device 12, the semiconductor element 11 must withstand the stresses applied to it. Accordingly, a desirable range of bending strength in the semiconductor element 11 is described below.

[0063] The semiconductor element 11 is subjected to 1000 cycles of the heating cycle test as described with reference to Fig. 7. In this case, the semiconductor element 11 exhibits cracking from an edge of the chip when it has a bending strength of 100 MPa to less than 700 MPa. On the other hand, the semiconductor element 11 does not exhibit such cracking when it has a bending strength of 700 MPa or more. Thus, the semiconductor element desirably has a bending strength of 700 MPa or more.

[0064] The bending strength of the semiconductor element 11 is based on the processes for manufacturing the semiconductor element 11 and its thickness t. In particular, the conditions during chip separation of the semiconductor elements 11 are important parameters. Fig. 9 and Fig. 10 are cross-sectional images of the semiconductor element 11 after chip separation as viewed through a microscope. It should be noted that the chip separation conditions vary between a sample in Fig. 9 and a sample in Fig. 10 differ from each other.

[0065] Fig. Figure 9 shows a crack K at the edge. This crack K triggers crack formation during the assessment of flexural strength. The crack K is therefore disadvantageous for improving flexural strength.

[0066] Fig. 10 shows no cracks. The semiconductor element 11 without cracks reduces triggers that lead to destruction during the evaluation of flexural strength. This means that the semiconductor unit 101, which includes the semiconductor element 11, offers high productivity. The sample in Fig. 10 is more desirable for improved flexural strength than the sample in Fig. 9.

[0067] That is, chip singulation is desirably performed in a chip singulation state that does not involve cracks. Specifically, improvement of chip singulation states is achieved by appropriately selecting the types and thicknesses of blades used in chip singulation, the types of a chip singulation strip per se, and the types of adhesive included in the chip singulation strip.

[0068] For example, it is desirable for the blade to have a thin thickness. Such a thin thickness reduces additional cracks caused during chip singulation. Furthermore, it is desirable for the adhesive contained in the chip singulation strip to have a high adhesion. Such a high adhesion prevents the target object (here, the semiconductor element 11) from being deformed by stresses caused during chip singulation using the blade.

[0069] Fig. Figure 11 illustrates graphs showing relationships between the cumulative failure rate and the bending strength of the semiconductor element 11, and illustrates graphs using a so-called Weibull plot. The right vertical axis denotes the cumulative failure rates F(t) of the semiconductor element 11 on a percentage basis. The left vertical axis denotes ln values ​​(ln(1 / (1-F(t))), where the value In represents a natural logarithm, and a value t in the value F(t) represents time. The horizontal axis in Fig. 11 denotes the degree of bending strength of the semiconductor element 11 in the unit MPa.

[0070] Note that a MOSFET made of SiC is used as the semiconductor element 11, and the thickness t of the semiconductor element 11 is 100 µm. The degree of bending strength is obtained by a three-point bending strength test. Fig. 11 shows regression lines J1 and J2, each showing the semiconductor element 11 manufactured in a first state during chip singulation and the semiconductor element 11 manufactured in a second state during chip singulation different from the first state during chip singulation.

[0071] In the second stage of chip singulation, the thickness of the blade is thinner, and the adhesive contained in the chip singulation strip has a higher adhesive strength than in the first stage of chip singulation. As indicated by the regression line J1, the semiconductor element 11 manufactured in the first stage of chip singulation has a bending strength of approximately 100 to 800 MPa. As indicated by the regression line J2, the semiconductor element 11 manufactured in the second stage of chip singulation has a bending strength of approximately 700 to 1100 MPa.

[0072] As can be seen from the above, the second die singulation stage has a stronger tendency to obtain the semiconductor element 11 with high bending strength than the first die singulation stage. Furthermore, the difference between regression lines J1 and J2 indicates that the second die singulation stage involves a smaller fluctuation in the degree of bending strength than the first die singulation stage.

[0073] Fig. Figure 12 illustrates graphs showing a degree of stress in a thickness direction (a degree of vertical stress) applied to the semiconductor element 11 in the semiconductor unit 101. These graphs are the results of a calculation performed using a computer-aided engineering (CAE) technique. The vertical axis indicates values ​​for the stress applied to the semiconductor element 11.

[0074] The horizontal axis indicates values ​​for the linear expansion coefficient of the insulating substrate 13, which is bonded to the semiconductor element 11 by the substrate bonding material 22. Note that the thickness t of the semiconductor element 11 is a parameter, and its values ​​are equal to 100 µm, 200 µm, and 300 µm.

[0075] The calculation results in Fig. 12 revealed that the value of the stress applied to the semiconductor element 11 is less than 400 MPa in terms of the linear expansion coefficient at any thickness t of the semiconductor element 11. Accordingly, the semiconductor element 11 is presumed to have cracking if it has a degree of flexural strength of less than 400 MPa; further, the semiconductor element 11 is presumed to have no defects if it has a degree of flexural strength of 400 MPa or more.

[0076] The calculation results in Fig. 12 are consistent with the fact that the semiconductor element 11, when it has a degree of flexural strength of 700 MPa or more, does not have defects such as cracking even after 1000 cycles of the heating cycle test.

[0077] The calculation results also showed that the smaller the thickness t, the higher the stress the semiconductor element 11 absorbs. In other words, the smaller the thickness t, the higher the bending strength the semiconductor element 11 must have. As described with reference to Fig. 7, the heating cycle life of the substrate bonding material 22 improves the more the thickness t is smaller.

[0078] Furthermore, the semiconductor element 11 with the cumulative failure rates F(t) in the graphs in Fig. 11 has a thickness t of 100 µm. Accordingly, the semiconductor element 11 further desirably has a degree of flexural strength of 1000 MPa or more in view of manufacturing variations.

[0079] Fig. Figure 13 illustrates graphs showing relationships between chip singulation conditions and crack propagation rates in depth. Each crack propagation rate in depth indicates the size of a crack induced in the final surface of a chip after chip singulation. Referring to Fig. 9, each crack propagation rate in depth is defined as a ratio of the depth d of the crack to the thickness L of the chip on a percentage basis (100 x d / L[%]). Terms “before an improvement” and “after an improvement” in Fig. 13 correspond to the first state during chip singulation and the second state during chip singulation.

[0080] As from Fig. As can be seen in Figure 13, the crack propagation rates in the second state during chip singulation are lower than in the first state during chip singulation. The crack propagation rates in the first state during chip singulation are above 30%, which indicates a reduction in strength in Fig. 11. Accordingly, the crack propagation rate into depth must be equal to or less than 30%.

[0081] The semiconductor unit 101 absorbs the thermal stresses in the semiconductor element 11 resulting from the difference between the linear thermal expansion coefficient of the semiconductor element 11 and the linear thermal expansion coefficient of the cooling device 12. This relieves the stresses induced in the connecting material 23.

[0082] As a result, the semiconductor device 101 is achieved, which has high thermal conductivity, high productivity, and high reliability. Furthermore, the lower limit on the thickness of the semiconductor element 11 does not degrade the yield of the semiconductor element 11 during manufacturing processes, thus avoiding any disruptive increase in costs. Second embodiment

[0083] Fig. 14 is a cross-sectional view of the structure of a semiconductor unit 102 according to a second embodiment. Unlike the structure of the semiconductor unit 101 in the first embodiment, the semiconductor unit 102 has a structure in which the insulating substrate 13 is replaced with an insulating substrate 14. The other components are the same as those of the semiconductor unit 101. Note that this drawing does not differentiate the semiconductor base 11a, the wiring electrode 11b, and the external output electrode 11c on the back side in the semiconductor element 11.

[0084] The insulating substrate 14 includes the insulating ceramic 6, copper plates 51 and 71, and aluminum plates 52 and 72. The copper plates 51 and 71 are made of copper. The aluminum plates 52 and 72 are made of aluminum.

[0085] The aluminum plates 52 and 72 are in contact with the insulating ceramic 6. The copper plate 51 and the copper plate 71 are in contact with the aluminum plate 52 and the aluminum plate 72, respectively. The aluminum plate 52 is sandwiched between the insulating ceramic 6 and the copper plate 51. The aluminum plate 72 is sandwiched between the insulating ceramic 6 and the copper plate 71. The copper plate 51 is bonded to the semiconductor element 11 by the substrate bonding material 22. The copper plate 71 is bonded to the cooling device 12 by the bonding material 23.

[0086] Accordingly, the copper plate 51 and the aluminum plate 52 as a whole can be regarded as the conductive plate 5, following the first embodiment. Similarly, the copper plate 71 and the aluminum plate 72 as a whole can be regarded as the conductive plate 7, following the first embodiment.

[0087] As described above, the conductive plate 7 has a stacked structure of copper, which has high thermal conductivity, and aluminum, which is susceptible to plastic deformation. Such a conductive plate 7 improves the reliability of a connection between the insulating substrate 14 and the cooling device 12 compared with a conductive plate 7 made solely of copper. This improvement is suitable for manufacturing the cooling device 12 using aluminum.

[0088] This is because thermal stresses are applied evenly to the elements sandwiching the connecting material 23, ie, the cooling device 12 and the conductive plate 7. Such an effect is particularly noticeable when the connecting material 23 is made of a solder.

[0089] It is desirable that the aluminum plate 72 be made of pure aluminum having a purity of at least 99.5% or higher, and preferably having a purity of 99.9% or higher. This allows the linear thermal expansion coefficient of the insulating substrate 14 as a whole to be close to the linear thermal expansion coefficient of aluminum, thus reducing stresses acting on the connecting material 23. Such a reduction in stresses is desirable for improved reliability of a connection between the insulating substrate 14 and the cooling device 12.It is also desirable that the aluminum plate 52 be made of pure aluminum having a purity of at least 99.5% or higher, and preferably having a purity of 99.9% or higher, so that the linear thermal expansion coefficient of the insulating substrate 14 as a whole is close to the linear thermal expansion coefficient of aluminum.

[0090] The Fig. 15 and Fig. 16 are cross-sectional views of successive steps for manufacturing the semiconductor device 102. Referring to Fig. 15, the insulating substrate 14 is first prepared. The term "prepared" here means that the insulating substrate 14 is prepared, which includes an insulating plate, which in this embodiment is the insulating ceramic 6, and the conductive plates 5 and 7 arranged on both surfaces of the insulating ceramic 6, and does not necessarily mean the production of the insulating substrate 14. The cooling device 12 is also prepared at this stage, which is not shown.

[0091] Fig. Fig. 16 illustrates a step in which the semiconductor element 11 is arranged on the insulating substrate 14 (specifically, on the copper plate 51) by the substrate bonding material 22. Then, the cooling device 12 is connected to the copper plate 71 in the insulating substrate 14 by the bonding material 23. The copper plate 71 is located on a side opposite the side on which the semiconductor element 11 is arranged. This results in the Fig. Configuration shown in Figure 14. Third embodiment

[0092] Fig. 17 is a cross-sectional view of the structure of a semiconductor unit 103 according to a third embodiment. Unlike the semiconductor unit 101 according to the first embodiment, the semiconductor unit 103 has a configuration in which both the rear external output electrode 11c and the conductive plate 5 are made of copper, and the substrate bonding material 22 is not included. That is, the rear external output electrode 11c and the conductive plate 5 are connected to each other without the substrate bonding material 22. The other components are the same as those of the semiconductor unit 101.

[0093] In such a configuration, the external output electrode 11c on the rear side and the conductive plate 5 are connected to each other by means of liquid-phase diffusion bonding or solid-phase diffusion bonding. Connection in this manner improves voltage insensitivity. This improves the reliability of the connection between the insulating substrate 13 and the semiconductor element 11.

[0094] Fig. 18 is a cross-sectional view of the structure of another semiconductor unit 104 according to the present embodiment. Unlike the semiconductor unit 102 according to the second embodiment, the semiconductor unit 104 has a configuration in which the external output electrode 11c on the rear side is made of copper and the substrate bonding material 22 is not included. That is, the external output electrode 11c on the rear side and the copper plate 51 are connected to each other without the substrate bonding material 22. The other components are the same as those of the semiconductor unit 102.

[0095] In such a configuration, the external output electrode 11c on the rear side and the copper plate 51 are bonded together by liquid-phase diffusion bonding or solid-phase diffusion bonding. Bonding in this manner improves voltage insensitivity. This improves the reliability of the connection between the insulating substrate 14 and the semiconductor element 11.

[0096] For example, a so-called direct bonded copper method for forming the conductive plate 5 of the insulating substrate 13 or the copper plate 51 of the insulating substrate 14 enables connection of the semiconductor element 11 to the insulating substrate 13 or connection of the semiconductor element 11 to the insulating substrate 14 by means of solid phase diffusion bonding or liquid phase diffusion bonding.

[0097] Of course, the semiconductor element 11 can be bonded to the insulating substrate 13 by the substrate bonding material 22, with the external output electrode 11c on the back and the conductive plate 5 made of copper. The conductive plate 7 can also be made of copper. Fourth embodiment

[0098] Fig. 19 is a cross-sectional view of the structure of a semiconductor unit 105 according to a fourth embodiment. Unlike the semiconductor unit 101 described in the first embodiment, the semiconductor unit 105 additionally includes a conductor 3, a bonding material 4, and a sealing resin 17. Note that the cooling device 12 in the present embodiment includes heat dissipation fins 12a. It should also be noted that this drawing does not differentiate the semiconductor base 11a, the wiring electrode 11b, and the external output electrode 11c on the back side in the semiconductor element 11.

[0099] The bonding material 4 is bonded to the semiconductor element 11 such that it is located away from the substrate bonding material 22 (i.e., the bonding material 4 is bonded to the first main surface). The conductor 3 is bonded to the semiconductor element 11 through the bonding material 4. The sealing resin 17 is disposed on the cooling device 12 and seals the conductor 3, the bonding material 4, the semiconductor element 11, the insulating substrate 13, the substrate bonding material 22, and the bonding material 23.

[0100] With such a configuration, the semiconductor device 105 can operate at a temperature exceeding 175°C, while including the semiconductor element 11 made of SiC. Furthermore, such a configuration reduces thermal resistance between the semiconductor element 11 and the cooling device 12, allowing the semiconductor device 105 to be downsized and thus increasing overall flexibility. This contributes to the downsizing of, for example, an inverter including the semiconductor device 105.

[0101] The Fig. 20 to 22 are cross-sectional views of sequential steps for manufacturing the semiconductor device 105 according to the present embodiment. First, the insulating substrate 13 is prepared, which is formed from the conductive plates 5 and 7 and the insulating ceramic 6 as they have been integrated with each other in advance. Next, the second main surface of the semiconductor element 11 is bonded by the substrate bonding material 22 (see FIG. Fig. 20) is connected to the conductive plate 5. Furthermore, the cooling device 12 is connected by the connecting material 23 (cf. Fig. 21) is connected to the conductive plate 7.

[0102] Subsequently, the connecting material 4 is connected to the first main surface of the semiconductor element 11, and furthermore, the conductor 3 is connected to the connecting material 4 on a side opposite to the side on which the semiconductor element 11 is arranged (see FIG. Fig. 22). The sealing resin 17 is then applied. Through these process steps, the Fig. 19 is achieved. In other words, these process steps contribute to the manufacture of the semiconductor device 105. EXPLANATION OF REFERENCE SYMBOLS 3 conductors 4, 23 Connecting material 5, 7 conductive plate 6 insulating ceramics 11 semiconductor element 11a Semiconductor base 12 Cooling device 13, 14 insulating substrate 17 Sealing resin 22 Substrate bond connection 51, 71 copper plate 52, 72 aluminum plate 101 to 105 semiconductor unit

Claims

[1] Semiconductor unit (101 to 105) comprising: - an insulating substrate (13, 14) comprising an insulating plate (6), a first conductive plate (5) arranged on one surface of the insulating plate, and a second conductive plate (7) arranged on the other surface of the insulating plate; - a sintered metal (22); - a semiconductor element (11) arranged on the first conductive plate through the sintered metal, the semiconductor element (11) having a crack propagation rate in depth of 30% or less, the crack propagation rate defining a ratio of a depth (d) of a crack (K) to the chip thickness (L) on a percentage basis, and having a thickness of 0.05 mm or more and 0.1 mm or less; - a connecting material (23); and - a cooling device (12) connected to the second conductive plate by the connecting material, wherein the semiconductor element (11) is adapted to absorb thermal stresses resulting from a difference between thermal expansion coefficients between the semiconductor element (11) and the cooling device (12), wherein the semiconductor element (11) has a degree of flexural strength of 700 MPa or more, wherein the sintered metal (22) has a thickness of 3 µm or more and 100 µm or less, and wherein the semiconductor element (11) has a semiconductor base (11a) made of SiC. [2] A semiconductor device (101 to 105) according to claim 1, wherein the insulating plate (6) is made of silicon nitride, aluminum nitride or aluminum oxide. [3] Semiconductor unit (102) according to claim 1, wherein the second conductive plate (7) has a stack structure made of copper or an alloy of copper (71) and aluminum or an alloy of aluminum (72). [4] The semiconductor device (102) according to claim 1, wherein the cooling device (12) is made of aluminum or an alloy of aluminum. [5] A method for manufacturing a semiconductor device, comprising the following steps: (a) producing an insulating substrate (13) comprising an insulating plate (6), a first conductive plate (5) arranged on one surface of the insulating plate, and a second conductive plate (7) arranged on the other surface of the insulating plate; (b) disposing a semiconductor element (11) through a sintered metal (22) on the first conductive plate, wherein the semiconductor element has a thickness of 0.05 mm or more and 0.1 mm or less and a crack propagation rate into the depth of 30% or less, wherein the crack propagation rate defines a ratio of a depth (d) of a crack (K) to the thickness (L) on a percentage basis, wherein the semiconductor element (11) is configured to absorb thermal stresses resulting from a difference in thermal expansion coefficients between the semiconductor element (11) and a cooling device (12), wherein the semiconductor element (11) has a degree of flexural strength of 700 MPa or more, wherein the sintered metal (22) has a thickness of 3 µm or more and 100 µm or less, and wherein the semiconductor element (11) has a semiconductor base (11a), which is made of SiC; and (c) connecting the cooling device (12) to the second conductive plate by a first connecting material (23). [6] A method of manufacturing a semiconductor device according to claim 5, further comprising the steps of: (d) connecting a conductor (3) by a second connecting material (4) to the semiconductor element (11) on a side opposite to a side on which the sintered metal (22) is arranged; and (e) sealing the semiconductor element, the insulating substrate (13) and the conductor with a sealing resin (17).

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