Tin-zinc microbump structures and methods for producing the same

Abstract

An integrated circuit, IC, package substrate (100) comprising: a dielectric layer (110) having via holes (112) formed therein, the via holes having a tapered shape; a metal layer (120) underlying a surface plane comprising copper contacts each exposed through one of the via holes, the copper contacts comprising a first copper contact; a first surface finish (114) directly on the first copper contact; a first seed layer (122) deposited on the first copper contact, the first seed layer comprising copper, the first seed layer being deposited on the first surface finish; and a first microbump formed on the first seed layer, the first microbump comprising tin and zinc.

Description

BACKGROUND1. TECHNICAL FIELDEmbodiments of the present invention generally relate to the field of integrated circuit package substrates and more particularly, but not exclusively, to fabrication processing that provides microbump interconnects.2. PRIOR ARTIntegrated circuits are typically formed on a semiconductor wafer made of materials such as silicon. The semiconductor wafer is then processed to form various electronic devices. The wafers are typically singulated into semiconductor chips (a chip is also known as a die) which are then attached to a substrate. The substrate is usually designed to directly or indirectly couple the die to a printed circuit board, socket, or other interconnect. The substrate may also perform one or more functions such as protecting, separating, insulating, and / or thermally controlling the die.The substrate (for example, an interposer) has conventionally been formed of a core composed of a laminated multilayer structure. Micro bumps and other such interconnect structures, as are known from publications US 2013 / 0 082 091 A1, US 2013 / 0 234 323 A1 and U.S. Pat. No. 9 401 350 B1, for example, are usually formed differently in or on the structure in order to enable an electrical coupling of a die to one or more other components. Coreless substrates have been developed to reduce the thickness of the substrate. In a coreless substrate, a removable core layer is typically provided, conductive and dielectric layers are built up on the removable core, and then the core is removed. The coreless substrate typically includes a plurality of vias formed therein as interlayer electrical connections.As successive generations of manufacturing technologies continue to scale, metallurgical properties of various materials have an ever more important impact on the formation and operation of interconnect structures. Accordingly, there is an increased need for incremental improvements in the fabrication of structures for interconnecting microelectronic circuit devices.BRIEF DESCRIPTION OF THE DRAWINGSThe various embodiments of the present invention are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which: FIGS. 1A, 1B are cross-sectional side views of processing to form a microbump according to an embodiment. FIG. 2 is a flow diagram illustrating elements of a method for forming one or more micro bumps, according to an embodiment. FIG. 3 is a cross-sectional diagram of an electronic package including interconnect structures according to an embodiment. FIG. 4 is a functional block diagram illustrating elements of a computing device according to an embodiment. FIG. 5 is a functional block diagram illustrating elements of an example computer system according to an embodiment. FIG. 6 is a cross-sectional view of an interposer according to an embodiment.DETAILED DESCRIPTIONEmbodiments discussed herein provide various techniques and mechanisms for improved metallurgical properties of microbump structures. Some embodiments reduce residual metal precipitation, which could otherwise increase the possibility of unreliable interconnects and / or unintentional conductive paths being formed.For example, in some metallization techniques, copper (Cu) is prone to be drawn from a seed layer and dissolved into an adjacent metal as part of an intermetallic compound (IMC) within a micro bump formed on the seed layer. The IMC is usually split in a subsequent reflow process (reflow process), resulting in a relatively high copper content in or on the microbump itself. Some embodiments reduce the formation of residual copper - which could otherwise form, e.g., as a result of a reflow process - on a micro-bump and / or an adjacent surface. For example, a microbump may comprise a combination of metals that promotes the formation of micro-constituent structures. As a result of an increased volume fraction of such micro-constituents, a micro-bump is relatively more likely to bind copper (as such, copper precipitates as residue on nearby surfaces). The term "microbump" is used variously to refer to either a conductive contact of a device or a solder connection formed from such a conductive contact. Unless otherwise indicated, "solder joint" herein refers to a solder joint formed by soldering with a microbump (such solder joint could also be colloquially referred to as a "microbump").The technologies described herein may be implemented in one or more electronic devices. Non-limiting examples of electronic devices that may utilize the technologies described herein include any type of mobile device and / or stationary device, such as cameras, cellular phones, computer terminals, desktop computers, electronic readers, facsimile machines, kisses, netbook computers, notebook computers, Internet devices, payment terminals, personal digital assistants, media players and / or recorders, servers (e.g., blade servers, frame mounted servers (rack mount servers), combinations thereof, etc.), set-top boxes, smart phones, tablet personal computers, ultra-mobile personal computers, wired phones, combinations thereof, and the like. Such devices may be portable or stationary. In some embodiments, the technologies described herein may be used in a desktop computer, laptop computer, smartphone, tablet computer, netbook computer, notebook computer, personal digital assistant, server, combinations thereof, and the like. More generally, the technologies described herein may be used with any of a variety of electronic devices including a substrate including interconnect structures for providing connectivity to an integrated circuit device.FIG. 2 is a flow diagram of a method 200 for manufacturing substrate structures of a microelectronic component according to another embodiment. To illustrate certain features of various embodiments, the method 200 is described herein with reference to FIGS. 1A, 1B. The cross-sectional views shown in FIGS. 1A, 1B variously illustrate respective stages 100- 105 of a substrate fabrication process, such as method 200, according to an example embodiment. However, in various embodiments, the method 200 may produce other structures other than or in addition to those represented by steps 100- 105. In one embodiment, processing such as that represented by stages 100- 105 and / or methods 200 is intended to form micro bumps-an interposer or other such substrate-that enable coupling to an integrated circuit die.The method 200 may include, at 210, patterning a dielectric layer with a copper contact exposed through an opening formed through the dielectric layer. The dielectric layer may comprise a dry film resist (DFR) or any of a variety of other such materials adapted from conventional substrate fabrication techniques. For example, a dielectric layer (e.g., a material of the dielectric surface layer 110 shown at stage 100) may be laminated or otherwise deposited over a patterned metal layer (e.g., subsurface metal layer 120) in a substrate build-up layer. A dielectric layer 110 and an subsurface metal layer 120 may include some or all of the corresponding features of the dielectric layer 110 and the subsurface metal layer 120.The patterning at 210 may include operations such as laser drilling or otherwise forming one or more openings (e.g., formed by the illustrative via holes 112 shown at step 100) into the dielectric layer (e.g., surface dielectric layer 110) to expose contacts including respective portions of the underlying metal layer 120. According to the invention, the method 200 further comprises, at step 220, forming a surface finish directly on the copper contact. Referring to the illustrative stage 100, forming at 220 may include variously depositing surface finish portions 114 on respective exposed contacts of the subsurface metal layer 120. Surface finish portions 114 may function as corresponding barrier layer regions, for example using electroless plating, PVD (sputtering, for example), or other such processes to form a tin layer (e.g., having a thickness of 3 μm to 7 μm), a palladium layer (e.g., having a thickness of 20 μm to 60 μm), or a gold layer (e.g., having a thickness of 30 μm to 100 μm) on the copper contact. The composition and / or thickness of such a surface finish may be adjusted from conventional techniques in some embodiments.The method 200 may further include, at 230, performing a deposition of a seed layer (e.g., seed layer 122 at stage 101) on the copper contact, wherein the seed layer includes copper. Electroless plating or physical vapor deposition (i.e., sputtering) technique may be used to deposit the seed layer 122, for example. Illustratively, and not by way of limitation, electroless plating of pure copper may form a seed layer having a thickness in a range from 0.3 μm to 1.0 μm. In another embodiment, a combination of copper and titanium (Ti) may be sputtered to form a seed layer having a thickness in a range from 50 nanometers (nm) to 250 nm. However, the seed layer 122 may have any of various other compositions and / or thicknesses in various embodiments. In other embodiments not according to the invention, the surface finish formation may be omitted at 220, with the seed layer instead being deposited (at 230) directly on exposed copper of the contact.In an embodiment, the method 200 further includes electroplating, at 240, tin directly on the seed layer, the tin to form part of a micro bump structure of the substrate. For example, as shown at stage 102, a patterned layer 130 of resist material may be formed over the seed layer 122, the patterned layer 130 including openings 132 that are each variously aligned over a respective one of the holes 112. Deposition, patterning, and / or other formation of the patterned layer 130 may include operations adapted from, for example, any of a variety of lithographic processes (exposure and development) known in the art. As shown at step 103, an electrolytic plating process may be performed to deposit tin 140 to at least partially fill the holes 112. Illustratively and not by way of limitation, tin 140 may be deposited to a thickness of at least a certain minimum amount (e.g., at least 1 μm to 10 μm) that provides a void-free bump of tin in one of the via holes 112. In some embodiments, tin 140 is electroplated to a plane that is above a top surface of the dielectric surface layer 110 (e.g., 1 μm or more above a highest extension of the seed layer 122), but below a top surface of the patterned layer 130, for example.The method 200 may further include electroplating, at 250, zinc (Zn) directly on the tin electroplated at 240 - e.g., where the zinc is also to partially form the same micro bump structure(s) including such tin. In the illustrative embodiment shown at stage 104, a subsequent electrolytic plating process is performed to deposit zinc 142 over tin 140 - e.g., with a thickness of zinc 142 being in a range of 5 μm to 30 μm. For example, only tin 140 - and not any copper of seed layer 122 - may be in direct contact with some or all bottom portions of zinc 142 (at least prior to reflow (reflow) or other processing of the micro bump structures including tin 140 and zinc 142).Although some embodiments are not limited in this regard, the method 200 may include or be followed by additional processing to build up and / or modify structures formed by the method 200. Illustratively, and not by way of limitation, as illustrated at step 105, the temporary patterned resist layer 130 may be subsequently removed to expose portions of the underlying seed layer 122. A reflow process may then be performed and / or grinding / polishing may be performed to reduce a height difference between respective micro bumps. Additionally or alternatively, flash etch processing (or other such subtractive operation) may be subsequently performed to remove portions 144 of seed layer 122. Such flash etching may provide electrical isolation of the micro bump structures from each other at a surface of the dielectric layer 110. In various embodiments, a solder connection may be formed with the microbump - e.g., including the performance of a thermoplastically compression bonding (TCB) process, such as one adapted from conventional techniques.In some embodiments, subsequent electroplating of tin 140 and zinc 142 promotes the formation of micro-constituents (such as primary micro-constituents) during reflow (reflow) and / or other processing of a micro-bump. An increased volume fraction of primary microconstituents in a microbump may reduce the tendency of residual copper to precipitate from a microbump and onto adjacent surfaces. Due to such electroplating-and in some embodiments due to reflow-a micro-bump according to one embodiment may have a mass fraction gradient (of zinc or tin, for example) along the height thereof. For example, a mass fraction of zinc (herein "zinc mass fraction") for a first region of a microbump may be different than a second zinc mass fraction for a second region of the microbump that is relatively far from an underlying copper contact compared to the first region. The different fractions of zinc (or tin) along the height of a microbump may exist at least before (and in some embodiments after) reflow processing of the microbump.Illustratively and not by way of limitation, lower 10% of a volume of a first microbump may have a first zinc mass fraction, wherein upper 10% of a volume of the first microbump has a second zinc mass fraction, wherein the second zinc mass fraction differs from the first zinc mass fraction by at least 5% of the first zinc mass fraction. In such an embodiment, the second zinc mass fraction may differ from the first zinc mass fraction by at least 10% (e.g., by at least 20%) of the first zinc mass fraction. Alternatively or additionally, a total volume of total zinc of the first microbump may be equal to at least 5% of a total volume of total tin of the first microbump. The total volume of total zinc of the first microbump may be equal to at least 10% (in some embodiments, at least 20%) of the total volume of total tin of the first microbump, for example. In some embodiments, a total zinc mass fraction (for the entire first microbump) is in a range of 5% to 30% of a total volume of the first microbump. The total zinc mass fraction may be, for example, in a range from 5% to 20% (and in some embodiments, in a range from 10% to 15%) of the total volume.FIG. 3 illustrates an electronic assembly 300 including interconnect structures according to an embodiment. The electronic assembly 300 is just one example of an embodiment, wherein an integrated circuit die is coupled to a substrate (e.g., an interposer) via one or more solder joints formed by respective micro bumps. Such micro bumps may result from processing, such as illustrated by stages 100- 105 and / or by methods 200. As stated above, a solder joint formed by soldering a micro bump according to an embodiment may itself be referred to as a "micro bump".A package substrate 310 of an electronic assembly 300 may include an interposer 312 and a die 314 positioned thereon. The die 314 may be formed of a material such as silicon and have circuitry thereon to be coupled to the interposer 312. Although some embodiments are not limited in this regard, the package substrate 310 may in turn be coupled to another body, for example, a computer main board (not shown). One or more connections between the package substrate 310, the interposer 312, and the die 314 - e.g., including some or all of the solder connections 316 and 318 - may have zinc-tin metallurgy. In some embodiments, such compounds may variously comprise an alloy of zinc and tin (and in some embodiments, copper). By way of illustration and not limitation, a given one of the solder connections 316, 318 may predominantly comprise tin (e.g., at least 75% tin, and in some embodiments, at least 90% tin). In such an embodiment, a total amount of zinc in the solder joint may be at least 5% (e.g., at least 10% and in some embodiments at least 15%) of the total amount of tin.Connections between the package substrate 310 and another body may be made using any suitable structure, such as the illustrative solder bumps 320 shown. The package substrate 310 may include a plurality of electronic structures formed thereon or therein. The interposer 312 may also include electronic structures formed thereon or therein. A variety of materials may be used to form the package substrate and the interposer. In certain embodiments, package substrate 310 is an organic substrate formed from one or more layers of a polymeric base material having conductive regions for transmitting signals. In certain embodiments, the interposer 312 is formed of a ceramic base material including metal regions for sending signals. Although some embodiments are not limited in this respect, the electronic assembly 300 may include space control structures 330- positioned between, e.g., the package substrate 310 and the interposer 312. Such gap control structures 330 may reduce a change in the height of the gap between the package substrate 310 and the interposer 312 that might otherwise occur during reflow while the die 314 is attached to the interposer 312. FIG. 3 also shows the presence of underflow material 328 between interposer 312 and die 314, and underflow material 326 between package substrate 310 and interposer 312. Underflow materials 326, 328 may be a polymer injected between the layers.FIG. 4 illustrates a computing device 400 according to an embodiment. The computing device 400 houses a board 402. The board 402 may include a number of components including, but not limited to, a processor 404 and at least one communication chip 406. The processor 404 is physically and electrically coupled to the board 402. In some implementations, the at least one communication chip 406 is further physically and electrically coupled to the board 402. In further implementations, the communication chip 406 is part of the processor 404.Depending on its applications, computing device 400 may include other components that may or may not be physically and electrically coupled to board 402. These other components include, but are not limited to, volatile memory (e.g., DRAM), nonvolatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), etc.).The communication chip 406 enables wireless communication for the transmission of data to and from the computing device 400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not. The communication chip 406 may implement any number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, and derivatives thereof, as well as any other wireless protocols that are referred to as 3G, 4G, 5G, and beyond. The computing device 400 may include a plurality of communication chips 406. For example, a first communication chip 406 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 406 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.The processor 404 of the computing device 400 includes an integrated circuit chip packaged within the processor 404. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that may be stored in registers and / or memory. The communication chip 406 further includes an integrated circuit die packaged within the communication chip 406.In various implementations, the computing device 400 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit (entertainment control unit), a digital camera, a portable music player, or a digital video recorder. In further implementations, computing device 400 may be any other electronic component that processes data.Some embodiments may be provided as a computer program product or software, which may include a machine readable medium having stored thereon instructions that may be used to program a computer system (or other electronic devices) to perform a process according to an embodiment. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). A machine-readable (e.g., computer-readable) medium includes, for example, a machine-readable (e.g., computer-readable) storage medium (e.g., read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine-readable (e.g., computer-readable) transmission medium (electrical, optical, acoustical or other forms of propagated signals (e.g., infrared signals, digital signals)), etc.FIG. 5 illustrates a schematic representation of a machine in the exemplary form of a computer system 500 in which a set of instructions may be executed to cause the machine to perform any one or more of the methods described herein. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a local area network (LAN), an intranet, an extranet, or the Internet. The machine may operate in nature as a server or client machine in a client-server network environment or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile telephone, a web appliance, a server, a network router, network switches (switch) or network bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Further, while only a single machine is illustrated, the term "machine" is intended to include any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methods described herein.The example computer system 500 includes a processor 502, a main memory 504 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory 518 (e.g., a data storage device) that communicate with each other via a bus 530.Processor 502 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, processor 502 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processor 502 may also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processor 502 is configured to execute the processing logic 526 to perform the operations described herein.The computer system 500 may further include a network interface device 508. The computer system 500 may also include a video display unit 510 (e.g., a liquid crystal display (LCD), a light emitting diode (LED) or cathode ray tube (CRT), an alphanumeric input device 512 (e.g., a keyboard), a cursor control device 514 (e.g., a mouse), and a signal generation device 516 (e.g., a speaker).The secondary storage 518 may include a machine-accessible storage medium (or more specifically, a computer-readable storage medium) 532 on which is / are stored one or more sets of instructions (e.g., software 522) embodying any one or more of the methods or functions described herein. Software 522 may also reside, completely or at least partially, within main memory 504 and / or within processor 502 during execution thereof by computer system 500, where main memory 504 and processor 502 also form machine readable storage media. Software 522 may further be sent or received over a network 520 via network interface device 508.While machine-accessible storage medium 532 is shown as a single medium in an example embodiment, the term "machine-readable storage medium" should include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" is also intended to include any medium capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any of one or more embodiments. The term "machine readable storage medium" is accordingly intended to include, but not be limited to, solid-state memories (solid-state memories) and optical and magnetic media.FIG. 6 illustrates an interposer 600 that includes one or more embodiments. Interposer 600 is an intermediate substrate used to bridge a first substrate 602 to a second substrate 604. The first substrate 602 may be, for example, an integrated circuit die. The second substrate 604 may be, for example, a memory module, a computer motherboard, or other integrated circuit die. Generally, the purpose of an interposer 600 is to propagate a connection to another distance or to redirect a connection to a different connection. For example, an interposer 600 may couple an integrated circuit die to a ball grid array (BGA) 606 - e.g., comprising or formed by one or more micro bumps, according to an embodiment - which may be subsequently coupled to the second substrate 604. In some embodiments, the first and second substrates 602, 604 are attached to opposite sides of the interposer 600. In other embodiments, the first and second substrates 602, 604 are attached to the same side of the interposer 600. And in further embodiments, three or more substrates are connected using interposer 600.The interposer 600 may be formed of an epoxy, a fiberglass reinforced epoxy, a ceramic, or a polymeric material, such as polyimide. In further implementations, the interposer may be formed of alternating rigid or flexible materials, which may include the same materials described above for use with a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials.The interposer may include metal interconnects 608 and vias 610, including but not limited to through-silicon via (TSV) 612. The interposer 600 may further include embedded devices 614 including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and ESD (ESD=electrostatic discharge). More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on interposer 600. According to some embodiments, devices or methods disclosed herein may be used in the fabrication of the interposer 600.In one implementation, an integrated circuit (IC) package substrate includes a dielectric layer having via holes formed therein, a subsurface metal layer including copper contacts each exposed for a respective one of the via holes, the copper contacts including a first copper contact, a first surface finish directly on the first copper contact, a first seed layer deposited on the first copper contact, the first seed layer including copper, the first seed layer deposited on the first surface finish, and a first micro-bump formed on the first seed layer, the first micro-bump including tin and zinc.In an embodiment, lower ten percent of a volume of the first micro-bump comprises a first zinc mass fraction, wherein upper 10% of a volume of the first micro-bump comprises a second zinc mass fraction, and wherein the second zinc mass fraction differs from the first zinc mass fraction by at least 5% of the first zinc mass fraction. In another embodiment, the second zinc mass fraction differs from the first zinc mass fraction by at least 10% of the first zinc mass fraction. In another embodiment, a total volume of zinc of the first microbump is equal to at least 5% of a total volume of tin of the first microbump. In another embodiment, the total volume of zinc of the first microbump is equal to at least 10% of the total volume of tin of the first microbump. In another embodiment, a total zinc mass fraction of the first microbump is in a range of 5% to 30%. In another embodiment, the total zinc mass fraction of the first microbump is in a range of 5% to 20%. In another embodiment, the first seed layer further comprises titanium.In another implementation, a method of forming micro bumps on a substrate includes patterning a dielectric layer with a copper contact exposed through an opening formed through the dielectric layer, forming a surface finish directly on the copper contact, performing a deposition of a seed layer on the surface finish, the seed layer including copper, electroplating tin of a first micro bump directly on the seed layer, and electroplating zinc of the first micro bump directly on the tin.In one embodiment, the tin of the microbump is electroplated directly on the copper seed layer. In another embodiment, lower ten percent of a volume of the first micro-bump comprises a first zinc mass fraction, wherein upper 10% of a volume of the first micro-bump comprises a second zinc mass fraction, and wherein the second zinc mass fraction differs from the first zinc mass fraction by at least 5% of the first zinc mass fraction. In another embodiment, the second zinc mass fraction differs from the first zinc mass fraction by at least 10% of the first zinc mass fraction. In another embodiment, a total volume of zinc of the first microbump is equal to at least 5% of a total volume of tin of the first microbump. In another embodiment, the total volume of zinc of the first microbump is equal to at least 10% of the total volume of tin of the first microbump. In another embodiment, a total zinc mass fraction of the first microbump is in a range of 5% to 30%. In another embodiment, the total zinc mass fraction of the first microbump is in a range of 5% to 20%.In another implementation, a device includes an integrated circuit (IC) die and a substrate including a dielectric layer having via holes formed therein, a subsurface metal layer including copper contacts each adjacent a respective one of the via holes, the copper contacts including a first copper contact, and a first seed layer deposited on the first copper contact, the first seed layer including copper. The device further includes solder joints including a first solder joint including zinc and tin, wherein the IC die and the first copper contact are coupled to each other via the first solder joint.In an embodiment, lower ten percent of a volume of the first micro-bump comprises a first zinc mass fraction, wherein upper 10% of a volume of the first micro-bump comprises a second zinc mass fraction, and wherein the second zinc mass fraction differs from the first zinc mass fraction by at least 5% of the first zinc mass fraction. In another embodiment, the second zinc mass fraction differs from the first zinc mass fraction by at least 10% of the first zinc mass fraction. In another embodiment, a total volume of zinc of the first microbump is equal to at least 5% of a total volume of tin of the first microbump. In another embodiment, the total volume of zinc of the first microbump is equal to at least 10% of the total volume of tin of the first microbump. In another embodiment, a total zinc mass fraction of the first microbump is in a range of 5% to 30%. In another embodiment, the total zinc mass fraction of the first microbump is in a range of 5% to 20%. In another embodiment, the first seed layer further comprises titanium.Techniques and architectures for making interconnect structures comprising tin are described herein. For convenience in explanation, in the above description, numerous specific details are set forth in order to provide a thorough understanding of the specific embodiments. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without these specific details. In other instances, structures and devices are shown in block diagram form to avoid obscuring the description.In the specification, reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.Some portions of the detailed description are presented herein in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the computer arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here and generally designed as a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transmitted, combined, compared, and otherwise manipulated. It has been found convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, images or characters, terms, numbers, or the like.It should be understood, however, that all of these and similar terms are intended to be associated with the appropriate physical quantities and are only convenient labels applied to these quantities. It is noted, unless otherwise specifically stated, as will be apparent from the discussion herein, that throughout the specification discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" or the like, refer to the actions and processes of a computer system or similar electronic computing device that(s) manipulate and transform data represented as physical (electronic) quantities within the registers and memories of the computer system to other data similarly represented as physical quantities within the memories or registers of the computer system, or to other such information storage, transfer or display devices.Certain embodiments also relate to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memories (ROMs), random access memories (RAMs) such as dynamic RAM (DRAM), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions and coupled to a computer system bus.The algorithms and displays presented herein do not inherently relate to any particular computer or other device. Various general purpose systems may be used with programs in accordance with the teachings herein or it may prove convenient to build a more specialized apparatus to perform the required method steps. The required structure for a variety of these systems will be apparent from the description herein. In addition, certain embodiments are not described with reference to any particular programming language. It should be appreciated that a variety of programming languages may be used to implement the teachings of such embodiments described herein.Apart from what is described herein, various modifications may be made to the disclosed embodiments and implementations thereof. Therefore, the illustrations and examples herein are to be interpreted in an illustrative and non-limiting sense. The scope of the invention is to be measured solely with reference to the following claims.

Claims

An integrated circuit, IC, package substrate (100) comprising: a dielectric layer (110) having via holes (112) formed therein, the via holes having a tapered shape; a sub-surface level metal layer (120) comprising copper contacts each exposed by one of the via holes, the copper contacts comprising a first copper contact; a first surface finish (114) directly on the first copper contact; a first seed layer (122) deposited on the first copper contact, the first seed layer comprising copper, the first seed layer being deposited on the first surface finish; and a first microbump formed on the first seed layer, the first microbump comprising tin and zinc.The IC package substrate of claim 1, wherein lower ten percent of the volume of the first microbump has a first zinc mass fraction, wherein upper 10% of the volume of the first microbump has a second zinc mass fraction, and wherein the second zinc mass fraction differs from the first zinc mass fraction by at least 5% of the first zinc mass fraction.The IC package substrate of claim 2, wherein the second zinc mass fraction differs from the first zinc mass fraction by at least 10% of the first zinc mass fraction.The IC package substrate of claim 1, wherein the total volume of zinc of the first microbump is equal to at least 5% of the total volume of tin of the first microbump.The IC package substrate of claim 4, wherein the total volume of zinc of the first microbump is equal to at least 10% of the total volume of tin of the first microbump.The IC package substrate of claim 1, wherein the total zinc mass fraction of the first micro bump is in a range of 5% to 30%.The IC package substrate of claim 6, wherein the total zinc mass fraction of the first micro bump is in a range of 5% to 20%.The IC package substrate of claim 1, wherein the first seed layer further comprises titanium.A method (200) of forming micro bumps on a substrate, the method comprising: patterning (210) a dielectric layer, wherein a copper contact is exposed through an opening formed through the dielectric layer, wherein the opening is laser drilled; forming (220) a surface finish directly on the copper contact; performing (230) a deposition of a seed layer directly on the surface finish, wherein the seed layer comprises copper; electroplating (240) tin of a first micro bump directly on the seed layer; and electroplating (250) zinc of the first micro bump directly on the tin.The method of claim 9, wherein the tin of the microbump is electroplated directly on the copper seed layer.The method of claim 9, wherein lower ten percent of the volume of the first microbump comprises a first zinc mass fraction, wherein upper 10% of the volume of the first microbump comprises a second zinc mass fraction, and wherein the second zinc mass fraction differs from the first zinc mass fraction by at least 5% of the first zinc mass fraction.The method of claim 11, wherein the second zinc mass fraction differs from the first zinc mass fraction by at least 10% of the first zinc mass fraction.The method of claim 9, wherein the total volume of zinc of the first microbump is equal to at least 5% of the total volume of tin of the first microbump.The method of claim 13, wherein the total volume of zinc of the first microbump is equal to at least 10% of the total volume of tin of the first microbump.The method of claim 9, wherein the total zinc mass fraction of the first microbump is in a range of 5% to 30%.The method of claim 15, wherein the total zinc mass fraction of the first microbump is in a range of 5% to 20%.A device, comprising: an integrated circuit, IC, die; a substrate comprising: a dielectric layer having via holes formed therein, the via holes having a tapered shape; an subsurface metal layer comprising copper contacts each adjacent a respective one of the via holes, the copper contacts comprising a first copper contact; and a first seed layer deposited directly on the first copper contact, the first seed layer comprising copper; and solder joints comprising a first solder joint comprising zinc and tin, wherein the IC die and the first copper contact are coupled to each other via the first solder joint.The device of claim 17, wherein lower ten percent of the volume of the first microbump comprises a first zinc mass fraction, wherein upper 10% of the volume of the first microbump comprises a second zinc mass fraction, and wherein the second zinc mass fraction differs from the first zinc mass fraction by at least 5% of the first zinc mass fraction.The device of claim 18, wherein the second zinc mass fraction differs from the first zinc mass fraction by at least 10% of the first zinc mass fraction.The device of claim 17, wherein the total volume of zinc of the first microbump is equal to at least 5% of the total volume of tin of the first microbump.The device of claim 20, wherein the total volume of zinc of the first microbump is equal to at least 10% of the total volume of tin of the first microbump.The device of claim 17, wherein the total zinc mass fraction of the first microbump is in a range of 5% to 30%.The device of claim 22, wherein the total zinc mass fraction of the first microbump is in a range of 5% to 20%.The device of claim 17, wherein the first seed layer further comprises titanium.

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