METHOD FOR A UNIT LAYOUT WITH VERTICAL TRANSISTORS AND STORAGE MEDIUM WITH PROGRAM

Abstract

Method for a unit layout with vertical transistors, which features: Identifying active area regions in a layout of a semiconductor unit with vertical transistors; Determining sets of adjacent active surface areas with the same electrical potential; Prioritizing the identified rates for a summary of adjacent active area areas based on one or more performance criteria; and Combining sets of adjacent active area areas to form larger active area areas according to the priority determined on the basis of one or more performance criteria, where combining sets of adjacent active area regions involves combining sets of adjacent active area regions across cell boundaries.

Description

TECHNICAL AREA

[0001] The present invention relates generally to semiconductor layouts and in particular to units and methods for arranging designs of vertical transistors with combined active areas (e.g. bottom source and drain areas) to reduce resistance and improve the layout area. BACKGROUND

[0002] Vertical field-effect transistors (VFETs) incorporate a channel perpendicular to a surface of the substrate on which the VFET is formed, rather than being placed along a plane of the substrate's surface. This increases the packing density of these units and improves the scaling limit beyond that of planar FinFETs.

[0003] One challenge with vertical FETs, however, lies in the separate nature of the units. The units, or even groups of units, are separated from each other by isolation boundaries, well boundaries, and region boundaries. Small, narrow active area (RX) regions can lead to higher resistance to power supplies due to typical critical dimensions (CDs) and variations in interference (e.g., between lithography masks, etc.). Consequently, power supply connections and unit structures, which must be adapted to these conditions, occupy valuable substrate space.

[0004] In this context, several documents have already been published. Document US 2011 / 0260259A1 describes a CMOS inverter coupled to a circuit, consisting of SGTs connected in series in two or more stages. Several of these CMOS inverters share a source diffusion layer on the substrate. Document US 2015 / 0270268A1 describes semiconductor structures in which a plurality of columns are arranged vertically on a semiconductor substrate. A plurality of secondary diffusion layers are arranged in the upper section of each column. Additionally, a conductive layer exists that is electrically connected to at least one of the secondary diffusion layers. Furthermore, at least one contact is formed on at least one of the plurality of secondary diffusion layers. Document US 2017 / 0125424A1 describes an SRAM device with vertical FET components.The individual SRAM cells are assembled into an array. Each SRAM cell contains six vertical field-effect transistors. Finally, the document by LIU, Hongyi [et al]: Structural design, layout analysis and routing strategy for constructing IC standard cells using emerging 3D vertical MOSFETs. In: Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, March 16, 2016, Art. 978103, pp. 1-10. DOI: https: / / doi.org / 10.1117 / 12.2219267, describes how optical lithography and conventional transistor structures can be further developed at the limits of what is physically possible. In particular, it discusses gate-all-around nanowire MOSFETs (GAA MOSFETs) and double-surrounding gate MOSFETs (DSG MOSFETs).

[0005] Despite these advances already made, there remains a need for circuit layouts for VFETs that reduce the load on power supplies and preserve layout area. SUMMARY

[0006] This task is solved by the independent patent claims. Further details are provided by the dependent claims.

[0007] According to one embodiment of the present invention, a method for a vertical transistor unit layout includes the detection of active area regions in the layout of a semiconductor unit with vertical transistors. Sets of adjacent active area regions with the same electrical potential are identified. The sets of adjacent active area regions to be grouped are prioritized based on one or more performance criteria. The sets of adjacent active area regions are grouped such that larger active area regions are formed according to a priority. Circuit layouts for vertical field-effect transistors (VFETs) according to the present embodiments reduce the load on power supplies and preserve layout areas by grouping regions, thus forming larger active area regions.

[0008] A non-transitory, computer-readable storage medium containing a computer-readable program for a vertical transistor unit layout is included, wherein the computer-readable program, when executed on a computer, causes the computer to perform the steps of detecting active area regions in a layout of a vertical transistor semiconductor unit; identifying sets of adjacent active area regions with the same electrical potential; prioritizing the sets of adjacent active area regions to be grouped based on one or more performance criteria; and grouping the sets of adjacent active area regions to form larger active area regions according to a priority.Circuit layouts for VFETs according to the present embodiments reduce the load on power supplies and preserve layout areas by combining areas, thus forming larger active area regions.

[0009] A semiconductor device comprises a substrate and an active area that forms a bottom source / drain region on the substrate. A plurality of vertical transistors are formed on the bottom source / drain region, which is shared by the plurality of vertical transistors. The vertical transistors comprise a vertical channel, a gate dielectric layer formed around the vertical channel, a gate conductor formed around the gate dielectric, and a top source / drain region formed on the vertical channel. Devices with VFETs according to the present embodiments reduce the load on power supplies and preserve layout areas by combining regions, thus forming larger active areas.

[0010] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which should be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Embodiments of the invention are now described only as examples with reference to the accompanying drawings, in which: Fig. 1 a layout view which represents a layout with aggregated active area areas, aggregated trench insulation areas and continuous supply and ground rails designed to provide an optimized layout with reduced resistance according to an embodiment of the present invention; Fig. 2 is a cross-sectional view showing vertical transistors utilizing a common active area including a bottom source / drain region according to an embodiment of the present invention; Fig. 3 is a layout view that represents a layout having aggregated active area areas shared by two or more logic units, according to an embodiment of the present invention; Fig. 4 is a layout view that represents a layout having active surface areas which have been combined with unfilled areas and dummy filled areas to form active surface areas which are connected to supply / ground rails and isolated from supply / ground rails, according to an embodiment of the present invention; Fig. 5 a layout view which represents a layout having aggregated active area areas which include an active area extending across cell boundaries, according to an embodiment of the present invention; Fig. 6 is a block / flowchart that represents a system for modifying or creating an optimized layout according to an embodiment of the present invention; and Fig. 7 is a block / flow diagram representing a system / method for a unit layout with vertical transistors according to embodiments of the present invention. DETAILED DESCRIPTION

[0012] Embodiments of the present invention include units, layouts, and methods for manufacturing semiconductor units. Particularly advantageous embodiments combine adjacent active regions (RX) into aggregated regions such that the power and ground supplies consume less current. This improves the performance of the semiconductor unit, for example, by simplifying layouts, reducing current requirements, and lowering resistance. These advantages apply under nominal conditions and under the most adverse conditions (under heavy load). By further adapting a layout to eliminate filler elements or other components between active regions, the resistance of the underlying source and drain (S / D) regions can be further reduced.

[0013] Active area regions (RX) comprise active semiconductor regions separated by dielectric isolation regions on a substrate (e.g., active silicon semiconductor or conductor regions isolated by shallow trench isolation, STI). One aspect of the present principles is to determine, according to a priority, which of these regions can be grouped together. The priority can be based on performance criteria or other criteria such as layout constraints or other limitations.

[0014] It is understood that aspects of the present invention are described with regard to a particular illustrative architecture; however, other architectures, structures, substrate materials and process features and steps may be varied within the scope of aspects of the present invention.

[0015] It is also understood that when an element, such as a layer, area, or substrate, is described as being "on" or "above" another element, it may be located directly on top of the other element, or there may be intermediate elements. However, when an element is described as being "directly on" or "directly above" another element, there are no intermediate elements. It is also understood that when an element is described as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intermediate elements. However, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intermediate elements.

[0016] The present embodiments may include a design for an integrated circuit chip that can be created in a graphical computer programming language and stored on a computer storage medium (such as a data disk, tape, physical hard disk, or virtual hard disk such as in a storage access network). If the developer does not manufacture chips or photolithographic masks used to manufacture chips, the developer may transfer the resulting design directly or indirectly to such entities by physical means (e.g., by providing a copy of the storage medium containing the design) or electronically (e.g., via the internet). The stored design is then used to manufacture photolithographic masks in the appropriate format (e.g.,The photolithography mask is converted to GDSII, which typically involves multiple copies of the chip design to be formed on a wafer. The photolithography masks are used to define areas on the wafer (and / or the layers on it) to be etched or otherwise processed.

[0017] Methods such as those described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of a raw wafer (that is, a single wafer containing multiple unpackaged chips), as a bare chip, or in a package. In the latter case, the chip is mounted in a single-chip package (such as on a plastic substrate with leads attached to a mainboard or other higher-level support) or in a multi-chip package (such as on a ceramic substrate having either surface interconnects, buried interconnects, or both).In any case, the chip is subsequently integrated with other chips, discrete circuit elements, and / or other signal processing units as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product that incorporates integrated circuit chips, ranging from toys and other simple applications to sophisticated computer products that include a display, a keyboard or other input device, and a central processing unit.

[0018] Furthermore, it is understood that material compounds are described in terms of listed elements, e.g., SiGe. These compounds contain varying proportions of the elements within the compound; for example, SiGe contains Si x Ge 1-x,where x is less than or equal to 1, etc. Furthermore, other elements may be included in the compound and continue to act according to the basic principles outlined above. Compounds with additional elements are referred to herein as alloys.

[0019] A reference in the description to "an embodiment" as well as other variants thereof means that a specific feature, structure, property, and so on, described in connection with the embodiment, is included in at least one embodiment. Consequently, the phrases "in an embodiment" or "in an embodiment," as well as any other variants that appear at various points in the description, do not necessarily all refer to the same embodiment.

[0020] It should be noted that the use of any of the following " / ", "and / or", and "at least one of"—for example, in the cases "A / B", "A and / or B", and "at least one of A and B"—should include only the selection of the first listed option (A), only the selection of the second listed option (B), or the selection of both options (A and B). As a further example, in the cases "A, B and / or C" and "at least one of A, B, and C," such wording should include only the selection of the first listed option (A), only the selection of the second listed option (B), only the selection of the third listed option (C), only the selection of the first and second listed options (A and B), only the selection of the first and third listed options (A and C), only the selection of the second and third listed options (B and C), or the selection of all three options (A, B, and C).As experts can easily see, this can be extended to all the listed elements.

[0021] The terminology used herein serves only to describe certain embodiments. As used herein, the singular forms "ein," "eine," and "der," "die," "das" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, it is understood that the terms "aufweist," "aufweisend," "beteiliget," and / or "beinhaltend," when used herein, denote the presence of specified features, integers, steps, processes, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, processes, elements, components, and / or groups thereof.

[0022] Spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used herein for the sake of simplicity to describe the relationship of an element or feature to one or more other elements or features, as illustrated in the FIGS. It is understood that the spatially relative terms are intended to encompass different orientations of the unit in use or operation in addition to the orientation shown in the FIGS. For example, if the unit in the FIGS is reversed, elements described as "under" or "below" other elements or features would be oriented "above" those other elements or features. Consequently, the term "below" can encompass an orientation both above and below.The unit can be oriented in other ways (rotated by 90 degrees or with other orientations), and the spatially relative descriptions used herein can be interpreted accordingly. Furthermore, it is understood that when a layer is described as being "between" two layers, it may refer to the only layer between the two layers, or it may also refer to one or more intervening layers.

[0023] It is understood that, although the terms first, second, etc. may be used herein to describe different elements, these elements should not be restricted by these terms. These terms are used only to distinguish one element from another. Consequently, a first element discussed below could be referred to as a second element without deviating from the scope of the present concept.

[0024] Referring to the drawings in which the same reference numerals represent the same or similar elements, and initially to Fig. Illustrative layouts 10 and 30 are shown to demonstrate an optimization of active areas (or active regions) according to aspects of the present invention. Layout 10 includes a plurality of active regions 18 that receive a supply voltage, Vdd. The active regions 18 include supply contacts 14, which are used to supply the supply voltage to vertical transistors arranged within each active region 18. Layout 10 further includes a plurality of active regions 28 that receive a ground voltage, GND. The active regions 28 include ground contacts 24, which are used to supply the supply voltage to vertical transistors arranged within each active region 28.

[0025] The (not shown) vertical transistors often have a bottom source or drain region which, depending on their placement in the layout, is connected to the potential Vdd or GND. In one embodiment, the active regions 18 for PFETs in an n-well (in Fig. 1 marked with a “P””), whereas the active regions 28 for NFETs are in a p-well (in Fig. 1 (marked with an “N”). The active regions 18 and 28 are defined by trench isolation regions 12. The trench isolation regions 12 provide electrical isolation between active regions 18 and 28 and between the active regions 18, 28 and external units or components. The active regions 18, 28 can each contain a single VFET source or drain region shared by a plurality of VFETs.

[0026] In layout 10, the active areas 18 and 28 are separated and require one or more contacts 14 or 24 for each active area 18 and 28. This results in less effective power and ground connections due to higher electrical resistance. Furthermore, layout 10 occupies a larger layout area and features multiple isolation trench areas 12 throughout layout 10. Other areas 16 may also be included in layout 10. These areas 16 may contain other components or structures, including filler materials, conductive materials, and other components or structures. These areas 16 are not at Vdd or GND potential.

[0027] According to one embodiment, adjacent active regions 18 or 28 of the layout 10 are combined such that the power and ground supplies have a significantly lower resistance, as shown in a layout 30. The layout 10 is redesigned such that lower source or drain regions (S / Ds) in active regions 18 are combined into a combined region 38, which is shared by a plurality of VFETs connected to the same potential (GND). Likewise, the layout 10 is redesigned such that lower source or drain regions (S / Ds) in active regions 28 are combined into a combined region 36, which is shared by a plurality of VFETs connected to the same potential (Vdd).

[0028] A common bus 34 forms a contact with an entire active region 36 for the Vdd power supply. Likewise, a common bus 35 forms a contact with an entire active region 38 for the GND power supply. In some embodiments, the bottom region (e.g., the active regions 36, 38) includes a source and is connected to Vdd or GND. In other embodiments, the bottom region (e.g., the active regions 36, 38) includes a drain and is connected to Vdd or GND. If adjacent VFETs have sources (or drains) connected to the same Vdd or GND potential (or any other common potential), trench isolation between the VFETs can be eliminated. This provides a reduced space requirement for trench isolation 32 between the VFETs. The VFETs can utilize a large shared, bottom source / drain region 36, 38.

[0029] Some of the advantages of aggregated active areas include continuous active areas, which reduce the resistance of trench silicide (TS) contacts with bottom-mounted source / drain (S / D) areas and provide lower lateral resistance of active areas (at least due to, for example, fewer components and interfaces between them). Increased unit drive current and improved thermal resistance are also achieved with aggregated S / D areas. Furthermore, less machining and shared active areas lead to reduced variability between units and their performance. Using a common active area (source or drain) helps to reduce or eliminate capacitance problems between aggregated units.The unit layout is simplified by using continuous power or ground contact rails, which also reduce resistance. This also leads to improved use of wiring traces for the VFETs and potential improvements in the definition of spacers and gates, since maintaining spacing between VFETs is less of a problem using aggregated active areas that are significantly larger and have improved resistance characteristics and lower capacitance.

[0030] With reference to Fig. Figure 2 shows a cross-sectional view of vertical field-effect transistors 50, which have a vertical fin 52 (a channel) and a gate structure 54 with a gate electrode 56, on a combined S / D area 58 according to an exemplary embodiment.

[0031] In one or more embodiments, a counter-doped layer 62 can be formed on or in a substrate 60, wherein the counter-doped layer 62 can be used to electrically insulate the combined source / drain region 58 from the main part of the substrate 60. The substrate 60 can comprise any suitable substrate materials such as Si, SiGe, SiC, silicon-on-insulator, III-V materials, etc.

[0032] A gate dielectric layer 74 can comprise one or more dielectric layers and can be formed on the vertical fin 54 and a lower spacer layer 64 (a dielectric layer, e.g., SiN). At least one layer of the gate dielectric layer 74 can be a high-k material, including, but not limited to, metal oxides such as hafnium oxide (e.g., HfO₂), hafnium silicon oxide (e.g., HfSiO₄). The gate electrode or gate conductor 56 comprises a metal or other highly conductive material and surrounds (completely or partially) the vertical fin 52 or the vertical channel. The gate electrode 56 is contacted by a gate contact 78. An overlying source / drain region 68 is contacted by a contact 76.The contact 76 can also be referred to as a trench silicide (TS) contact, since a silicide may be formed at the interface between the upper source / drain region 68 and the contact 76. The upper source / drain region 68 is enclosed in a dielectric layer 72 (e.g., an oxide). A barrier layer or lining 70 (e.g., TiN, TaN, etc.) may also be formed in the openings for the contacts 76 and 78. The vertical transistors 50 are enclosed in an interlayer dielectric material 82, for example, silicon dioxide (e.g., SiO2).

[0033] It goes without saying that the in Fig. The units shown in Figure 2 are for illustrative purposes only. Other vertical FET designs and configurations can be used. Furthermore, vertical nanowires or other vertical units can also be employed.

[0034] Fig. Figure 2 illustrates two VFETs 50 that share a common bottom S / D region 58. In conventional structures, areas of shallow trench insulation or other barriers may be present through the bottom S / D region 58 and into the substrate 60. These barriers would be located between the units 50 (e.g., along the boundary line 90). The present embodiments eliminate the need for such a barrier and combine the bottom S / D regions 58 between the VFETs 50.

[0035] Any number of other VFETs can also utilize the shared S / D region 58. Units 50 that can share a shared S / D region 58 can be identified if the units 50 exhibit the same fixed or transient potential adjacent to a fill region (a region filled with a dielectric material). Conveniently, the shared region is associated with a common potential and is tolerant of different conductivities and dopant concentrations. Therefore, the active regions 58 can be shared across cell boundaries (e.g., nn or pp cell boundaries). Furthermore, sharing between multiple FETs can be performed for a single or multiple components, e.g.,Units in the same cell, units in adjacent cells (nn or pp), adjacent units sharing below S / D areas connected to the same bus (GND or Vdd), adjacent units having below S / D areas extending into or through fill areas, etc.

[0036] In one embodiment, combinational logic elements and sequential logic elements can be combined. For example, an active inverter region can be combined with an active region of another adjacent inverter; an active NAND gate region can be combined with an active region of another NAND gate or inverter; an active NOR gate region can be combined with another active NOR gate or inverter region, and so on. In another example, a fill area can be combined with an active area of ​​an inverter, a NAND gate, a NOR gate, and so on. A fill area n region can be combined with an adjacent unit, and a p region can be combined with a corresponding unit in the opposite direction.

[0037] The present embodiments can be applied to any unit in which a channel current flows in the vertical direction. This can include vertical transport FinFETs, complementary vertical gate metal oxide semiconductor (CMOS) FETs, vertical nanowire units, etc.

[0038] With reference to Fig. Figure 3 presents another example, showing a layout 102 with numerous isolated active areas 108, 110, 112 and active areas 114, 116, 118. Active area 108 includes components 124 for forming a NOR gate. Active areas 110 and 112 include components 126 for forming inverters (INV). Active area 114 includes components 128 for forming a NAND gate. Active areas 116 and 118 include components 126 for forming the inverters. Due to the interrupted and separated arrangement of the active areas, the isolated active areas 108, 110, 112 and the active areas 114, 116, 118 are sensitive to higher resistance (both nominal and variable).

[0039] Furthermore, contacts that overlap a supply rail 106 or a ground rail 104 are small due to the limited unit widths and highly dependent on overlap tolerances. For example, in area 120, an overlap of the active area 118 and the rail 106 indicates an overlap area where a contact (e.g., a TS contact) could be inappropriate or subject to short circuits due to the lack of an overlapping surface.

[0040] According to one aspect of the present invention, active areas in a layout 132 for VFETs of combinational and sequential logic units such as NOR gates, inverters, and NAND gates, etc., of layout 102 are combined. The isolated active areas 108, 110, 112 are combined such that a larger active area 138 is formed in the layout 132. The active area 138 serves the NOR gate and two inverters. The isolated active areas 114, 116, 118 are combined such that a larger active area 144 is formed in the layout 132. The active area 144 serves the NAND gate and the two inverters.

[0041] Contacts 140 can now be formed continuously along each active area 138, 140 to further increase the contact size and reduce narrow overlapping areas (120). A supply rail 136 or ground rail 134 has a larger overlap with the active area 144 or the active area 138, respectively. In this way, contacts (e.g., TS contacts) can be considerably larger.

[0042] The larger active areas 138, 144 and larger contact overlap areas for TS contacts offer lower resistance, including lower resistance of TS contacts to active areas, lower lateral resistance across active areas, and lower thermal resistance (better heat flow).

[0043] With reference to Fig. 4. Layouts 202 and 226 can be improved into layout 230 or layout 240. Layouts 202 and 226 contain unfilled areas 220 and dummy fill areas 222, respectively. The unfilled areas 220 and the dummy fill areas 222 can be combined with active areas to provide layouts 230 or 240.

[0044] In one example, layouts 202 and 226 each include active areas 204 and 206, and active surface areas 212 and 210. Furthermore, other components 208 and 214 are also provided, which may include other active surface areas, other structures, or other components.

[0045] In layout 202, active area sections 204, 206, and the unfilled area 220 can be combined to form an active area section 234 in layout 230. Active area sections 212, 210, and the unfilled area 220 are combined to form an active area section 232. Components 208 and 214 remain. Layout 230 includes areas 232 and 234 with a greater overlap of busbars 236 and 238 than the overlap of busbars 216 and 218 in layouts 202 and 226. The combined components in layout 230 are connected along busbars 236 and 238. The unfilled area 220 has been eliminated and is now included in area 260 of the active areas 234 and 232, which offer a larger active area and a further reduced resistance.

[0046] In layout 226, the active area sections 204, 206, and the dummy filler area 222 can be combined to form an active area section 234 in layout 230. The active area sections 212, 210, and the dummy filler area 222 are combined to form the active area section 232. Components 208 and 214 remain unchanged. Layout 230 includes areas 232 and 234 with a greater overlap of busbars 236 and 238 than the overlap of busbars 216 and 218 in layouts 202 and 226. The combined components in layout 230 are connected along busbars 236 and 238. The dummy fill area 222 has been eliminated and is now included in area 260 of the active areas 234 and 232, which offer a larger active area and a further reduced resistance.

[0047] In layout 230, in one example, a filling area 222 and the n-region 204, 206 can be combined, and a filling area 222 and the p-region 210, 212 can be combined, in which units with different conductivities of dopants are formed across the filling area.

[0048] In layout 240, active area sections 204 and 206 in layout 202 can be combined to form active area section 244. Active area sections 212 and 210, and the unfilled area 220, can be combined to form active area section 242. Component 208 and the unfilled area 220 can be combined to form a new active area section 246, which is isolated from rail 236. Component 214 remains unchanged. Layout 240 includes areas 242 and 244, which have a greater overlap of busbars 238 and 236, respectively, than the overlap of busbars 218 and 216 in layouts 202 and 226. The unfilled area 220 is now included in area 260 of the active surface areas 246 and 242, which offers a larger active area and further reduces resistance.

[0049] In layout 240, active area sections 204 and 206 in layout 226 can be combined to form active area section 244. Active area sections 212 and 210, along with dummy filler section 222, can be combined to form active area section 242. Component 208 and dummy filler section 222 can be combined to form a new active area section 246, which is isolated from rail 236. Component 214 remains unchanged. Layout 240 includes sections 242 and 244, which have a greater overlap of busbars 238 and 236, respectively, than the overlap of busbars 218 and 216 in layouts 202 and 226. The dummy filling area 222 is now included in area 260 of the active surface areas 246 and 242, which offers a larger active area and further reduces resistance.

[0050] With reference to Fig. 5. A layout 302 is transformed into a layout 320 by combining active area regions that include regions across an nn or pp cell boundary 306. For example, logic circuits can be placed in a row on a chip, and additional rows are placed above and below each circuit row, with the n region or p region extending across the cell boundary. The layout 306 includes rails 304, 306, and 308, where rail 306 also represents a dopant boundary between pp or nn cells. The layout 306 includes the active regions 310, 312, and 316. In addition, an unfilled region 314 is arranged between other regions in the layout 302. Components 318 can include active area regions or other components or units.

[0051] In layout 320, areas 310 are combined into an active area 330; areas 312 and part of the unfilled area 314 are combined into an active area 332, and areas 316 and part of the unfilled area 314 are combined into an active area 336.

[0052] The active area 332 is combined across cell boundaries between regions with different dopant concentrations or even different dopant conductivities. In one embodiment, all sections of the active area 332 can be held at the same potential to allow the combination of different cell regions.

[0053] It is understood that in the area regions shown in the FIG., the active areas contain or will contain two or more VFETs or other transistor structures formed thereon. These units share a common S / D region (e.g., a bottom S / D region). These VFETs are configured with aggregated active areas that may include one or more of: adjacent units sharing bottom S / D regions and connected by a current bus, units in the same cell, units in adjacent cells (nn or pp units), adjacent units with bottom S / D regions connected by a ground bus, adjacent units with bottom S / D regions extending into filled (or unfilled) regions, adjacent regions with bottom S / D regions aggregated by a filled (or unfilled) region, etc.These VFETs with aggregated active area regions can, for example, include an inverter aggregated with another inverter, a NAND gate aggregated with another NAND gate or inverter, a NOR gate aggregated with another NOR gate or inverter, or any combination of combinational logic circuits and / or sequential logic circuits. Fill area active area regions can aggregate with inverters, NAND gates, NOR gates, or other gate structures or transistor groupings. For example, a fill area n region can aggregate with a unit adjacent to the fill area, and a unit in a p region can aggregate with a unit in the opposite direction.

[0054] With reference to Fig. Figure 6 illustrates an exemplary processing system 400 to which the present invention can be applied, according to one embodiment. The processing system 400 includes at least one processor (CPU) 402, which is operatively connected to other components via a system bus 405. A cache 406, a read-only memory (ROM) 408, a random access memory (RAM) 410, an input / output (I / O) adapter 420, an audio adapter 430, a network adapter 440, a user interface adapter 450, and a display adapter 460 are operatively connected to the system bus 405.

[0055] A first storage unit 422 and a second storage unit 424 are operatively connected to the system bus 405 via the I / O adapter 420. Storage units 422 and 424 can be disk storage units (e.g., magnetic or optical disk storage units), semiconductor magnetic units, and so on. Storage units 422 and 424 can be of the same type or of different types.

[0056] A loudspeaker 432 is connected to the system bus 405 via the audio adapter 130. A transmitter-receiver 442 is connected to the system bus 405 via the network adapter 440. A display unit 462 is connected to the system bus 405 via the display adapter 460.

[0057] A first user input unit 452, a second user input unit 454, and a third user input unit 456 are operatively connected to the system bus 405 via the user interface adapter 450. The user input units 452, 454, and 456 can be a keyboard, a mouse, a keypad, an image capture unit, a motion capture unit, a microphone, a unit comprising the functionality of at least two of the preceding units, and so on. Of course, other types of input units can also be used, as long as the essential content of the present invention is maintained. The user input units 452, 454, and 456 can be of the same type or different types. The user input units 452, 454, and 456 are used to input data into and output data from the system 400.

[0058] Naturally, the processing system 400 can also include other (not shown) elements, as a person skilled in the art can readily consider, and may omit certain elements. For example, depending on its specific implementation, the processing system 400 can include various other input and / or output units, as a person skilled in the art can readily understand. For instance, different types of wireless and / or wired input and / or output units can be used. Furthermore, additional processors, control units, memory, and so on can be incorporated in various configurations, as a person skilled in the art can readily see. These and other variants of the processing system 400 are readily apparent to a person skilled in the art when considering the teachings of the present invention provided herein.

[0059] Memory units 422 and 424 can include a circuit layout modification tool 470. A design layout can be entered into the system 400, and tool 470 evaluates the design to identify active area regions, trench isolation regions, and filled / unfilled regions that can be combined to reduce resistance and decrease the layout area for vertical transistor semiconductor units. Tool 470 employs the procedures described in Fig. 7 set forth and described herein.

[0060] The present invention may be a system, a method, and / or a computer program product. The computer program product may include a computer-readable storage medium (or media) on which computer-readable program instructions are stored to induce a processor to execute aspects of the present invention.

[0061] A computer-readable storage medium can be a physical unit capable of retaining and storing instructions for use by a system to execute instructions. For example, a computer-readable storage medium can be an electronic storage unit, a magnetic storage unit, an optical storage unit, an electromagnetic storage unit, a semiconductor storage unit, or any suitable combination thereof, without limitation. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), and erasable programmable read-only memory (EPROM).Flash memory), static random-access memory (SRAM), portable compact storage disk-read-only memory (CD-ROM), DVD (digital versatile disc), USB flash drive, floppy disk, a mechanically coded unit such as punched cards or raised structures in a groove on which instructions are stored, and any suitable combination thereof. A computer-readable storage medium shall not, in its use herein, be understood as volatile signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses guided by a fiber optic cable), or electrical signals transmitted by a wire.

[0062] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to individual data processing units or, via a network such as the internet, a local area network, a wide area network, and / or a wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission lines, wireless transmission, routing computers, firewalls, switching units, gateway computers, and / or edge servers. A network adapter card or network interface in each data processing unit receives computer-readable program instructions from the network and forwards them for storage on a computer-readable storage medium within the respective data processing unit.

[0063] Computer-readable program instructions for executing the steps of the present invention can be assembly instructions, ISA (Instruction Set Architecture) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., as well as conventional procedural programming languages ​​such as C or similar languages. The computer-readable program instructions can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server.In the latter case, the remotely located computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be established with an external computer (for example, via the internet using an internet service provider). In some embodiments, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), can execute computer-readable program instructions by using state information from the computer-readable program instructions to personalize the electronic circuits to perform aspects of the present invention.

[0064] Aspects of the present invention are described herein with reference to flowcharts and / or block diagrams or diagrams of methods, devices (systems), and computer program products according to embodiments of the invention. It is pointed out that each block of the flowcharts and / or block diagrams or diagrams, as well as combinations of blocks in the flowcharts and / or block diagrams or diagrams, can be executed by computer-readable program instructions.

[0065] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a specialized computer, or another programmable data processing device to create a machine, such that the instructions executed via the processor of the computer or other programmable data processing device generate a means of implementing the functions / steps specified in the block(s) of the flowcharts and / or block diagrams or charts.These computer-readable program instructions may also be stored on a computer-readable storage medium capable of controlling a computer, programmable data processing device, and / or other units to function in a particular manner, such that the computer-readable storage medium on which instructions are stored has a manufactured product, including instructions that implement aspects of the function / step specified in the block(s) of the flowchart and / or block diagrams or charts.

[0066] The computer-readable program instructions can also be loaded onto a computer, other programmable data processing device, or other unit to cause the execution of a series of process steps on the computer or other programmable device or other unit in order to generate a process executed on a computer, such that the instructions executed on the computer, other programmable device, or other unit implement the functions / steps specified in the block(s) of the flowcharts and / or block diagrams or charts.

[0067] The flowcharts and block diagrams or charts in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this context, each block in the flowcharts or block diagrams or charts can represent a module, segment, or part of instructions that includes one or more executable instructions for performing the specific logical function(s). In some alternative embodiments, the functions specified in the block may occur in a different order than shown in the figures. For example, two blocks shown consecutively may in reality be executed essentially simultaneously, or the blocks may sometimes be executed in reverse order depending on the corresponding functionality.It should also be noted that each block of the block diagrams or charts and / or flowcharts, as well as combinations of blocks in the block diagrams or charts and / or flowcharts, can be implemented by special hardware-based systems that perform the specified functions or steps, or execute combinations of special hardware and computer instructions.

[0068] With reference to Fig. 7. Procedures for a unit layout with vertical transistors are presented for illustration. In block 502, a unit layout can be created by inserting a summarization tool (470, Fig.6) provided (e.g., an existing or potential design), created, or improved. The Summary Tool 470 may be part of a package of design tools, or it may be a standalone tool or program that is executed using input from the layout or design. The layout or design is input into the tool or program for optimization. The tool or tool package may be deployed over a network or distributed computing system.

[0069] Block 504 identifies areas for grouping. Block 506 identifies active area areas for grouping in a layout of a semiconductor unit with vertical transistors. Filled (dummy-filled) or unfilled areas adjacent to active area areas can also be identified in the layout for grouping with the active areas.

[0070] Block 508 identifies sets of adjacent active surface areas with the same electrical potential. This may include identifying sets of adjacent active surface areas with the same fixed and / or a fixed or transient potential next to a filled or unfilled area. Other grouping criteria are also considered.

[0071] In Block 510, the sets of adjacent active area regions to be combined are prioritized based on one or more performance criteria. The one or more performance criteria are selected from the group consisting of resistance, capacitance, variability reduction, thermal resistance, circuit power, and worst-case variability reduction (e.g., evaluation based on worst-case scenarios of power or layout conflicts). Priorities can be established by defining rules to determine when and how a combination should be performed.

[0072] In Block 512, the sets of adjacent active areas are grouped together to create larger active areas according to a priority. The shapes of the sets of adjacent active areas can be modified to group them according to the prioritized grouping of the active areas.

[0073] In block 514, the sets of adjacent active area regions between logic units, e.g., between one or more inverters, NAND gates, NOR gates, etc., can be grouped together.

[0074] In Block 516, aggregation involves connecting the larger active area regions into one or more continuous buses, with the continuous buses replacing multiple separate supply or ground contacts. In Block 518, aggregation involves reducing trench isolation areas between sets of adjacent active area regions. In Block 520, aggregation may involve aggregating sets of adjacent active area regions across cell boundaries. This includes boundaries with differing dopant conductivities.

[0075] Block 522 specifies a new layout with consolidated active area regions, reduced shallow trench insulation, shared power and ground rails, etc. Among other advantages, the new layout includes reduced resistance and load on power supplies, lower resistance across source and drain regions, lower capacitance between VFETs sharing an active area, and better utilization of unfilled or dummy-filled regions.

Claims

[1] Method for a unit layout with vertical transistors, which has: Identifying active area regions in a layout of a semiconductor unit with vertical transistors; Determining sets of adjacent active surface areas with the same electrical potential; Prioritizing the identified rates for a summary of adjacent active area areas based on one or more performance criteria; and Combining sets of adjacent active area areas to form larger active area areas according to the priority determined on the basis of one or more performance criteria, where combining sets of adjacent active area regions involves combining sets of adjacent active area regions across cell boundaries. [2] The method of claim 1, further comprising: Detecting filled or unfilled areas adjacent to active areas in the layout; Combining filled or unfilled areas with sets of adjacent active area areas to form larger active area areas. [3] Method according to claim 2, wherein determining the sets of adjacent active surface areas with the same electrical potential comprises determining the sets of adjacent active surface areas with a fixed or transient potential next to a filled or unfilled area. [4] Method according to claim 1, wherein determining the sets of adjacent active surface areas with the same electrical potential comprises determining the sets of adjacent active surface areas with the same fixed potential. [5] Method according to claim 1, wherein the combining of sets of adjacent active area regions comprises modifying shapes of the active area regions to combine prioritized active area regions. [6] Method according to claim 1, wherein the grouping of sets of adjacent active area regions comprises a grouping of active area regions between logic units. [7] Method according to claim 6, wherein the logic units are selected from the group consisting of combinational logic elements and sequential logic elements. [8] Method according to claim 1, further comprising connecting the larger active area regions to form one or more through buses, wherein the through buses replace a plurality of separate supply or ground contacts. [9] Method according to claim 1, wherein the combining of sets of adjacent active area areas further comprises a reduction of trench isolation areas between the sets of adjacent active area areas. [10] Method according to claim 1, wherein the combining of sets of adjacent active area regions comprises combining sets of adjacent active area regions across cell boundaries between different rows. [11] Method according to claim 1, wherein one or more performance criteria are selected from the group consisting of resistance, capacitance, reduction of variability, thermal resistance, circuit power and reduction of worst case variability; [12] Non-transitory, computer-readable storage medium comprising a computer-readable program for a unit layout with vertical transistors, wherein the computer-readable program, when executed on a computer, causes the computer to perform the steps according to the method according to any one of claims 1 to 11.

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