SiC wafer, semiconductor device, method for manufacturing the SiC wafer and method for tracing defects in SiC wafers and semiconductor devices

Abstract

SiC wafers the difference between the density of filament dislocations exposed on a first surface and the density of filament dislocations exposed on a second surface is 10% or less of the filament dislocation density on the surface with the higher filament dislocation density on the first surface and the second surface, 90% or more of the filament dislocations exposed on the surface with the higher filament dislocation density extend to the surface with the lower filament dislocation density, and The density of exposed dislocations on the surface with the higher dislocation density between the first and second surfaces is at most 1.5 dislocations / mm². 2 amounts, wherein the filament dislocations exposed on a first surface and a second surface of a SiC wafer can be matched by identifying the exposed filament dislocations on one of the surfaces through non-destructive measurement.

Description

TECHNICAL AREA

[0001] The present invention relates to a SiC wafer, a semiconductor device, a method for producing the SiC wafer and a method for tracking defects in SiC wafers and semiconductor devices. TECHNICAL BACKGROUND

[0002] Silicon carbide (SiC) exhibits a dielectric breakdown strength that is an order of magnitude higher than that of silicon (Si), and its band gap is three times larger than that of silicon (Si). Additionally, the thermal conductivity of silicon carbide (SiC) is approximately three times higher than that of silicon (Si). Therefore, the application of silicon carbide (SiC) is expected in power devices, high-frequency devices, devices operating at high temperatures, and similar applications.

[0003] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a well-known semiconductor device that utilizes an epitaxial SiC wafer. In a MOSFET, a gate oxide film is formed on an epitaxial SiC layer through thermal oxidation or similar processes, and a gate electrode is formed on this gate oxide film. If a defect occurs in the SiC wafer, which serves as the substrate on which the semiconductor device is formed, abnormalities can arise in the semiconductor device (for example, PTL1 and the like). Therefore, to promote the practical application of semiconductor devices using epitaxial SiC wafers, it is crucial to provide high-quality epitaxial SiC wafers and high-quality epitaxial growth techniques.

[0004] On the other hand, various defects are present in the epitaxial SiC wafer. Not all defects affect semiconductor devices. This means that, depending on the defect type, some defects may have no or only a minor impact on semiconductor devices. For example, it is known that threading dislocations and the like can cause semiconductor device failure, but it is not precisely known which type of threading dislocation, in particular, can become a killer defect. Therefore, it is necessary to identify, among various defects, those that have a major impact on the semiconductor device and to suppress their generation. In this patent, a wafer before epitaxial growth is referred to as a SiC wafer, and a wafer after epitaxial growth is referred to as an epitaxial SiC wafer.

[0005] DE 102 47 017A1, JP 2008- 290 885A, DE 11 2013 001 934 T5 and DE 10 2009 016131 A1 disclose methods for the production of SiC wafers with a low density of defects. Citation listPatent literature

[0006] [PTL 1] Published Japanese translation JP 2015-521378 A of the international PCT publication WO 2014 / 043 104 A1 SUMMARY OF THE INVENTION Technical Problem

[0007] However, identifying which fault mode among the filament dislocations can become a killer defect is still insufficiently advanced. This is because filament dislocations leading to semiconductor device failure can combine during a crystal growth process or, in some cases, be newly generated, and it is difficult to specify the cause of filament dislocation generation that impacts the semiconductor device. Additionally, because the semiconductor device forms on the surface of the SiC wafer, determining which surface defect will lead to failure requires examining the surface condition of the SiC wafer, which destroys the semiconductor device. However, destroying the semiconductor device requires precise machining, which is time-consuming and costly.Furthermore, there are cases where new scratches and the like are added during the destruction.

[0008] The present invention was made in view of the above problems, and one of its objectives is to provide a SiC wafer in which a defect that causes a failure of a semiconductor device can be identified non-destructively after the device has been manufactured, and a method for its manufacture. Solution to the problem

[0009] Through intensive investigations, the present inventors have discovered that defects which cause a failure of a semiconductor device can be identified non-destructively even after the device has been manufactured, by matching threading disclocations exposed on a first surface and a second surface of a SiC wafer, and have thereby made the present invention.

[0010] The present invention is defined in the accompanying patent claims.

[0011] One aspect of the present invention is a SiC wafer, wherein the difference between the density of filament dislocations exposed on a first surface and the density of filament dislocations exposed on a second surface is 10% or less of the filament dislocation density on the surface with the higher filament dislocation density on the first surface and the second surface, 90% or more of the filament dislocations exposed on the surface with the higher filament dislocation density extend to the surface with the lower filament dislocation density, and the density of the filament dislocations exposed on the surface with the higher filament dislocation density is at most 1.5 filament dislocations / mm 2 amounts, wherein the filament dislocations exposed on a first surface and a second surface of a SiC wafer can be matched by identifying the exposed filament dislocations on one of the surfaces through non-destructive measurement.

[0012] Another aspect of the present invention is a semiconductor device comprising a SiC wafer according to the invention, an oxide insulating layer formed on the SiC wafer, and an electrode formed on the oxide insulating layer, wherein the SiC wafer has an exposed surface with exposed filament dislocations, wherein the position of the failure defect in the electrode and the oxide insulating layer corresponds to the position of one of the exposed filament dislocations, and wherein the exposed filament dislocations can be identified by non-destructive measurement.

[0013] Another aspect of the present invention is a method for producing a SiC wafer according to the invention, which comprises the following: a manufacturing step for producing a seed crystal with an areal density of 1.5 or fewer thread dislocations / mm 2 , a crystal growth step for carrying out a crystal growth such that the diameter of a crystal does not increase from that of a seed crystal in a crucible and the crystal growth surface and isotherms in the crucible are parallel to each other, and a cutting step in which a SiC ingot obtained in the crystal growth step is cut up.

[0014] Another aspect of the present invention is a method for tracking defects in a SiC wafer, which comprises the steps of the inventive method for producing a SiC wafer, a step in which the filament dislocations exposed on the first surface and the second surface of the SiC wafer are identified, and a step in which the filament dislocations exposed on the first surface and the second surface are matched to each other.

[0015] Another aspect of the present invention is a method for tracking defects in a semiconductor device, wherein the semiconductor device comprises a SiC wafer according to the invention, an oxide insulating layer formed on the SiC wafer, and an electrode formed on the oxide insulating layer, wherein the SiC wafer has an exposed surface with exposed filament dislocations, and wherein the method comprises a step in which the filament dislocations exposed on the first surface and the second surface of the SiC wafer are identified, and a step in which the filament dislocations exposed on the first surface and the second surface are matched to each other. Advantageous effects of the invention

[0016] In the SiC wafer according to the present invention, a defect that causes a failure of a semiconductor device can be identified non-destructively after the device has been manufactured.

[0017] In the method for producing a SiC wafer according to the present invention, a SiC wafer can be obtained in which a defect that causes a failure of a semiconductor device can be identified non-destructively after the device has been manufactured. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] They show: Fig. 1 a schematic sectional view of a SiC wafer according to an embodiment of the present invention, Fig. 2 a schematic sectional view of an example of a semiconductor device produced using the SiC wafer according to the embodiment of the present invention, Fig. 3 a schematic sectional view of an example of a semiconductor device formed using a SiC wafer in which no exposed filament dislocations occur on either a first or a second face, and Fig. 4 a transmission x-ray topographic image of a SiC wafer. DESCRIPTION OF EXECUTION FORMS

[0019] An embodiment is described in detail below with appropriate reference to the drawings. In the drawings used in the following description, there are instances where, for the sake of clarity, characteristic sections have been enlarged to facilitate understanding of the features of the present invention, whereby the dimensional ratios and corresponding characteristics of the respective components may differ from reality. Furthermore, the materials, dimensions, and the like presented in the following description serve only as examples, and the present invention is not limited to them and can be implemented by suitably modified versions that do not alter the fundamental concept of the invention. (SiC wafer)

[0020] Fig. Figure 1 is a schematic sectional view of a SiC wafer according to an embodiment of the present invention. A Fig. 1 The SiC wafer 1 shown has threading dislocations 2 which pass through a first surface 1a and a second surface 1b.

[0021] The SiC wafer 1 typically has a c-plane (0001) as its main plane. In the Fig. In the SiC wafer 1 shown, the first surface 1a is a (surface) on the side of the crystal growth direction, and the second surface 1b is a surface opposite the first surface 1a. Here, the "surface on the side of the crystal growth direction" means the surface on the side where a crystal has grown after an ingot growth process. That is, in the Fig. In the SiC wafer 1 shown, an ingot grows from the side of the second surface 1b to the side of the first surface 1a before the SiC wafer 1 is cut.

[0022] The SiC wafer 1 is not designed for the case of Fig. 1 restricted. The first surface 1a can be located on a Si-{0001} surface plane or on a C-{000-1} surface plane.

[0023] The thread dislocations 2 penetrate the SiC wafer 1 in the thickness direction and are exposed on both the first face 1a and the second face 1b. The thread dislocations 2 extend perpendicular to the c-plane of the SiC wafer 1. In the case of a SiC wafer obtained by cutting a SiC ingot produced from a seed crystal using step-flow growth, the thread dislocations 2 emerge through the SiC wafer 1 with a slight inclination with respect to the first face 1a and the second face 1b, as shown in Fig. 1 is shown. On the other hand, if a SiC wafer obtained by cutting a SiC ingot grown on a flat surface without offset angles is used, the thread dislocations 2 pass perpendicularly through the first surface 1a and the second surface 1b of the SiC wafer 1.

[0024] In both cases, the dislocations 2 are exposed on the first surface 1a and the second surface 1b. This means that the dislocations 2a exposed on the first surface 1a and the dislocations 2b exposed on the second surface 1b merely appear as identical dislocations 2 on different surfaces and exhibit a corresponding relationship.

[0025] Fig. Figure 2 is a schematic sectional view of an example of a semiconductor device formed using the SiC wafer according to the embodiment of the present invention. An example case is described here in which epitaxial C-area growth occurs on the first surface 1a to form a semiconductor device.

[0026] One in Fig. 2 The semiconductor device 10 shown has an oxide insulating layer 3 formed on the first surface 1a of the SiC wafer 1 described above, and an electrode 4 formed on the surface of the oxide insulating layer 3 which is located on the opposite side of the SiC wafer.

[0027] At the Fig. In the semiconductor device 10 shown in Figure 2, for example, if a section of the filament dislocation 2a exposed on the first surface 1 is a killer defect that leads to a failure of the semiconductor device 10, the thickness of the oxide insulating layer 3 formed on the killer defect can vary. Furthermore, if a voltage is applied to the electrode 4 formed on the oxide insulating layer 3, a voltage concentration occurs in a section where the film thickness of the oxide insulating layer 3 is small, and a short circuit of the element occurs, which can cause a failure fault 5.

[0028] This means that the failure defect 5 occurs at a position corresponding to the thread dislocation 2a exposed on the first surface 1a of the SiC wafer 1.

[0029] As described above, in the semiconductor device 10, in which the SiC wafer according to the embodiment of the present invention is used, the failure defect 5 and the filament dislocation 2a exposed on the first surface 1a are related, and the filament dislocation 2a exposed on the first surface 1a and the filament dislocation 2b exposed on the second surface 1b are related. In other words, the cause of the failure defect 5 can be traced back to the filament dislocation 2b exposed on the second surface 1b. Therefore, by identifying the filament dislocation 2b exposed on the second surface 1b by non-destructive measurement, such as X-ray topography, the history of a killer defect that leads to a failure can be traced on the second surface 1b.

[0030] At the Fig. Figure 2 of the semiconductor device 10 describes the case in which the oxide insulating layer 3 and the electrode 4 are formed on the first surface 1a. However, a killer defect can also be traced in the same way in a case in which the oxide insulating layer 3 and the electrode 4 are formed on the second surface 1b. The epitaxial growth to form the semiconductor device can be either epitaxial carbon surface growth or epitaxial silicon surface growth.

[0031] In contrast, as with a SiC wafer 21, which is in a Fig. The semiconductor device 20 shown in Figure 3 contains a case in which the filament dislocations 22 are not exposed on both a first surface 21a and a second surface 21b. In this case, a killer defect cannot be traced. The Fig. The thread dislocation 22 shown in Figure 3 is generated by converting a basal plane dislocation 22a into a thread dislocation 22b.

[0032] This means that in the SiC wafer 1 according to the embodiment of the present invention, most of the filament dislocations exposed on the first surface 1a are the filament dislocations 2 extending to the second surface 1b, and that defects which become the cause of the failure defect 5 of the semiconductor device 10 can be traced non-destructively.

[0033] The difference between the dislocation density of the dislocations exposed on the first surface 1a and the dislocation density of the dislocations exposed on the second surface 1b is at most 10% of the dislocation density of the dislocations on the first surface 1a and the second surface 1b, which has the higher dislocation density. Furthermore, the difference is preferably at most 5% and more preferably at most 1% of the dislocation density of the dislocations on the first surface 1a and the second surface 1b, which has the higher dislocation density.

[0034] If the difference between the thread dislocation density of thread dislocations exposed at the first surface 1a and the thread dislocation density of thread dislocations exposed at the second surface 1b lies within the above range, it can be postulated that the thread dislocations exposed at the first surface 1a and the thread dislocations exposed at the second surface 1b exhibit a correlation with each other.

[0035] On the other hand, it cannot be said that the filament dislocations exposed on the first surface 1a and the filament dislocations exposed on the second surface 1b exhibit a correlation simply because the difference between the filament dislocation density of the filament dislocations exposed on the first surface 1a and the filament dislocation density of the filament dislocations exposed on the second surface 1b is satisfied. This is because there is a case in which the filament dislocation densities of both surfaces are close to each other, even if there is no correlation between them.

[0036] Therefore, of the filament dislocations in the SiC wafer, the proportion of filament dislocations 2 that penetrate the first surface 1a and the second surface 1b is 90% or more, preferably 95% or more, and even more preferably 99% or more. Here, the number of filament dislocations in the SiC wafer can be considered to be equal to the number of filament dislocations exposed at the surface of the first surface 1a and the second surface 1b that has a higher filament dislocation density.

[0037] As described above, because the filament dislocations 2 connect the first surface 1a with the second surface 1b, the cause of the failure fault 5 can be traced. On the other hand, if most of the filament dislocations 2a exposed on the first surface 1a have a correspondence relationship, the history of the failure fault 5 can be sufficiently traced even if some of the filament dislocations 22 in Fig. 3 remain. Therefore, if the proportion of filament dislocations 2 that penetrate the first surface 1a and the second surface 1b is within the range mentioned above, many filament dislocations in the SiC wafer can be traced and the cause of the failure defect 5 can be found.

[0038] It is preferred that, in the SiC wafer 1, the number of exposed dislocations 2a on the first surface 1a and the number of exposed dislocations 2b on the second surface 1b are essentially equal. Here, "essentially equal" need not be exactly equal and allows a difference of approximately 0.02 dislocations / mm. 2As described above, because the thread dislocations 2 connect the first surface 1a to the second surface 1b, the cause of the failure 5 can be traced. That is, if the number of thread dislocations 2a of the first surface 1a and the number of thread dislocations 2b of the second surface 1b are substantially equal, the cause can be traced. With regard to tracing all results, it is preferred that the number be exactly the same.

[0039] It can be confirmed using an X-ray topographic image of a wafer that thread dislocations penetrate the wafer. Fig. Figure 4 is a transmission X-ray topographic image of an actual manufactured wafer. In the image, the positions of threading edge dislocations (TED) and threading screw dislocations (TSD) are indicated by arrows. It is possible that the threading screw dislocation (TSD) in the figure is a mixed dislocation of a threading screw dislocation and an edge dislocation; however, it is in any case a threading dislocation. Other black dots are different from threading dislocations, such as basal plane dislocations. Because the in Fig.As shown in Figure 4, when viewed through the entire thickness direction of the wafer, a filament dislocation is identified by its shape, e.g., a V-shape, if the filament dislocation transforms or disappears along part of its path. In this image, the filament dislocations are represented as short, beard-like contrasts, and these filament dislocations do not interact with or combine with the basal plane dislocations, nor do they disappear. This means that the filament dislocations extend through the interior of the wafer.

[0040] The filamentary dislocations exposed at the first surface 1a and the second surface 1b of the SiC wafer 1, the basal plane dislocations (which differ from the filamentary dislocations), and the like are distinguished and observed based on their lengths in the transmission X-ray topography image. The basal plane dislocations extend in the a-axis direction within the wafer and are accordingly observed as filamentary dislocations that are longer than the filamentary dislocations in the image. The transmission topography image is the simplest method for observing dislocations. However, there is a case in which it is difficult to determine whether the dislocations are exposed. In such a case, a method similar to cross-sectional topography can be used to determine whether observed dislocations are embedded within the substrate or exposed.Alternatively, reflection topography using X-rays with high surface resolution and low energy can be employed. In particular, there is a method for photographing a (1 1 - 2 8) diffraction surface using Cu-Kα rays.

[0041] Additionally, in the SiC wafer 1, the density of the filamentary dislocations 2 exposed on the surface 1a and the surface 1b, which has the higher filamentary dislocation density, is preferably at most 1.5 filamentary dislocations / mm². 2 , preferably no more than 0.8 thread displacements / mm 2 and even more preferably a maximum of 0.15 thread displacements / mm 2 .

[0042] The filament dislocation densities of the first surface 1a and the second surface 1b of the SiC wafer 1 are calculated as follows. Observation points are selected within a 500 µm × 500 µm area of ​​the first surface 1a and the second surface 1b of the SiC wafer 1, passing through the center of the wafer at 5 mm intervals in the form of straight lines. Observation points are also selected in a direction where the straight lines are rotated by 90°, passing through the center of the wafer at 5 mm intervals in the form of straight lines. Filament dislocations in each area are counted using the X-ray topographic image, allowing the filament dislocations to be distinguished from other basal plane dislocations and the like, and enabling the calculation of the average filament dislocation density per area.

[0043] Based on the obtained thread dislocation density of the first surface 1a and the obtained thread dislocation density of the second surface 1b, the difference between the density of the thread dislocations exposed on the first surface 1a and the density of the thread dislocations exposed on the second surface 1b can be calculated.

[0044] The filamentary dislocations penetrating the substrate do not necessarily extend perpendicularly due to different growth modes, the presence of an offset angle, and the like, and may sometimes be bent within the substrate. In other words, it is necessary to reduce the filamentary dislocation densities to a certain degree to specify whether the filamentary dislocations observed from the back side correspond to a defective section of the surface. Furthermore, overlaps between dislocations must be almost entirely absent. With this in mind, the filamentary dislocation density that can be used in this application is 1.5 filamentary dislocations / mm². 2 .

[0045] The high density of thread dislocations exposed at the surface with the higher dislocation density of the first surface 1a and the second surface 1b of the SiC wafer 1 means that the probability increases that the thread dislocations can combine and disappear during crystal growth. As the absolute number of thread dislocations that can combine and disappear increases, the proportion of thread dislocations penetrating both the first surface 1a and the second surface 1b is usually low. Additionally, the total number of thread dislocations also increases, making it difficult to establish a correspondence between the first surface 1a and the second surface 1b.

[0046] On the other hand, if the density of the thread dislocations 2 is sufficiently low, the correspondence relationship between the thread dislocations 2a and 2b exposed at the first surface 1a and the second surface 1b, respectively, can be readily established. This means that the cause of the failure defect 5 can be precisely traced. Additionally, the probability that the thread dislocations can combine and disappear decreases, thus increasing the proportion of thread dislocations 2 penetrating both the first surface 1a and the second surface 1b.

[0047] Additionally, the difference between the density of the filament dislocations exposed on the first surface 1a and the density of the filament dislocations exposed on the second surface 1b is preferably at most 0.02 filament dislocations / mm². 2 and preferably at most 0.002 thread displacements / mm 2 .

[0048] If the densities of the filamentary dislocations exposed on the first surface 1a and the second surface 1b are close to each other, the number of newly generated filamentary dislocations is small. This means that filamentary dislocations other than the traced faults are neither generated nor disappear.

[0049] When considering the actual defect tracking process, it is conceivable to first measure the densities of the filament dislocations exposed at the first surface 1a and the second surface 1b and to check for any difference in these densities. This is because if the measured filament dislocation densities differ significantly, it suggests that the proportion of filament dislocations penetrating both the first surface 1a and the second surface 1b is decreasing, indicating that the SiC wafer is not suitable for defect tracking. Conversely, if there is only a small difference between the density of filament dislocations exposed at the first surface 1a and the density of filament dislocations exposed at the second surface 1b, it can be easily determined that the SiC wafer is suitable for defect tracking, thus increasing the effectiveness of the defect tracking process.

[0050] As described above, by using the SiC wafer according to the embodiment of the present invention, a defect that becomes a cause of failure of a semiconductor device can be identified non-destructively after the device has been built.

[0051] (Method for producing a SiC wafer) A method for producing a SiC wafer according to the embodiment of the present invention comprises a manufacturing step in which a seed crystal or seeding crystal with a surface density of 1.5 or less filament dislocations / mm² is prepared. 2 The process involves a crystal growth step in which the diameter of the crystal does not increase compared to that of the seed crystal in a crucible and the crystal growth surface and isotherms in the crucible are parallel to each other, and a cutting step in which a SiC ingot or SiC block obtained in the crystal growth step is cut up. <herstellungsschritt>

[0052] First, the seed crystal is produced in the manufacturing step. The seed crystal is obtained by a repeated a-plane (RAF) process. In the RAF process, c-plane growth is performed after at least one a-plane growth. By using the RAF process, a SiC single crystal can be produced that is essentially free of screw dislocations and stacking faults. This is because defects present in the SiC single crystal after a-plane growth become basal plane-directed defects during c-plane growth and do not propagate. Details of the RAF process are described, for example, in the unexamined Japanese patent application with first publication number 2003-321298.

[0053] Additionally, the crystal grown using the RAF method can be used as a seed crystal. Furthermore, c-plane (0001-plane) growth can be performed on it to produce a crystal with a reduced number of thread dislocations, and this crystal can then be used as a seed crystal. As the crystal growth progresses, the thread dislocations merge, and the thread dislocation density decreases. This means that by performing the crystal growth step sufficiently, the thread dislocation density can be further reduced. This further reduces the variation in the number of thread dislocations during the crystal growth process, thus making it easier and more reliable to obtain a desired SiC wafer.

[0054] The seed crystal produced by this procedure exhibits very few or no filament dislocations.

[0055] The areal density of thread dislocations in the seed crystal is preferably at most 1.5 thread dislocations / mm². 2 , preferably 0.8 or fewer thread offsets / mm 2 and even more preferred 0.15 or fewer thread displacements / mm 2 If the number of thread dislocations in the seed crystal is small, the number of thread dislocations in the first and second faces of the SiC wafer can easily be kept constant.

[0056] The surface density of the thread dislocations in the seed crystal can, at least on the surface where the SiC ingot grows, satisfy the aforementioned range. Additionally, the surface density of the thread dislocations in the seed crystal is measured, as are the thread dislocation densities of the first surface 1a and the second surface 1b of the SiC wafer 1.

[0057] The thread dislocations in the seed crystal can combine during the crystal growth process to obtain a SiC ingot based on the seed crystal, and their number can be reduced. If the thread dislocation density in the seed crystal is high, the probability of the thread dislocations combining during the crystal growth process increases. If the number of thread dislocations varies during the crystal growth process, this usually results in a difference in the number of thread dislocations between the first and second faces of the SiC wafer obtained by slicing the SiC ingot.

[0058] If, on the other hand, the thread dislocation density of the initial seed crystal is sufficiently low, the probability of thread dislocations combining can be reduced. This means that it is easily possible to ensure that the number of thread dislocations in the first and second faces of the SiC wafer remains constant. If a seed crystal has at most 0.15 thread dislocations / mm² 2 When this method is used, a combination of thread dislocations and their disappearance largely does not occur. Therefore, with respect to the thread dislocations caused by the seed crystal, the number of thread dislocations exposed on the first and second faces of the SiC wafer can be kept essentially equal. <Kristallzüchtungsschritt>

[0059] Next, a crystal growth process is performed on the obtained seed crystal to produce a SiC ingot. During the crystal growth step, the variation in the number of thread dislocations is not limited to the combination of thread dislocations; the conversion of thread dislocations to basal plane dislocations or similar is also a contributing factor.

[0060] Therefore, during the crystal growth step, the crystal growth is performed in such a way that the conversion of thread dislocations to basal plane dislocations or the generation of new thread dislocations is suppressed, in addition to the suppression of combinations of thread dislocations. To suppress the variation in the number of thread dislocations during the crystal growth step, the crystal growth is performed taking the following points into account.

[0061] The first point is that the diameter of the crystal is not increased during crystal growth. In recent years, a need has arisen to increase the diameter of a SiC wafer to obtain many semiconductor devices from a single substrate. Therefore, the diameter of a crystal is generally increased using a conical guide. The conical guide refers to a conical element whose diameter increases from a seed crystal to a SiC source when a SiC crystal is grown by a sublimation process. When the conical guide is used, the SiC crystal grows along the cone shape, so the diameter can be increased by making the shape of the growth surface convex.

[0062] However, with increasing diameter, a transformation of thread dislocations into basal plane dislocations readily occurs, particularly in an end section of the SiC ingot. This means that with increasing diameter, the number of thread dislocations varies slightly during crystal growth, and it becomes difficult to keep the number of thread dislocations constant in the first and second faces of the SiC wafer.

[0063] Therefore, in the method for producing a SiC wafer according to the embodiment of the present invention, the diameter is not increased. In a method where the diameter is not increased, a cylindrical guide with a constant diameter is used instead of a conical guide.

[0064] The second point is that crystal growth should be carried out in such a way that the crystal growth surface and the isotherms in the crucible become parallel to each other. During the growth process, the conversion of thread dislocations to basal plane dislocations occurs readily in the final section if the crystal growth surface is curved, as is the case with increasing diameter. This means that it is preferable to keep the crystal growth surface as flat as possible during crystal growth.

[0065] Crystal growth is highly influenced by temperature. Therefore, a flat crystal growth surface can be maintained by positioning the isotherms parallel to the crystal growth surface. The isotherms need not be perfectly parallel to the crystal growth surface and can be substantially parallel to it. It is particularly preferred to carry out the crystal growth such that the inclination angle of the isotherms with respect to the crystal growth surface is less than 2° in absolute terms in every direction.

[0066] To maintain the isotherms in a temperature distribution parallel to the crystal growth surface during crystal growth, a method disclosed in the unexamined Japanese patent application with first publication number 2008-290885 can be used. In particular, a crystal growth device using a sublimation process can be used, which is constructed such that an upper and a lower heater are provided, including a heater opposite a side plane at a location where a seed crystal is located and a heater opposite a side plane at a location where a source is located, and a partition section made of a heat-insulating element is provided between the upper and the lower heaters.The partition section prevents heat transfer from the lower heating element to the top of the crucible, and it can therefore be ensured that the isotherms are parallel to the surface of the seed crystal.

[0067] During crystal growth by sublimation, the growth surface exhibits a striped pattern due to differences in nitrogen (N) concentration as the growth process progresses while the amount of nitrogen (N) doping is periodically varied. This pattern is sectioned longitudinally, and the shape of the growth surface can be determined at any time by observing the interface with its color changes. If the growth surface changes shape during growth, its shape can be maintained by making adjustments according to the following procedure.

[0068] Maintaining the isotherms during crystal growth can also be achieved by combining other techniques. In particular, a crucible is moved during growth so that any change in the growth surface shape obtained beforehand in the method described above is corrected, and a technique is used in combination with this in which the isotherms and the height of the growth surface are kept consistent.

[0069] First, a partition section made of a heat-insulating material is provided between a high-temperature area and a low-temperature area to achieve a temperature distribution where the isotherms are parallel to the seed crystal surface at the start of the growth process. Then, the height of the growth surface is derived at any given time from previously confirmed growth results under the same conditions. Growth is carried out while the height of the growth surface is controlled so that it equals the height of the partition section formed from the heat-insulating material. The angle of the isotherms can then be maintained parallel to the surface of the seed crystal.

[0070] Furthermore, a method using a cylindrical guide can be combined with the method of keeping the isotherms parallel to the surface of the seed crystal. This method is very effective. The cylindrical guide, which is parallel to the crucible in the vertical direction, ensures, compared to a guide inclined to increase its diameter, that the isotherms are parallel to the surface of the seed crystal in a simple manner.

[0071] Additionally, dislocations of SiC can propagate if strong stresses occur in a crystal during growth. If the temperature gradient near the crystal increases during growth, the stresses in the crystal also increase. Temperature gradients near the crystal include a growth-direction (growth axis) and a radial temperature gradient. The radial temperature gradient can be reduced by aligning the isotherms parallel to the surface of the seed crystal using a device with a partition section and top and bottom heating elements, as described above. The growth-axis temperature gradient can be reduced by decreasing the temperature difference between the seed crystal and the heat source.If the temperature gradient is too low, growth becomes unstable, so it is preferred if the temperature gradient in the direction of the growing axis is about 50 Kcm. -1 The propagation of dislocations due to stress can be suppressed by controlling both the temperature gradient in the growth axis direction and the temperature gradient in the radial direction to small values ​​in a range where stable growth can be achieved.

[0072] Additionally, there are cases where the growth atmosphere becomes carbon-rich, carbon inclusions occur, and dislocations are generated as a result. The generation of dislocations by carbon inclusions can be suppressed by determining whether the growth atmosphere of the fault condition is carbon-rich and adjusting the conditions accordingly. To prevent the growth atmosphere from becoming carbon-rich, methods such as adding silicon to the source in addition to SiC, covering the crucible wall with a TaC element or similar material, and the like can be employed.

[0073] As described above, variations in thread dislocations during the crystal growth step can be reduced by maintaining the isotherms without increasing the diameter and performing crystal growth while suppressing the generation of new thread dislocations. This easily ensures that the number of thread dislocations in the first and second faces of the SiC wafer remains constant. <schneidschritt>

[0074] Finally, the resulting SiC ingot is cut. A known method for cutting the SiC ingot can be used. For example, a wire saw or similar tool can be used.

[0075] As described above, in the method for producing a SiC wafer according to the embodiment of the present invention, a SiC wafer can be obtained in which a defect that causes a failure of a semiconductor device can be identified non-destructively after the formation of the device. List of reference symbols 1, 21 SiC wafers 1a, 21a first area 1b, 21b second area 2, 2a, 2b, 22, 22B thread dislocation 3 Oxide insulating layer 4 electrode 5 failure errors 10, 20 Semiconductor device 22A Basal Plane Dislocation< / schneidschritt> < / herstellungsschritt>

Claims

[1] SiC wafer, where the difference between the density of thread dislocations exposed on a first surface and the density of thread dislocations exposed on a second surface is 10% or less of the thread dislocation density on that of the first surface and the second surface having the higher thread dislocation density, 90% or more of the thread dislocations exposed at that of the first surface and the second surface having the higher thread dislocation density extend to the surface having the lower thread dislocation density, and the density of the thread dislocations exposed on that of the first surface and the second surface which has the higher thread dislocation density is not more than 1.5 thread dislocations / mm 2 amounts, wherein the thread dislocations exposed on a first surface and a second surface of a SiC wafer can be associated with each other by identifying the exposed thread dislocations on one of the surfaces by a non-destructive measurement. [2] The SiC wafer according to claim 1, wherein the difference between the density of the filamentary dislocations exposed on the first surface and the density of the filamentary dislocations exposed on the second surface is at most 0.02 filamentary dislocations / mm 2 amounts. [3] A semiconductor device comprising a SiC wafer according to claim 1 or 2, an oxide insulating layer formed on the SiC wafer, and an electrode formed on the oxide insulating layer, the SiC wafer having an exposed surface with exposed filamentary dislocations, the position of the failure defect in the electrode and the oxide insulating layer corresponding to the position of one of the exposed filamentary dislocations, the exposed filamentary dislocations being identifiable by non-destructive measurement. [4] A method for producing a SiC wafer according to any one of claims 1 to 3, comprising: a manufacturing step for producing a seed crystal with an areal density of 1.5 or less thread dislocations / mm 2 , a crystal growth step for carrying out crystal growth such that the diameter of a crystal does not increase from that of a seed crystal in a crucible and the crystal growth surface and isotherms in the crucible are parallel to each other, and a cutting step in which a SiC ingot obtained during the crystal growth step is cut up. [5] A method for tracking defects in a SiC wafer, comprising the steps of the method for manufacturing a SiC wafer according to claim 4, a step of identifying the thread dislocations exposed on the first surface and the second surface of the SiC wafer, and a step of associating the thread dislocations exposed on the first surface and the second surface. [6] A method for tracking defects in a semiconductor device, the semiconductor device including the SiC wafer according to claim 1 or 2, an oxide insulating layer formed on the SiC wafer, and an electrode formed on the oxide insulating layer, the SiC wafer having an exposed surface with exposed filamentary dislocations, the method comprising a step of identifying the filamentary dislocations exposed on the first surface and the second surface of the SiC wafer, and a step of associating the filamentary dislocations exposed on the first surface and the second surface with each other.

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