FREQUENCY ESTIMATION, CORRECTION AND NOISE REDUCTION FOR MODEMS

Abstract

A frequency shift keying (FSK) demodulator (100, 200) comprising the following: a frequency estimator (104, 204) based on a digital phase-locked loop (DPLL) configured to convert a phase signal into a frequency signal; a frequency offset estimator (106) that is communicatively coupled to the DPLL-based frequency estimator (104, 204), wherein the frequency offset estimator is configured to estimate and track a direct current (DC) component of the frequency signal; and a mean value filter (108, 208A, 208B) which is communicatively coupled to the frequency offset estimator (106), wherein the mean value filter (208A, 208B) is configured to perform an accumulate-and-discharge operation to improve a signal-to-noise ratio (SNR) at the symbol level of the frequency signal.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of communication devices and, more particularly, to frequency modulation schemes used in communication devices. BACKGROUND

[0002] A modem (modulator-demodulator) is a network device that modulates and demodulates signals to enable the transmission of information. A modem may employ some type of frequency modulation scheme to implement modulation and demodulation. For example, modems such as Bluetooth modems, ZigBee modems, Bluetooth Low Energy (BLE) modems, and the like may employ some type of frequency modulation scheme called frequency shift keying (FSK) modulation. FSK modulation may be configured to enable the transmission of digital information through discrete frequency changes. However, it should be noted that currently available FSK demodulation techniques may not satisfy some performance requirements. Furthermore, the disclosure of US 2005 / 0 249 307 A1 may be helpful for understanding the present invention.This document discloses an integrated burst FSK receiver for receiving and evaluating an RF signal with FSK modulation. The integrated burst FSK receiver uses a programmable RF local oscillator to downconvert a received signal to an IF range or baseband, where it is filtered and sampled for subsequent digital processing. Digital filtering and detection are used to improve the overall bit error rate performance and receiver sensitivity. A programmable digital low-pass or band-pass filter can also be used for interference rejection. A matched filter correlator can be used for detection and symbol timing adjustment in one mode, while an adaptive frequency comparator can be used in another mode. Circuits are provided to estimate carrier offset, frequency deviation, and signal strength.These measurements can then be used to optimize receiver performance. A method for receiving and interpreting an RF signal with FSK modulation is also provided. OVERVIEW

[0003] Embodiments of the present disclosure relate to a frequency shift keying (FSK) demodulator comprising: a digital phase-locked loop (DPLL)-based frequency estimator for converting a phase signal into a frequency signal, a frequency offset estimator for estimating and tracking a direct current (DC) component of the frequency signal, and an average filter communicatively coupled to the frequency offset estimator for performing an accumulate-and-dump operation to improve a symbol-level signal-to-noise ratio (SNR) of the frequency signal.

[0004] It should be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not necessarily limiting of the present disclosure. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate the subject matter of the disclosure. The descriptions and drawings together serve to explain the basic principles of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The numerous advantages of the disclosure may be better understood by those skilled in the art by reference to the accompanying figures in which: Fig. Figure 1 is a simplified block diagram illustrating a BLE demodulator; Fig. 2 is a simplified block diagram illustrating a BLE demodulator configured in accordance with an embodiment of the present disclosure; Fig. 3 is a block diagram of a modem equipped with an FSK demodulator configured according to an embodiment of the present disclosure; and Fig. 4 is a diagram illustrating experimental data illustrating the effectiveness of an FSK demodulator configured in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0006] Reference will now be made in detail to the disclosed subject matter, which is illustrated in the accompanying drawings.

[0007] Generally referring to Fig. 1, a simplified block diagram illustrating a BLE demodulator 100 is shown. Since BLE demodulators are well understood by those skilled in the art, it is noted that detailed descriptions of each component of the BLE demodulator 100 illustrated in Fig. 1, are not repeated in the present disclosure. In general, the BLE demodulator 100 may include a Cartesian coordinate-to-phase converter 102 configured to convert oversampled IQ data into phase. A frequency estimator 104 may then convert the phase signal into a frequency signal. A frequency offset estimator 106 may be used to estimate and track a direct current (DC) component of the frequency signal due to carrier frequency offset and clock error. An average filter 108 and a downsampler 110 may then jointly perform an accumulate-and-dump operation to collect more energy from the oversampled signal and suppress the noise to improve the symbol-level signal-to-noise ratio (SNR). In some embodiments, a synchronizer 112 may be used to search the access code of the BLE packet and find the best timing for the downsampler.An equalizer 114 may be configured to remove frequency-domain intersymbol interference (ISI) for the payload. A slicer 116 may convert the equalized symbols into bits to complete the demodulation process.

[0008] It should be noted that current implementations of BLE demodulators have various problems. For example, because frequency estimators 104 are typically implemented as phase differentiators, they are sensitive to phase estimation errors. Furthermore, the accuracies of currently available implementations of frequency offset estimators 106 are limited. Furthermore, current implementations of mean filters 108 may introduce an ISI that cannot be removed from preambles and access addresses of BLE packets. The additional ISI may degrade the detection performance of the preamble and access code, negatively impacting the performance of the BLE demodulator 100.

[0009] Fig. Figure 2 is a simplified block diagram of a BLE demodulator 200 configured in accordance with some embodiments of the present disclosure. As shown in Fig. 2, the frequency estimator may be implemented as a frequency estimator based on a digital phase-locked loop (DPLL) 204. In some embodiments, the transfer function of the DPLL may be Y(z)X(z)=K(1−z−1)1−(1−K)z−1 In this way, the DPLL-based frequency estimator 204 can be configured to, by setting K = 1 (i.e., setting the transfer function to 1-z -1 ) to act as a phase differentiator. Alternatively, the DPLL-based frequency estimator 204 may be configured to provide some flexibility to the DPLL bandwidth by fine-tuning (adjusting) the value of the variable K to improve frequency estimation accuracy.

[0010] In addition, as in Fig. As shown in Figure 2, the frequency offset estimator can be implemented using an envelope tracker 206 to help track positive and negative envelopes of the frequency signal. The envelope tracker 206 can be implemented as a circuit that takes a high-frequency signal as input and provides an output that is the envelope of the original signal. The envelopes can be used to enable the estimation of the frequency offset. In some embodiments, the envelope tracker 206 can be configured to support at least one acquisition mode and one tracking mode. In some embodiments, the envelopes can be lightly filtered in acquisition mode and heavily filtered in tracking mode. In some embodiments, the frequency offset can be estimated as follows: w1=PosHull in acquisition mode−NegHull in acquisition mode2 +w2=PosHull in tracking mode−NegHull in tracking mode2 where w1 and w2 are acquisition mode and tracking mode weights, respectively, and where w1 + w2 = 1. In some embodiments, the receiver may initially set a higher weight at w1. After synchronization is complete, the receiver may reduce the weight and increase the weight at w2 (i.e., rely more on tracking mode results). It is contemplated that configuring the envelope tracker 206 in this manner may allow the filtering process to be applied more directly at the frequency extrema, thereby more efficiently suppressing noise.

[0011] Furthermore, as in Fig. 2, two separate mean filters 208A and 208B may be used to enable data demodulation and synchronization. It is contemplated that using two separate mean filters 208A and 208B may help reduce ISI. For example, in some embodiments, a first mean filter 208A may be specifically configured for data demodulation. This mean filter 208A may be implemented in a similar manner to the mean filter 108 used in conventional BLE demodulators, meaning that the accumulation length of this mean filter 208A may be configured to be equal to the symbol duration.

[0012] A second mean filter 208B may be configured to have a shorter accumulation length and thus a reduced ISI. The second mean filter 208B may be used specifically for synchronization. In some embodiments, the second mean filter 208B may operate specifically on preambles and access addresses of the received packets to complete synchronization. After synchronization is complete, the first mean filter 208A may be configured to perform data equalization and demodulation.

[0013] It is contemplated that the accumulation length of the second mean filter 208B may be selected based on various factors. For example, if the accumulation length is set to one, the second mean filter 208B may have the lowest ISI but potentially the worst SNR. Increasing the accumulation length may increase the ISI but reduce the SNR. It is therefore contemplated that the accumulation length of the second mean filter 208B may be selected as a compromise between SNR and ISI. It is understood that the accumulation length of the second mean filter 208B may vary without departing from the spirit and scope of the present disclosure.

[0014] In some embodiments, a delay matching block 208C is used to align the timing of the two mean filters. Thus, the timing acquired by the second mean filter 208B can be directly applied to the data demodulation performed by the first mean filter 208A.

[0015] As can be seen from the above, the DPLL-based frequency estimator 204 configured according to embodiments of the present disclosure can provide the flexibility to adjust the DPLL bandwidth to improve the accuracy of the frequency estimation. Furthermore, using the envelope tracker 206 as a frequency offset estimator allows filtering to be applied directly at the frequency extrema, making the frequency offset estimator more effective at suppressing noise. Furthermore, using two separate mean filters 208A and 208B for data demodulation and synchronization can help reduce ISI, which negatively impacts the performance of the BLE demodulator 200.

[0016] Although the BLE demodulator 200 is shown implementing a combination of the DPLL-based frequency estimator 204, the envelope tracker 206, and the two separate mean filters 208A and 208B, it is understood that this combination is not required. It is contemplated that a BLE demodulator configured according to the present disclosure may implement any one or any combinations of the DPLL-based frequency estimator 204, the envelope tracker 206, and the two separate mean filters 208A and 208B described above without departing from the spirit and scope of the present disclosure.

[0017] It should also be understood that although the descriptions above made specific references to BLE demodulators, such references are made for illustrative purposes only and are not intended to be limiting. It is contemplated that the DPLL-based frequency estimator 204, the envelope tracker 206, and the two separate mean filters 208A and 208B described above may be used in various types of FSK demodulators without departing from the spirit and scope of the present disclosure.

[0018] Now referring to Fig. 3, a block diagram illustrating a modem 300 equipped with an FSK demodulator configured according to an embodiment of the present disclosure is shown. In particular, the modem 300 may include an FSK modulator 302 and an FSK demodulator 304. Both the FSK modulator 302 and the FSK demodulator 304 may be implemented as a hardware component of the modem 300. In some embodiments, the modem 300 may be implemented as an application-specific integrated circuit (ASIC), a portion of which implements the various Fig. 2 that form the FSK demodulator 304. It should be noted that since FSK modulators are well understood by those skilled in the art, detailed descriptions of FSK modulators are not repeated in the present disclosure.

[0019] In Fig. 3. Also shown is a radio frequency (RF) transceiver 306 communicatively coupled to modem 300. RF transceiver 306 may include a transmitter 308 and a receiver 310. Transmitter 308 may be configured to transmit signals provided by FSK modulator 302 to external devices. Receiver 310, on the other hand, may be configured to receive signals from external devices and provide the received signals to an FSK demodulator 304 for processing. It is contemplated that FSK demodulator 304 may be configured to process the received signal as described above.

[0020] Fig.Figure 4 is a diagram illustrating experimental data illustrating the effectiveness of FSK demodulator 304. Compared to the baseline established using conventional implementations, FSK demodulators configured according to the present disclosure achieved a -1.7 dB improvement with a packet error ratio (PER) of 30% and a -3.3 dB improvement with a packet error ratio (PER) of 10% for a payload length of 37 bytes.

[0021] It is believed that the systems and devices disclosed herein, and many of their attendant advantages, will be understood from the foregoing description, and it will be appreciated that various changes in the form, construction, and arrangement of components thereof may be made without departing from the broad scope of the present disclosure or without losing all of its material advantages. The form described hereinabove represents merely an illustrative embodiment thereof; it is the intent of the following claims to encompass and embrace such changes.

[0022] The above description is illustrative and not limiting. The embodiments described above (or one or more aspects thereof) may be used in combination with one another. Other embodiments will be apparent to those skilled in the art after reviewing the above description. Throughout this document, the terms "a," "an," or "another" are used, as is common in patent documents, to include one or more than one. Throughout this document, the term "or" is used to mean non-exclusive, or such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise noted.In the event of inconsistent uses of this document and those documents incorporated by reference, the use in the incorporated references shall be considered supplementary to this document; in the event of irreconcilable inconsistencies, the use of this document shall supersede the use in the incorporated references.

[0023] Although the claimed subject matter has been described with reference to specific embodiments, it will be evident that various modifications and changes may be made to those embodiments without departing from the broader spirit and scope of what is claimed. Accordingly, the specification and drawings are to be regarded as illustrative and not restrictive. The scope of the claims should, therefore, be determined by reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. In the appended claims, the terms "comprising" and "in which" are used as simple equivalents of the terms "including" and "wherein," respectively.Furthermore, in the following claims, the terms "comprising" and "including" are open-ended; a system, device, article, or process that includes elements in addition to those listed after such a term in a claim is still intended to be within the scope of that claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc., are used only as labels and are not intended to impose numerical requirements on their objects.

Claims

[1] A frequency shift keying (FSK) demodulator (100, 200) that includes: a digital phase-locked loop (DPLL) frequency estimator (104, 204) configured to convert a phase signal into a frequency signal; a frequency offset estimator (106) communicatively coupled to the DPLL-based frequency estimator (104, 204), the frequency offset estimator configured to estimate and track a direct current (DC) component of the frequency signal; and a mean filter (108, 208A, 208B) communicatively coupled to the frequency offset estimator (106), the mean filter (208A, 208B) configured to perform an accumulate-and-dump operation to improve a symbol-level signal-to-noise ratio (SNR) of the frequency signal. [2] The FSK demodulator (200) of claim 1, wherein the frequency offset estimator (106) includes an envelope detector (206). [3] The FSK demodulator (200) of claim 2, wherein the envelope detector (206) is configured to support at least one acquisition mode and one tracking mode. [4] The FSK demodulator (200) of claim 3, wherein a first weight is assigned to the acquisition mode and a second weight is assigned to the tracking mode, wherein the first weight is initially set to be greater than the second weight, and wherein after completion of synchronization, the first weight is reduced to be lower than the second weight. [5] The FSK demodulator (200) of claim 1, wherein the mean filter includes a first mean filter (208A) and a second mean filter (208B) separate from the first mean filter (208A). [6] The FSK demodulator (200) of claim 5, wherein the first mean filter (208A) has a first accumulation length that matches a symbol duration of data being demodulated. [7] The FSK demodulator (200) of claim 6, wherein the second mean filter (208B) has a second accumulation length that is shorter than the first accumulation length of the first mean filter (208A). [8] The FSK demodulator (200) of claim 7, wherein the second mean filter (208B) is configured to operate on preambles and access addresses of received packets to complete synchronization, and wherein, after completion of synchronization, the first mean filter (208A) is configured to engage in performing data equalization and demodulation. [9] The FSK demodulator (100, 200) of claim 1, wherein the DPLL-based frequency estimator (104, 204) defines a transfer function that can be configured to act as a phase differentiator. [10] The FSK demodulator (100, 200) of claim 9, wherein the transfer function may be configured to provide flexibility to a bandwidth of a DPLL by adjusting a variable in the transfer function. [11] FSK demodulator (100, 200) according to claim 1, wherein the FSK demodulator is a Bluetooth demodulator or a Bluetooth Low Energy (BLE) demodulator. [12] A frequency shift keying (FSK) demodulator (100, 200) including: a digital phase-locked loop (DPLL) frequency estimator (104, 204) configured to convert a phase signal into a frequency signal; a frequency offset estimator (106) communicatively coupled to the DPLL-based frequency estimator (104, 204), the frequency offset estimator (106) including an envelope detector (206) and configured to estimate and track a direct current (DC) component of the frequency signal; and a mean filter (108, 208A, 208B) communicatively coupled to the frequency offset estimator (106), the mean filter (108, 208A, 208B) configured to perform an accumulate-and-dump operation to improve a symbol-level signal-to-noise ratio (SNR) of the frequency signal. [13] The FSK demodulator (200) of claim 12, wherein the envelope detector (206) is configured to support at least one acquisition mode and one tracking mode. [14] The FSK demodulator (200) of claim 13, wherein a first weight is assigned to the acquisition mode and a second weight is assigned to the tracking mode, wherein the first weight is initially set to be greater than the second weight, and wherein after completion of synchronization, the first weight is reduced to be lower than the second weight. [15] The FSK demodulator (200) of claim 12, wherein the mean filter includes a first mean filter (208A) and a second mean filter (208B) separate from the first mean filter (208A), the first mean filter (208A) having a first accumulation length that matches a symbol duration of data being demodulated, and the second mean filter (208B) having a second accumulation length that is shorter than the first accumulation length of the first mean filter (208A). [16] FSK demodulator (200) according to claim 15, wherein the second mean filter (208B) is configured to operate on preambles and access addresses of received packets to complete the synchronization, and wherein after completion of the synchronization, the first mean filter (208A) is configured to deal with performing data equalization and demodulation. [17] The FSK demodulator (100, 200) of claim 12, wherein the DPLL-based frequency estimator (104, 204) defines a transfer function that may be configured to act as a phase differentiator, and wherein the transfer function may be configured to provide flexibility to a bandwidth of a DPLL by adjusting a variable in the transfer function. [18] A frequency shift keying (FSK) modem (300) that includes: an FSK modulator (302); and an FSK demodulator (304), wherein the FSK demodulator (304) further includes: a digital phase-locked loop (DPLL) frequency estimator (104, 204) configured to convert a phase signal into a frequency signal; a frequency offset estimator (106) communicatively coupled to the DPLL-based frequency estimator (104, 204), the frequency offset estimator (106) configured to estimate and track a direct current (DC) component of the frequency signal; and a mean filter (108, 208A, 208B) communicatively coupled to the frequency offset estimator (106), the mean filter (108, 208A, 208B) configured to perform an accumulate-and-dump operation to improve a symbol-level signal-to-noise ratio (SNR) of the frequency signal. [19] The FSK modem (300) of claim 18, wherein the frequency offset estimator (106) includes an envelope detector (206), and wherein the envelope detector (206) is configured to support at least one acquisition mode and one tracking mode. [20] The FSK modem (300) of claim 18, wherein the mean filter includes a first mean filter (208A) and a second mean filter (208B) separate from the first mean filter (208A), the first mean filter (208A) having a first accumulation length that matches a symbol duration of data being demodulated, and the second mean filter (208B) having a second accumulation length that is shorter than the first accumulation length of the first mean filter (208A).

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