Inter-plate connection structure

Abstract

Inter-plate interconnection structure comprising: a plate-shaped earth conductor (11) provided in an inner layer of a first dielectric plate (100); a first signal pad (21) provided in an outer layer of the first dielectric plate (100); a first ground pad (14) provided in the outer layer of the first dielectric plate (100) and in a region surrounding the first signal pad (21); a columnar conductor (13) electrically connecting the plate-shaped earth conductor (11) and the first ground pad (14); a first signal conductor (22) provided in the outer or inner layer of the first dielectric plate (100); a second signal conductor (24) extending from the first signal conductor (22) to the first signal pad (21) and including a first capacitive component (25, 25A) between the second signal conductor and the first signal pad (21) forms;a third signal conductor (23) branching off from and extending from a connecting section between the first signal conductor (22) and the second signal conductor (24), and electrically connected to the first signal pad (21); a second signal pad (71) provided in an outer layer of a second dielectric plate (600); a second ground pad (61) provided in the outer layer of the second dielectric plate (600) and in an area surrounding the second signal pad (71); a signal bump (51) electrically connecting the first signal pad (21) and the second signal pad (71); and a ground bump (41) electrically connecting the first ground pad (14) and the second ground pad (61).

Description

AREA OF TECHNOLOGY The present disclosure relates to an interplate interconnection structure that electrically connects electrode pads between plates using solder bumps. TECHNICAL BACKGROUND In BGA-type modules, an inter-plate interconnect structure is used, electrically connecting electrode pads between plates using solder bumps. In a conventional interplate interconnect structure, to reduce the parasitic capacitance component formed between a pad on a dielectric plate and a ground wire located in an inner layer of the dielectric plate, thus improving high-frequency characteristics, a portion of the ground wire directly beneath the pad is removed to create a punched hole. However, because the punched hole for the ground wire causes coupling with a wire located in the inner layer of the dielectric plate, there are instances where such a punched hole cannot be used for an interplate interconnect structure. For example, patent document 1 describes a structure for improving high-frequency properties without creating punched holes in a ground conductor. In a structure described in patent document 1, the length of a coated stub line and the shape of an external electrode pad are configured to connect a substrate and a semiconductor element such that the coated stub line and the external electrode pad exhibit a capacitance within a desired frequency range in the substrate. Furthermore, by limiting a conductor wire running from the external electrode pad to a part connected to an electrode pad of the semiconductor element to an area within the range of the electrical influence of the coated stub wire or the external electrode pad, a conductor with uniform impedance is implemented. Patent document 2 describes an electrical component that incorporates integrated passive elements with low ohmic losses. For this purpose, a reactance element, comprising an inductor, a capacitor, or a transmission line, is arranged between a substrate and a chip mounted on the substrate. Patent document 3 describes a structure and a method for connecting a semiconductor chip and a substrate with improved high-frequency properties. Here, the ground conductor on the substrate is designed to surround the signal pad, thus confining the electromagnetic field to this region. Patent document 4 also describes structures that enable a connection between a chip and a substrate, through which a 60 GHz longitudinal radiator antenna can be integrated into a chip package. Patent document 5 also deals with antennas, which here are formed in the form of spur lines in a substrate. Patent document 6 describes a connection structure that enables low-loss signal transmission by connecting a signal pad for connection to a semiconductor element and a signal pad for connection to a substrate through a conductor pattern that runs parallel to the surface of the connection structure. Patent literature 7 describes a printed circuit board design that allows the input capacitance of a semiconductor element to be adjusted by deforming the ground conductor. LIST OF COUNTERPOINTMENTS PATENT DOCUMENTS Patent document 1: JP 2001-168236 APatent document 2: DE 10 2007 020 288 A1Patent document 3: US 2013 / 0 256 849 A1Patent document 4: US 2015 / 0 097 633 A1Patent document 5: US 2005 / 0 122 265 A1Patent document 6: JP 2014-93332 APatent document 7: JP 2001-217349 A SUMMARY OF THE INVENTION TECHNICAL PROBLEM However, in the conventional intermediate plate connection structure, which is exemplified in patent document 1, the size of a signal conductor must be increased relative to the ground conductor if a ground capacitance component, necessary for impedance matching, is to be provided. Therefore, the problem arises that the size of the impedance matching circuit increases. The present disclosure is intended to solve the above-mentioned problem, and therefore one objective of the present disclosure is to create an inter-plate interconnect structure that can reduce the size of an impedance matching circuit. SOLUTION TO THE PROBLEM An interplate interconnection structure according to the present disclosure comprises: a plate-shaped ground conductor provided in an inner layer of a first dielectric plate; a first signal pad provided in an outer layer of the first dielectric plate; a first ground pad provided in the outer layer of the first dielectric plate and in a region surrounding the first signal pad; a columnar conductor electrically connecting the plate-shaped ground conductor and the first ground pad; a first signal conductor provided in the outer or inner layer of the first dielectric plate; a second signal conductor extending in one direction from the first signal conductor to the first signal pad and forming a capacitive component between the second signal conductor and the first signal pad;a third signal conductor branching off from and running from a connecting section between the first and second signal conductors, and electrically connected to the first signal pad; a second signal pad provided in an outer layer of a second dielectric plate; a second ground pad provided in the outer layer of the second dielectric plate and in an area surrounding the second signal pad; a signal hump electrically connecting the first and second signal pads; and a ground hump electrically connecting the first and second ground pads; ADVANTAGEOUS EFFECTS OF THE INVENTION According to the present disclosure, no punched hole is provided in the plate-shaped ground conductor located in the inner layer of the first dielectric plate, and the third signal conductor is designed to be small in order to reduce the size of the impedance matching circuit. However, the capacitance necessary for impedance matching can still be ensured by the capacitive component formed between the first signal pad and the second signal conductor. Consequently, the impedance matching circuit can be miniaturized. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a cross-sectional view showing the configuration of a module having an inter-plate interconnect structure according to a first embodiment of the present disclosure; Fig. 1B is a cross-sectional view showing the module in the plane of line AA' of Fig. 1A, wherein the module has the inter-plate interconnect structure according to the first embodiment; Fig. 1C is a cross-sectional view showing the module in the plane of line BB' of Fig. 1A, wherein the module has the inter-plate interconnect structure according to the first embodiment; Fig. 2A is a sketch showing a conductor pattern in an outer layer of a printed circuit that does not have a section forming an intermediate signal capacitor; Fig. 2B is a sketch showing a conductor pattern in an outer layer of a printed circuit that has a section forming an intermediate signal capacitor; Fig.Figure 2C is a graph showing the results of a simulation of the reflection properties of an electromagnetic field in both an inter-plate interconnect structure comprising the printed circuit of Figure 2A and an inter-plate interconnect structure comprising the printed circuit of Figure 2B; Figure 3A is a cross-sectional view showing the configuration of a module comprising an inter-plate interconnect structure according to a second embodiment of the present disclosure; Figure 3B is a cross-sectional view showing the module in the plane of line AA' of Figure 3A, wherein the module comprises the inter-plate interconnect structure according to the second embodiment; Figure 3C is a cross-sectional view showing the module in the plane of line BB' of Figure 3A, wherein the module comprises the inter-plate interconnect structure according to the second embodiment; FigureFigure 4A is a cross-sectional view showing the configuration of a module having an intermediate plate connection structure according to a third embodiment of the present disclosure; Figure 4B is a cross-sectional view showing the module in the plane of line AA' of Figure 4A, wherein the module has the intermediate plate connection structure according to the third embodiment; Figure 4C is a cross-sectional view showing the module in the plane of line BB' of Figure 4A, wherein the module has the intermediate plate connection structure according to the third embodiment; Figure 5A is a cross-sectional view showing the configuration of a module having an intermediate plate connection structure according to a fourth embodiment of the present disclosure; Figure 5B is a cross-sectional view showing the module in the plane of line AA' of Figure 5A, wherein the module has the intermediate plate connection structure according to the fourth embodiment; and FigureFigure 5C is a cross-sectional view showing the module in the plane of line BB' of Fig. 5A, wherein the module has the intermediate plate connection structure according to the 4th embodiment. DESCRIPTION OF EXECUTION FORMS In order to explain the present disclosure in more detail, preferred embodiments of the present disclosure will now be described with reference to the accompanying drawings. 1. Design Fig. 1A is a cross-sectional view showing the configuration of a module 1 provided with an intermediate plate connection structure according to the first embodiment of the present disclosure, and showing a view of the module 1 along line CC' of Fig. 1B. Fig. 1B is a cross-sectional view of the module 1 in the plane of line AA' of Fig. 1A. Line AA' divides each of the following components—ground pads 14, a signal pad 21, a signal conductor 22, a signal conductor 23, and a signal conductor 24—in two parts in a thickness direction. Fig. 1C is a cross-sectional view of the module 1 in the plane of line BB' of Fig. 1A. Line BB' divides a plate-shaped ground conductor 11 in two parts in the thickness direction. Module 1 comprises a printed circuit 100 and a semiconductor board 600, and electrode pads between the printed circuit 100 and the semiconductor board 600 are connected to each other by the interplate interconnect structure according to the 1st embodiment. The printed circuit 100 is a first dielectric plate in which at least one plate-shaped ground conductor 11 is provided in an inner layer. Each plate-shaped ground conductor 11 is a rigid ground provided everywhere in a corresponding plane in the inner layer of the printed circuit 100, as shown in Fig. 1C. For example, in Fig. 1A, two plate-shaped earth conductor layers 11 are provided in the inner layer of the printed circuit board 100. The two plate-shaped earth conductor layers 11 are electrically connected via several earth passage holes 12, which are column conductors, and are kept at the same electrical potential. By providing the multiple plate-shaped earth conductors 11, the ground pads 14 can be grounded more reliably. On a front face of the printed circuit board 100 are provided the ground pads 14, the signal pad 21, the signal conductor 22, the signal conductor 23, and the signal conductor 24. The ground pads 14 are first ground pads provided in an outer layer of the printed circuit board 100 and in an area surrounding the signal pad 21, as shown in Fig. 1B. As shown in Fig. 1A, the ground pads 14 are electrically connected to the plate-shaped ground conductors 11 via ground holes 13, which are column conductors, so that the ground pads have an electrical ground potential. The signal pad 21 is a first signal pad provided in the outer layer of the printed circuit board 100. The signal conductor 22 is a first signal conductor provided in the outer layer of the printed circuit 100, and one end of the signal conductor 22 is connected to both the signal conductor 23 and the signal conductor 24. Although Fig. 1A and Fig. 1B show that the signal conductor 22 is arranged in the outer layer of the printed circuit 100, the signal conductor 22 can also be arranged in the inner layer of the printed circuit 100. The signal conductor 23 is a third signal conductor that branches off and runs from a connecting section between the signal conductor 22 and the signal conductor 24 and is electrically connected to the signal pad 21, as shown in Fig. 1B. To provide a capacitance that is used to match the impedance and to reduce the size of an impedance matching circuit, for example, the signal line conductor 23 is formed from a wire having a wire width that is smaller than that of the signal line conductor 22 and the signal line conductor 24, the wire being bent so that it travels a long distance until it reaches the signal pad 21. By designing the signal conductor 23 in such a way that the signal conductor has a smaller size, an earth capacitance component in the signal conductor 23 is reduced. The signal conductor 24 is a second signal conductor extending in one direction from the signal conductor 22 to the signal pad 21. Its leading end is open, and it forms a capacitive component between the signal conductor 24 and the signal pad 21. This causes the leading end of the signal conductor 24 to extend close to the signal pad 21, so that the signal pad 21 and the signal conductor 24 are opposite each other, thus forming a capacitive component corresponding to the distance G between the signal pad 21 and the signal conductor 24. This section is referred to as an intermediate signal capacitance-forming section 25. Furthermore, the signal conductor 24 can be designed to extend further along the outer edge of the signal pad 21, as shown in Fig. 1B. In this configuration, the section where the signal pad 21 and the signal conductor 24 are close to each other, i.e., the intermediate signal capacitance-forming section 25, is long, and therefore the capacitive component formed in the intermediate signal capacitance-forming section 25 becomes larger. In a case where the distance G is made shorter than the distance H between the plate-shaped earth conductor 11 and the signal conductor 24 in Fig. 1A, the capacitive component formed in the section 25 forming the intermediate signal capacitance becomes larger. In the intermediate plate connection structure according to the 1st embodiment, the signal conductor 23 is made smaller, so that its ground capacitance component is reduced, but nevertheless the capacitance necessary for impedance matching is ensured both by the capacitive component formed in the intermediate signal capacitance section 25 and by the ground capacitance component in the signal conductor 24. The semiconductor plate 600 is a second dielectric plate in which the ground pads 61 and a signal pad 71 are provided on a back side. A wiring layer 601 is provided in an inner layer of the semiconductor plate 600, and at least one ground conductor 62 and one signal conductor 72 are provided in the wiring layer 601. The ground pads 61 are secondary ground pads provided in an outer layer of the semiconductor plate 600 and are electrically connected to the earth conductor 62 provided in the inner layer of the semiconductor plate 600. The signal pad 71 is a second signal pad provided in the outer layer of the semiconductor plate 600 and is electrically connected to the signal conductor 72 provided in the inner layer of the semiconductor plate 600. After the printed circuit 100 and the semiconductor board 600 have been arranged such that the front of the printed circuit 100 and the back of the semiconductor board 600 are opposite each other, the ground pads 14 and the ground pads 61 are electrically connected by ground bumps 41, and the signal pad 21 and the signal pad 71 are electrically connected by a signal bump 51. The ground bosses 41 and the signal bosses 51 are solder bosses, and the electrode pads are electrically connected, for example, by melting and solidifying solder. As shown in Fig. 1C, the intermediate plate connection structure according to the first embodiment does not include any punched holes in the plate-shaped earth conductors 11. Therefore, the upper circuit and the lower circuit, which are adjacent to each other in the plane of line B-B' shown in Fig. 1A, are separated from each other, but this does not change the functions of the upper circuit. The influence of the presence or absence of the intermediate signal capacitance section 25 on the size of the impedance matching circuit will now be explained. Fig. 2A shows a conductor pattern in an outer layer of a printed circuit 1000 that does not have the intermediate signal capacitance section 25. Fig. 2B shows the conductor pattern in the outer layer of the printed circuit 100 that does have the intermediate signal capacitance section 25. Fig. 2C is a graph showing the results of a simulation of the reflection properties of an electromagnetic field in both an intermediate-plate interconnect structure, which includes the printed circuit 1000 of Fig. 2A, and an intermediate-plate interconnect structure, which includes the printed circuit 100 of Fig. 2B.For the simulation of the electric field, a tool for analyzing an electric field in three dimensions is used. A signal conductor 240 in the printed circuit 1000 originates from a signal conductor 22 and is provided in place of the signal conductor 24 in the printed circuit 100. The signal conductor 240 runs away from a signal pad 21 in one direction, unlike the signal conductor 24, and thus no section 25 forming an intermediate signal capacitance is formed in the printed circuit 1000. In Fig. 2C, the simulation is performed with the relative permittivity of each of the printed circuits 100 and 1000 set to 3.3, the relative permittivity of the wiring layer 601 set to 3.5, and the nominal impedance set to 50 Ω. Furthermore, both the inter-plate interconnect structure of printed circuit 1000 and the inter-plate interconnect structure of printed circuit 100 are designed to have a point of coincidence at the same frequency (approximately 42 GHz). Consequently, the reflection characteristic curve a of the inter-plate interconnect structure of printed circuit 1000 and the reflection characteristic curve b of the inter-plate interconnect structure of printed circuit 100 are nearly identical, and both reflection characteristic curves behave similarly. In a case where the interplate connection structure lacking the section 25 forming an intersignal capacitance and the interplate connection structure having the section 25 forming an intersignal capacitance are designed such that their reflection properties are identical, a significant difference arises between the lengths L of the signal conductors 23 and 23A in a right-hand or left-hand direction, see Fig. 2A and Fig. 2B. While the length of the signal conductor 23A of the intermediate plate connection structure, which does not have the section 25 forming an intermediate signal capacitance, is L=0.40 mm, as shown in Fig. 2A, the length of the signal conductor 23 of the intermediate plate connection structure, which has the section 25 forming an intermediate signal capacitance, is L=0.37 mm, as shown in Fig. 2B. More precisely, section 25, which forms an intermediate signal capacitance, is effective in reducing the size of the impedance matching circuit. Although Fig. 1A shows the interplate interconnect structure between the printed circuit board 100 and the semiconductor board 600, a different type of board can be used as long as it is possible to electrically connect the electrode pads between the boards using solder bosses. For example, a printed circuit board, a ceramic board, or the like can be used instead of the semiconductor board 600. Although Fig. 1B shows the case where each of the multiple ground pads 14 is independently provided in the outer layer of the printed circuit 100, the multiple ground pads 14 in the outer layer of the printed circuit 100 can be electrically connected to each other. In this case, the ground pads are formed in an opening in a solder mask. As stated above, in the intermediate plate connection structure according to the first embodiment, no punch holes are provided in the plate-shaped ground conductors 11 located in the inner layer of the printed circuit 100, and the signal conductor 23 is designed to be smaller in order to reduce the size of the impedance matching circuit. However, the capacitance necessary for impedance matching can still be ensured by the capacitive component formed in the section 25, which forms an intermediate signal capacitance, and the ground capacitance component in the signal conductor 24. Consequently, the impedance matching circuit can be reduced in size. Furthermore, by configuring the signal conductor 24 with a wire running along the outer edge of the signal pad 21, the section 25 forming an intermediate signal capacitance is extended, thus making it easy to provide a capacitance value. 2. Design Fig. 3A is a cross-sectional view showing the configuration of a module 1A having an intermediate plate connection structure according to the second embodiment of the present disclosure, and shows the module 1A along line CC' of Fig. 3B. Fig. 3B is a cross-sectional view of the module 1A in the plane of line AA' of Fig. 3A. Line AA' divides each of the following components—ground pads 14, a signal pad 21, a signal conductor 22, a signal conductor 23, and a signal conductor 24A—into two parts in the thickness direction. Fig. 3C is a cross-sectional view of the module 1A in the plane of line BB' of Fig. 3A. Line BB' divides a plate-shaped ground conductor 11 into two parts in the thickness direction. In Fig. 3A, Fig. 3B and Fig. 3C, components that are identical to those shown in Fig. 1A, Fig. 1B and Fig. 1C are provided with the same reference numerals, and no further explanation of the components is required. Module 1A comprises a printed circuit 100A and a semiconductor board 600, and electrode pads between the printed circuit 100A and the semiconductor board 600 are connected to each other by the inter-board interconnect structure according to the second embodiment. The printed circuit 100A is a first dielectric plate in which at least one plate-shaped ground conductor 11 is provided in an inner layer. Each plate-shaped ground conductor 11 is a solid ground provided everywhere in a corresponding plane of the inner layer of the printed circuit 100A, as shown in Fig. 3C, and no punched hole is provided in any of the plate-shaped ground conductors. For example, in Fig. 3A, two plate-shaped earth conductor layers 11 are provided in the inner layer of the printed circuit board 100A. The two plate-shaped earth conductor layers 11 are electrically connected via several earth passage holes 12, which are column conductors, and are kept at the same electrical potential. By providing the multiple plate-shaped earth conductors 11, the ground pads 14 can be grounded more reliably. On one front side of the printed circuit board 100A are provided the ground pads 14, the signal pad 21, the signal conductor 22, the signal conductor 23 and the signal conductor 24A. The signal conductor 24A is a second signal conductor comprising a portion extending from the signal conductor 22 shown in Fig. 3B, a signal conductor 27 shown in Fig. 3A, which is provided in the inner layer of the printed circuit 100A, and a signal through-hole 26 shown in Fig. 3A. For example, in the signal conductor 24A, the portion extending from the signal conductor 22 to the signal pad 21 is electrically connected to the signal conductor 27 via the signal through-hole 26. The signal conductor 27 extends to a region encompassing a point immediately below the signal pad 21, such that it is opposite the signal pad 21 with respect to a thickness direction of the printed circuit 100A, and that a capacitive component is formed between the signal pad 21 and the signal conductor 27. This section is referred to as an intermediate signal capacitance-forming section 25A. A front end of the signal conductor 27 can have a shape such as a circle or a rectangle. In the intermediate plate connection structure according to the 2nd embodiment, the signal line conductor 23 is designed to be small in size in order to reduce the size of an impedance matching circuit, but nevertheless a capacitance necessary for impedance matching is ensured by the capacitive component formed in the section 25A forming an intermediate signal capacitance. In the intermediate plate connection structure according to the 2nd embodiment, a pad surface of the signal pad 21 and a wiring surface of the signal conductor 27 (a surface in a width direction of the signal conductor 27) are opposite each other, and therefore a higher capacitance value can be provided than in a configuration in which the signal pad 21 and the signal conductor 24 are brought close to each other, as in the 1st embodiment. As a result, a capacity necessary for impedance matching can be ensured even though the size of the signal conductor 23 is reduced compared to the configuration shown in the 1st embodiment. Even though the spacing of a conductor pattern in a typical printed circuit is on the order of 100 µm to 200 µm, in the inter-plate interconnect structure according to the 1st embodiment it is the spacing G that makes it possible to provide a capacitance on the order of a few tens of µm, which is necessary for impedance matching. In contrast, in the interplate interconnect structure according to the second embodiment, a suitable capacitance value is provided depending on the size and position of the signal conductor 27 in the inner layer. For this reason, microfabrication of a conductor pattern on the order of a few tens of micrometers is not necessary. As stated above, in the interlayer connection structure according to the second embodiment, the signal conductor 27 is provided in the inner layer of the printed circuit 100A and is located opposite the signal pad 21 with respect to the thickness direction of the printed circuit 100A. Providing this configuration eliminates the need for fine wiring on the outer layer of the printed circuit 100A, which is an additional advantage to that shown in the first embodiment. Consequently, a standardized printed circuit can be used, the degree of flexibility in the choice of board can be increased, and a reduction in board costs can also be achieved. 3. Design Fig. 4A is a cross-sectional view showing the configuration of a module 1B having an intermediate plate connection structure according to the third embodiment of the present disclosure, and shows the module 1B along line CC' of Fig. 4B. Fig. 4B is a cross-sectional view of the module 1B in the plane of line AA' of Fig. 4A. Line AA' divides each of the following components—ground pads 14, a signal pad 21, a signal conductor 22, a signal conductor 23, and a signal conductor 24B—into two parts in the thickness direction. Fig. 4C is a cross-sectional view of the module 1B in the plane of line BB' of Fig. 4A. Line BB' divides a plate-shaped ground conductor 11 into two parts in the thickness direction. Module 1B comprises a printed circuit 100B and a semiconductor board 600, and electrode pads between the printed circuit 100B and the semiconductor board 600 are connected to each other by the inter-board interconnect structure according to the 3rd embodiment. The printed circuit 100B is a first dielectric plate in which at least one plate-shaped ground conductor 11 is provided in an inner layer. Each plate-shaped ground conductor 11 is a solid ground provided everywhere in a corresponding plane of the inner layer of the printed circuit 100B, as shown in Fig. 4C, and none of the plate-shaped ground conductors has a punched hole. For example, in Fig. 4A, two plate-shaped earth conductor layers 11 are provided in the inner layer of the printed circuit board 100B. The two plate-shaped earth conductor layers 11 are electrically connected via several earth passage holes 12, which are column conductors, and are kept at the same electrical potential. By providing the multiple plate-shaped earth conductors 11, the ground pads 14 can be grounded more reliably. On one front side of the printed circuit board 100B are provided the ground pads 14, the signal pad 21, the signal conductor 22, the signal conductor 23 and the signal conductor 24B. The signal conductor 24B is a second signal conductor that runs from the signal conductor 22 along the outer edge of the signal pad 21 and further along the outer edge of a ground pad 14, as shown in Fig. 4B. In the intermediate plate connection structure according to the 3rd embodiment, a capacitive component is formed between the signal pad 21 and the signal conductor 24B, as in the case of the 1st embodiment, and furthermore, a capacitive component is formed between the ground pad 14 and the signal conductor 24B. The section between the ground pad 14 and the signal conductor 24B is referred to as a section 28 forming a signal-to-ground capacitance. Since the signal conductor 24B runs along the outer edge of the signal pad 21 and then continues along the outer edge of the ground pad 14, the wire length of the signal conductor 24B is greater than that of the signal conductor 24 shown in the first embodiment. Consequently, the ground capacitance component formed between the signal conductor 24B and the plate-shaped ground conductor 11 is also larger. In the intermediate plate connection structure according to the 3rd embodiment, a capacitance necessary for impedance matching is ensured by the capacitive component formed in section 25 forming an intermediate signal capacitance, by the capacitive component formed in section 28 forming a signal-to-ground capacitance, and by the ground capacitance component in the signal line conductor 24B. As a result, the intermediate plate connection structure according to the 3rd embodiment can provide a capacitance value that is higher than that of the configuration in which the signal pad 21 and the signal conductor 24 are brought close together, as in the 1st embodiment, and thus provide a capacitance necessary for impedance matching, even though the signal conductor 23 is designed to be smaller than in the configuration shown in the 1st embodiment. The signal conductor 24B does not increase the area of ​​an impedance matching circuit, since the wire length of the signal conductor 24B is extended without changing the arrangement of the ground pads 14 and the signal pad 21, as shown in Fig. 4B. As indicated above, in the intermediate plate connection structure according to the 3rd embodiment, the signal conductor 24B runs along the outer edge of the signal pad 21 and forms a capacitive component between the signal conductor 24B and the signal pad 21, and further runs along the outer edge of a ground pad 14 and forms a capacitive component between the signal conductor 24B and the ground pad 14. Such a design allows the earth capacitance component required for impedance matching to be increased without increasing the area of ​​the impedance matching circuit. 4. Design Fig. 5A is a cross-sectional view showing the configuration of a module 1C having an intermediate plate connection structure according to the 4th embodiment of the present disclosure, and shows the module 1C along line CC' of Fig. 5B. Fig. 5B is a cross-sectional view of the module 1C in the plane of line AA' of Fig. 5A. Line AA' divides each of the following components—ground pads 14, a signal pad 21, a signal conductor 22, a signal conductor 23, and a signal conductor 24C—into two parts in the thickness direction. Fig. 5C is a cross-sectional view of the module 1C in the plane of line BB' of Fig. 5A. Line BB' divides a plate-shaped ground conductor 11 into two parts in the thickness direction. Module 1C comprises a printed circuit 100C and a semiconductor board 600, and electrode pads between the printed circuit 100C and the semiconductor board 600 are connected to each other by the interplate interconnect structure according to the 4th embodiment. The printed circuit 100C is a first dielectric plate in which at least one plate-shaped ground conductor 11 is provided in an inner layer. Each plate-shaped ground conductor 11 is a rigid ground provided everywhere in a corresponding plane of the inner layer of the printed circuit 100C, as shown in Fig. 5C, and none of the plate-shaped ground conductors has a punched hole. For example, in Fig. 5A, two plate-shaped earth conductor layers 11 are provided in the inner layer of the printed circuit board 100C. The two plate-shaped earth conductor layers 11 are electrically connected via several earth passage holes 12, which are column conductors, and are kept at the same electrical potential. By providing the multiple plate-shaped earth conductors 11, the ground pads 14 can be grounded more reliably. On one front side of the printed circuit board 100C are provided the ground pads 14, the signal pad 21, the signal conductor 22, the signal conductor 23 and the signal conductor 24C. The signal conductor 24C is a second signal conductor that runs between the signal pad 21 and an adjacent ground pad 14 along the outer edge of the ground pad 21 and around it, as shown in Fig. 5B. Since the signal conductor 24C runs along the outer edge of the signal pad 21 and around it, the section where the signal pad 21 and the signal conductor 24C are close to each other, i.e., a section 25 forming an intermediate signal capacitance, is long. Consequently, the capacitive component formed in the section 25 forming an intermediate signal capacitance is increased compared to the configuration shown in Fig. 1B. Furthermore, the wire length of the signal conductor 24C is greater than that of the signal conductor 24 shown in the first embodiment by the length of the portion that runs around the outer edge of the signal pad 21. Consequently, the ground capacitance component formed between the signal conductor 24C and the plate-shaped ground conductor 11 is also larger. Even if the signal conductor 23 in the intermediate plate connection structure according to the 4th embodiment is designed to be small, the capacitance necessary for impedance matching is thus ensured both by the capacitive component formed in the intermediate signal capacitance section 25 and by the earth capacitance component in the signal conductor 24C. As a result, the intermediate plate connection structure according to the 4th embodiment can provide a capacitance value that is higher than that of the configuration in which the signal pad 21 and the signal conductor 24 are brought close together, as in the 1st embodiment, and thus provide a capacitance necessary for impedance matching, even though the signal conductor 23 is designed to be smaller than in the configuration shown in the 1st embodiment. Although Fig. 5B shows that the signal conductor 24C is designed to run around approximately half of the outer edge of the signal pad 21, the signal conductor 24C can be designed to run over more than half of the outer edge of the signal pad. Since the wire length of the signal conductor 24C is increased without changing the arrangement of the ground pads 14 and the signal pad 21, as shown in Fig. 5B, there is also no increase in the area of ​​an impedance matching circuit. As described above, in the interplate connection structure according to the 4th embodiment, the signal conductor 24C runs between the signal pad 21 and an adjacent ground pad 14 along the outer edge of the signal pad 21 and around it. This design allows the ground capacitance component required for impedance matching to be increased without increasing the area of ​​the impedance matching circuit. It should be clarified that within the scope of the present disclosure any combination of two or more of the above-mentioned embodiments may be made, that various modifications may be made to any component in any of the above-mentioned embodiments, or that any component may be omitted in any of the above-mentioned embodiments. INDUSTRIAL APPLICABILITY Since the interplate interconnect structure according to the present disclosure can reduce the size of an impedance matching circuit, the interplate interconnect structure is suitable for various types of high-frequency transmission circuits. LIST OF REFERENCE MARKS 1, 1A to 1C module, 11 plate-shaped ground conductor, 12, 13 ground through hole, 14, 61 ground pad, 21, 71 signal pad, 22 to 24, 24A to 24C, 27, 72, 240 signal conductor, 25, 25A intermediate signal capacitance forming section, 26 signal through hole, 28 signal-to-ground capacitance forming section, 41 ground bump, 51 signal bump, 62 ground conductor, 100, 100A to 100C, 1000 printed circuit, 600 semiconductor board; and 601 wiring layer.

Claims

Inter-plate interconnection structure comprising: a plate-shaped earth conductor (11) provided in an inner layer of a first dielectric plate (100); a first signal pad (21) provided in an outer layer of the first dielectric plate (100); a first ground pad (14) provided in the outer layer of the first dielectric plate (100) and in a region surrounding the first signal pad (21); a columnar conductor (13) electrically connecting the plate-shaped earth conductor (11) and the first ground pad (14); a first signal conductor (22) provided in the outer or inner layer of the first dielectric plate (100); a second signal conductor (24) extending from the first signal conductor (22) to the first signal pad (21) and including a first capacitive component (25, 25A) between the second signal conductor and the first signal pad (21) forms;a third signal conductor (23) branching off from and extending from a connecting section between the first signal conductor (22) and the second signal conductor (24), and electrically connected to the first signal pad (21); a second signal pad (71) provided in an outer layer of a second dielectric plate (600); a second ground pad (61) provided in the outer layer of the second dielectric plate (600) and in an area surrounding the second signal pad (71); a signal bump (51) electrically connecting the first signal pad (21) and the second signal pad (71); and a ground bump (41) electrically connecting the first ground pad (14) and the second ground pad (61). Intermediate plate connection structure according to claim 1, wherein the second signal conductor (24) extends along an outer edge of the first signal pad (21) and a side surface in a thickness direction of the second signal conductor (24) is opposite a side surface in a thickness direction of the first signal pad (21) between the second signal conductor (24) and the first signal pad (21). Inter-plate interconnect structure according to claim 1, wherein the second signal conductor (27) is provided in the inner layer of the first dielectric plate (100A) and is opposite the first signal pad (21) with respect to a thickness direction of the first dielectric plate (100A). Intermediate plate connection structure according to claim 2, wherein the second signal conductor (24B) further extends along an outer edge of the first ground pad (14) and forms a second capacitive component (28) between the second signal conductor (24B) and the first ground pad (14). Intermediate plate connection structure according to claim 2, wherein the second signal conductor (24C) runs between the first signal pad (21) and the first ground pad (14), adjacent to the first signal pad (21), along the outer edge of the first signal pad (21) and around it.

Images