SEMICONDUCTOR COMPONENT

Abstract

Semiconductor device (100) comprising the following: an insulating substrate (41) with a main surface; a semiconductor element (2) arranged on the main surface of the insulating substrate (41); a housing part (5) that surrounds the semiconductor element (2) and is attached to the insulating substrate (41); and a sealing material (1) arranged in an inner area surrounded by the housing part (5) and the insulating substrate (41) and surrounding the semiconductor element (2); and an electrode terminal (7) which is connected to the semiconductor element (2) and which is formed together with the housing part (5), wherein the housing part (5) has a recess (51) which is formed continuously with a connection area of ​​the housing part (5) connected to the insulating substrate (41) and faces the interior area, wherein the recess (51) has a counter surface (61) which faces the main surface of the insulating substrate (41), wherein the counter surface (61) extends from an end on the outer circumferential side to an end on the inner circumferential side of the housing part (5), wherein the electrode connection (7) has a first region extending in a direction along the main surface of the insulating substrate (41) and a second region extending in a vertical direction intersecting the first region, wherein a distance (H1) from the main surface of the insulating substrate (41) to the end on the inner circumferential side of the counter surface (61) is greater than a distance (H2) from the main surface to an upper surface (2a) of the semiconductor element (2), and wherein the opposite surface (61) is arranged between the first area and the main surface, and wherein the opposite surface (61) is parallel to the main surface of the insulating substrate (41), or the opposite surface (61) is inclined relative to the main surface of the insulating substrate (41), so that the distance of the counter surface (61) from the main surface of the insulating substrate (41) gradually increases from the end on the outer circumferential side to the end on the inner circumferential side.

Description

TECHNICAL AREA

[0001] The present invention relates to a semiconductor device in which a semiconductor element arranged on an insulating substrate is sealed with a sealing resin. STATE OF THE ART

[0002] Semiconductor devices such as inverters, which are installed in industrial equipment and cars, require higher density and smaller size. This need has led to an increased packing density of semiconductor elements within these devices. In a semiconductor device with a high packing density, the exposed area of ​​the insulating substrate on which the semiconductor elements are mounted is relatively small. Consequently, the contact area between a sealing material protecting the semiconductor elements and the insulating substrate is rather small. This small contact area can lead to peeling between the sealing material and the insulating substrate, as stresses arise during storage at high temperatures or during thermal cycling within the semiconductor device.There is a risk that such peeling between the sealing material and the insulating substrate will reduce the insulation of the semiconductor device and thus impair the reliability of the semiconductor device.

[0003] To suppress peeling between a sealing material and an insulating substrate or the like, thereby ensuring the reliability of a semiconductor device, patent document 1 describes the formation of two or more rows of grooves around the ceramic substrate on the surface of a copper base to which a ceramic substrate is bonded as an insulating substrate. In patent document 1, epoxy resin is transfer-molded as the sealing material to fill the grooves with a portion of the epoxy resin, thereby improving the adhesion between the sealing material and the copper base.

[0004] Patent document 2 describes a semiconductor device in which a semiconductor element is arranged in a cavity of a ceramic housing and the inside of the cavity is sealed with a sealing material, the cavity having a recess on a lower part of its side wall. In the semiconductor device of patent document 2, the recess in the lower part of the side wall is provided with a mating surface facing a bottom surface. The mating surface of the recess is located between a height position of the upper surface and a position of the lower surface height of the semiconductor element. In the semiconductor device of patent document 2, an upward stress from the bottom of the cavity and a downward stress from an upper part of the side wall on the semiconductor element, which are generated by the application of heat, cancel each other out.According to patent document 2, this reduces the connection stress directed upwards from the underside of the cavity and suppresses the deformation of the semiconductor element caused by the connection stress.

[0005] Patent document 3 discloses a semiconductor device constructed in an insulating housing frame. It describes a terminal block with numerous guide pins inserted and fixed in the frame, a heat-dissipating base plate with an attached circuit board, and a potting compound secured against leakage by a sealing element and a vent.

[0006] Patent document 4 describes a semiconductor chip that is arranged on a base plate and enclosed by a housing, with connecting pins attached to the chip and everything encapsulated by a potting resin.

[0007] Patent document 5 shows a semiconductor device with an insulating substrate housed in a housing opening section of a resin package. STATE OF THE ART Patent document 1: Japanese patent application disclosure JP 2007 - 184 315 A Patent document 2: Japanese patent application disclosure JP 2009 - 16 884 A Patent document 3: Japanese patent application disclosure JP H08 - 162 571 A Patent document 4: Japanese patent application disclosure JP 2015 - 162 649 A Patent document 5: German patent application publication DE 10 2016 208 034 A1 BRIEF DESCRIPTION OF THE INVENTION Problems to be solved with the invention

[0008] Although the method described in patent document 1 can create an anchoring effect of the sealing material against the copper base due to the grooves provided in the copper base, peeling between the ceramic substrate and the sealing material cannot be directly suppressed. Furthermore, it is necessary to secure an area for the formation of the grooves on the surface of the copper base that prevents the semiconductor device from shrinking. Since the semiconductor device described in patent document 1 is a transfer-type semiconductor device, the grooves in the copper base surface can be provided at one end region of the semiconductor device. However, in the case of a package module, the package part is connected to the outer circumference of the insulating substrate, so that, due to space constraints and the like, it can be difficult to form grooves in the surface of the insulating substrate.

[0009] In the semiconductor device described in patent document 2, the counter surface of the recess must be positioned between the height of the upper surface and the height of the lower surface of the semiconductor device to suppress deformation. However, when mounting a semiconductor device reduced in size and thickness onto a printed circuit board on an insulating substrate with an adhesive, the height from the insulating substrate to the counter surface is extremely small. In this case, it is difficult to fill the recess with the adhesive, and a void can form at the interface between the adhesive and the insulating substrate near the recess. Consequently, the reliability of the semiconductor device may be compromised.

[0010] The present invention was conceived with such problems in mind and aims to demonstrate a semiconductor device that can be miniaturized and exhibits high reliability. Means of solving the problems

[0011] The problem described above is solved by a semiconductor device according to claim 1. Effect of the invention

[0012] In this semiconductor device, the package features a recess that extends through the connection area between the package and the insulating substrate. This recess is of sufficient size to allow for increased packing density of the semiconductor elements and a reduced overall size. Therefore, the recess can be reliably filled with the sealing material, increasing the contact area between the sealing material and the insulating substrate compared to a device without this recess. This improves the bond strength between the sealing material and the insulating substrate, thereby increasing the thermal resistance of the miniaturized semiconductor device. This, in turn, enables miniaturization of the semiconductor device and the achievement of high reliability. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention; Fig. 2 is a schematic partial cross-section of the in Fig. 1 of the semiconductor device shown; Fig. Figure 3 is a schematic cross-sectional view of a semiconductor device according to a comparative example of the present invention; Fig. 4 is a schematic partial cross-section of the in Fig. 3 semiconductor device shown; Fig. Figure 5 is a schematic cross-sectional view showing a peeled-off sealing material in the semiconductor device according to the figure in Fig. The comparison example shown in section 3 illustrates this; Fig. Figure 6 is a schematic partial cross-section with a first modification of the one shown in Fig. 1 of the semiconductor device shown; Fig. Figure 7 is a schematic partial cross-section, representing a second modification of the one in Fig. 1 shows the semiconductor device depicted; Fig. Figure 8 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present invention; Fig. 9 is a schematic partial cross-section of the in Fig. 8 semiconductor device shown; Fig. Figure 10 is a schematic partial cross-section, representing a first modification of the one in Fig. 8 shows the semiconductor device depicted; Fig. Figure 11 is a schematic top view, which is a second variation of the one in Fig. 8 shows the semiconductor device depicted; Fig. Figure 12 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present invention; Fig. 13 is a schematic partial cross-section of the in Fig. 12 depicted semiconductor device, and Fig. Figure 14 is a schematic partial cross-section, which is a modification of the one in Fig. 12 shows the semiconductor device depicted. DESCRIPTION OF THE EXECUTION FORMS

[0013] Embodiments of the present invention are described below with reference to the drawings. In subsequent drawings, the same or corresponding components are identified by the same reference numeral, and the description is not repeated. Design 1 Configuration of the semiconductor device

[0014] Fig. Figure 1 is a schematic cross-sectional view showing a basic structure of a semiconductor device according to a first embodiment of the present invention. Fig. 2 is a schematic partial cross-section of the in Fig. 1 of the semiconductor device shown. The configuration of the semiconductor device according to the first embodiment of the present invention is described with reference to Fig. 1 and Fig. 2 described. The in Fig. 1 and Fig. 2 The semiconductor device 100 shown is a semiconductor power module, which is used, for example, for industrial purposes or for automobiles.

[0015] With reference to Fig. The semiconductor device 100 essentially comprises an insulating substrate 41, a metal base plate 3, semiconductor elements 2 connected to the insulating substrate 41, wiring elements 4a, 4b, a housing part 5 surrounding the semiconductor elements 2, an electrode connection 7, and a sealing resin 1. The housing part 5 is bonded to the insulating substrate 41 by an adhesive 6. The housing part 5 has a recess 51 on its inner surface at its end region on the side facing the insulating substrate 41. The recess 51 is filled with the sealing resin. The insulating substrate 41 includes an insulating layer 8 with a front surface and a back surface, a first circuit board 31 on the front surface of the insulating layer 8, and a second circuit board 32 on the back surface of the insulating layer 8. The insulating layer 8 has a greater width than the first circuit board 31 and the second circuit board 32.Therefore, the insulating layer has 8 ends that extend outwards opposite the ends of the first circuit board 31 and the ends of the second circuit board 32.

[0016] The semiconductor element 2 is arranged on the insulating substrate 41. The semiconductor element 2 is connected to the first circuit board 31 of the insulating substrate 41 by a first connecting material 21. The insulating substrate 41 is provided on the metal base plate 3. The metal base plate 3 and the insulating substrate 41 are connected to each other by a second connecting material 22.

[0017] The housing part 5 is bonded to the insulating layer 8 of the insulating substrate 41 using an intermediate adhesive 6. The adhesive 6 can be, as shown in Fig. 2, shown, are brought into contact with the housing part 5, the insulating layer 8, and the first printed circuit board 31. Two semiconductor elements 2 are connected to each other via the wiring element 4a. One of the semiconductor elements 2 is connected to the electrode terminal 7 via the wiring element 4b. The electrode terminal 7 is formed together with the housing part 5. One end region of the electrode terminal 7 is a connection region connected to the wiring element 4b. The electrode terminal 7 extends through the housing part 5 from one end region that is exposed on the inner circumferential surface of the housing part 5 and projects beyond the housing part 5. The connection region of the electrode terminal 7 connected to the wiring element 4b is a first region that extends in one direction along a surface of the first printed circuit board 31.The electrode connection 7 also has a second area that extends vertically and intersects the first area. The second area includes a section that extends through and beyond the housing part 5.

[0018] The housing part 5, viewed from above on the surface of the first circuit board 31, has a rectangular shape to, for example, surround the semiconductor elements 2. An inner circumferential surface of the recess 51 provided in the housing part 5 consists of a surface of the housing part 5 and the surface of the first circuit board 31. The recess 51 is filled with sealing resin 1. The recess 51 has a counter surface 61 facing the first circuit board 31, which is higher than an upper surface 2a of the semiconductor element 2. More precisely, the distance H1 from the surface of the first circuit board 31 to the counter surface 61 is greater than the distance H2 from the surface of the first circuit board 31 to the upper surface 2a of the semiconductor element 2.

[0019] The distance H1 from the first circuit board 31 to the mating surface 61, which is opposite the first circuit board 31, should be set to, for example, no less than 0.5 mm and no more than 10 mm. If the distance H1 is less than 0.5 mm, there is insufficient space in the recess 51 for filling with sealing resin 1, which can lead to difficulties during filling; if the distance H1 is greater than 10 mm, on the other hand, the semiconductor component 100 will be too large.

[0020] The thickness T1 of the housing part 5, located outside the recess 51, is preferably set to a specific thickness to maintain the strength of the housing part 5. For example, the thickness T1 can be set to no less than 1 mm and no more than 20 mm. If the thickness T1 is less than 1 mm, the strength of the housing part 5 may be insufficient. Conversely, if the thickness T1 is more than 20 mm, the area on the inner circumferential side of the housing part 5, namely the mounting area for the semiconductor elements 2, is reduced, assuming the housing part 5 has a constant outer circumference.

[0021] The semiconductor element 2 can be, for example, an IGBT (Insulated Gate Bipolar Transistor) for quickly switching a large amount of current, or a reflux diode arranged in parallel with the semiconductor element. Examples of materials that can be used for the semiconductor element 2 include not only silicon (Si), but also so-called broadband gap semiconductors with larger band gaps than silicon. Examples of broadband gap semiconductors that can be used are: composite semiconductors such as silicon carbide (SiC), gallium nitride (GaN), or diamond. The number of semiconductor elements 2 can be one, three, or more, without limiting to two, as in Fig. 1 is shown to be limited. The number of semiconductor elements 2 can be arbitrary depending on the intended use of the semiconductor device.

[0022] Although copper is normally used as the material for the first circuit board 31, the second circuit board 32, and the electrode connections 7, the material is not limited to this. The material is not particularly restricted as long as it has the required heat dissipation properties. For example, aluminum (Al), iron (Fe), or an aluminum-iron alloy can be used. Alternatively, a composite material, such as a multilayer material consisting of different materials like copper-invar copper, can be used. Furthermore, an alloy such as an aluminum-silicon carbide alloy (AlSiC) or a copper-molybdenum alloy (CuMo) can be used.

[0023] A plated layer, such as a nickel-plated (Ni) layer, is normally formed on the surfaces of the first circuit board 31 and the electrode terminal 7. However, the plated layer may or may not be formed on the surfaces, as long as current and voltage can be supplied to the semiconductor element 2. When forming a plated layer, a gold-plated layer or a tin-plated layer can be formed in addition to the nickel-plated layer, for example.

[0024] On the surface of the first circuit board 31, there is normally a positioning element 14 for defining a position at which the first connecting material 21 is mounted, as shown in Fig. 2 is shown, arranged. A resist material can be applied as the positioning element 14. Polyimide can be used as the material for the positioning element 14, provided that the position at which the first connecting material 21 is mounted can be defined. Alternatively, the positioning element 14 described above can be omitted.

[0025] The insulating layer 8 is typically a substrate made of a ceramic insulating material such as aluminum oxide (Al₂O₃), aluminum nitride (AlN), or silicon nitride (Si₃N₄). The material for the insulating layer 8 is not limited to the materials described above but can also be silicon dioxide (SiO₂), boron nitride (BN), or the like. The insulating layer 8 is not limited to a ceramic substrate but can also be a resin insulating substrate formed by curing a resin in which ceramic powders are dispersed. In the insulating substrate 41, the insulating layer 8 has a first circuit board 31 on one surface and a second circuit board 32 on its back surface, which is the other surface. Any suitable method can be used to connect the first circuit board 31 and the second circuit board 32 to the insulating layer 8.

[0026] In the insulating substrate formed by the curing of a resin, in which ceramic powders are dispersed and which serves as an insulating layer 8, aluminum oxide (Al₂O₃), silicon dioxide (SiO₂), aluminum nitride (AlN), boron nitride (BN), silicon nitride (Si₃N₄), or the like can be used as ceramic powders. The material for the ceramic powders is not limited to the materials described above. For example, diamond (C), silicon carbide (SiC), or boron oxide (B₂O₃) can be used.

[0027] Powders to be dispersed in the resin insulating substrate as insulating layer 8 can include not only ceramic powders but also resin powders such as silicone resin or acrylic resin. The powders can be spherical or have other shapes. For example, they can be in a pulverized form, where a bulk material has simply been pulverized (granular form), a grain-like form, or another shape. Alternatively, an aggregate containing a variety of unit powders can be used. The quantity of powder provided in the insulating resin substrate as insulating layer 8 can be determined to achieve the required heat dissipation and insulation properties. Although epoxy resin is typically used as the material for the resin forming the insulating substrate, it is not the only option. For example, polyimide resin, silicone resin, or acrylic resin can be used as the resin material.Any resin can be used, as long as the resin has both insulating and adhesive properties.

[0028] Although a metal such as copper (Cu) or aluminum (Al) is typically used as the material for the metal base plate 3, the material is not limited to these. For example, an alloy such as an aluminum-silicon carbide alloy (AlSiC) or a copper-molybdenum alloy (CuMo) can be used as the material for the metal base plate 3. Alternatively, an organic material such as epoxy resin, polyimide resin, or acrylic resin can also be used as the material for the metal base plate 3.

[0029] Although, for example, a wire made of metal such as aluminum with a circular cross-sectional shape is used as wiring elements 4a, 4b, the wiring elements 4a, 4b are not limited to this. A strip obtained by forming copper or aluminum (Al) into a strip can be used as wiring elements 4a, 4b. A wire with a circular cross-sectional shape and a strip can be combined for use as wiring elements 4a, 4b. Although the Fig. 1 and Fig. 2. This figure shows a structure in which one or two wiring elements 4a, 4b are connected to a semiconductor element 2. Fig. 1 and Fig. 2 a simplified connection state between the wiring elements 4a, 4b and the semiconductor element 2. In the actual semiconductor device 100, a required number of wiring elements 4a, 4b can be provided, depending on conditions such as the current density of the semiconductor element 2 and the operating temperature of the semiconductor device 100.

[0030] Although LCP (Liquid Crystal Polymer) and PPS (Polyphenylene Sulfate) are primarily used as materials for housing part 5, the material options are not limited to these. A thermoplastic material such as PBT (Polybutylene Terephthalate) can also be used for housing part 5. In fact, any material can be used for housing part 5, provided it is heat-resistant and easily formable.

[0031] Although epoxy resin is used as a material for sealant resin 1, the material options are not limited to epoxy. Any material with a desired modulus of elasticity, heat resistance, and adhesive properties can be used for sealant resin 1. For example, silicone resin, urethane resin, polyimide resin, polyamide resin, or acrylic resin can be used as a material for sealant resin 1. Functions and effects

[0032] The semiconductor device 100 described above comprises the insulating substrate 41 with a main surface, semiconductor elements 2, the housing part 5, and sealing resin 1 as a sealing material. The semiconductor element 2 is arranged on the main surface of the insulating substrate 41. The housing part 5 encloses the semiconductor element 2 and is connected to the insulating substrate 41. Sealing resin 1 is arranged in an inner region surrounded by the housing part 5 and the insulating substrate 41 and encloses the semiconductor element 2. The housing part 5 includes the recess 51, which extends through a connection area of ​​the housing part 5 connected to the insulating substrate 41 and faces the inner region. The recess 51 includes the counter surface 61 as an inner wall region opposite the main surface of the insulating substrate 41.The distance H1 from the main surface of the insulating substrate 41 (the upper surface of the first circuit board 31) to the opposite surface 61, as the inner wall area, is greater than the distance H2 from the main surface to the upper surface 2a of the semiconductor element 2. In other words, as in . Fig. 1 and Fig. Figure 2 shows the insulating substrate 41 mounted on the metal base plate 3 in the semiconductor device 100 of the present embodiment. The semiconductor device 2 is mounted on the insulating substrate 41. The housing part 5 is provided for enclosing the semiconductor device 2. In such a semiconductor device 100, the underside of the housing part 5 is provided with the recess 51 and the mating surface 61, which is higher than the upper surface 2a of the semiconductor device 2.

[0033] In such a semiconductor device 100, since the recess 51 in the housing part 5 is formed such that it faces the semiconductor element 2 as described above, the adhesion area between the sealing resin 1 and the first circuit board 31 in the vicinity of the semiconductor element 2 can be increased. This reduces the possibility of peeling between the insulating substrate 41 and the sealing resin 1 due to thermal stress and improves the reliability of the semiconductor device 100 with respect to thermal stress.

[0034] In the semiconductor device 100 described above, the mating surface 61 is formed as an inner wall region parallel to the main surface of the insulating substrate 41, in particular the surface of the first printed circuit board 31. In this case, the recess 51 can be sufficiently enlarged compared to an example where the mating surface 61 is inclined relative to this surface. Therefore, the recess 51 can be adequately filled with sealing resin 1.

[0035] In the semiconductor device 100 described above, the housing part 5 is provided with the recess 51 in an area with the shortest distance to the semiconductor element 2. In this case, the recess 51 can be positioned relatively close to the semiconductor element 2. This increases the adhesion area between the insulating substrate 41 and the sealing resin 1 in the recess 51, thereby increasing the adhesion between the sealing resin 1 and the insulating substrate 41 at the point near the semiconductor element 2. This reduces the possibility of damage to the semiconductor element 2 caused by the sealing resin 1 peeling off the insulating substrate 41.

[0036] In the semiconductor device 100 described above, the housing part 5 is attached to the insulating substrate 41. In this case, the sealing resin 1 is also attached to the housing part 5. Therefore, the sealing resin 1 can be attached to the insulating substrate 41 via the housing part 5. This reduces the possibility of the sealing resin 1 peeling off the insulating substrate 41.

[0037] In the semiconductor device 100 described above, the sealing resin 1 is either epoxy resin or silicone resin. In this case, the semiconductor device 2 can be reliably sealed with the sealing resin 1.

[0038] The reason why the reliability with respect to thermal stress in the semiconductor device 100 of the present embodiment can be improved will now be described in a comparative example with reference to a semiconductor device 101. Fig. Figure 3 is a schematic cross-sectional view of the semiconductor device 101 in the comparative example of the present invention. Fig. 4 is a schematic partial cross-section of the in Fig. 3 Semiconductor device 101 shown. The semiconductor device 101 as a comparative example in Fig. 3 and Fig. 4 is essentially structured similarly to the one in Fig. The semiconductor device shown in Figure 100 differs from the one shown in the diagram. Fig. 1 Semiconductor component 100 shown in the illustration, by the fact that the housing part 5 is not provided with the recess 51 (see Fig. 1).

[0039] In semiconductor device 101 as a comparative example in Fig. 3 the distance L2 between the end of the semiconductor element 2 mounted on the insulating substrate 41 and the inner wall of the housing part 5 is smaller than the distance L1 between the end of the semiconductor element 2 and the inner wall of the housing part 5 in the semiconductor device 100 according to Fig. 1. The distance L3 between the end of the other semiconductor element 2 and the inner wall of the housing part 5 in Fig. 3 is also smaller than the distance of the corresponding area in Fig. 1.

[0040] As from Fig. As can be seen in Figure 3, the distance L2 is a distance between the inner wall of the housing part 5 on one side of the housing part 5 with the electrode connection 7 and the end of the semiconductor element 2. This distance L2 is significantly smaller than the corresponding distance L1 in Figure 3. Fig. 1. The electrode terminal 7 is electrically connected to the semiconductor element 2 via the wiring element 4b. To connect the wiring element 4b to the electrode terminal 7, a large width L4 of the electrode terminal 7 projection must extend from the housing part 5 (see Fig. 4) are provided to prevent a wiring device, such as a wire bonder, from colliding with the housing part 5. Accordingly, the thickness L5 of the housing part 5 is on the side with electrode connection 7 (see Fig. 4) greater than a thickness L6 of the housing part 5 without electrode connection 7 (see Fig. 3) Therefore, the distance L2 is usually particularly small.

[0041] The small gap L2 reduces the adhesive area between the sealing resin 1 and the first circuit board 31 in the area between the semiconductor element 2 and the housing part 5 near the semiconductor element 2. With this reduced adhesive area, the adhesive force between the sealing resin 1 and the first circuit board 31 cannot withstand thermal stress. This results in a peeling area 10 as shown in Fig. 5 shown. Fig. Figure 5 is a schematic cross-sectional view from the first circuit board 31 in the semiconductor device 101. Fig. 3 peeled-off sealing resin 1. This peeling normally occurs at the end of the first circuit board 31. In the case of the in Fig. 3 and Fig. In the semiconductor device 101 shown in Figure 4, peeling occurs due to thermal stress caused by the small distance L2 (see Figure 4). Fig. 4) and reaches the semiconductor element 2 and the first connecting material 21 as in Fig. 5 shown. As peeling progresses in this area, there is a risk of reduced insulation safety and the occurrence of cracks in the first connecting material 21 due to thermal stress.

[0042] In contrast to the one in Fig. 3, Fig. 4 to Fig. The comparative example shown in section 5 is used in the semiconductor device 100 in Fig. 1 and Fig. 2. The recess 51 is formed on the inside of the housing part 5. Therefore, the adhesive surface between the sealing resin 1 and the insulating substrate 41, more precisely, the adhesive surface between the sealing resin 1 and the first circuit board 31 near the semiconductor element 2, is larger than that of the semiconductor element 101 in the comparative example. This improves the adhesion between the sealing resin 1 and the first circuit board 31 and increases the tolerance within which the semiconductor element 100 can be subjected to thermal stress. This suppresses the occurrence of peeling under thermal stress in the semiconductor element 100. Configuration, functions, and effects of modifications

[0043] Fig. Figure 6 is a schematic partial cross-section with a first modification of the one shown in Fig. 1 of the semiconductor device shown. The one in Fig. The semiconductor device 100 shown in Figure 6 is essentially structured similarly to the one in Figure 6. Fig. 1 and Fig. The semiconductor component shown in section 2 differs from the one in [reference missing]. Fig. 1 and Fig. 2 Semiconductor component 100 shown with regard to the shape of the electrode connection 7 and the first circuit board 31. That is, in which in Fig. In the semiconductor device 100 shown in Figure 6, the surfaces of the respective areas of the electrode terminal 7 and the first circuit board 31 that come into contact with the sealing resin 1 are provided with irregularity areas 11, 12, including smaller irregularities, to improve adhesion to the sealing resin 1. The electrode terminal 7 is provided with an irregularity area 12 at a location adjacent to the connection area connected to the wiring element 4b. The first circuit board 31 is provided with the irregularity area 11 in an area within the recess 51. Because such irregularity areas 11, 12 are formed, the adhesion between the sealing resin 1 and the electrode terminal 7 and between the sealing resin 1 and the first circuit board 31 is improved.

[0044] Fig. Figure 7 is a schematic partial cross-section, representing a second modification of the one in Fig. The semiconductor device shown in Figure 1 is depicted. Fig. The semiconductor device 100 shown in Figure 7 is essentially structured similarly to the one in Figure 7. Fig. 1 and Fig. The semiconductor component shown in section 2 differs from the one in [reference missing]. Fig. 1 and Fig. The semiconductor device 100 shown in Figure 2 is constructed by forming a surface-treated layer 13 on a portion of the surface of the electrode terminal 7 and the first circuit board 31. That is to say, in the Fig. In the semiconductor device 100 shown in Figure 7, an adhesion promoter layer is formed as a surface-treated layer 13 on the surface of the electrode terminal 7 and the first circuit board 31, which is in contact with the sealing resin 1. The electrode terminal 7 is provided with the surface-treated layer 13 at a location adjacent to the connection area connected to the wiring element 4b. The first circuit board 31 is provided with the surface-treated layer 13 in an area within the recess 51. The surface-treated layer 13 is formed by applying an adhesion promoter. Because this surface-treated layer 13 is formed, the adhesion between the sealing resin 1 and the electrode terminal 7, and between the sealing resin 1 and the first circuit board 31, is improved.

[0045] The surface-treated layer 13 can be applied to the surface of the electrode terminal 7 and the first circuit board 31 by means of primer treatment and the like. A silane adhesion promoter, polyimide, or epoxy resin can be used, for example, as an adhesion promoter. Any material can be used as an adhesion promoter as long as it improves the adhesion between the electrode terminal 7 and the sealing resin 1, and between the first circuit board 31 and the sealing resin 1. Design 2 Configuration of the semiconductor device

[0046] Fig. Figure 8 is a schematic cross-sectional view showing a basic structure of a semiconductor device 200 according to a second embodiment of the present invention. The configuration of the semiconductor device 200 according to the second embodiment of the present invention is described with reference to Fig. 8 described.

[0047] As in Fig. As shown in Figure 8, the semiconductor device 200 is essentially structured similarly to the one in Fig. 1 and Fig. The semiconductor component shown in section 2 differs from the one in [reference missing]. Fig. 1 and Fig. The semiconductor device 100 shown in section 2 is distinguished by the fact that it has a through-hole 9 in the housing part 5. That is to say, the Fig. The semiconductor component 200 shown in Figure 8 is provided with the through-hole 9, which extends from inside the recess 51 to an upper end of the housing part 5. Functions and effects

[0048] The in Fig. The semiconductor device 200 shown in Figure 8 can achieve essentially similar effects to the one in Figure 8. Fig. 1 Semiconductor component shown 100. Furthermore, in the Fig. In the semiconductor device 200 shown in Figure 8, the through-hole 9, which is provided in the housing part 5, extends through the housing part 5 from the opposite surface 61 of the recess 51 to an upper surface of the housing part 5. The housing part 5 is provided with the through-hole 9, which extends from the inner recess 51 to a region of a surface of the housing part 5 other than the recess 51. Since the through-hole 9 is formed, the filling with sealing resin 1 in the recess 51 can be improved. This is shown in Figure 8. Fig. 9 explained. Fig. 9 is a schematic partial cross-section in a manufacturing process of the in Fig. 8 of the semiconductor device shown, to illustrate the effect of the through-hole 9 in this semiconductor device.

[0049] As in Fig. As shown in Figure 9, during filling with sealing resin 1 in the semiconductor device 200, the sealing resin 1 can come into contact with the housing part 5 at a position higher than the counter surface 61 of the recess 51, for example, if the sealing resin 1 is not very fluid. In this case, an unfilled area 71 is created in the recess 51 in which no sealing resin 1 is present. If such an unfilled area 71 remains in the recess 51 after the sealing resin 1 has cured, there is a risk that the insulating and peeling resistance of the sealing resin 1 will decrease.

[0050] In the semiconductor device 200 of the second embodiment, the air volume present in the unfilled area 71 can be discharged to the outside of the semiconductor device 200 via the through-hole 9. Thus, if an inner peripheral side opening in the recess 51 is sealed with sealing resin 1, while the unfilled area 71 remains as described in Fig. As shown in Figure 9, the air volume remaining in the unfilled area 71 is discharged to the outside through the through-hole 9, as indicated by the arrows in Figure 9. Fig. Figure 9 illustrates this. Therefore, the flow of the sealing resin 1 into the recess 51 through the air space is not prevented. Accordingly, the unfilled area 71 is also filled with sealing resin 1, so that the sealing resin 1 is completely contained within the recess 51. The semiconductor device with high reliability can thus be provided.

[0051] Configuration, Functions, and Effects of Variations: Any shape can be used for the through-hole 9, as long as the air volume present in the unfilled area 71 within the recess 51 can be discharged outside the recess 51. The through-hole 9 does not necessarily have to lead from the opposite surface 61 to the top of the housing part 5, as shown in Fig. 8 and Fig. 9 shown. Fig. 10 is a schematic partial cross-section with a first modification of the one in Fig. 8 of the semiconductor device shown and a schematic cross-sectional view with a further configuration example of the through-hole 9. Fig. 10 corresponds Fig. Figure 9 shows the filling of the sealing resin 1 in the space on the inner circumferential side of the housing part 5 in a manufacturing process of the semiconductor device.

[0052] The in Fig. The semiconductor device shown in 10 is fundamentally similar in structure to the one in Fig. 8 and Fig. The semiconductor component shown in 9 differs from the one in Fig. 8 and Fig. The semiconductor device shown in Figure 9 is in the configuration of the through-hole 9. That is, in which in Fig. In the semiconductor device shown in Figure 10, the through-hole 9 is designed such that it extends from the recess 51 in the housing part 5 below the electrode terminal 7 to an upper surface of the projection of the inner surface of the housing part 5 in which the electrode terminal 7 is partially arranged.

[0053] As in Fig. As shown in Figure 10, the recess 51 in the side of the housing part 5, in which the electrode terminal 7 is located, has a greater distance L1 between the end of the semiconductor element 2 and the inner wall of the recess 51 in the housing part 5 than when the recess 51 is formed on the other side. Thus, the unfilled area 71 tends to form in the recess 51. By providing the through-hole 9 in the projection of the side of the housing part 5, in which the electrode terminal 7 is located, as shown in Figure 10, the recess 51 is formed in the housing part 5. Fig. As shown in Figure 10, the air can be discharged from the inner recess 51 below the electrode connection 7 into a space above the protrusion through the through-hole 9. Accordingly, the discharge of the air space or volume present in the unfilled area 71 can be facilitated in order to completely fill the recess 51 with sealing resin 1, as shown in Figure 10. Fig. 10 shown.

[0054] The through-hole 9 is preferably placed where an unfilled area tends to be created in the semiconductor device 200. Fig. Figure 11 is a schematic top view showing a second modification of the semiconductor device 200 in the present embodiment.

[0055] The in Fig. The semiconductor device shown in 11 is fundamentally similar in structure to the one in Fig. 8 and Fig. The semiconductor component shown in 9 differs from the one in Fig. 8 and Fig. The semiconductor device shown in Figure 9 is in the configuration of the through-hole 9. That is, in which in Fig. In the semiconductor device shown in Figure 11, a plurality of through-holes 9a to 9c are formed on the side of the housing part 5 where the electrode terminals 7 are located. Several electrode terminals 7 are arranged on this side of the housing part 5. The numerous through-holes 9a to 9c are arranged between one another to sandwich the electrode terminals 7. In other words, the plurality of through-holes 9a to 9c are arranged so that they are aligned with the electrode terminals 7 in the direction in which this side extends. The through-holes 9a to 9c can have the same diameter or different diameters. For example, as shown in Fig. Figure 11 shows that through-holes 9b and 9c, located in areas closer to the corners of the housing part 5, have a larger diameter than through-hole 9a, which is located in a central area of ​​this side of the housing part 5. An unfilled area 71 is more likely to form at the corners of the housing part 5. Due to the relatively large diameter of through-holes 9b and 9c, air can be extracted more reliably from the unfilled area 71.

[0056] The location where an unfilled region 71 is generated depends on the arrangement of the semiconductor element 2, the wiring elements 4, and the like. In a simple configuration, e.g., if the end face of the semiconductor element 2 is substantially parallel to one side of the housing part 5, the unfilled region 71 generated at a point of initial impact of the sealing resin 1 in the housing part 5 can be eliminated by arranging the through-hole 9a in a central region of this one side of the housing part 5, as shown in Fig. Figure 11 illustrates this. Furthermore, unfilled areas 71 that arise at the end filling points of the sealing resin 1 can be eliminated by the arrangement of through holes 9b and 9c at the corners of the housing part 5. When the through hole 9a is arranged in the central part of one side of the housing part 5, the through hole 9a is preferably positioned at some distance from the electrode connection 7 to avoid interference with the electrode connection 7. Design 3 Configuration of the semiconductor device

[0057] Fig. Figure 12 is a schematic cross-sectional view showing a basic structure of a semiconductor device 300 according to a third embodiment of the present invention. The configuration of the semiconductor device 300 according to the third embodiment of the present invention is described with reference to Fig. 12 described.

[0058] As in Fig. As shown in Figure 12, the semiconductor device 300 is in principle similar to the one in Fig. The semiconductor device shown in section 8 is constructed using 200 components, but differs from the one shown in Fig. The semiconductor device 200 shown in section 8 is defined by the shape of the inner wall of the recess 51. That is, in the Fig. In the semiconductor device 300 shown in Figure 12, the opposite surface 61 of the recess 51 is inclined relative to the insulating substrate 41 with respect to the front surface of the insulating layer 8 or the surface of the first circuit board 31.

[0059] In other words, the mating surface 61 of the recess 51 is a surface inclined such that its distance to the insulating layer 8 or first circuit board 31 gradually increases from the end on the outer circumferential side to the end on the inner circumferential side of the housing part 5. The through-hole 9 extends from a central region of the mating surface 61, i.e., this inclined surface, to the upper surface of the housing part 5. Functions and effects

[0060] The in Fig. The semiconductor device 300 shown in Figure 12 can achieve essentially similar effects to the one in Figure 12. Fig. 8 shows the semiconductor device. Furthermore, semiconductor device 300 is shown in Fig. 12, the opposite surface 61 of the recess 51 as an inner wall region facing the first circuit board 31, a plane inclined relative to the main surface of the insulating substrate 41 (e.g., the surface of the first circuit board 31). Thus, the volume of the unfilled area 71 created in the recess 51 tends to be dissipated outwards along the opposite surface 61 of the recess 51. This reduces the possibility of the unfilled area 71 remaining in the recess 51 and provides the semiconductor device with high reliability.

[0061] The in Fig. The 12 effects of the semiconductor device 300 shown are described with reference to Fig. 13 described in more detail. Fig. Figure 13 is a schematic partial cross-section of the semiconductor device 300 in Fig. 12, which represents a step in the manufacturing process of the semiconductor device 300 in Fig. 12 shows. Fig. 13 corresponds Fig. 9.

[0062] In the Fig. In the semiconductor device shown in Figure 13, the opposite surface 61 of the recess is an inclined surface. Therefore, the [missing information] in the recess 51 (see Figure 13) can [missing information]. Fig. 12) During sealing with sealant 1, the unfilled area 71, or the volume along the counter surface 61, the inclined surface, moves slightly upwards. Accordingly, the unfilled area 71 is disposed of from the upper surface of the sealant 1 to the outside of the semiconductor device 300, while the unfilled area 71 that arises during filling with sealant 1 cannot move from the inside out when the counter surface 61 is parallel to the surface of the first circuit board 31, unless the air in the unfilled area 71 can be discharged through the through-hole 9. Therefore, it is possible that an unfilled area 71 remains in the recess 51. This possibility can be addressed in the Fig. The number of semiconductor components shown in 12 can be reduced to 300. Configuration, functions, and effects of the modification

[0063] Fig. Figure 14 is a schematic partial cross-section representing a modification of the semiconductor device 300 in Fig. Figure 12 shows the configuration of the semiconductor device according to the modification of the third embodiment of the present invention. Fig. 14 described. Fig. 14 corresponds Fig. 13.

[0064] The in Fig. The semiconductor device shown in 14 is essentially structured similarly to the one in Fig. The semiconductor device 300 shown in Figure 12 differs from the one in Fig. 12 shown semiconductor device 300 by the shape of the inner wall of the recess 51 (see Fig. 12). That is, in which Fig. The opposite surface 61 of the recess 51 of the semiconductor device shown in Figure 14 is (see Fig. 12), which faces the insulating substrate 41, is curved, while it is inclined relative to the front surface of the insulating layer 8 or to the surface of the first circuit board 31. In other words, in the Fig. In the semiconductor device shown in Figure 14, the counter surface 61 is convexly curved towards the insulating substrate 41. The distance of the counter surface 61 from the front face of the insulating layer 8 or the surface of the first circuit board 31 gradually increases from the outer circumferential surface to the inner circumferential surface of the housing part 5. The counter surface 61 has a cross-sectional shape of Fig. 14 arc-shaped. The through-hole 9 is shaped such that it extends from the curved counter-surface 61 to the upper surface of the housing part 5.

[0065] The in Fig. The semiconductor device shown in 14 can achieve similar effects to the one in Fig. 12 semiconductor components shown 300.

[0066] The configurations of the embodiments described above can be combined as needed. For example, the configuration described in Fig. 6 or Fig. The structure shown in Figure 7 is applied to the semiconductor devices 200 or 300 according to the second or third embodiment. Fig. 10 or Fig. The structure shown in 11 can be applied to the semiconductor device 300 according to the third embodiment. Reference symbol list 1 Sealing resin 2 Semiconductor element 2a upper surface 3 Metal base plate 4a, 4b Wiring element 5 Housing part 6 glue 7 Electrode connection 8 Insulation layer 9, 9a, 9b, 9c Through hole 10 peeling area 11, 12 Irregularity range 13 surface-treated layers 14 Positioning element 21 first joining material 22 second joining material 31 first circuit board 32 second circuit board 41 Insulating substrate 51 Recess / Cutout 61 Opposite surface 71 unfilled area 100, 101, 200, 300 semiconductor device

Claims

[1] Semiconductor device (100) comprising the following: an insulating substrate (41) with a main surface; a semiconductor element (2) arranged on the main surface of the insulating substrate (41); a housing part (5) that surrounds the semiconductor element (2) and is attached to the insulating substrate (41); and a sealing material (1) arranged in an inner area surrounded by the housing part (5) and the insulating substrate (41) and surrounding the semiconductor element (2); and an electrode terminal (7) which is connected to the semiconductor element (2) and which is formed together with the housing part (5), wherein the housing part (5) has a recess (51) which is formed continuously with a connection area of ​​the housing part (5) connected to the insulating substrate (41) and faces the interior area, wherein the recess (51) has a counter surface (61) which faces the main surface of the insulating substrate (41), wherein the counter surface (61) extends from an end on the outer circumferential side to an end on the inner circumferential side of the housing part (5), wherein the electrode connection (7) has a first region extending in a direction along the main surface of the insulating substrate (41) and a second region extending in a vertical direction intersecting the first region, wherein a distance (H1) from the main surface of the insulating substrate (41) to the end on the inner circumferential side of the counter surface (61) is greater than a distance (H2) from the main surface to an upper surface (2a) of the semiconductor element (2), and wherein the opposite surface (61) is arranged between the first area and the main surface, and wherein the opposite surface (61) is parallel to the main surface of the insulating substrate (41), or the opposite surface (61) is inclined relative to the main surface of the insulating substrate (41), so that the distance of the counter surface (61) from the main surface of the insulating substrate (41) gradually increases from the end on the outer circumferential side to the end on the inner circumferential side. [2] Semiconductor device according to claim 1, wherein the housing part (5) is provided with a through hole (9) extending from inside the recess (51) to an area of ​​a surface of the housing part (5) other than the recess (51). [3] Semiconductor device according to claim 1, wherein the counter surface (61) has a curved surface between the end on the outer circumferential side and the end on the inner circumferential side. [4] Semiconductor device according to one of claims 1 to 3, wherein the housing part (5) is provided with the recess (51) in an area with the shortest distance to the semiconductor element (2). [5] Semiconductor device according to any one of claims 1 to 4, wherein the sealing material comprises epoxy resin or silicone resin.

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