Power conversion device

Abstract

Power conversion device comprising the following: a first power semiconductor element (165); a second power semiconductor element (165); and a printed circuit board (400) which is arranged next to the first power semiconductor element (165) and the second power semiconductor element (165) and contains a circuit for transmitting a control signal of the first power semiconductor element (165) and the second power semiconductor element (165), characterized by the fact that the circuit board contains (400): a first emitter line (421) which is formed along an arrangement direction of the first power semiconductor element (165) to the second power semiconductor element (165), a first gate line (411) which is arranged between the first power semiconductor element (165) and the first emitter line (421), a second gate line (412) which is arranged between the second power semiconductor element (165) and the first emitter line (421), a third gate line (413) which is arranged opposite the first gate line (411) and the second gate line (412), wherein the first emitter line (421) is inserted between the third gate line (413) and the first gate line (411) and the second gate line (412), and a first gate resistor (431) that connects the first gate line (411) and the third gate line (413) across the first emitter line (421). a second gate resistor (432) that connects the second gate line (412) and the third gate line (413) across the first emitter line (421).

Description

Technical field

[0001] The present invention relates to a power conversion device that converts direct current power into alternating current power or alternating current power into direct current power, and in particular to a power conversion device that is used in a hybrid vehicle and in an electric vehicle. State of the art

[0002] In a power conversion device used in a hybrid and an electric vehicle, it is necessary to increase the output power while simultaneously increasing the drive torque of both the hybrid and electric vehicles. To handle the increase in output power, several power semiconductors are connected in parallel.

[0003] However, the parallel-connected power semiconductors must be connected simultaneously to achieve their full performance. It is essential to prevent an impedance imbalance in the control signal line, through which a control signal is transmitted to each power semiconductor.

[0004] With regard to such a problem, PTL 1 discloses a configuration in which control signal lines are stacked to suppress the current of an emitter loop formed in emitters of several power semiconductors, causing a current imbalance. PTL 2 discloses that in a semiconductor arrangement with at least one semiconductor body located on an insulating substrate equipped with terminals, a low-inductance arrangement can be achieved by arranging the connecting lines in close proximity to each other and at least partially parallel to each other. PTL 3 discloses a power output circuit for use in high-current and high-frequency applications. The output circuit provides an array of geometrically symmetrical, parallel-spaced semiconductor converters arranged such that the voltage for each semiconductor output device is essentially the same and minimal for each device. PTL 4 discloses a semiconductor device comprising at least one semiconductor chip, a gate wiring connected to at least one semiconductor chip, a first wiring connected to at least one semiconductor chip and a second wiring connected to at least one semiconductor chip. PTL 5 reveals several MOS transistors arranged on the top surface of a conductor substrate, which serves as a drain electrode. The drain contact of each MOS transistor is connected to the conductor substrate. The source contact of each MOS transistor is connected via a bond wire to the output conductor path, which also serves as a source electrode. The gate contact of each MOS transistor is connected via a bond wire to a driver signal conductor path, which also serves as a gate electrode. The source contacts of the MOS transistors are interconnected via a bridge electrode and a bond wire. PTL 6 discloses a semiconductor element comprising a semiconductor substrate and a transistor formed on the semiconductor substrate. Furthermore, a control electrode terminal, forming an external electrode terminal of the transistor, and a first electrode terminal for sending an output signal are provided on the main surface of the semiconductor substrate. PTL 7 discloses a method for constructing and connecting four power transistor chips to operate at a first frequency without oscillation at a second frequency which is higher than the first frequency but lower than a cutoff frequency of the transistors. PTL 8 discloses a wiring pattern on the emitter substrates which are connected to the emitters of the corresponding IGBT chips via aluminium wires, and the mutually facing ends of the pattern are connected to the aforementioned first and third pads. PTL 9 discloses a semiconductor switching device in which a plurality of semiconductor elements are connected in parallel, and a ferrite core is inserted along any path between module gate wiring branch points and IGBT element gate pads, so that high-frequency vibration during IGBT turn-off can be eliminated and faulty operation of the module can be prevented. PTL 10 discloses several semiconductor switching elements arranged symmetrically with respect to a symmetry line and the symmetrically arranged semiconductor switching elements are arranged in parallel. PTL 11 discloses a power semiconductor module having the main electrode terminal to which the collector-emitter current of the power semiconductor element flows, and a wiring board that performs the electrical control of the power semiconductor element and is located near the main electrode terminal. PTL 12 discloses, according to one embodiment, a semiconductor package, a first substrate, first conductive layers, first semiconductor chips, a second conductive layer, a first terminal, and a second terminal. The first substrate has a first surface. The first conductive layers are deposited on the first surface. Each of the first semiconductor chips contains a first electrode and a second electrode. Each of the first conductive layers is connected to at least one of the first electrodes. The second conductive layer is provided on the first surface to be separated from the first conductive layers. The second conductive layer is connected to a plurality of the second electrodes. The first terminal is connected to the first conductive layers. The inductances between the first extension unit and each of the first conductive layers are substantially equal.The second connection is connected to the second conductive layer. PTL 13 discloses that the respective main electrodes of the semiconductor switching elements, such as IGBTs, which are each mounted on the plurality of insulating plates, are electrically interconnected via the conductor portion. This configuration makes it possible to suppress the occurrence of the resonant voltage due to the junction capacitance and the parasitic inductance of each semiconductor switching element.

[0005] However, there is a need to stack the control signal lines in a multi-layer substrate, which causes a tendency towards a larger control signal substrate. List of oppositions patent literature PTL 1: JP 2016-46842 A PTL 2: US 4 907 068 A PTL 3: US 35 807 E PTL 4: WO 2014 / 002 625 A1 PTL 5: DE 600 32 651 T2 PTL 6: JP 2006- 94 557 A PTL 7: DE 603 ​​08 148 T2 PTL 8: JP 2005- 101 256 A PTL 9: JP 2001- 185 679 A PTL 10: JP 2010- 27 710 A PTL 11: JP 2009- 21345 A PTL 12: US 2017 / 0 069 569 A1 PTL 13: US 2013 / 0 001 805 A1 Summary of the invention: Technical problem

[0006] One object of the invention is to suppress a tendency towards a larger control signal substrate, while suppressing a current imbalance of a control signal transmitted to each power semiconductor. Solution to the problem

[0007] The above-mentioned problem is solved by the invention according to the independent claims. In particular, a power conversion device according to the invention comprises a first power semiconductor element, a second power semiconductor element and a printed circuit board which includes a circuit for transmitting a control signal of the first power semiconductor element and the second power semiconductor element.The printed circuit board includes a first emitter line formed along an arrangement direction of the first power semiconductor element and the second power semiconductor element, a first gate line arranged between the first power semiconductor element and the first emitter line, a second gate line arranged between the second power semiconductor element and the emitter line, a third gate line arranged opposite the first gate line and the second gate line, the emitter line being inserted between the third gate line and the first gate line and the second gate line, and a first gate resistor connecting the first gate line and the third gate line across the first emitter line. Advantageous effects of the invention

[0008] According to the invention, it is possible to reduce an inductance difference between control signal lines of a power semiconductor and to suppress a tendency towards a larger control signal substrate, while suppressing a current imbalance of the control signal. Brief description of the drawings Fig. 1 is a circuit diagram of a power conversion device of an embodiment Fig. Figure 2 is a conceptual perspective exploded view of a power conversion device 500 of the embodiment. Fig. Figure 3 is a schematic representation showing an example of a power module 100 in which IGBTs and diodes are arranged in a circuit structure consisting of Fig. 1 are configured using four power semiconductors. Fig. Figure 4 is a top view of the power module when four IGBT elements 165 are connected in parallel. Fig. Figure 5 is a schematic representation showing the connection between a gate line, an emitter line and the IGBT of a first embodiment. Fig. Figure 6 is a schematic representation showing a circuit diagram of the gate line and the emitter line of the first embodiment. Fig. Figure 7 is a schematic representation that shows an example of a configuration in which normally four IGBTs and a control signal substrate are arranged. Fig. Figure 8 is a schematic representation showing the connection between the gate line, the emitter line and the IGBT in the configuration shown. Fig. 7 represents. Fig. Figure 9 is a circuit diagram of the gate line and the emitter line in the configuration from Fig. 7. Fig. Figure 10 is a perspective external view of the power semiconductor module 100. Fig. Figure 11 is a perspective exploded view showing a procedure for mounting a module sealing body 191 into a housing 103 of the power semiconductor module 100. Fig. Figure 12 is a perspective exploded view of a circuit component of a series connection of an upper / lower branch of the power semiconductor module 100. Fig. Figure 13 is a schematic representation showing an example of a configuration in which eight IGBTs and the control signal substrate of the first embodiment are arranged. Description of embodiments

[0009] The following describes embodiments using the drawings. First embodiment

[0010] In this embodiment, a description is given of an example of a power conversion device that can reduce an inductance difference between control signal lines of a power semiconductor and that can suppress a current imbalance of the control signals.

[0011] Fig. Figure 1 is a circuit diagram of a power conversion device 500 of this embodiment. Using Fig. 1 describes an operating principle of the power conversion device 500 of this embodiment.

[0012] The power conversion device 500 is configured by a power semiconductor module 100, a capacitor module 200, a positive pole conductor 310, and a negative pole conductor 320. This embodiment of the power conversion device 500 converts direct current into three-phase alternating current or three-phase alternating current into direct current and is configured by three power semiconductor modules 100U, 100V, and 100W.

[0013] Each of the 100U to 100W power semiconductor modules is equipped with an AC connection. In other words, the 100U power semiconductor module includes a 150U AC connection. The 100V power semiconductor module includes a 150V AC connection. The 100W power semiconductor module includes a 150W AC connection. The 150U, 150V, and 150W AC module connections are connected to a three-phase motor.

[0014] A DC input / output terminal 319 of the positive pole of conductor 310 is connected to a terminal of the positive pole of a high-voltage battery. A DC input / output terminal 329 of the negative pole of the circuit board 320 is connected to a terminal of the negative pole of the high-voltage battery.

[0015] The capacitor module 200 is provided with a positive pole connection, which is electrically connected to the conductor 310 of the positive pole, and with a negative pole connection, which is electrically connected to the conductor 320 of the negative pole.

[0016] The power semiconductor module 100 is configured with an upper branch and a lower branch. Furthermore, an insulated-layer bipolar transistor (IGBT) is used as an example semiconductor element and is abbreviated as IGBT. The upper branch of the power semiconductor module 100 is configured with an IGBT 161 and a diode 162. A control terminal 171 is also provided in the upper branch to switch the IGBT 161 on or off. The lower branch of the power semiconductor module 100 is configured with an IGBT 163 and a diode 164. A control terminal 172 is also provided in the lower branch to switch the IGBT 163 on or off.

[0017] In the collector of the IGBT 161 of the upper branch, a terminal 111 of the positive pole of the first module is provided for connection to the positive pole conductor 310. In the emitter of the IGBT 163 of the lower branch, a terminal 121 of the negative pole of the first module is provided for connection to the negative pole conductor 320. Furthermore, a module AC terminal 150 is provided between the emitter of the IGBT 161 of the upper branch and the collector of the IGBT 163 of the lower branch.

[0018] The power conversion device 500 can convert a direct current into an alternating current or an alternating current into a direct current by switching a control signal applied to the control terminal 171 of the upper branch and to the control terminal 172 of the lower branch. For example, in a normal state, when the IGBT 161 of the upper branch of the power semiconductor module 100 is switched on and thus the IGBT 163 of the lower branch is switched off, the current flows from the circuit board 310 of the positive terminal via the module terminal 111 of the positive terminal to the module AC terminal 150. Conversely, in a normal state, when the IGBT 161 of the upper branch of the power semiconductor module 100 is switched off and the IGBT 163 of the lower branch is switched on, the current flows from the module AC terminal 150 to the module terminal 121 of the negative terminal.

[0019] Fig. Figure 2 is a conceptual perspective exploded view of the power conversion device 500 of the embodiment.

[0020] The power conversion device 500 is configured by the positive terminal conductor 310, the negative terminal conductor 320, the power semiconductor module 100, and the capacitor module 200. The capacitor module 200 is provided with a positive terminal that is electrically connected to the positive terminal conductor 310, and with a negative terminal that is electrically connected to the negative terminal conductor 320.

[0021] Terminal 111 of the positive pole of the first module of the power semiconductor module 100 is electrically connected to a first terminal 311 of the positive pole of conductor 310. Terminal 121 of the negative pole of the first module of the power semiconductor module 100 is electrically connected to a first terminal 321 of the negative pole of conductor 320.

[0022] The following is a description of an example configuration if several power semiconductors are connected in parallel to improve the output power. Fig. Figure 3 is a schematic representation showing an example of the power module 100, in which IGBTs and diodes are arranged in a circuit structure consisting of Fig. 1 are configured using four power semiconductors.

[0023] In the upper branch, four IGBTs 161 and four diodes 162 are connected in parallel. The source terminals of the four IGBTs 161 and the cathode terminals of the diodes 162 are connected to the module terminal 111 of the positive pole. Furthermore, the emitter terminals of the four IGBTs 161 and the anode terminals of the diodes 162 are connected to the module AC terminal 150.

[0024] On the lower branch side, the four IGBTs 163 and the four diodes 164 are connected in parallel. The source terminals of the four IGBTs 163 and the cathode terminals of the diodes 164 are connected to the module's AC terminal 150. Furthermore, the emitter terminals of the four IGBTs 163 and the anode terminals of the diodes 164 are connected to the module's negative terminal 121.

[0025] The gate terminals 166 of IGBTs 162 and 163 are connected to the gate wires provided in a control signal substrate 400. The emitter terminals 167 of IGBTs 162 and 163 are connected to the emitter lines provided in the control signal substrate 400.

[0026] To suppress resonance between the gates of the parallel-connected IGBTs 162 and 163, four gate resistors 430 are inserted into each of the gate lines of the two control signal substrates 400.

[0027] The gate signals input from control terminals 171 and 172 are fed into a gate terminal 410 and an emitter terminal 420 of the control signal substrate 400. These signals are branched into four by the lines on the control signal substrate 400 and fed into the gate terminal 166 and the emitter terminal 167 of the IGBTs 162 and 163.

[0028] Fig. Figure 4 is a top view of a power module when the four IGBTs 165 are connected in parallel.

[0029] The IGBTs 165 are arranged in a 2x2 configuration, with the control signal substrate 400 inserted between the IGBTs 165. The control signal substrate 400 contains a first gate line 411, a second gate line 412, a third gate line 413, a fourth gate line 414, and a fifth gate line 415.

[0030] Furthermore, a first emitter line 421 is arranged between the first gate line 411 and the third gate line 413 and between the second gate line 412 and the third gate line 413.

[0031] A second emitter line 422 is arranged between the fourth gate line 414 and the third gate line 413 and between the fifth gate line 415 and the third gate line 413.

[0032] The first gate line 411 and the third gate line 413 are connected to a first gate resistor 431 via the first emitter line 421.

[0033] A second gate resistor 432 is connected to the second gate line 412 and to the third gate line 413 via the first emitter line 421.

[0034] Similarly, a third gate resistor 433 is connected via the second emitter line 422 to the fourth gate line 414 and to the third gate line 413. A fourth gate resistor 434 is connected via the second emitter line 422 to the fifth gate line 415 and to the third gate line 413.

[0035] The gate terminal 166 of the IGBT 165 is connected to the gate line of the control signal substrate 400 via a wire contact 440. The emitter terminal 167 of the IGBT 165 is also connected to the emitter line of the control signal substrate 400 via the wire contact 440.

[0036] With such a configuration, the gate signal input between the gate terminal 410 and the emitter terminal 420 of the control signal substrate 400 can be branched at equal distances through the gate line on the control signal substrate 400 to be transmitted to each IGBT.

[0037] Furthermore, another effect is that the magnetic flux caused by the gate signal flowing in the gate line is canceled out by the magnetic flux caused by the gate current flowing to the emitter line between the two gate lines. This allows the inductance of the gate line to be reduced. Since the gate resistor is placed across the emitter line, it is also possible to reduce the required mounting area of ​​a signal wire substrate.

[0038] The following describes a principle for reducing the induction of the gate line.

[0039] Fig. Figure 5 represents a connection structure between the gate line, the emitter line, and the IGBT of this embodiment. For illustrative purposes, the connection configuration of two IGBTs is described here.

[0040] A gate current 21g, input into the gate terminal 410 of the control signal substrate 400, is branched via the third gate line 413 to the first gate resistor 431 and to the second gate resistor 432.

[0041] A gate current Ig, conducted via the first gate resistor 431, is applied to the first gate line 411 and is applied to a gate terminal 183 of a first IGBT 181. Conversely, the gate current Ig flowing in the emitter line returns via the first emitter line 421 from the emitter terminal 184 of the first IGBT 181 to the emitter terminal 420 of the control signal substrate.

[0042] Similarly, the gate current Ig is applied via the second gate resistor 432 and the second gate line 412 to a gate terminal 185 of the second IGBT 182. Furthermore, the gate current Ig returns from the emitter terminal 186 of the second IGBT 182 via the first emitter line 421 to the emitter terminal 420 of the control signal substrate.

[0043] At the same time, the self-inductance of the first gate line 411 is designated by Lg1, the self-inductance of the second gate line 412 is designated by Lg2, the self-inductance of the third gate line 413 is designated by Lg3, the self-inductance of the emitter line 421, which is opposite the first gate line, is designated by Le1, and the self-inductance of the emitter line 421, which is opposite the second gate line 412, is designated by Le2.

[0044] Furthermore, an in Fig. 6 shown circuit diagram, if the mutual inductance between the first gate line 411 and the first emitter line 421 is designated by M1, the mutual inductance between the second gate line 412 and the first emitter line 421 is designated by M2, and the mutual inductance between the third gate line 413 and the first emitter line 421 is designated by M3.

[0045] To focus attention on the influence of the inductances of each gate and emitter line, the resistance of each line is ignored here. Furthermore, the mutual inductance between the first gate line 411 and the third gate line 413 is ignored because they are separated by a distance. A voltage Vge1 between the gate terminal 183 and the emitter terminal 184 of the first IGBT 181 is defined by the following equation, where the voltage between the gate terminal 410 and the emitter terminal 420 of the control signal substrate 400 is Vge, and the current flowing is represented by Ig. Vge1=Vge−(Lg3⋅2Ig−M3⋅Ig)−(Lg1⋅Ig+M1⋅Ig)=Vge−(2Lg3+Lg1+M1−M3)Ig

[0046] Here, it is assumed that the current Ig flows equally in the first gate line 411 and in the second gate line 412. On the other hand, a voltage Vge2 between the gate terminal 185 and the emitter terminal 186 of the second IGBT 182 is defined by the following equation. Vge2=Vge−(Lg3⋅2Ig−M3⋅Ig)−(Lg2⋅Ig−M2⋅Ig)−(Le1⋅Ig+M1⋅Ig−M3⋅2Ig)−(Le2⋅Ig−M2⋅Ig) =Vge−(2Bg3+Bg2+Be1+Be2−2M2−2M3)Ig

[0047] The difference between the gate voltages applied to the first IGBT and the second IGBT is defined as the following Math. 3 from Math. 1 and 2. Vge1−Vge2=(2Lg3+Lg2+Le1+Le2−2M2−2M3)Ig−(2Lg3+Lg1+M1−M3)Ig =(−Lg1+Lg2+Le1+Le2−M1−2M2−M3)Ig

[0048] In other words, a voltage difference is expressed by the product of the inductance and the gate current Ig. If, for the sake of simplicity, we assume here that the lines are symmetrical, and if Lg = Lg1 = LG2, Le = Le1 = Le2, M = M1 = M2 = M3 are assumed, then the difference between the gate voltages applied to the first IGBT 181 and the second IGBT 182 (i.e., the gate-line inductance difference ΔL) is defined as Math. 4. ΔL=2(Le−2M)

[0049] The following section considers a normal control signal substrate in which the emitter line is not crossed by the gate resistor. This is described in Fig. The control signal substrate shown in Figure 7 is considered. The gate current applied to the gate terminal of the control signal substrate is branched through four gate resistors 431 to 434 after passing through the third gate line and reaches four IGBTs 165.

[0050] The following section describes the connection configuration of two IGBTs, as shown in [reference to relevant document / reference]. Fig. Figure 8 is shown. The gate current 21g, which is input into the gate terminal 410 of the control signal substrate, is branched via the third gate line 413 to the first gate resistor 431 and to the second gate resistor 432.

[0051] A gate current Ig flowing through the first gate resistor 431 is applied to the first gate line 411 and is applied to a gate terminal 183 of the first IGBT 181. Conversely, the gate current Ig flowing into the emitter line returns from an emitter terminal 184 of the first IGBT 181 via the first emitter line 421 to the emitter terminal 420 of the control signal substrate.

[0052] Similarly, the gate current Ig applied to the gate terminal 185 of the second IGBT 182 flows via the second gate resistor 432 and via the second gate line 412. Furthermore, the gate current Ig from the emitter terminal 186 of the second IGBT 182 returns via the first emitter line 421 to the emitter terminal 420 of the control signal substrate. Simultaneously, the self-inductance of the first gate line 411 is designated by L'g1, the self-inductance of the second gate line 412 is designated by L'g2, the self-inductance of the third gate line 413 is designated by L'g3, the self-inductance of the emitter line 421 opposite the first gate line is designated by L'e1, and the self-inductance of the emitter line 421 opposite the second gate line 412 is designated by L'e2. Furthermore, a Fig. The equivalent circuit shown in Figure 9 can be expressed if the mutual inductance between the first gate line 411 and the first emitter line 421 is denoted by M'1, the mutual inductance between the second gate line 412 and the first emitter line 421 is denoted by M'2, and the mutual inductance between the first gate line 411 and the third gate line 413 is denoted by M'4. To focus attention on the influence of the inductances of each gate and emitter line, the resistance of each line is ignored here. Furthermore, the mutual inductance between the third gate line 413 and the first emitter line 421 is ignored because they are separated by a distance.A voltage V'ge1 between the gate terminal 183 and the emitter terminal 184 of the first IGBT 181 is defined as the following equation, in which the voltage between the gate terminal 410 and the emitter terminal 420 of the control signal substrate 400 is represented by Vge and the current flowing is represented by Ig. V'ge1=Vge−(L'g3⋅2Ig−M'4⋅Ig)−(L'g1⋅Ig+M'1⋅Ig)=Vge−(2L'g3+L'g1+M'1−M'4)Ig

[0053] Here, it is assumed that the current Ig flows equally in the first gate line 411 and in the second gate line 412. On the other hand, a voltage V'ge2 between the gate terminal 185 and the emitter terminal 186 of the second IGBT 182 is defined by the following equation. V'ge2=Vge−(L'g3⋅2Ig−M'4⋅Ig)−(L'g2⋅Ig−M'2⋅Ig)−(L'e1⋅Ig+M'1⋅Ig)−(L'e2⋅Ig−M'2⋅Ig) =Vge−(2L'g3+L'g2+L'e1+L'e2+M'1−2M'2−M'4)Ig

[0054] A difference between the gate voltages applied to the first IGBT and the second IGBT is defined as the following Math. 7 from Math. 5 and 6. [Math. 7] V'ge1−V'ge2=(2L'g3+L'g2+L'e1+L'e2+M'1−2M'2−M'4)Ig−(2Lg3'+Lg1'+M'1−M'4)Ig =(−L'g1+L'g2+L'e1+L'e2−2M'2)Ig

[0055] In other words, a voltage difference is expressed by the product of the inductance and the gate current Ig. If, for the sake of simplicity, we assume here that the lines are symmetrical, and if L'g = L'g1 = L'g2, L'e = L'e1 = L'e2 and M' = M'1 = M'2 = M'4 are assumed, then the difference between the gate voltages applied to the first IGBT 181 and the second IGBT 182 (i.e., the gate-line inductance difference ΔL) is defined as follows (Math. 8). ΔL'=2(L'e−M')

[0056] The following section describes the inductance difference (Math. 4) of the control signal in the Fig. 4 layout of this embodiment shown and the inductance difference (Math. 8) in the in Fig. The normal layout shown in Figure 7 is compared. If the conductor width and spacing are the same in both layouts, the self-inductance of the emitter line and the mutual inductance between the lines become equal in both layouts. In other words, Le = L'e and M = M' are satisfied. Simultaneously, it can be seen that the inductance difference of this embodiment (Math. 4) becomes small and that the current imbalance of the control signal applied to the IGBT can be suppressed.

[0057] An exemplary configuration of the power semiconductor module 100 used in the power conversion device of the first embodiment is described below. Fig. Figure 10 is a schematic representation showing an example of a configuration of the power semiconductor module 100 used in the power conversion device of this embodiment. As shown in Fig. As shown in Figure 3, the power semiconductor module 100 is configured by the IGBT 161 and the diode 162 of the upper branch and by the IGBT 163 and the diode 164 of the lower branch.

[0058] The power semiconductor module 100 of this embodiment is encapsulated with resin to protect the IGBTs and the diodes within it. The encapsulated terminal surface 190 of the power semiconductor module 100 provides the positive terminal 111, the negative terminal 121, and the AC terminal 150 for connection to the positive terminal 311 or the negative terminal 321. Furthermore, these terminals (positive terminal 111, negative terminal 121, and AC terminal 150) are arranged such that each of the main surfaces overlaps on a virtual surface. Thus, the encapsulation procedure for the power semiconductor module 100 can be easily performed, as the shape of the encapsulation tool for the terminal section can be readily manufactured.

[0059] The description is given using Fig. Figures 10 to 12 show an example of a detailed embodiment of the power semiconductor module. Fig. Figure 10 shows a perspective external view of the power semiconductor module 100. The power semiconductor module 100 contains the housing 103, in which the entire section is sealed except for the opening where the connection is brought out. The housing 103 is configured by a frame 104, which forms side walls and a bottom surface, by a heat dissipation fin 105, which cools the power semiconductor element, and by a flange section 106.

[0060] The heat dissipation fin 105 is formed on a front surface that is widest and perpendicular to the side walls and the bottom surface of the housing 103. The heat dissipation fin 105 is also formed in a similar shape on a surface opposite the front surface.

[0061] When the power semiconductor module 100 is mounted on the power conversion device, the flange section 106 plays a positioning role. It is assumed that the power semiconductor module 100 of this embodiment is a power conversion device in which a heat dissipation section, in which the heat dissipation fin 105 is formed, is in direct contact with a coolant. The flange section 106 also plays a role in ensuring airtightness between the connection and the heat dissipation section where the coolant is located. A groove 106A provided in the flange section 106 contains a component for ensuring airtightness, such as an O-ring. Furthermore, a direct cooling type of the power conversion device described above is described here.However, the power semiconductor module of this embodiment is not particularly limited to these uses and can be used in other types of power conversion devices.

[0062] An insulating potting connection 193 is configured via the module connection 111 of the positive pole, via the module connection 121 of the negative pole, via the module AC connection 150, via the module control connections 171 and 172 and via a potting element 194.

[0063] The potting element 194 has several through-holes to allow these connections (the positive pole module connection 111, the negative pole module connection 121, the AC module connection 150, and the control module connections 171 and 172) to pass through. The potting element 194 electrically isolates these connections from each other.

[0064] Additionally, a separate insulating plate can be configured to be mounted between the terminals to ensure insulation.

[0065] Fig. Figure 11 is a perspective exploded view illustrating a procedure for mounting a module sealing body 191 to the housing 103 of the power semiconductor module 100. The module sealing body 191, in which the power semiconductor elements (the IGBT 161 and the diode 162 of the upper branch and the IGBT 163 and the diode 164 of the lower branch) are sealed and installed, is inserted into an insertion hole 107 of the housing 103. Simultaneously, an insulating element 108 is positioned opposite each surface of the module sealing body 191.

[0066] Fig. Figure 12 is a perspective exploded view of a circuit component of a series connection of an upper / lower branch of the power semiconductor module 100. Fig. 12 is a sealing material of the sealing body 191 of the module, not shown.

[0067] Four IGBTs 161 connected in parallel in the circuit of the upper branch are arranged such that the collector electrode of the IGBT 161 is contacted to a printed circuit board 199. The four diodes 162 connected in parallel in the circuit of the upper branch are arranged such that the cathode electrode of the diode 162 is contacted to the printed circuit board 199. An electrode plate 196 is arranged opposite the electrode plate 199, with the IGBT 161 and the diode 162 inserted between the electrode plate 196 and the electrode plate 199. The electrode plate 196 is contacted to the emitter electrode of the IGBT 161 and to the anode electrode of the diode 162. The power semiconductor elements (the IGBT 161, the diode 162) of the circuit of the upper branch are connected in parallel, so that the power semiconductor elements are inserted in parallel between the electrode plate 199 and the electrode plate 196.Furthermore, the control signal substrate 400 is arranged on the circuit board 199 to branch and transmit the control signal to the parallel-connected IGBT 161.

[0068] Four parallel-connected IGBTs 163 of the lower branch circuit are arranged such that the collector electrode of the IGBT 163 is contacted to a printed circuit board 195. The four parallel-connected diodes 164 of the lower branch circuit are arranged such that the cathode electrode of the diode 164 is contacted to the printed circuit board 195. An electrode plate 197 is arranged opposite the electrode plate 195, with the IGBT 163 and the diode 164 inserted between the electrode plate 197 and the electrode plate 195. The electrode plate 197 is contacted to the emitter electrode of the IGBT 163 and to the anode electrode of the diode 164. The power semiconductor elements (the IGBT 163, the diode 164) of the lower branch circuit are connected in parallel, so that the power semiconductor elements are inserted in parallel between the electrode plate 195 and the electrode plate 197.Furthermore, the control signal substrate 400 is arranged on the circuit board 195 to branch and transmit the control signal to the parallel-connected IGBT 161.

[0069] The printed circuit board 196 and the printed circuit board 195 are connected by metal contacts between an intermediate electrode 198A formed in the printed circuit board 196 and an intermediate electrode 198B formed in the printed circuit board 195. In other words, the power semiconductor elements (the IGBT 161, the diode 162) of the circuit of the upper branch and the power semiconductor elements (the IGBT 163, the diode 164) of the circuit of the lower branch form a series connection.

[0070] Furthermore, the signal terminals 171 and 172 are connected to the gate terminal 410 or to the emitter terminal 420 of the control signal substrate by means of a contact wire.

[0071] Circuit board 196 and circuit board 197 are arranged in the same plane. As shown in Fig. As shown in Figure 11, these circuit boards 196 and 197 are also arranged in such a way that the surfaces opposite the surface where the IGBT and the diode are contacted are exposed to sealing material of the module sealing body 191.

[0072] Circuit board 195 and circuit board 199 are arranged in the same plane. Although this is in Fig. Not shown in Figure 11, these circuit boards 195 and 199 are also arranged such that the surfaces opposite the surface where the IGBT and the diode are contacted are exposed from the sealing material of the module sealing body 191.

[0073] The exposed surfaces of the circuit boards 195, 196, 197 and 199 are arranged opposite the heat dissipation fin 105 of the housing 103.

[0074] Furthermore, the module terminal 111 of the positive pole, the module terminal 121 of the negative pole, and the module AC terminal 150 protrude from the module terminal surface 190 of the module sealing body 191. As described above, these terminals are arranged such that the main surfaces overlap with a virtual plane.

[0075] The housing 103 in the power semiconductor module 100 of this embodiment is formed from a conductive element, e.g., from a composite material such as Cu, a Cu alloy, Cu-C and Cu-CuO, or from a composite material such as Al, an Al alloy, AlSiC and Al-C. Furthermore, the housing 103 is formed by a contacting process with a high water resistance property, such as welding, forging, or casting.

[0076] A novolac-based resin, a multi-purpose epoxy resin, or a biphenyl-based epoxy resin can be used as a sealing material for the module sealing body 191. To bring the coefficient of thermal expansion close to that of printed circuit boards 195, 196, 197, and 199, ceramics such as SiO2, Al2O3, Aln, and BN, a gel, or rubber are integrated. This configuration reduces the difference in the coefficient of thermal expansion between the components. Thermal stress, which arises when the temperature increases depending on the operating environment, is significantly reduced. Thus, it is possible to extend the lifetime of the power semiconductor module.

[0077] A metal contact adhesive used for contacting the printed circuit board and the power semiconductor element can be, for example, a soft soldering material (solder) based on a Sn alloy, a hard soldering material such as an Al alloy and a Cu alloy, or a sintered metal material using nanometal particles / micrometal particles. Second embodiment

[0078] This embodiment describes an example of a configuration in which eight IGBTs are connected in parallel.

[0079] The configuration of the power conversion device of this embodiment is achieved using Fig. 13 described. However, the description of sections with the same function as those of the configurations to which the same reference numeral is attached, which have already been described in the first embodiment, is omitted.

[0080] Fig.Figure 13 is a schematic representation illustrating an example configuration of the power conversion device of this embodiment. This embodiment describes a structure that can reduce the current imbalance between the IGBTs when the eight IGBTs 165 are connected in parallel. The control signal substrate 400 contains the gate lines 411 to 419, which branch the gate signal applied to the gate terminal 410 of the control substrate to the eight IGBTs 165. The third gate line 413, the first gate line 411, the second gate line 412, a sixth line 416, and a seventh gate line 417 are connected via the gate resistor 430 across the first emitter line 421. These gate lines are arranged adjacent to the first emitter line 421.Thus, the inductance difference can be reduced according to the principle described in the first embodiment by canceling the inductance caused by the current flowing in the gate line and the current flowing in the emitter line. Similarly, the third gate line 413, the fourth gate line 414, the fifth gate line 415, an eighth gate line 418, and a ninth gate line 419 are connected via the gate resistor 430 across the second emitter line 422. These gate lines are arranged adjacent to the second emitter line 422. Thus, the inductance difference can be reduced by canceling the inductance caused by the current flowing in the gate line and the current flowing in the emitter line.

[0081] Furthermore, the invention is not limited to the embodiments described above, but may include various modifications. For example, the embodiments of the invention described above have been described in detail in a clearly understandable manner and are not necessarily limited to those with all the described configurations. Moreover, in the embodiment described above, the Si-IGBT has been described as the power semiconductor. However, similar effects can also be obtained if a power semiconductor made of SiC or GaN is used. Furthermore, some of the configurations of a particular embodiment can be replaced by the configurations of other embodiments, and the configurations of other embodiments can be added to the configurations of the respective embodiment.Furthermore, some of the configurations of each embodiment can be omitted, replaced by other configurations, and added to other configurations. Reference symbol list 100 Power Semiconductor Module 103 cases 104 frames 105 Heat dissipation fin 106 Flange 106A Nut 107 Entry hole 108 Insulating element 111 Module connection of the positive pole 121 Module connection of the negative pole 150 module AC connection 161 IGBT of the upper branch 162 Diode of the upper branch 163 lower branch IGBTs 164 Diode of the lower branch 165 IGBT 166 Gate connection of the IGBT 167 Emitter connection of the IGBT 171 Control connection of the upper branch 172 Control connection of the lower branch 190 potted connection surfaces 191 Module sealing bodies 193 insulating potting connection 194 Casting element 195 circuit board 196 circuit board 197 printed circuit board 198 Intermediate electrode 199 printed circuit board 200 capacitor module 310 Conductor of the positive pole 311 Connection of the positive pole 319 DC input / output connection of the positive pole 320 conductors of the negative pole 321 Connection of the negative pole 329 DC input / output connection of the negative pole 400 control signal substrate 410 Gate connector 411 first gate line 412 second gate line 413 third gate line 414 fourth gate line 415 fifth gate line 416 sixth gate line 417 seventh gate line 418 eighth gate line 419 ninth gate line 420 Emitter connection 421 first emitter line 422 second emitter line 430 Gate resistor of the control signal substrate 431 first gate resistor 432 second gate resistor 433 third gate resistor 434 fourth gate resistor 440 wire contact 500 Power conversion device

Claims

[1] Power conversion device comprising the following: a first power semiconductor element (165); a second power semiconductor element (165); and a printed circuit board (400) which is arranged next to the first power semiconductor element (165) and the second power semiconductor element (165) and contains a circuit for transmitting a control signal of the first power semiconductor element (165) and the second power semiconductor element (165), characterized by the fact that the circuit board contains (400): a first emitter line (421) which is formed along an arrangement direction of the first power semiconductor element (165) to the second power semiconductor element (165), a first gate line (411) which is arranged between the first power semiconductor element (165) and the first emitter line (421), a second gate line (412) which is arranged between the second power semiconductor element (165) and the first emitter line (421), a third gate line (413) which is arranged opposite the first gate line (411) and the second gate line (412), wherein the first emitter line (421) is inserted between the third gate line (413) and the first gate line (411) and the second gate line (412), and a first gate resistor (431) that connects the first gate line (411) and the third gate line (413) across the first emitter line (421). a second gate resistor (432) that connects the second gate line (412) and the third gate line (413) across the first emitter line (421). [2] Power conversion device comprising: a first power semiconductor element (165); a second power semiconductor element (165); and a printed circuit board (400) which is arranged between the first power semiconductor element (165) and the second power semiconductor element (165) and includes a circuit for transmitting a control signal of the first power semiconductor element (165) and the second power semiconductor element (165), characterized by the fact that the circuit board contains (400): a first emitter line (421) and a second emitter line (422) which are formed in a transverse direction with respect to an arrangement direction of the first power semiconductor element (165) to the second power semiconductor element (165), a first gate line (411) arranged between the first power semiconductor element (165) and the first emitter line (421), a fourth gate line (414) arranged between the second power semiconductor element (165) and the second emitter line (422), a third gate line (413) arranged between the first emitter line (421) and the second emitter line (422), and a first gate resistor (431) that connects the first gate line (411) and the third gate line (413) across the first emitter line (421). a second gate resistor (432) which connects the fourth gate line (414) and the third gate line (413) via the second emitter line (422).

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