IMPROVING MTJ DEVICE PERFORMANCE BY CONTROLLING DEVICE SHAPE

Abstract

A method for controlling layer distortion effects during the formation of a magnetic thin film device, the method comprising: Providing a substrate (10) having a flat upper surface; forming an electrode layer (25, 27) on the substrate having a flat upper surface; symmetrically shaping the flat upper surface of the electrode layer to form a curved surface having an axis of symmetry; sequentially depositing a layered device structure over the symmetrically shaped upper surface of the electrode layer, whereby each layer in the layered device structure assumes a shape corresponding to the symmetrically shaped upper surface of the electrode layer with laterally extending portions over the flat upper surface of the substrate; then Removing symmetrical portions of the layered device structure and the electrode layer at a distance from the axis of symmetry, which are arranged laterally on each side of the axis of symmetry, using a hard mask layer (85, 87) as a guide, thereby leaving a remaining portion of the layered device structure, the removed portions of the layered device structure having regions (100) where the curved surfaces meet the surrounding flat surfaces, such that layers in the removed portions have vacancies, crystal defects, holes, and dislocations that have migrated into the regions and collected there during formation of the layered device structure, and such that the remaining portion of the layered device structure is relatively free of vacancies, crystal defects, holes, and dislocations, wherein a first sidewall of the remaining portion of the layered device structure and a second sidewall of a remaining portion of the electrode layer are coplanar and perpendicular to a top surface of the substrate.

Description

STATE OF THE ART1. Technical field

[0001] This disclosure relates generally to magnetic memory devices, and more particularly to the effect of a device's shape on its performance. 2. Description of the state of the art

[0002] The crystalline nature of a magnetic memory device's structure, particularly that of the ferromagnetic / MgO tunnel barrier interface of a magnetic tunnel junction (MTJ) device, plays a critical role in device performance. In particular, structural constraints can significantly alter the device's properties for reasons discussed below.

[0003] Magnetic memory devices comprise a stack of layers in which two ferromagnetic layers, typically referred to as a reference layer and a free layer, are separated by a thin, non-magnetic dielectric layer called the barrier layer. In the classical physical system, an electron current passing from one ferromagnetic layer to the other would not be able to pass through the barrier layer, which is non-conductive; but according to quantum mechanics, electrons can "tunnel" through the barrier layer if the right conditions exist in terms of the spin of the tunneling electrons and the magnetization directions of the two ferromagnetic layers on either side of the barrier. The conditions necessary for the electrons to tunnel successfully also depend on the quality of the interfaces between the barrier layer and the ferromagnetic layers.Defects in the interfaces make it difficult to achieve high TMR (tunnel magnetoresistance) values, which measure the ability of electrons to tunnel successfully when the correct magnetization conditions are met. Such defects result from lattice defects between the ferromagnetic layers and the non-magnetic barrier layer and from defects that arise during crystal growth of materials. These undesirable qualities are associated with strain, which in turn causes a reduction in TMR values, as documented, for example, in “Loong, L. [et al.]: Strain-enhanced tunneling magnetoresistance in MgO magnetic tunnel junctions. In: Scientific Reports, Vol. 4, 2014, Number 6505, pp. 1-7”, and also “ZHANG, Hao [et al.]: Tuning the magnetic anisotropy of CoFeB grown on flexible substrates. In: Chinese Phys. B, Vol. 24, 2015, pp. 077501-1-077501-5”.

[0004] Given that the shape of a crystalline layer affects the stresses and strains within the layer, which in turn affect the growth of defects in that layer, controlling the layer shape should allow for appropriate control and even targeted manipulation of these stresses in an MTJ film stack. Therefore, such a shape-control process should enable improvements in device performance, for example, improving the TMR and coercivity of the device. More specifically, the new shape of a device, if properly designed and fabricated, can be expected to reduce the interfacial defect concentration and improve interfacial lattice epitaxy, thus overall improving device performance.

[0005] Attempts to influence device performance through shape control are known in the art, for example, Ahn et al. (US 7,998,758 B2) and Kim et al. (US 9,305,928 B2). However, these attempts do not use the same methods or produce the same effects as described herein. Further prior art is US 2002 / 0 155 627 A1, US 2013 / 0 015 540 A1, DE 10 2015 112 860 A1, US 2004 / 0 188 733 A1. SUMMARY

[0006] A first object of the present disclosure is to provide a method for improving the performance of a layered MTJ device by controlling its shape.

[0007] A second object of the present disclosure is to provide such a method that reduces interface defect concentrations and lattice defects and improves lattice epitaxy, thereby providing a measurable improvement in TMR.

[0008] A third object of the present disclosure is to provide such a method that allows to control and manipulate the shape of a layered device during its manufacture and thereby to individualize its shape.

[0009] A fourth object of the present disclosure is to control the stresses in a layered TMJ film stack or similar device structure by controlling its shape such that the stresses thereby cause crystal defects to migrate to regions of the structure that can subsequently be removed.

[0010] The objectives are achieved by designing and fabricating a structured, layered MTJ device, controlling its shape in such a way that crystal defects, such as vacancies, holes, and dislocations within the stack, are moved to an undesirable weak zone, which can subsequently be removed. The relatively defect-free remaining portion of the device will exhibit higher coercivity and improved TMR values. The new device shape will therefore reduce the interfacial defect concentration and improve interfacial lattice epitaxy, both of which result in improved device performance, as measured, for example, by the improved TMR values. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a schematic illustration of a prior art MTJ device. Fig. Figure 2 shows schematically a dome-shaped bottom electrode for the device in Fig. 1 in accordance with the method of the present disclosure. Fig. Figure 3 schematically shows the effects on the formation of a layered MTJ stack when the stack is placed over the dome-shaped electrode of Fig. 2 is formed. Fig. Figure 4 is a schematic illustration showing the effects of structuring the stack of Fig. 3, so that laterally disposed regions of the stack containing defects resulting from its formation over a dome-shaped electrode are eliminated. Fig. Figure 5 is a schematic illustration of an alternative electrode that is concave instead of convex, as is the dome-shaped electrode. Fig. 6 is a schematic representation analogous to that of Fig. 3, but now shows the effects of forming an MTJ stack over the concave electrode of Fig. 5. Fig. Figure 7 is a schematic illustration showing the effects of structuring the stack of Fig. 6, so that laterally disposed regions of the stack containing defects resulting from its formation over a concave electrode are eliminated. DETAILED DESCRIPTION

[0011] With reference to Fig. Figure 1 is a standard-structured layered magnetic tunnel junction (MTJ) device, as commonly used in a random access memory (RAM) array. Although no specific substrate is required to define the device, for clarity, the device is considered to be formed on a functional substrate, such as a CMOS substrate, which may already contain circuitry and conductive vias to access various elements of the devices in a RAM array.

[0012] The device is formed by first providing a CMOS substrate 10 on which it is to be formed. A top bottom electrode (BE) 20 is deposited on the CMOS substrate so that it properly contacts the vias in this substrate. The bottom electrode 20 is then deposited thereon in sequence through a series of horizontal layers that the MTJ stack will comprise. These layers include a seed layer 30, a pinned magnetic layer 40, a tunnel barrier layer 50, a free magnetic layer 60, and a cap layer 70. A hard mask 80 is deposited on the cap layer. The hard mask is then patterned using a standard photolithography process (not shown), and the film stack is then patterned using the patterned hard mask as a guide. Note that the bottom electrode is also shown patterned and is laterally surrounded by dielectric fill material 90.

[0013] The process steps leading to the formation of the typical MTJ in the state of the art, as described in Fig. 1 and described in detail above, can be summarized in the flowchart of Table 1 below.

[0014] The method of the present disclosure will now be described as related to Fig. 2 - Fig. 4. It is noted in passing that the method is described with respect to an MTJ device, but can be applied to any layered crystalline structure that can be expected to combine different types of defects during growth.

[0015] Similar to the process flow diagram in Fig. 1, the method of the present disclosure begins with a CMOS substrate 10 (although other substrates are also possible), and on this substrate is deposited a bottom electrode layer 20 formed of conductive material. However, the present method differs from the prior art method above in that the electrode is patterned and etched to form a "dome" (i.e., a symmetrically convex) shape 25, as shown in Fig. 2. Note that the "dome" or convex shape here is axisymmetric (about a horizontal axis), so that it is more accurately a cylinder (or a semicircular cylinder if the convex shape has a semicircular cross-section).

[0016] There are several methods by which the electrode can be formed with a surface having a convex, cylindrical shape, or by which an electrode can actually be formed with various surface shapes other than a convex shape, such as a concave shape, which will be discussed below. For example, an initial etching can be performed on a layer of electrode material to create a solid rectangular prism, and then a partial etching (or a series of partial etchings) can be performed, sequentially removing corners of the electrode to give it the rounded surface shape. Alternatively, sputter etching can be performed to create a rounded surface shape. To form a concave surface, isotropic physical etching can be performed.

[0017] Next, with regard to the schematic Fig. 3 is the result of a subsequent deposition process in which a seed layer 35 is first deposited on the convex cylindrical electrode 25, followed by a pinned layer 45, a barrier layer 55, a free layer 65, a cap layer 75, and a hard mask layer 85. These layers will all conform to the shape of the electrode, with each layer sequentially corresponding to the formed layers below it. For clarity, the process steps above can be applied to a typical MTJ structure comprising a seed layer of Ta, Ru, W or NiCr with a range of thicknesses between approximately 5-50 nm (Angstroms), ferromagnetic layers for pinned and free layers formed of CoFeB with a range of thicknesses between approximately 1-10 nm, a tunnel barrier layer of AlOx or MgO with a thickness between approximately 0.5-5 nm and a cap layer of Ta, W or Mg with a range of thicknesses between approximately 1-10 nm.The convex electrode may have a thickness between approximately 10-1000 nm and a width between approximately 50-500 nm.

[0018] Due to the underlying convex shape, as successive layers are formed and their crystalline structures develop, the inevitable defects generated by the crystal growth mechanism, such as holes, vacancies, and dislocations (defects), will migrate away from the apex of the convexity of each successively formed layer and accumulate at the corners, where the underlying curved shape of the electrode becomes a horizontal layer. This is the so-called "weak" region of the structure (see the region 100 surrounded by an ellipse).

[0019] The region of the stack, which includes a small area on each side of the apex of the convex structure, will be relatively defect-free. By controlling the slope (curvature) of the convexity, the film strain can be manipulated, and the lattice defect and interfacial defect concentration can be reduced within a desired range symmetrically located on each side of the apex of the convex structure. It is noted that the width of the convexity that can be considered relatively defect-free can cover most of the total width of the curved region, with the exception of the weak region 100 nm near the corners. In most cases, more than half of the width of the convexity centered around its highest point can be considered defect-free. For example, an electrode having a base width of 200 nm will produce a defect-free device shape of at least 100 nm.

[0020] After the convex structure is patterned to create the vertical stack, which is actually a cylindrical disc, as shown in the schematic Fig. 4, the gaps on each side 110 are filled with a gap-filling dielectric material (not shown), and the top surfaces of the stack and its surrounding dielectric are planarized and polished to remove the mask layer in preparation for further process integration. It is noted that Table 2 below is a process flow diagram briefly describing the sequence of steps leading to the structure in Fig. 4 and are discussed above.

[0021] Next, with regard to the schematic Fig. 5, an alternative embodiment of the present process is shown where the bottom electrode 27 is shaped to have a concave top surface and is otherwise axisymmetric.

[0022] Next, regarding Fig. 6, it is shown that the film stack of the MTJ (or any layered crystalline construction) can be deposited over the concave bottom electrode 27 in the same manner as it was deposited over the convex electrode described previously. Fig. Figure 6 schematically shows the result of a sequential deposition process in which a seed layer 37 is first deposited on the concave electrode 27, followed by a pinned layer 47, a barrier layer 57, a free layer 67, a cap layer 77, and a hard mask layer 87. These layers will all attempt to match the concave shape of the electrode, with each layer sequentially corresponding to the concave-shaped layers below it. Note that the material layers can be formed from the same materials and with the same dimensions as described above for the convex structure.

[0023] Due to the underlying concave shape, as successive layers are formed and their crystalline structures develop, the inevitable defects generated by the crystal growth mechanism, such as holes, vacancies, and dislocations, will migrate away from the bottom point of the concavity of each layer and accumulate at the top corners, where the concavity converges discontinuously with the horizontal layer of the substrate 10. The region of the stack that includes a small area on each side of the concave minimum will be relatively defect-free. This region surrounding the discontinuity, called a "weak" region, is shown to be enclosed within an elliptical region 100. Defects will accumulate at this weak region.By controlling the shape of the electrode 27, the film strain in the successively deposited layers can be manipulated and the lattice defect and the interface defect concentration can be reduced in a certain region.

[0024] After the concave shaped structure is patterned to create the vertical stack, which now includes the defect-free bottom of the concavity, as shown in the schematic Fig. 7, the gaps on each side 110 are filled with a gap-filling dielectric material, and the top surfaces of the stack and its surrounding dielectric are planarized and polished in preparation for further process integration (not shown).

[0025] It is noted that Table 3 below is a process flow diagram that briefly describes the sequence of steps leading to Fig. 7 and are discussed above.

Claims

[1] A method for controlling layer distortion effects during the formation of a magnetic thin film device, the method comprising: Providing a substrate (10) having a flat upper surface; forming an electrode layer (25, 27) on the substrate having a flat upper surface; symmetrically shaping the flat upper surface of the electrode layer to form a curved surface having an axis of symmetry; sequentially depositing a layered device structure over the symmetrically shaped upper surface of the electrode layer, whereby each layer in the layered device structure assumes a shape corresponding to the symmetrically shaped upper surface of the electrode layer with laterally extending portions over the flat upper surface of the substrate; then Removing symmetrical portions of the layered device structure and the electrode layer at a distance from the axis of symmetry, which are arranged laterally on each side of the axis of symmetry, using a hard mask layer (85, 87) as a guide, thereby leaving a remaining portion of the layered device structure, the removed portions of the layered device structure having regions (100) where the curved surfaces meet the surrounding flat surfaces, such that layers in the removed portions have vacancies, crystal defects, holes, and dislocations that have migrated into the regions and collected there during formation of the layered device structure, and such that the remaining portion of the layered device structure is relatively free of vacancies, crystal defects, holes, and dislocations, wherein a first sidewall of the remaining portion of the layered device structure and a second sidewall of a remaining portion of the electrode layer are coplanar and perpendicular to a top surface of the substrate. [2] The method of claim 1, further comprising: Surrounding the remaining portion of the layered device structure with a dielectric fill layer; and Planarizing the remaining section surrounded by the dielectric in preparation for further process integration. [3] The method according to claim 1 or 2, wherein the vacancies, crystal defects, holes and dislocations migrate into the laterally arranged regions as a result of strains induced in layers due to curvature. [4] A method according to any one of the preceding claims, wherein the curved region is convex. [5] A method according to any one of the preceding claims, wherein the electrode layer forms a bottom electrode having a surface curved symmetrically about an axis, wherein the following is successively formed on the bottom electrode: a germ layer (35, 37); a ferromagnetic pinning layer (45, 47); a tunnel junction layer (55, 57); a ferromagnetic free layer (65, 67); a cover layer (75, 77); and which is a hard mask layer. [6] Method according to claim 5, wherein the seed layer is a layer of Ta, Ru, W or NiCr with a range of thicknesses between approximately 5-50 nm, wherein the ferromagnetic free layers and pinning layers are formed of CoFeB with a range of thicknesses between approximately 1-10 nm, wherein the tunnel barrier layer is formed of AlOx or MgO with a thickness between approximately 0.5-5 nm, wherein the capping layer is formed of Ta, W or Mg with a range of thicknesses between about 1-10 nm. [7] The method of claim 5 or 6, wherein the electrode layer has a thickness between about 100-1000 nm and a width between about 50-500 nm. [8] The method of claim 7, wherein two regions symmetrically disposed about the symmetry axis of the layered device structure are removed, whereby a remaining portion of the layered device structure has a width between approximately 50-500 nm. [9] A magnetic layered device comprising strain-free and defect-free crystalline layers and comprising: a bottom electrode (25, 27) on a substrate (10) having an axially symmetric curved upper surface and a flat lower surface; a sequence of layers formed on the curved upper surface of the bottom electrode, the sequence of layers comprising layers having a crystalline structure and corresponding to the curved upper surface of the bottom electrode, wherein each of the sequence of layers is defect-free and arranged symmetrically around the axis of symmetry of the bottom electrode, wherein a first sidewall of the sequence of layers and a second sidewall of the bottom electrode are coplanar and perpendicular to a top surface of the substrate. [10] The device of claim 9, wherein a dielectric fill layer is deposited on each side of the sequence of layers. [11] The device of claim 9 or 10, wherein the curved upper surface of the bottom electrode is convex. [12] The device of claim 9 or 10, wherein the curved upper surface of the bottom electrode is concave. [13] A device according to any one of claims 10 to 12, wherein the layers comprise a TMJ device, the device comprising: the ground electrode; a germ layer (35, 37); a ferromagnetic pinned layer (45, 47); a tunnel barrier layer (55, 57); a ferromagnetic free layer (65, 67); and a covering layer (75, 77). [14] Device according to claim 12, wherein the bottom electrode is a layer of conductive material, the seed layer is a layer of Ta, Ru, W or NiCr with a range of thicknesses between approximately 5-50 nm, wherein the ferromagnetic free layers and pinning layers are formed of CoFeB with a range of thicknesses between approximately 1-10 nm, wherein the tunnel barrier layer is formed of AlOx or MgO of thicknesses between approximately 0.5-5 nm, wherein the capping layer is formed of Ta, W or Mg with a range of thicknesses between approximately 1-10 nm. [15] The device of claim 14, wherein the bottom electrode is formed with a convex axisymmetric upper surface shape. [16] The device of claim 14, wherein the bottom electrode is formed with a concave axisymmetric upper surface shape.

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