A method for performing an analog-to-digital conversion

Abstract

Method for performing an analog-to-digital conversion using a proximity register (SAR) analog-to-digital converter (ADC), comprising: Performing bit trials using a digital-to-analog converter (DAW) circuit of the SAR-ADW to convert a first sample of an analog input signal into a digital N-bit output; Before performing bit trials on a second sample of the analog input signal, compare the digital N-bit output with a first range, the first range being based on the digital N-bit output; If the digital N-bit output lies within the first range, preload M bits of the digital N-bit output from the first sample value onto the DAW circuit; If the digital N-bit output lies outside the first range, preload M bits of the digital N-bit output from the first sample plus an offset to the DAW circuitry; and Performing bit trials on a second sample to determine the remaining bits.

Description

Claim of priority

[0001] The present patent application claims priority from US application no. 16 / 040,140, ​​filed on July 19, 2018, which claims priority from US preliminary patent application no. 62 / 648,225, filed on March 26, 2018, and from US application no. 15 / 700,957, filed on September 11, 2017. Field of invention

[0002] The present disclosure relates to a method for performing an analog-to-digital conversion. General state of the art

[0003] Analog-to-digital converters (ADWs) convert analog input signals into digital codes. One type of ADW is a SAR (Successive Approximation Register). Approximation Register (SAR) ADW. A SAR ADW essentially guesses a digital output code by successively comparing different digital codes to the input signal. This is done using a digital-to-analog converter (DAW). The DAW is set to a specific value, and its analog output is compared to the analog input signal. For example, in a 4-bit DAW, the DAW might be set to 1,0,0,0, which generates an analog signal at the midpoint of the DAW's range. If the analog input signal is above this value, the SAR holds the '1' and moves to the next bit. If the analog input signal is below this value, it sets that bit to '0'. Assuming the analog input signal was above the digital signal, the SAR sets the DAW to 1,1,0,0 and performs the same comparison.Each of these comparisons is called a bit trial, and the process continues until the SAR settles on a digital code that is an approximation of the analog input.

[0004] If the input signal moves slowly, it is likely that the most significant bit (MSB) will not change between conversions. To speed up the process and reduce power consumption, the MSB can be preloaded. Instead of performing bit trials for all bits, bit trials are performed only for the most recent bits. However, as the input signal moves toward the bit boundary, it becomes increasingly likely that the next digital output signal will not share the MSB. If the MSB is preloaded based on the previous digital output, errors can occur.

[0005] US 7,038,609 B1 relates to a SAR converter with improved performance achieved by effectively preloading the most significant bits of the SAR with a value that makes the associated DAC output nearly identical to the signal being converted. A normal SAR conversion is then completed using the unpreloaded SAR bits. The value used to preload the most significant bits of the SAR is preferably derived from a high-speed, low-resolution converter, such as a flash memory. The range of DAC bits used in the normal SAR conversion can be increased to correct errors up to a certain order of magnitude in the high-speed converter. Reducing the power consumption of a SAR system is easily achieved by decreasing the comparator supply voltage.

[0006] US 2015 / 0073228A1 concerns a medical device and an associated procedure that convert an analog signal using a variable number of bits. The medical device includes an analog-to-digital converter (ADC) for receiving an analog signal. The ADC has an end-of-scale range and a total number of bits spanning that range. The ADC converts the analog signal to a digital signal through conversion cycles using a variable number of bits, such that in at least some of the conversion cycles, the ADC uses a modified number of bits spanning a portion of the end-of-scale range that is less than the total number of bits to convert the analog signal.

[0007] WO 2013 / 006026A1 relates to a method for converting an analog signal into a digital signal using a successive approximation analog-to-digital converter. The method allows the SAR-ADC (100) to perform a first iteration of the bit cycle and then store the most significant bits and watch bits in a register of the SAR-ADC (100). The most significant bits are fixed for the subsequent iteration of the bit cycle until a change in the watch bits is detected. Brief presentation of the Revelation

[0008] A method for performing an analog-to-digital conversion using a SAR (Successive Approximation Register) analog-to-digital converter (ADC). A previous digital output is compared to a range based on the first M bits of the preceding digital output. If the preceding digital output lies within this range, the SAR-ADC's analog-to-digital converter (DAW) is preloaded with the first M bits of the preceding digital output before bit trials begin. If the preceding digital output lies outside this range, an offset is applied to the first M bits of the preceding digital output, and the DAW is preloaded based on the M bits and the offset before bit trials are performed. This method reduces the possibility of the next input lying outside a further range defined by the preload.

[0009] In a first aspect, the present disclosure provides a method for performing an analog-to-digital conversion using a SAR (Successive Approximation Register - approximation register) ADW (analog-to-digital converter), comprising: performing bit trials using a digital-to-analog converter (DAW) circuit of the SAR-ADW to convert a first sample of an analog input signal into a digital N-bit output; before performing bit trials on a second sample of the analog input signal, comparing the digital N-bit output with a first range, the first range being based on the digital N-bit output; if the digital N-bit output is within the first range, preloading M bits of the digital N-bit output from the first sample onto the DAW circuit; if the digital N-bit output is outside the first rangeLoading M bits of the digital N-bit output from the first sample plus an offset onto the DAW circuit; performing bit trials on a second sample to determine the remaining bits.

[0010] In a second aspect, the present disclosure provides a SAR-ADW configured to perform bit trials to convert a first sample of an analog input signal into a digital N-bit output, the SAR-ADW comprising: a digital-to-analog converter (DAW) circuit; and a control circuit configured to: compare the digital N-bit output with a first range, the first range being based on the digital N-bit output, before performing bit trials on a second sample of the analog input signal; instruct the DAW to preload M bits of the digital N-bit output from the first sample onto the DAW circuit if the digital N-bit output is within the first range; instruct the DAW to preload M bits of the digital N-bit output from the first sample plus an offset onto the DAW circuit if the digital N-bit output is outside the first range;and instructing the DAW to perform bit trials on a second sample to determine the remaining bits.

[0011] In a third aspect, the present disclosure provides a method for preloading a digital-to-analog converter (DAW) designed for performing bit trials in an analog-to-digital converter (ADW), comprising: determining a sub-range defined by the first M bits of the preceding N-bit digital output of the ADW, wherein the sub-range has a middle section and edge sections; determining the position of the preceding digital output within the sub-range; if the preceding digital output lies within the middle section of the sub-range, preloading the M bits onto the DAW; if the preceding digital output lies within the edge sections, preloading the M bits plus an offset onto the DAW.

[0012] Further aspects of the disclosure are described in the description and defined in the attached claims. Brief description of the drawings

[0013] The revelation will now be described only by way of example and with reference to the accompanying drawings. These show: Fig. 1 a schematic circuit diagram of a SAR-ADW according to an embodiment of the disclosure; Fig. 2 a range defined by preloading M bits; Fig. 3. The way in which the area can be divided into quarters; Fig. 4, how an offset can be added to the summons, according to one embodiment of the disclosure; Fig. 5 a schematic circuit diagram of a binary weighted capacitive DAW according to an embodiment of the disclosure; Fig. 6. A flowchart illustrating the operation of the SAR-ADW. Fig. 1 shows; Fig. 7 a flowchart illustrating another way the SAR-ADW works Fig. 1 shows; Fig. 8 a schematic circuit diagram of a binary-weighted capacitive DAW according to an alternative embodiment of the disclosure; and Fig. Figure 9 shows a graph representing an average number of bit attempts versus an average code load for a variety of SAR-ADWs. Detailed description

[0014] The present disclosure provides an analog-to-digital conversion method in which the preloaded bits can be modified to account for the preceding digital output that is close to the bit boundary. It does this by determining how close the preceding digital output is to the bit boundary. If it is sufficiently far from the boundary, the preload is not modified, and the first bit or bits are preloaded to be the same as the first bit or bits of the preceding digital output. If the preceding digital output is close to the boundary, an offset is added to the first bit or bits to center the preceding digital output in the middle of the region defined by the preload.

[0015] For example, if the preceding digital output is close to the upper limit, half a bit is added to the preload. If the preceding digital output is close to the lower limit, half a bit is subtracted from the preload. This half-bit can be achieved using split capacitors in the DAW, allowing each bit to be set to half its value.

[0016] Fig. Figure 1 is a schematic circuit diagram of a SAR-ADW 100 according to an embodiment of this disclosure. The SAR-ADW 100 comprises a digital-to-analog converter (DAW) 101 and a SAR logic 102. The DAW 101 is a binary-weighted capacitive DAW. As such, the DAW 101 performs sample and hold operations on the analog input signal V. IN through. Furthermore, the DAW 101 features a comparator for comparing sample values ​​of the analog input signal V. INwith an analog signal generated by the DAW during bit trials. The DAW receives V IN The DAW 101 acts as an input and also receives a control signal 103 from the SAR logic 102. The control signal 103 is used to control switches within the DAW 101 to generate different voltage levels based on a digital code generated by the SAR logic 102. The comparator of the DAW 101 generates an output 104, which is used by the SAR logic to determine a digital output signal DouT that approximates the analog input signal V. IN Further details of the structure and functionality of the DAW 101 are presented below.

[0017] The SAR-ADW operates by performing bit trials using the DAW 101 to determine a digital output signal DQUT that approximates the analog input signal V| NThe DAW 101 features a number of binary-weighted capacitors, each capacitor representing a bit (although some bits may have two capacitors, as will be described in more detail below). The SAR logic 102 controls each capacitor using several switches to generate a voltage equivalent to the bit represented by the capacitor. These voltages are then compared to the analog input signal V by the comparator. IN The bits are compared to determine whether they should be set to a '1' or a '0'. The SAR logic 102 does this by starting with the most significant bit (MSB) and moving through the capacitors to the least significant bit (LSB). This process continues until all bit trials are complete and the SAR logic 102 has determined the digital output signal DouT.

[0018] The SAR-ADW 100 is also capable of preloading some bits of the DAW 101 to reduce the SAR-ADW 100's power consumption. For example, based on the N-bit digital output signal DouT of the previous sample value of the analog input signal V| NThe DAW preloads the first M bits before performing bit trials on the remaining bits. In this example, the first bit is the MSB, and the last bit is the LSB. Therefore, the Mth bit is the MSB plus M bits. All bits from the MSB to the Mth bit are preloaded. If the input signal moves slowly, it's likely that the next digital output will share some number of bits with the preceding digital output. Assuming the first M bits are shared between the preceding and next digital outputs, there's no need to perform bit trials on the first M bits. Therefore, preloading these bits saves power.

[0019] To determine the value of the preloaded bits, the SAR-ADW 100 includes a preload control circuit 105. The preload control circuit 105 contains a memory 106 and an offset control 107. The memory 106 receives the N-bit digital output DouT from the SAR logic 102 of the preceding conversion. The memory 106 provides an offset control 107 with the preceding N-bit digital output signal via a connection 108. The offset control 107 determines how many bits should be preloaded and what the value of those bits should be. After this determination, the offset control 107 instructs the SAR logic 102 via connection 109 to preload the necessary bits into the DAW 101. In this example, the number of preloaded bits is fixed for each conversion.

[0020] As will be described in more detail below, after the M bits have been preloaded, the next sample of the analog input signal V must be taken. INpossess a digital value where the first M bits are the same as the preloaded bits. If this is not the case, the circuit will generate an error signal or it will have to clear the preloaded bits and perform bit trials for all bits. While it is likely that the next digital output will share M bits with the preload, there may be cases where this will not be the case. An example is given in Fig. Figure 2 shows that the preloaded bits essentially define a range within which the next signal must fall. In this example, a 6-bit DAW is used. The preceding signal was 101110 (46) and M = 2. As such, the preloaded bits will be 1,0. The possible range for the next digital output is then 100000 (32) to 110000 (48). In this case, the preceding digital output of 101110 (46) is very close to the edge of the range. As such, the first sample of the analog input signal could very easily fall outside this range. In this example, the digital equivalent of the next signal is 110001 (49). In this situation, the SAR-ADW 100 must either ven / verfen the preloaded bits and perform bit trials on all bits, or it will produce an erroneous output. Basically, any given binary number can fall somewhere within a range defined by the first M bits.This means that ven / vendening the first M bits of the preceding digital output as the basis for a range in which the next output must fall is prone to error if the preceding digital output lies at the edge of that range. The offset control 107 determines where the preceding digital output falls within the range defined by the first M bits of that output. If the preceding output falls within a central section of this range, the offset control 107 instructs the SAR logic 102 to preload the first M bits of the preceding digital output into the DAW 101. However, if the preceding digital signal lies at one end of this range, the offset control 107 adds an offset to the preload to shift the range up or down. This shifts the range so that the preceding digital output lies in the center of the range. This increases the probability that the next sample will fall within the central section of the range and reduces the probability of errors.For example, the offset control 107 can determine whether the preceding digital signal lies within the middle quarters of the range or towards the outer quarters of the range. This is in . Fig. 3 shown.

[0021] Fig. Figure 4 shows an example of the offset applied by the offset control 107 based on the value in Fig. 3 previous digital output shown. In this example, to determine whether the previous digital output lies within the middle quarters, the offset controller 107 must determine the upper and lower bounds of the subrange defined by the middle quarters. The offset controller 107 determines the lower bound of the subrange by adding one-quarter of the M-th bit to the M bits and the upper bound by adding three-quarters of the M-th bit to the M bits. For a 6-bit digital signal, where M is 2, the M-th bit is equal to 16. As such, four (000100) are added to the M bits to obtain the lower bound, and twelve (001100) are added to the M bits to obtain the upper bound. In the example above, the M bits are 1.0, and as such, the lower limit is 100100 and the upper limit is 101100. The preceding digital output is 101110, which is in the upper quarter, outside this range.As such, the offset control 107 adds an offset to the preload. In this example, the offset is...

[0022] Offset half the M-th bit; i.e., 0.1 / 2. As such, the preload becomes 1.1 / 2, and the range then becomes 101000 (40) to 111000 (56), as in Fig. Figure 4 shows that the preceding digital output now lies in the middle of the range, and in the example given above, the next analog input signal also lies within the range.

[0023] The half-bit is provided by using a partial capacitor arrangement. Some of the bits of the DAW 101 are represented by two capacitors, each having half the value of a single equivalent capacitor. For example, in a 6-bit DAW, the second bit, representing 16, can have two capacitors equivalent to the third bit, representing 8. As such, using both capacitors, the DAW output is equivalent to 16, whereas using only one, the output is equivalent to 8. This arrangement is referred to in Fig. 5 described in more detail.

[0024] Fig. Figure 5 is a schematic diagram showing the internal components of the DAW 101. As mentioned above, the DAW 101 is a binary-weighted capacitive DAW. As such, it has a number of capacitors that represent the different bits of the digital input code. In the diagram shown... Fig. In the example shown, the DAW is a 6-bit DAW. Each bit of the DAW contains a binary-weighted capacitor or a pair of subcapacitors, each capable of holding a charge equivalent to that bit. Bit 1 is the most significant bit (MSB) and represents a binary equivalent of thirty-two. In this example, bit 1 is represented by a pair of subcapacitors 110A and 100B, each with a value equivalent to sixteen. Bit 2 represents the binary equivalent of sixteen and has a pair of subcapacitors 111A and 111B. Each of these capacitors has a value equivalent to eight. Bit 3 represents the digital equivalent of eight and has a single capacitor 112. Bit 4 has a single capacitor 113, representing a digital 4. Bit 5 has a capacitor 114, representing a digital 2. Bit 6 is the least significant bit (LSB) with a single capacitor 115, which represents a digital 1.Bit 7 is a dummy bit, which is equivalent in value to 115.

[0025] The capacitance of bit 1 is C, and as such, the capacitance of each capacitor is 110A and 110B C / 2. The capacitance of the remaining bits is as follows: Bit 2 = C / 2; Bit 3 = C / 4; Bit 4 = C / 8 Bit 5=0 / 16Bit 6=0 / 32Bit 7=0 / 32

[0026] As such, the value of the remaining capacitors is as follows: 111A=0 / 4 111B=0 / 4 112=0 / 4 113=0 / 8 114=0 / 16 115=0 / 32 116=0 / 32

[0027] The total capacitance CTOTAL for the array is 20. The dummy bit (bit 7) is there to ensure that the sum is 20. The top plates of each capacitor are connected to a common node 117, which is connected to the negative input of comparator 118. The common node 117 is also connected to ground via switch 119. The bottom plate of each capacitor is connected to a respective switch 120A to 120I. Each switch is a three-way switch connected to the analog input signal V. IN , can be connected to a reference voltage VREF and ground. The analog input signal V IN is connected to the switches via another switch 121. The switches are controlled by the control signal 103 from the SAR logic 102.

[0028] The functionality of the SAR-ADW 100 will now be described with reference to Fig. 6 described. In this case, M = 2 and as such the SAR-ADW 100 is configured to preload bits 1 and 2. A first sample of the analog input signal V IN The signal is converted into a digital output signal (S600) without precharging the capacitors of the DAW 101. The process of determining a digital output signal based on the first sample of the analog input signal is described in Fig. Figure 7 shows that to capture the input signal, switch 119 is closed to connect the common terminal 117 to ground. Switch 121 is closed, and each of switches 120A to 1201 is connected to the analog input signal V. IN connected (S700). After detection, switches 121 and 119 are opened and a V IN Equivalent charge is stored on the array of capacitors (S701).

[0029] Switches 120A to 1201 are then connected to ground to cause the common terminal 117 to be at -V| N The bit trials then begin with the most significant bit (MSB) (S702). For this purpose, capacitors 110A and HOB are connected to VREF, resulting in a voltage equivalent to 1 / 2 x VREF at -V| N The values ​​are added (S703). The common voltage at node 117 is therefore -V| N + 1 / 2 × VREF - Comparator 118 then compares the voltage at the common node to zero (S704). Comparator 118 generates a logic 1 if the common voltage is less than 0 (i.e., if V IN greater than 1 / 2 x VREF). Comparator 118 generates a logic 0 if the common voltage is greater than 0 (i.e., if V IN(less than 1 / 2 of VREF). If the comparator generates a logic 1, the SAR logic 102 keeps capacitors 110A and HOB connected to VREF and stores the logic 1 in memory (S705). The SAR logic determines whether any further bits are present (S706). If so, the bit trials then move on to the next bit, and the process continues. In this case, capacitors 111A and 111B are then connected to VREF, adding a voltage equivalent to VREF / 4 to the voltage at the common node 117. If the common voltage is below 0, the comparator generates a logic 1, and if the voltage at common node 117 is above 0, it generates a logic 0. In the case of a logic 0, the SAR logic stores this in memory and connects capacitors 111A and 111B to ground, thus disconnecting the voltage VREF / 4 from node 117 (S707).This process continues until all bit trials have been completed. A digital N-bit word is then stored in memory 106, representing the first sample of the analog input signal V. IN represents (S708).

[0030] The offset control 107 then determines the value of the bits to be preloaded into the DAW 101 for the second conversion. In this example, the SAR-ADW 100 is configured to preload the first two bits of the DAW. As noted above, the first two bits of the DAW have partial capacitors. The value of the first two bits defines a range within which the subsequent bit trials are performed. For example, if the value of the first two bits is 1,0, and if these bits have been preloaded, the range would be 1,0,0,0,0,0 and 1,1,0,0,0,0. This range can be further subdivided into four quarters. The purpose of the offset control 107 is to determine whether the preceding digital output lies within the middle two quarters or within the outer quarters. As such, the offset control 107 defines a subrange equivalent to the inner two quarters.It does this by adding a quarter of the second (M-th) bit to the first two bits to determine the lower bound (S601). Using the in . Fig. 2 and Fig. In the example shown, the lower limit would be 1,0,0,0,0,0 (32) plus 0,0,0,1,0,0 (4), which equals 1,0,0,1,0,0 (36). The offset control 107 then adds three-quarters to the first two bits to determine the upper limit (S602). In this example, the upper limit would be 1,0,0,0,0,0 (32) plus 0,0,1,1,0,0 (12), which equals 1,0,1,1,0,0 (44).

[0031] The offset controller 107 then determines whether the preceding digital output stored in memory 106 lies within the subrange (S603). If it does, the offset controller 107 instructs the SAR logic 102 to preload the first two bits so that they are the same as the preceding digital output (S604). It does this after the second sample of the analog input signal has been loaded onto node 117 by connecting each of the capacitors 110A, 11OB, 111A, and 111B to either VREF or ground, depending on the preceding digital output. In the example given above, the preloaded bits would be 1, 0, and as such, capacitors 110A and 11OB would be connected to VREF, and capacitors 111A and 111B would be connected to ground. The bit trials then continue with bit 3 in the manner described above (S605).

[0032] In this example, the preceding digital output 1,0,1,1,1,0 lies outside the subrange. Therefore, the offset control 107 next determines whether the preceding digital value is in the upper or lower quarter (S606). In this example, it is in the upper quarter, and therefore the SAR logic 102 adds an offset to the first M bits (S607). half a bit to bit 2 (the M-th bit). As such, the precharge will be 1.5. This causes the range within which further bit trials are made to move upwards by half the M-th bit, thus centering the preceding digital output in the middle of the range. This reduces the possibility of the next input being outside the range. In this example, capacitors 110A and HOB are precharged by connecting them to VREF, so that bit 1 is set to '1'; and the digital equivalent of 32. Capacitor 111A is precharged by connecting it to VREF, whereas 111B is not precharged by connecting it to ground, so that bit 2 is set to '1 / 2'; the digital equivalent of 8. The bit trials then continue with bit 3 in the manner described above (S605).If the preceding digital output was in the lower quarter, the offset control 107 would instruct the SAR logic 107 to subtract half a bit (S608). As such, the precharge will be 1 / 2. In this alternative, capacitors 110A and 111A are precharged by connecting them to VREF, so that bit 1 is set to '1 / 2'; the digital equivalent of 16. Capacitors HOB and 1HB are not precharged by connecting them to ground, thus setting bit 2 to '1 / 2'; the digital equivalent of 8. As such, the total precharge is 24. The bit trials then proceed with bit 3 in the manner described above (S605). In the examples above, the DAW is a 6-bit DAW, and the number of preloaded bits is 2. It is understood that the revelation can be applied to DAWs with different numbers of bits and with different values ​​of M.

[0033] The above example is given in the context of a single-beat input. The disclosure can also be applied to differential SAR-ADWs. An example of a differential DAW 800 used to implement the present disclosure is given in Fig. 8 shown. The arrangement of Fig. 8 is similar to the one in Fig. 5 shown, but there are two binary weighted capacitor arrays; one for each input.

[0034] In the Fig. In the example shown, the DAW is a 6-bit differential DAW. Each input is connected to a different array of capacitors. A first array 801A is connected to a first analog input V. INPA second array 801B is connected to a second analog input VINM. In this example, bit 1 of the first array is represented by a pair of subcapacitors 802A and 802B, each with a value equivalent to sixteen. Bit 2 of the first array represents the binary equivalent of 16 and contains a pair of subcapacitors 803A and 803B, each with a value equivalent to eight. Bit 3 represents the digital equivalent of 8 and has a single capacitor 804. Bit 4 has a single capacitor 805, representing a digital 4. Bit 5 has a capacitor 806, representing a digital 2. Bit 6 is the least significant bit (LSB) with a single capacitor 807, representing a digital 1. Bit 7 is a dummy bit that has a capacitor 808, which is equivalent in value to 807.

[0035] The second array contains a set of capacitors that mirror the capacitors of the first array. In this example, bit 1 of the second array is represented by a pair of subcapacitors 809A and 809B, each with a value equivalent to sixteen. Bit 2 of the second array represents the binary equivalent of 16 and contains a pair of subcapacitors 810A and 810B, each with a value equivalent to eight. Bit 3 represents the digital equivalent of 8 and contains a single capacitor 811. Bit 4 has a single capacitor 812, representing a digital 4. Bit 5 has a capacitor 813, representing a digital 2. Bit 6 is the least significant bit (LSB) with a single capacitor 814, representing a digital 1. Bit 7 is a dummy bit that has a capacitor 815, which is equivalent in value to 814.

[0036] The capacitance of bit 1 is C, and as such, the capacitance of each capacitor 802A, 802B, 809A, and 809B is C / 2. The capacitance of the remaining bits is as follows: Bit 2=C / 2 Bit 3=C / 4 Bit 4=C / 8 Bit 5=0 / 16 Bit 6=0 / 32 Bit 7=0 / 32

[0037] As such, the value of the remaining capacitors is as follows: 803A = C / 4 803B=C / 4 810A=C / 4 810B=C / 4 804=C / 4 811=C / 4 805=C / 8 812=C / 8 806=C / 16 813=C / 16 807=C / 32 814=C / 32 808=C / 32 815=C / 32

[0038] The total capacity CTOTAL for the array is 2C. The dummy bit (bit 7) is there to ensure that the sum is 2C.

[0039] The top plates of each of the capacitors in the first array are connected to respective switches 816A to 8161. Each switch is a three-way switch connected to the analog input signal V. INP , can be connected to a reference voltage VREF and ground. The analog input signal V INP is connected to the switches via another switch 817. The lower plate of each of the capacitors is connected to a common node 818, which is connected to the positive input of the comparator 819. The common node 819 is also connected to ground via a switch 820.

[0040] The lower plates of each of the capacitors in the second array are connected to respective switches 821A to 821I. Each switch is a three-way switch that can be connected to the analog input signal VINM, a reference voltage VREF, and ground. The analog input signal V INMis connected to the switches via another switch 822. The top plate of each of the capacitors is connected to a common node 823, which is connected to the negative input of comparator 819. The common node 823 is also connected to ground via switch 824.

[0041] The switches are controlled by the control signal from the SAR logic, as in the one in Fig. The 5 DAWs shown. Apart from the structural difference mentioned above, the one in Fig. The 8 DAWs shown function in the same way as the SAR-ADW 100.

[0042] Fig.Figure 9 is a graph showing the mean number of bit attempts versus mean code change for four different 10-bit SAR-ADWs. Regardless of the code change per sample, a conventional SAR always performs 10 bit attempts, as would be expected. An LSB-first SAR performs more than 10 bit attempts as the mean code change increases. An adaptive SAR without the offset stabilizes at approximately 10 bit attempts per sample as the mean code change increases. The SAR-ADW of the present disclosure also stabilizes at approximately 10 bit attempts per sample using the offset, with the bit performing better than an adaptive SAR without the offset at lower mean code changes.

[0043] It is understood that this revelation can be applied to DAWs with arrangements other than those described above.

Claims

[1] A method for performing analog-to-digital conversion using an approximate register (SAR) analog-to-digital converter (ADC), comprising: performing bit trials using a digital-to-analog converter (DAC) circuit of the SAR-ADC to convert a first sample of an analog input signal into an N-bit digital output; before performing bit trials on a second sample of the analog input signal, comparing the N-bit digital output with a first range, the first range being based on the N-bit digital output; if the N-bit digital output is within the first range, preloading M bits of the N-bit digital output from the first sample to the DAC circuit; if the N-bit digital output is outside the first range, precharging M bits of the N-bit digital output from the first sample plus an offset to the DAC circuit; and Perform bit trials on a second sample to determine the remaining bits. [2] The method of claim 1, wherein the N-bit digital output defines a second range and the N-bit digital output is within the second range and the first range is a sub-range of the second range. [3] The method of claim 2, wherein the second region has a width equal to the M-th bit of the N-bit digital output. [4] The method of claim 3, wherein a lower limit of the second range is the value of the most significant bit (MSB) of the M-th bit of the N-bit digital output and an upper limit is the value of the lower limit plus the value of the M-th bit. [5] The method of claim 4, wherein the first region has a width equal to the Mth + 1 bit of the N-bit digital output. [6] The method of claim 1, wherein the offset is half of the M-th bit. [7] The method of claim 6, wherein if the N-bit digital output is above an upper limit of the first range, half a bit is added to the M-th bit, and if the N-bit digital output is below the lower limit, half a bit is subtracted from the M-th bit. [8] The method of claim 7, wherein the DAC comprises at least one capacitor per bit and for the MSB to the M-th bit of the DAC comprises a pair of capacitors, each having half the value of a single capacitor. [9] The method of claim 8, wherein half a bit is added using a pair of capacitors for the M-th bit. [10] An approximate register (SAR) analog-to-digital converter (ADC) configured to perform bit trials to convert a first sample of an analog input signal into an N-bit digital output, the SAR ADC comprising: a digital-to-analog converter (DAC) circuit; and a control circuit configured to: Comparing the N-bit digital output to a first range, the first range being based on the N-bit digital output, before performing bit trials on a second sample of the analog input signal; instructing the DAC to preload M bits of the N-bit digital output from the first sample onto the DAC circuit if the N-bit digital output is within the first range; instructing the DAC to preload M bits of the N-bit digital output from the first sample plus an offset onto the DAC circuit if the N-bit digital output is outside the first range; and Instruct the DAC to perform bit trials on a second sample to determine the remaining bits. [11] SAR-ADW according to claim 10, wherein the DAC comprises: an array of binary-weighted capacitors, where one or more of the binary-weighted capacitors corresponds to each bit of the DAC. [12] The SAR-ADC of claim 11, wherein one or more of the bits of the DAC have a corresponding pair of binary weighted capacitors in the array, and each of the pair of capacitors is configured to produce an analog output equivalent to half a bit. [13] The SAR-ADC of claim 12, wherein each pair of binary weighted capacitors in the array is further configured to generate an analog output equivalent to the corresponding bit of the DAC. [14] The SAR-ADC of claim 12, wherein the half-bit value is achieved by charging one of the capacitors and the full-bit value is achieved by charging both capacitors. [15] The SAR-ADC of claim 10, wherein the offset is half of the M-th bit. [16] SAR-ADW according to claim 10, wherein the M-th bit is counted from the most significant bit (MSB). [17] A method for precharging a digital-to-analog converter (DAC) designed to perform bit tests in an analog-to-digital converter (ADC), comprising: determining a sub-range defined by the first M bits of the preceding N-bit digital output of the ADC, the sub-range having a central portion and edge portions; Determining the position of the previous digital output within the subrange; if the previous digital output is within the middle section of the subrange, preload the M bits to the DAC; if the previous digital output is within the margins, preload the M bits plus an offset on the DAC. [18] The method of claim 17, wherein the offset is a half bit. [19] The method of claim 17, wherein the central portion is the middle two-quarters of the region and the edge portions are the outer two-quarters of the sub-region. [20] The method of claim 17, wherein when the previous digital output is in a top margin, a positive offset is added to the precharge, and when the previous digital output is in a bottom margin, a negative offset is added to the precharge.

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