CHIP RESISTANCE

Abstract

Chip resistor comprising: • a substrate (1) having a front surface (11) and a back surface (12) oriented in opposite directions along a thickness direction, and a side surface (13) located between the front surface (11) and the back surface (12); • a resistive layer (2) located on the front surface (11); • a first conductive layer (3) located on the front surface (11) and electrically connected to the resistive layer (2); • an insulating layer (9) covering the resistive layer (2) and the first conductive layer (3) and having a first edge (93) located on the first conductive layer (3); • a second conductive layer (4) covering the first conductive layer (3) and the insulating layer (9) while spanning the first edge (93), and having a second edge (41) has, which is arranged on the insulating layer (9);• a third conductive layer (5) covering the second conductive layer (4) and the insulating layer (9) while spanning the second edge (41), and having a third edge (51) arranged on the second conductive layer (4); and • a fourth conductive layer (6) covering the second conductive layer (4) and the third conductive layer (5) while spanning the third edge (51), wherein the bond strength between the third conductive layer (5) and the fourth conductive layer (6) is greater than the bond strength between the second conductive layer (4) and the fourth conductive layer (6), and wherein the third edge (51) is arranged between the first edge (93) and the second edge (41).

Description

TECHNICAL FIELDThe present disclosure relates to a chip resistor.PRIOR ARTAn example of a conventional chip resistor is provided with a substrate, a resistor layer, a conductive layer, a plating layer, and an insulating layer. The resistance layer is formed on the front surface of the substrate. The conductive layer is electrically connected to the resistor layer by contacting the resistor layer. The insulating layer covers the entire resistor layer and a part of the conductive layer. The plating layer covers a portion of the conductive layer exposed to the insulating layer.Further chip resistors are known from the documents U.S. Pat. No. 2017) / 0 202 089 A1, U.S. Pat. No. 2016 / 0 247 610 A1, JP H07-302 510 A and U.S. Pat. No. 2004 / 0 027 234 A1.SUMMARY OF THE INVENTIONAccording to the present disclosure, there is provided a chip resistor having the features of claim 1. The chip resistor includes a substrate, a resistor layer, a first conductive layer, an insulating layer, a second conductive layer, a third conductive layer, and a fourth conductive layer. The substrate has a front surface and a back surface facing opposite directions to each other in a thickness direction, and also has a side surface disposed between the front surface and the back surface. The resistance layer is disposed on the front surface. The first conductive layer is disposed on the front surface, and is electrically connected to the resistance layer. The insulating layer covers the resistor layer and the first conductive layer and has a first edge disposed on the first conductive layer. The second conductive layer covers the first conductive layer and the insulating layer while crossing over the first edge, and has a second edge disposed on the insulating layer. The third conductive layer covers the second conductive layer and the insulating layer while spanning the second edge, and has a third edge disposed on the second conductive layer. The fourth conductive layer covers the second conductive layer and the third conductive layer while spanning the third edge. The bonding strength between the third conductive layer and the fourth conductive layer is stronger than the bonding strength between the second conductive layer and the fourth conductive layer.Preferred embodiments are defined in the dependent claims.Other features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGFIG. 1 is a main-part plan view showing a chip resistor according to a first embodiment of the present disclosure. FIG. 2 is a main-part bottom view showing the chip resistor according to a first embodiment of the present disclosure. FIG. 3 is a cross-sectional view taken along a line III-III in FIG. 1. FIG. 4 is an enlarged main-part cross-sectional view showing the chip resistor according to a first embodiment of the present disclosure. FIG. 5 is an enlarged main-part cross-sectional view showing the chip resistor according to a first embodiment of the present disclosure. FIG. 6 is an enlarged main-part cross-sectional view showing the chip resistor according to a first embodiment of the present disclosure. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 1. FIG. 8 is an enlarged main-part cross-sectional view showing a chip resistor according to a second embodiment of the present disclosure. FIG. 9 is a main-part plan view showing a chip resistor according to a third embodiment of the present disclosure. FIG. 10 is a cross-sectional view taken along a line X-X in FIG. 9. FIG. 11 is a cross-sectional view taken along a line XI-XI in FIG. 9. FIG. 12 is a cross-sectional view taken along a line XII-XII in FIG. 9. FIG. 13 is an enlarged main-part cross-sectional view showing a chip resistor according to a third embodiment of the present disclosure. FIG. 14 is a plan view showing a manufacturing process of the chip resistor according to a third embodiment of the present disclosure. FIG. 15 is a cross-sectional view taken along a line XV-XV in FIG. 14. FIG. 16 is a cross-sectional view taken along a line XVI-XVI in FIG. 14. FIG. 17 is an enlarged main-part cross-sectional view showing a manufacturing process of the chip resistor according to a third embodiment of the present disclosure. FIG. 18 is a main-part plan view showing a chip resistor according to a fourth embodiment of the present disclosure. FIG. 19 is a cross-sectional view taken along a line XIX-XIX in FIG. 18. FIG. 20 is a cross-sectional view taken along a line XX-XX in FIG. 18. FIG. 21 is a cross-sectional view taken along a line XXI-XXI in FIG. 18. FIG. 22 is a cross-sectional view taken along a line XXII-XXII in FIG. 18. FIG. 23 is a cross-sectional view taken along a line XXIII-XXIII in FIG. 18. FIG. 24 is a cross-sectional view showing a chip resistor according to a fifth embodiment of the present disclosure. FIG. 25 is an enlarged main-part cross-sectional view showing the chip resistor according to a fifth embodiment of the present disclosure. FIG. 26 is an enlarged main-part cross-sectional view showing a manufacturing process of the chip resistor according to a fifth embodiment of the present disclosure.MODE FOR CARRYING OUT THE INVENTIONHereinafter, modes for implementing the present disclosure will be described with reference to the accompanying drawings.Terms such as "first", "second", and "third" in the present disclosure are used only as names, and are not intended to assign an order to these terms.FIGS. 1 to 7 show a chip resistor according to a first embodiment of the present disclosure. A chip resistor A 1 of this embodiment includes a substrate 1, a resistor layer 2, a pair of first conductive layers 3, a pair of second conductive layers 4, a pair of third conductive layers 5, a pair of fourth conductive layers 6, a pair of fifth conductive layers 7, and an insulating layer 9.FIG. 1 is a plan view showing the chip resistor A 1. FIG. 2 is a bottom view showing the chip resistor A 1. FIG. 3 is a cross-sectional view taken along a line III-III in FIG. 1, FIG. 4 is an enlarged main-part cross-sectional view showing the chip resistor A 1. FIG. 5 is an enlarged main-part cross-sectional view showing the chip resistor A 1. FIG. 6 is an enlarged main-part cross-sectional view showing the chip resistor A 1. FIG. 7 is a cross-sectional view taken along a line VII-VII in FIG. 1 Note that, in FIG. 1, components other than the substrate 1, the resistor layer 2, and the first conductive layers 3 are omitted, and in FIG. 2, components other than the substrate 1 and the sixth conductive layers 8 are omitted. In these figures, the thickness direction of the substrate 1 of the chip resistor A1 is the z direction. The x direction and the y direction are directions that are perpendicular to the z direction, respectively. A view in the z-direction may be conveniently referred to as a top view.The substrate 1 supports the resistor layer 2, the pair of first conductive layers 3, the pair of second conductive layers 4, the pair of third conductive layers 5, the pair of fourth conductive layers 6, the pair of fifth conductive layers 7, and the insulating layer 9. In the example shown, the substrate 1 has a substantially rectangular parallelepiped shape. Further, in the example shown, the substrate 1 has a long rectangular shape, wherein the x direction is the longitudinal direction and wherein the y direction is the transverse direction. At least the surface of the substrate 1 has insulating properties, and the substrate 1 is conventionally formed of an insulating material. Examples of the material of the substrate 1 include ceramics such as Al 2 O 3 and AlN. The size of the substrate 1 is not particularly limited, and in one example, the dimensions of the substrate 1 in the x direction and the y direction are about 0.2 mm to 4 mm, and the dimensions in the z direction are about 0.1 to 0.8 mm.The front surface 11 and the back surface 12 are surfaces facing each other in the z direction and facing in opposite directions in the z direction, respectively. The pair of side surfaces 13 face opposite directions to each other in the x direction, and each surface of the pair of side surfaces 13 is disposed between the front surface 11 and the back surface 12. In the example shown, the substrate 1 has a plurality of inclined surfaces 15. The inclined surfaces 15 are respectively disposed between the side surface 13 and the front surface 11 or the back surface 12. The inclined surfaces 15 are inclined with respect to the z direction. The inclined surfaces 15 are formed, for example, where a part of a recess provided to divide a substrate material for forming the substrate 1 remains.The resistor layer 2 is disposed on the front surface 11 of the substrate 1, and is a portion defining the resistance value of the chip resistor A 1. The shape of the resistor layer 2 is not particularly limited, and in the example shown, is a substantially rectangular shape having two pairs of sides in the x direction and the y direction, respectively, as shown in FIG. 1. In the example shown, the resistor layer 2 is spaced inwardly from the outer edges of the substrate 1 when viewed in the z-direction.The material of the resistor layer 2 is not particularly limited, and a material that is possible to realize a resistance value required for the chip resistor A 1 may be suitably used. The material of the resistor layer 2 is, for example, a material including RuO 2 or an Ag-Pd alloy, and this material may further include glass. The thickness of the resistor layer 2 is not particularly limited, and is, for example, 5 μm to 10 μm, and preferably 7 μm to 8 μm. Such a resistor layer 2 is formed, for example, by printing a paste containing metal particles of RuO 2 or an Ag-Pd alloy or the like and frit glass on a substrate material serving as the material of the substrate 1 using a screen ("silk screen") or the like, and firing ("baking") this paste.The pair of first conductive layers 3 are disposed on the front surface 11 and are provided on both sides of the resistor layer 2 in the x direction with the resistor layer 2 interposed therebetween. The first conductive layers 3 are electrically connected to the resistor layer 2. As shown in FIG. 4, the resistance layer 2 in the example shown has a covering portion 21. The covering portion 21 is a portion covering the first conductive layers 3. Thus, the first conductive layers 3 are electrically connected to the resistor layer 2. As shown in FIG. 1, the first conductive layers 3 in the example shown have a substantially rectangular shape when viewed in the z direction. Further, the first conductive layers 3 reach the side surfaces 13 when viewed in the z direction. The first conductive layers 3 are separated from the edge of the substrate 1 in the y direction. In the example shown, the first conductive layers 3 have a cover inclined portion 31 and a curved surface portion 32. the cover inclined portion 31 is a portion covering the inclined surfaces 15 of the substrate 1. The curved surface portion 32 is a portion forming a convex curved surface disposed above the cover inclined portion 31 in the z direction.The material of the first conductive layers 3 is not particularly limited, and a material that is suitably conductive with the resistor layer 2 and has lower electrical resistance than the material of the resistor layer 2 may be selected. examples of the material of the first conductive layers 3 include a mixed material containing Ag and glass. The thickness of the first conductive layers 3 is not particularly limited, and is, for example. 5 to 12 μm, and preferably 7 to 10 μm. Such first conductive layers 3 are formed, for example, by printing a paste containing Ag particles and frit glass on a substrate material serving as the material of the substrate 1 using a screen or the like and firing this paste.The insulating layer 9 covers the resistor layer 2 and the pair of first conductive layers 3 to protect them. In the example shown, the insulating layer 9 covers the entire resistor layer 2 and a part of each of the pair of first conductive layers 3. The first edge 93 is an edge disposed on the first conductive layer 3 and extending in the y direction. As shown in FIG. 7, in the example shown, the insulating layer 9 does not reach the edge of the substrate 1 in the y direction, but a configuration in which the insulating layer 9 reaches the edge of the substrate 1 in the y direction may be adopted.The insulating layer 9 is formed of a single layer or a plurality of layers of insulating material. Examples of the material of the insulating layer 9 include a glass layer and an epoxy resin. The thickness of the insulating layer 9 is not particularly limited, and is, for example. 15 to 40 μm. As shown in FIG. 4, in the example shown, the insulating layer 9 has a shape having a portion where the thickness in the z direction gradually decreases from the center in the x direction toward the first edge 93. Such an insulating layer 9 is formed by, for example, printing a glass paste on the resistor layer 2 and the first conductive layers 3 using a screen or the like and firing this paste.The pair of second conductive layers 4 are provided spaced apart from each other in the x direction. The second conductive layers 4 cover the first conductive layers 3 and the insulating layer 9 while crossing the first edge 93 of the insulating layer 9. In the example shown, the second conductive layers 4 cover a portion of the first conductive layers 3 exposed to the first conductive layers 3 and the insulating layer 9, respectively, and a part of the insulating layer 9. The second conductive layers 4 have a second edge 41. The second edge 41 is disposed on the insulating layer 9 and extends in the y direction. The second edge 41 is disposed closer to the center in the x direction than the first edge 93.The second conductive layers 4 have a second bulging portion 42 and a curved surface portion 44. The second bulging portion 42 is a portion having a shape bulging away from the substrate 1 in the z direction, and is disposed substantially closer to the side surface 13 of the substrate 1 than the first edge 93 in the x direction. A concave portion 45 is an end portion in the x direction of the second bulging portion 42 and is a concave portion disposed substantially on the first edge 93. The curved surface portion 44 is a portion adjacent to the curved surface portion 32 of the first conductive layers 3 upward in the z direction, and is a portion formed of a convexly curved surface.The material of the second conductive layers 4 is not particularly limited, and a material that is suitably conductive with the first conductive layers 3 and has lower resistivity ("resistivity") than the material of the resistor layer 2 may be selected. examples of the material of the second conductive layers 4 include a mixed material containing conductive particles and a resin. The conductive particles are, for example. Carbon particles. In addition, the shape of the carbon particles is not particularly limited, and examples include a spherical shape and a flake-like shape. As shown in FIGS. 5 and 6, the second conductive layers 4 contain flake-like carbon particles in the example shown. These carbon particles have a dimension of about 5 to 15 μm in the longitudinal direction perpendicular to the thickness direction, for example, and a dimension of about 2 to 5 μm in the transverse direction. Further, since the second conductive layers 4 contain flake-like carbon particles, the surface of the second conductive layers 4 has an uneven shape. The thickness of the second conductive layers 4 is not particularly limited, and is, for example. 10 to 25 μm, and preferably 12 to 15 μm. Such second conductive layers 4 are formed, for example, by printing a paste containing flake-like carbon particles and mainly containing a flexible epoxy resin on the first conductive layers 3 and the insulating layer 9 using a screen or the like and firing this paste.The pair of third conductive layers 5 are provided spaced apart from each other in the x direction. The third conductive layers 5 cover the second conductive layers 4 and the insulating layer 9 while spanning over the second edge 41 of the second conductive layers 4. In the example shown, the third conductive layers 5 cover a part of the second conductive layers 4 and a part of the insulating layer 9. the third conductive layers 5 have a third edge 51 and a fourth edge 54. the third edge 51 is arranged on the second conductive layers 4 and extends in the y-direction. The fourth edge 54 is disposed on the insulating layer 9 and extends in the y direction. In the example shown, the third edge 51 is arranged in the x-direction between the first edge 93 of the insulating layer 9 and the second edge 41 of the second conductive layers 4.The third conductive layers 5 have a third bulging portion 52, and in the example shown, the third conductive layers 5 are formed of the third bulging portion 52. The third bulging portion 52 is a portion having a shape bulging away from the substrate 1 in the z direction. A tip 53 is a portion of the third bulging portion 52 that is farthest from the substrate 1 in the z direction. In the example shown, the tip 53 is arranged farther from the substrate 1 than the tip 43 in the z direction. The thickness of the portion of the third bulging portion 52 including the tip 53 is greater than the thickness of the portion of the second conductive layers 4 covered by the third bulging portion 52.The material of the third conductive layers 5 is not particularly limited, and a material that is suitably conductive with the second conductive layers 4 and has a lower electric resistance than the material of the resistor layer 2 may be selected. examples of the material of the third conductive layers 5 include a mixed material containing conductive particles and a resin. The conductive particles are, for example. Ag particles. In addition, the shape of the Ag particles is not particularly limited, and examples include a spherical shape and a flake-like shape. As shown in FIG. 6, the third conductive layers 5 in the example shown include a resin 501 and flake-like metal particles 502. These metal particles 502 have, for example, a dimension in the longitudinal direction perpendicular to the thickness direction of about 5 to 15 μm and a dimension in the transverse direction of about 2 to 5 μm, and in the example shown, these dimensions are smaller than those of the carbon particles 402 of the second conductive layers 4. Since the third conductive layers 5 further contain the flake-like metal particles 502, the surface of the third conductive layers 5 has an uneven shape. Such third conductive layers 5 are formed, for example, by printing a paste containing flake-like Ag particles and mainly containing a flexible epoxy resin on the second conductive layers 4 and the insulating layer 9 using a screen or the like and firing this paste.The pair of sixth conductive layers 8 are disposed on the back surface 12 and are provided on both sides in the x direction. As shown in FIG. 2, the sixth conductive layers 8 in the example shown have a substantially rectangular shape when viewed in the z direction. In addition, the sixth conductive layers 8 reach the side surfaces 13 when viewed in the z direction. The sixth conductive layers 8 are spaced apart from the edge of the substrate 1 in the y direction. In the example shown, the sixth conductive layers 8 have an inclined covering portion 81. the inclined covering portion 81 is a portion covering the inclined surfaces 15 of the substrate 1.The material of the sixth conductive layers 8 is not particularly limited, and a material having lower electrical resistance than the material of the resistor layer 2 may be selected. examples of the material of the sixth conductive layers 8 include a mixed material containing Ag and glass. The thickness of the sixth conductive layers 8 is not particularly limited, and is, for example. 5 to 12 μm, and preferably 7 to 10 μm. Such sixth conductive layers 8 are formed, for example, by printing a paste containing Ag particles and frit glass on a substrate material serving as the material of the substrate 1 using a screen or the like and firing this paste.The pair of fourth conductive layers 6 are provided on both sides in the x direction. As shown in FIG. 3, the fourth conductive layers 6 have a front surface portion 61, a rear surface portion 62, and a side surface portion 63. the front surface portion 61 is a portion supported by the front surface 11 via the first conductive layers 3, the second conductive layers 4, the third conductive layers 5, the insulating layer 9, and the like. The back surface portion 62 is a portion supported by the back surface 12 via the sixth conductive layers 8, and covers the sixth conductive layers 8.As shown in FIG. 4, the front surface portion 61 of the fourth conductive layers 6 covers the second conductive layers 4 and the third conductive layers 5, and covers the second conductive layers 4 and the third conductive layers 5 as a whole in the examples shown. Consequently, the fourth edge 54 of the third conductive layers 5 is covered by the fourth conductive layers 6. Further, a part of the front surface portion 61 of the fourth conductive layers 6 is disposed on the insulating layer 9.The fourth conductive layers 6 are formed of a single metal layer or a plurality of metal layers. Examples of a metal layer include a metal layer formed by a thin film forming technique such as sputtering and a metal layer formed by plating. In the example shown, the metal layers include an underlayer formed by sputtering (not shown) and a plating layer (not shown) formed on the underlayer. The material of the fourth conductive layers 6 is not particularly limited, and examples of the material include metals such as Ni and Cr or alloys including these materials. The thickness of the fourth conductive layers 6 is, for example. 3 μm to 7 μm. The fourth conductive layers 6 have a shape matching the surface shape of the substrate 1, the second conductive layers 4, the third conductive layers 5, and the sixth conductive layers 8.The material of the second conductive layers 4, the third conductive layers 5, and the fourth conductive layers 6 may be selected such that the bonding strength between the third conductive layers 5 and the fourth conductive layers 6 is stronger than the bonding strength between the second conductive layers 4 and the fourth conductive layers 6.The pair of fifth conductive layers 7 are provided on both sides in the x direction. As shown in FIG. 3, the fifth conductive layers 7 have a front surface portion 71, a rear surface portion 72, and a side surface portion 73. the front surface portion 71 is a portion supported by the front surface 11 via the first conductive layer 3, the second conductive layers 4, the third conductive layers 5, the fourth conductive layers 6, the insulating layer 9, and the like. The back surface portion 72 is a portion supported by the back surface 12 via the fourth conductive layers 6 and the sixth conductive layers 8, and covers the back surface portion 62 of the fourth conductive layers 6. the side surface portion 73 is a portion supported by the side surfaces 13 via the fourth conductive layers 6, and covers the side surface portion 63 of the fourth conductive layers 6.As shown in FIG. 4, the front surface portion 71 of the fifth conductive layers 7 covers the front surface portion 61 of the fourth conductive layers 6 and covers the entire front surface portion 61 in the example shown.The fifth conductive layers 7 are formed of a single metal layer or a plurality of metal layers. A metal layer is, for example, a metal such as Sn or an alloy containing this metal. The thickness of the fourth conductive layers 6 is, for example. 3 μm to 7 μm. The fifth conductive layers 7 are formed by depositing Sn, for example, by barrel plating.The fifth conductive layers 7 have a shape that matches the surface shape of the fourth conductive layers 6. As shown in FIG. 4, the front surface portion 71 of the fifth conductive layers 7 has a tip 75, a tip 76, and a concave portion 77. The tip 75 is a portion substantially located on the tip 43 of the second bulging portion 42 of the second conductive layers 4. The tip 76 is a portion substantially located on the tip 53 of the third bulging portion 52 of the third conductive layers 5. The concave portion 77 is a portion substantially disposed on the first edge 93 of the insulating layer 9 and the concave portion 45 of the second conductive layers 4. That is, the concave portion 77 is disposed between the tip 75 and the tip 76 in the x direction. The concave portion 77 is a portion recessed between the tips 75 and 76 in the z direction. The tip 75 is a portion that is located between the concave portion 77 and the side surface 13 furthest from the substrate 1 in the z direction. The tip 76 is a portion located on the center in the x direction relative to the concave portion 77 farthest from the substrate 1 in the z direction. In the example shown, the tip 76 is arranged farther from the substrate 1 than the tip 75 in the z direction, the tip 75 is arranged closer to the substrate 1 than the tip 75 (or 53) and the tip 76 in the z direction, and the tip 76 is arranged at a position overlapping the insulating layer 9 when viewed in the z direction.Next, an operation of the chip resistor A 1 will be described.According to the present embodiment, as shown in FIG. 4, the second edge 41 of the second conductive layer 4 is covered by the third conductive layers 5. It is thus possible to suppress entry of external gas, liquid, and the like, which may exist depending on the use environment, into the first conductive layers 3 from the second edge 41, which is the boundary between the second conductive layers 4 and the insulating layer 9. It is thus possible to suppress a change or the like of the first conductive layers 3, and it is possible to avoid poor conductivity or the like of the first conductive layers 3. Also, the bonding strength of the third conductive layers 5 to the fourth conductive layers 6 is stronger than the bonding strength of the second conductive layers 4 to the fourth conductive layers 6, and therefore it is possible to suppress a portion of the fourth conductive layers 6 overlapping the second edge 41 from being peeled off (peeled off) or from a crack (crack) being generated at that location. Consequently, it is possible to suppress entry of external gas, liquid, and the like. Therefore, it is possible to suppress deterioration of the function of the chip resistor A 1. Specifically, in the present embodiment, the first conductive layers 3 include Ag. Therefore, there is a concern that the first conductive layers 3 become insulating when the Ag is sulfurized ("sulfurized") by the entry of external gas, liquid, or the like. According to the present embodiment, it is possible to suppress sulfurization of the first conductive layers 3 and avoid insulation of the first conductive layers 3.Referring to FIGS. 5 and 6, the second conductive layers 4 include the flake-like carbon particles 402. As a result, the surface of the second conductive layers 4 can be made into an uneven shape, and the bonding strength between the third conductive layers 5 and the fourth conductive layers 6 can be increased. Further, the carbon particles 402 are suitable for increasing the area exposed on the surface of the second conductive layers 4, and it is possible to more reliably provide electrical connectivity of the second conductive layers 4 with the third conductive layers 5 and the fourth conductive layers 6. Also, exposing the carbon particles 402 is preferable for enhancing the bonding strength with the fourth conductive layers 6.As shown in FIG. 6, the third conductive layers 5 include metal particles 502 containing flake-like Ag. Accordingly, it is possible to increase the bonding strength between the third conductive layers 5 and the fourth conductive layers 6. Further, since the metal particles 502 are easily exposed to the resin 501, the metal particles 502 and the carbon particles 402 of the second conductive layers 4 easily come into contact with each other. This is suitable for more reliably providing electrical connectivity between the second conductive layers 4 and the third conductive layers 5.As shown in FIG. 4, the third edge 51 of the third conductive layers 5 is disposed between the first edge 93 of the insulating layer 9 and the second edge 41 of the second conductive layers 4. Therefore, even when an external gas, liquid, or the like enters at the third edge 51, the insulating layer 9 is disposed between the third edge 51 and the first conductive layers 3. Therefore, even when a liquid or the like penetrates downward in the z direction ("permeate"), the insulating layer 9 can prevent the liquid or the like from reaching the first conductive layers 3. Therefore, a change or the like of the first conductive layers 3 can be prevented. In addition, it is possible to suppress sulfurization of the first conductive layers 3 and avoid insulation of the first conductive layers 3.When the chip resistor A 1 is mounted on a circuit substrate or the like of an electronic component or the like, the back surface 12 of the substrate 1 is mounted to face the circuit substrate. At this time, solder serving as a bonding conductive material adheres to the fifth conductive layers 7. In some cases, it is preferable that the solder adheres to the side surface 73 and the front surface 71, in addition to adhering to the back surface portion 72 of the fifth conductive layers 7. In the present embodiment, the tip 76 of the fifth conductive layers 7 is a portion located farthest from the substrate 1. It is therefore possible to achieve the solder to remain at the tip 76, and it is possible to prevent the solder from reaching the insulating layer 9 beyond the third conductive layers 5. Further, from the viewpoint of providing the tip 76, it is preferable that the third conductive layers 5 have the third bulging portion 52, and that the tip 53 is disposed higher than the tip 43 in the z direction. The portion of the third bulging portion 52 including the tip 53 is thicker than the portion of the second conductive layers 4 covered by the third conductive layers 5. Consequently, the tips 53 and 76 can be positioned higher. Further, since the fifth conductive layers 7 have the tip 75, it is such that an effect that the solder is held at the tip 75 can be expected. From the viewpoint of providing the tip 75, it is preferable that the second conductive layers 4 have the second bulging portion 42 and that the tip 43 is formed. In addition, since the fifth conductive layers 7 have the concave portion 77, it is possible to achieve the solder to remain in the concave portion 77. From the viewpoint of providing the concave portion 77, it is preferable that the second conductive layers 4 have the concave portion 45.The inclined covering portion 31 of the third conductive layers 5 covering the inclined surface 15 of the substrate 1 tends to have a surface that is slightly inclined with respect to the z direction. Further, the curved surface portion 32 is formed of a convex curved surface connected to the cover inclined portion 31. The curved surface portion 44 of the second conductive layers 4 is a convex curved surface following the curved surface portion 32 of the first conductive layers 3, and is a moderate curved surface than the curved surface portion 32. Therefore, the fourth conductive layers 6 and the fifth conductive layers 7 covering that portion have a moderate shape, and the thickness thereof is likely to be more uniform. Therefore, the portion of the first conductive layers 3 and the second conductive layers 4 covering the vicinity of the boundary between the inclined surface 15 and the front surface 11 can be prevented from being exposed to the fourth conductive layers 6 and the fifth conductive layers 7.FIGS. 8-26 illustrate further embodiments of the present disclosure. In these figures, the same or similar elements as those in the above embodiment are denoted by the same reference numerals as those used in the above embodiment.FIG. 8 illustrates a chip resistor according to a second embodiment of the present disclosure. In the chip resistor A 2 of the present embodiment, the configuration of the third conductive layers 5 is different from that in the above-described embodiment.In the present embodiment, the third conductive layers 5 have a third bulging portion 52 and a fourth bulging portion 55. Like the third bulging portion 52, the fourth bulging portion 55 is a portion having a shape bulging in the z direction away from the substrate 1. The fourth bulging portion 55 is separated from the third bulging portion 52 and is disposed between the third bulging portion (fourth bulging portion) 55 and the side surface 13 in the x direction in the x direction. In the example shown, the bulging portion 55 is disposed above the first edge 93 in the z direction and covers the concave portion 45 of the second conductive layers 4.Also in this type of embodiment, it is possible to suppress deterioration of the function of the chip resistor A 2. Further, since the third conductive layers 5 have the fourth bulging portion 55, in addition to the third bulging portion 52, peeling (off) of the fourth conductive layers 6 or generation of a crack between the fourth conductive layers 6 and the second conductive layers 4 and the third conductive layers 5 can be preferably suppressed.FIGS. 9 to 16 show a chip resistor according to a third embodiment of the present disclosure. The chip resistor A 3 of this embodiment has a configuration that is intended to suppress damage and the like when a surge current (surge current) flows by extending the conduction path of the resistor layer 2.FIG. 9 is a main-part plan view showing the chip resistor A 3. FIG. 10 is a cross-sectional view taken along a line X-X in FIG. 9, FIG. 11 is a cross-sectional view taken along a line XI-XI in FIG. 9, FIG. 12 is a cross-sectional view taken along a line XII-XII in FIG. 9, FIG. 13 is an enlarged main-part cross-sectional view showing the chip resistor A 3. FIG. 14 is a plan view showing a manufacturing process of the chip resistor A 3. FIG. 15 is a cross-sectional view taken along a line XV-XV in FIG. 14, FIG. 16 is a cross-sectional view taken along a line XVI-XVI in FIG. 14, FIG. 17 is an enlarged main-part cross-sectional view showing a manufacturing process of the chip resistor A 3.In the present embodiment, the first conductive layers 3 have an extension portion 33. the extension portion 33 is a portion extending toward the center in the x direction. The resistor layer 2 has an extension portion 23. The extension portion 23 is a portion extending outward in the x direction. The portion of the extension portion 23 that overlaps the extension portion 33 is the covering portion 21.The resistor layer 2 has a plurality of recesses 22. Each recess 22 is an elongated recess portion formed in a shape entering toward the inside of the resistance layer 2. It should be noted that in these figures, the recesses 22 and grooves 22, respectively, are surrounded by a dashed line for a more convenient understanding, and that this also applies in the figures below. In the present embodiment, each of the thin recesses 22 has an elongated shape whose longitudinal direction is the y direction. The plurality of recesses 22 are provided alternately on the upper side in the y-direction and on the lower side in the y-direction. By providing such a plurality of recesses 22, the resistor layer 2 has a meandering shape, and the conduction path is elongated as compared with the resistor layer 2 of the chip resistor A 1. Each of the plurality of recesses 22 extends in the y-direction.In the present embodiment, the plurality of recesses 22 include first recesses 221 and second recesses 222. As shown in FIGS. 9 and 13, the first recesses 221 expose the front surface 11. The second recesses 222 coincide with recess portions 17 formed in the substrate 1 when viewed in the z direction. As shown in FIGS. 10 to 12, the recessed portions 17 are recessed from the front surface 11 and have a narrow shape in which the y direction is its longitudinal direction in the example shown. In the example shown, two of the first recesses 221 are disposed near the center in the x-direction, and two of the second recesses 222 are disposed outward in the x-direction. The two first recesses 221 are provided on opposite sides in the y direction, and the two second recesses 222 are provided on opposite sides in the y direction.In the present embodiment, the insulating layer 9 includes a first insulating layer 91 and a second insulating layer 92. The first insulating layer 91 directly covers the substrate 1 and the resistor layer 2. the second insulating layer 92 covers the first insulating layer 91 and the resistor layer 2 and the first conductive layers 3 disposed in the vicinity of the first insulating layer 91. As shown in FIGS. 10 and 11, the first insulating layer 91 covers most of the resistor layer 2 except a part of the extension portion 23 of the resistor layer 2, and does not cover the first conductive layers 3. In the example shown, the first insulating layer 91 is made of, for example, glass, and the second insulating layer 92 is made of, for example, an epoxy resin. In forming the insulating layer 9, for example, a glass paste is printed and then fired to form the first insulating layer 91, and a paste containing an epoxy resin as a main component is printed to cover the first insulating layer 91, and then fired. Thus, the second insulating layer 92 is also formed.As shown in FIG. 13, a portion of the front surface 11 exposed to the first recesses 221 is covered by the first insulating layer 91. On the other hand, as shown in FIGS. 10 to 12, the first insulating layer 91 has grooves 911. The recesses 911 are opening portions that completely coincide with the recess portions 17 of the substrate 1 when viewed in the z direction. That is, the recess portions 17, the second recesses 222, and the recesses 911 coincide with each other when viewed in the z direction. Therefore, the recessed portions 17 are not covered by the first insulating layer 91, but are covered by the second insulating layer 92. In other words, the second insulating layer 92 fills the second recesses 222 of the resistor layer 2 and the recess portions 17 of the substrate 1 via the recesses 911 of the first insulating layer 91. the inner surfaces of the recess portions 17, the second recesses 222, and the recesses 911 are smoothly connected to each other without any step or the like therebetween.FIGS. 14 to 17 show an example of a manufacturing process of the chip resistor A3. In this example, a substrate material 10 capable of forming a plurality of substrates 1 is used. As shown in FIGS. 14 to 16, the resistor layer 2, the first conductive layers 3, and the first insulating layer 91 are formed on the front surface 11 of the substrate material 10 by printing and firing. Note that in FIG. 14, the first insulating layer 91 is omitted for better understanding. The resistor layer 2 has two recesses 22 and two concave portions 24. Each of the two recesses 22 is a first recess 221. The recess portions 17 described above are not yet formed in the substrate 1. The location of the substrate 1 where the recess portions 17 are provided is covered by the resistor layer 2 and the first insulating layer 91. That is, the resistor layer 2 does not have the second recesses 222, and the first insulating layer 91 does not have the recesses 911. In the example shown, the two concave portions 24 are used to indicate where second recesses 222 are to be formed in a process described later.Next, as shown in FIGS. 14 and 17, the resistor layer 2 is trimmed using a laser beam L. The purpose of trimming is, for example, to lengthen the conduction path of the resistor layer 2 and adjust the resistance value of the resistor layer 2. As shown in FIG. 14, the laser beam L is scanned from the concave portion 24 to the path shown by the arrow. Thereby, as shown in FIG. 17, the portion of the first insulating layer 91 and the resistor layer 2 irradiated by the laser beam L are removed over the entire thickness. Further, the portion of the substrate 1 irradiated with the laser beam L is removed. As a result, the recess portions 17 are formed in the substrate 1, and the second recesses 222 and the recesses 911 are formed in the resistance layer 2 and the first insulating layer 91, respectively. By applying such a technique, the recess portions 17, the second recesses 222, and the recesses 911 coincide with each other when viewed in the z direction. Further, the inner surfaces of the recess portion 17, the second recesses 222, and the recesses 911 are smoothly joined to each other without a step or the like being present therebetween.Also according to this kind of embodiment, it is possible to suppress deterioration of the function of the chip resistor A 3. Further, due to the fact that the conduction path of the resistor layer 2 is elongated, it is possible to suppress damage and the like when a surge current flows.FIGS. 18 to 23 show a chip resistor according to a fourth embodiment of the present disclosure.FIG. 18 is a main-part plan view showing a chip resistor A 4. FIG. 19 is a sectional view taken along a line XIX-XIX in FIG. 18, FIG. 20 is a sectional view taken along a line XX-XX in FIG. 18, FIG. 21 is a sectional view taken along a line XXII-XXII in FIG. 18, FIG. 22 is a sectional view taken along a line XXII-XXII in FIG. 18, FIG. 23 is a sectional view taken along a line XXIII-XXIII in FIG. 18, it is to be noted that components other than the substrate 1, the resistor layer 2, and the first conductive layers 3 are omitted for better understanding in FIG. 18.In the chip resistor A 4 of the present embodiment, the ratio of the dimension in the x direction and the dimension in the y direction when viewed in the z direction is different from that of the chip resistors A 1 to A 3. In this embodiment, the dimension of the chip resistor A4 in the y direction is longer than the dimension in the x direction.The pair of first conductive layers 3 are provided on both sides in the x direction on the front surface 11 of the substrate 1. The first conductive layer 3 on the right side of the drawing in FIG. 18 has a shorter dimension in the y direction than the first conductive layer 3 on the left side of the drawing, and is disposed offset upward in the y direction in the drawing.Similarly to the chip resistor A 3 described above, the conduction path of the resistor layer 2 is extended also in this embodiment. The resistor layer 2 has a plurality of recesses 22. In the present embodiment, the plurality of recesses 22 include only the second recesses 222, but may also include the first recesses 221 described above. The two second recesses 222 include a second recess 222 having its longitudinal direction in the x direction and a second recess 222 having its longitudinal direction in the y direction. As shown in FIGS. 18, 20, 21, and 23, the second recesses 222 coincide with the recess portions 17 of the substrate 1 when viewed in the z direction. Further, the second recesses 222 are coincident with the recesses 911 of the first insulating layer 91 when viewed in the z direction. Such second recesses 222 may be formed by, for example, a technique similar to the technique shown in FIG. 17.Also according to this kind of embodiment, it is possible to suppress deterioration of the function of the chip resistor A 4. Further, due to the fact that the conduction path of the resistor layer 2 is elongated, it is possible to suppress damage and the like when a surge current flows.FIGS. 24 to 26 show a chip resistor according to a fifth embodiment of the present disclosure.FIG. 24 is a sectional view showing a chip resistor A 5. FIG. 25 is an enlarged main-part sectional view showing the chip resistor A 5. FIG. 26 is an enlarged main-part sectional view showing a manufacturing process of the chip resistor A 5.As shown in FIGS. 24 and 25, the chip resistor A 5 includes a substrate 1, a resistor layer 2, first conductive layers 3, an underlying conductive layer 60, fourth conductive layers 6, and fifth conductive layers 7. The insulating layer 9 includes a first insulating layer 91 and a second insulating layer 92, similar to those of the chip resistors A 3 and A 4 described above.The underlying conductive layer 60 is made of a metal layer, for example, a Ni layer formed by sputtering. The thickness of the underlying conductive layer 60 is not particularly limited, and is, for example. 300 nm to 700 nm. The underlying conductive layer 60 includes a front surface portion 601, a rear surface portion 602, and a side surface portion 603.The front surface portion 601 is supported by the front surface 11 of the substrate 1 via the resistor layer 2, the first conductive layers 3, and the first insulating layer 91. the front surface portion 601 covers the first insulating layer 91 and the first conductive layers 3 while straddling the first edge 93 of the first insulating layer 91. The back surface portion 602 is supported on the back surface 12 of the substrate 1 via the sixth conductive layers 8, the back surface portion 602 covers a part of the sixth conductive layers 8, the side surface portion 603 is supported by the side surface 13 and covers the side surface 13 and the inclined covering portion 31 of the first conductive layers 3.As shown in FIG. 25, the second insulating layer 92 covers a part of the front surface portion 601 of the underlying conductive layer 60. the fifth edge 94 of the second insulating layer 92 is disposed on the front surface portion 601 and is disposed closer to the center in the x direction than the first edge 93.The front surface portion 61 of the fourth conductive layers 6 covers a portion of the front surface portion 601 of the underlying conductive layer 60 exposed to the second insulating layer 92. That is, the front surface portion 61 is provided substantially outside in the x direction with respect to the fifth edge 94 of the second insulating layer 92.The front surface portion 71 of the fifth conductive layers 7 covers the front surface portion 61 of the fourth conductive layers 6. the front surface portion 71 may cover a part of the second insulating layer 92 near the fifth edge 94, but exposes a majority of the second insulating layer 92.FIG. 26 shows an example of a manufacturing process of the chip resistor A 5. The resistor layer 2, the first conductive layers 3, and the first insulating layer 91 are formed on the substrate material 10 using, for example, printing and firing. Next, in a state where a part of the first insulating layer 91 is exposed using a mask M, the underlying conductive layer 60 is formed by sputtering. Thus, the front surface portion 601 of the underlying conductive layer 60 has a configuration that partially covers the first insulating layer 91. After that, the second insulating layer 92 is formed to cover the first insulating layer 91 and a part of the front surface portion 601 of the underlying conductive layer 60. Subsequently, the chip resistor A 5 is obtained by sequentially forming the fourth conductive layers 6 and the fifth conductive layers 7.According to this type of embodiment, the second insulating layer 92 of the insulating layer 9 and the front surface portion 61 of the fourth conductive layers 6 are joined to the front surface portion 601 of the underlying conductive layer 60 with the fifth edge 94 interposed therebetween. Since the underlying conductive layer 60 is formed using sputtering, the surface area where the underlying conductive layer 60 is formed is likely to be a fine rough surface having fine irregularities. Therefore, it is possible to increase the bonding strength of the first insulating layer 91 with the second insulating layer 92 and the front surface portion 61 and suppress external gas, liquid, or the like from entering the inside from the fifth edge 94. It is therefore possible to suppress deterioration of the function of the chip resistor A 5. In addition, it is possible to suppress sulfurization of the first conductive layers 3 and avoid insulation of the first conductive layers 3.Clause 1.A chip resistor comprising:a substrate having a front surface and a back surface facing opposite directions to each other in a thickness direction, and having a side surface disposed between the front surface and the back surface;a resistor layer disposed on the front surface;a first conductive layer disposed on the front surface and electrically connected to the resistor layer;an insulating layer covering the resistor layer and the first conductive layer and having a first edge disposed on the first conductive layer;a second conductive layer covering the first conductive layer and the insulating layer while spanning the first edge and having a second edge disposed on the insulating layer;a third conductive layer covering the second conductive layer and the insulating layer while spanning the second edge and having a third edge disposed on the second conductive layer; anda fourth conductive layer covering the second conductive layer and the third conductive layer while spanning the third edge,wherein a bonding strength between the third conductive layer and the fourth conductive layer is stronger than a bonding strength between the second conductive layer and the fourth conductive layer.Clause 2.The chip resistor according to clause 1, wherein the first conductive layer includes Ag.Clause 3.The chip resistor according to Clause 1 or 2, wherein the second conductive layer includes a resin and carbon.Clause 4.The chip resistor according to Clause 3, wherein the carbon contained in the second conductive layer is flake-like.Clause 5.The chip resistor according to any one of Clause 1 to Clause 4, wherein the third conductive layer includes a resin and Ag.Clause 6.The chip resistor according to Clause 5, wherein the Ag contained in the third conductive layer is flake-like.Clause 7.The chip resistor of any of clause 1 to 6, wherein the third edge is disposed between the first edge and the second edge.Clause 8.The chip resistor of clause 7, wherein the third conductive layer has a fourth edge disposed on the insulating layer.Clause 9.The chip resistor of clause 8, wherein the fourth conductive layer covers the fourth edge.Clause 10.The chip resistor according to any one of Clause 1 to Clause 9, wherein the second conductive layer includes a second bulging portion between the side surface of the substrate and the first edge of the insulating layer, the second bulging portion bulging away from the front surface of the substrate.Clause 11.The chip resistor according to clause 10, wherein the third conductive layer includes a third bulging portion of the substrate and a third bulging portion bulging away from the substrate, respectively.Clause 12.The chip resistor according to clause 11, wherein a tip of the third bulging portion is farther from the front surface of the substrate than a tip of the second bulging portion.Clause 13.The chip resistor according to any one of Clause 1 to Clause 12, wherein the fourth conductive layer includes Ni.Clause 14.The chip resistor according to any one of clause 1 to claim 13, further comprising a fifth conductive layer covering the fourth conductive layer.Clause 15.The chip resistor of clause 14, wherein the fifth conductive layer includes Sn.Clause 16.The chip resistor according to any one of Clause 1 to Clause 15, wherein the resistor layer is formed with a plurality of recesses.Clause 17.The chip resistor of clause 16, wherein the plurality of recesses comprises:a first recess exposing the front surface of the substrate; anda second recess that corresponds to a recess portion formed on the substrate and recessed from the front surface when viewed in the thickness direction.Clause 18.The chip resistor of clause 16 or 17, wherein the first conductive layer includes a pair of first conductive layers spaced apart from each other in a first direction, and wherein the plurality of recesses extend along a second direction that is perpendicular to the first direction.Clause 19.The chip resistor of clause 16 or 17, wherein the first conductive layer includes a pair of first conductive layers spaced apart from each other in a first direction, and wherein the plurality of recesses includes one recess extending along the first direction and another recess extending along a second direction that is perpendicular to the first direction.

Claims

A chip resistor, comprising: • a substrate (1) having a front surface (11) and a back surface (12) facing in opposite directions in a thickness direction, and having a side surface (13) disposed between the front surface (11) and the back surface (12); • a resistor layer (2) disposed on the front surface (11); • a first conductive layer (3) disposed on the front surface (11) and electrically connected to the resistor layer (2); • an insulating layer (9) covering the resistor layer (2) and the first conductive layer (3) and having a first edge (93) disposed on the first conductive layer (3); • a second conductive layer (4) covering the first conductive layer (3) and the insulating layer (9) while spanning the first edge (93) and having a second edge (41) disposed on the insulating layer (9); • a third conductive layer (5) covering the second conductive layer (4) and the insulating layer (9) while spanning the second edge (41) and having a third edge (51) disposed on the second conductive layer (4); • a fourth conductive layer (6) covering the second conductive layer (4) and the third conductive layer (5) while spanning the third edge (51), wherein a bonding strength between the third conductive layer (5) and the fourth conductive layer (6) is stronger than a bonding strength between the second conductive layer (4) and the fourth conductive layer (6), and wherein the third edge (51) is disposed between the first edge (93) and the second edge (41).The chip resistor according to claim 1, wherein the first conductive layer (3) contains Ag.The chip resistor according to claim 1 or 2, wherein the second conductive layer (4) contains a synthetic resin and carbon.The chip resistor according to claim 3, wherein the carbon contained in the second conductive layer (4) is flake-like.The chip resistor according to any one of claims 1 to 4, wherein the third conductive layer (5) includes a synthetic resin and Ag.The chip resistor according to claim 5, wherein the Ag contained in the third conductive layer (5) is flake-like.The chip resistor according to any one of claims 1 to 6, wherein the third conductive layer (5) has a fourth edge (54) disposed on the insulating layer (9).The chip resistor according to claim 7, wherein the fourth conductive layer (6) covers the fourth edge (54).The chip resistor according to any one of claims 1 to 8, wherein the second conductive layer (4) has a second bulging portion (42) between the side surface (13) of the substrate (1) and the first edge (93) of the insulating layer (9), the second bulging portion (42) bulging away from the front surface (11) of the substrate (1).The chip resistor according to claim 9, wherein the third conductive layer (5) has a third bulging portion (52) bulging away from the substrate (1).The chip resistor according to claim 10, wherein a tip (53) of the third bulging portion (52) is located farther from the front surface (11) of the substrate (1) than a tip (43) of the second bulging portion (42).The chip resistor according to any one of claims 1 to 11, wherein the fourth conductive layer (6) contains Ni.The chip resistor according to any one of claims 1 to 12, further comprising a fifth conductive layer (7) covering the fourth conductive layer (6).The chip resistor according to claim 13, wherein the fifth conductive layer (7) contains Sn.The chip resistor according to any one of claims 1 to 14, wherein the resistor layer (2) is formed with a plurality of recesses (22).The chip resistor according to claim 15, wherein the plurality of recesses (22) include: • a first recess (221) that exposes the front surface (11) of the substrate (1), and • a second recess (222) that coincides with a recess portion (17) formed on the substrate (1) and that is recessed from the front surface (11) when viewed in the thickness direction.The chip resistor according to claim 15 or 16, wherein the first conductive layer (3) includes a pair of first conductive layers (3) spaced apart from each other in a first direction, and wherein the plurality of recesses (22) extend along a second direction that is perpendicular to the first direction.The chip resistor according to claim 15 or 16, wherein the first conductive layer (3) has a pair of first conductive layers (3) spaced apart from each other in a first direction, and wherein the plurality of recesses (22) includes a recess (222) extending along the first direction and another recess (222) extending along a second direction perpendicular to the first direction.

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