POWER LEVEL SETTINGS IN WORK MEMORY DEVICES

Abstract

Working memory device (103), comprising: a non-volatile memory (109); a communication interface (105) for receiving a command (111) for accessing the non-volatile memory (109) of the memory device (103); and a controller (107) configured to do the following: Determining a workload level (121, 123, 125) by the command (111) to be executed by the controller (107) executing the command (111), based on the determination of a command type to be executed by the controller (107), wherein the command (111) specifies the command type; Selecting a computational power level (131, 133, 135) of the controller (107) according to the workload level (121, 123, 125); and Setting the controller (107) to the computing power level (131, 133, 135) during the execution of the command (111).

Description

RELATED REGISTRATIONS

[0001] The present application claims priority over US Patent No. 15 / 840,709, filed on December 13, 2017, entitled “Performance Level Adjustments in Memory Devices”. AREA OF TECHNOLOGY

[0002] At least some embodiments disclosed herein relate to computer data storage devices in general and, in particular, to power management in working memory devices. GENERAL STATE OF THE ART

[0003] A main memory system can include multiple memory modules and a memory controller. Several techniques have been developed for managing power consumption within a main memory system.

[0004] For example, US 9 384 818 B2, titled "Memory Power Management", published on July 5, 2016, reveals a technique in which a circuit is put into a lower power consumption mode when no read or write operation is being performed on a particular memory module.

[0005] For example, US 9 189 053 B2, entitled “Performance based Power Management of a Memory and a Data Storage System using the Memory”, published on November 17, 2015, discloses a technique in which a memory arrangement is supplied with a voltage corresponding to a memory power level, which can be a full power level or a power-saving power level.

[0006] For example, US 8 745 427 B2, titled "Memory Link Power Management," published on June 3, 2014, reveals that various components of a memory subsystem may enter low-power states under certain operating conditions, such as when a memory controller is no longer performing transactions directed to a memory unit.

[0007] For example, US 7 730 338 B2, entitled "Interface Circuit System and Method for Autonomous Performing Power Management Operations in Conjunction with a Plurality of Memory Circuits," published on June 1, 2010, discloses an interface circuit that autonomously performs a first power management operation in a first instruction operation period on a first memory circuit and a second power management operation in a second instruction operation period on a second memory circuit, wherein the power management operations are initiated by non-power management signals, such as address and data signals.

[0008] US 2014 / 0344597A1 discloses systems, methods, and devices for dynamically scaling the clock frequency of an I / O interface to a non-volatile storage device. The scaling can be based on monitoring the idle time of the I / O interface, the priority of one or more applications with read / write requests queued for forwarding to the I / O interface, the utilization of the queued read / write requests, or a combination of priority and utilization.

[0009] US patent 2012 / 0224425A1 discloses a method for performing memory operations that includes retrieving stored temperature information. The temperature information relates to the temperature approximately at the time the data was written to the non-volatile memory cells. Processing data read from the non-volatile memory cells is based on information about the temperature.

[0010] The invention relates to the working memory device claimed in claim 1 and the method claimed in claim 14. Advantageous embodiments are claimed in claims 2 to 13 and 15. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The embodiments are illustrated by way of example and without limitation in the figures of the accompanying drawings, in which similar references indicate similar elements. Fig. Figure 1 illustrates a working memory device according to one embodiment. Fig. Figure 2 illustrates a configuration file for setting an operating parameter of a memory device according to one embodiment. Fig. Figure 3 illustrates an instruction that can be parsed by a working memory device to set one of its operating parameters according to an embodiment. Fig. Figure 4 shows a method for operating a working memory device according to one embodiment. Fig. Figure 5 shows a detailed method for operating a working memory device according to one embodiment. DETAILED DESCRIPTION

[0012] At least some of the embodiments disclosed herein provide a memory device that estimates the workload of a received instruction for a memory device controller and sets an operating parameter of the controller (e.g., the clock speed) to manage the energy consumption and / or temperature of the memory device without, if at all, significant degradation of the overall performance of the memory device.

[0013] A working memory device is typically housed in a casing without an internal cooling element. The energy management techniques disclosed herein can reduce energy consumption and / or manage the temperature of the working memory device, particularly when the working memory device is used at an extreme temperature, such as in a vehicle operated on a hot day.

[0014] The memory device can comprise a set of components, such as one or more memory chips and a control chip, stacked and sealed within the same integrated circuit package. Depending on the instructions received by a memory device, the performance bottleneck may or may not be in the control chip.

[0015] During the execution of some instructions with some data sets, the performance bottleneck of the memory device may be in the controller; and during the execution of other instructions with other data sets, the performance bottleneck of the memory device may be in one or more of the memory chips. The performance balance between the components within the memory device can therefore depend on the type of operations to be performed for the received instruction (e.g., read, write, erase) and / or the size and pattern of the data set to be processed for the instruction.

[0016] If the power bottleneck is not in the controller, the controller can be operated at a reduced power level and thus at a reduced energy consumption level, without affecting the overall performance of the working memory device when executing the received command.

[0017] Preferably, in response to a given instruction, the control of the memory device is operated at a specific power level that matches the power limitation of the other components of the memory device, so that, for example, a further increase in the power level of the control does not further reduce the overall execution time of the instruction.

[0018] For example, the power level of the memory device's controller can be throttled by adjusting the memory device's clock speed. During the execution of a given instruction with a given data set, the controller's clock speed can be reduced to an optimal level without increasing the instruction's execution time for that data. Preferably, the clock speed reduction is optimized such that further reduction from the optimal level makes the controller a performance bottleneck and increases the execution time. Conversely, increasing the clock speed from the optimal level increases power consumption without reducing the instruction's execution time. Therefore, the increased clock speed is not optimal.

[0019] In general, a main memory device comprises a number of components. Each component can have different power levels, corresponding to different trade-offs between performance and power consumption. For a given instruction on a given data set, an optimal set of power levels is determined for the components such that increasing the power level of any component increases power consumption without decreasing the execution time of the instruction on the data set; and decreasing the power level of any component from the optimal set increases the execution time of the instruction. Preferably, the components are operated at the optimal power level determined for the given instruction on the data set. In this way, the power levels of the components can be set on a command-by-command basis.

[0020] Fig. Figure 1 illustrates a working memory device (103) according to one embodiment.

[0021] The in Fig. 1 Illustrated data storage device (103) includes a controller (107), a communication interface (105), a non-volatile memory (109), a volatile memory (106) and optional firmware (104).

[0022] In Fig. The performance of the controller (107) is controllable via a clock (101). If the frequency of the clock (101) (e.g., clock speed) is increased, the processing power of the controller (107) increases in order to shorten the time the controller (107) needs to execute a particular operation. However, an increase in the clock speed increases the energy consumption of the controller (107).

[0023] In some cases, the controller (107) has several circuits for performing the same operation. These circuits exhibit different trade-offs in performance and energy consumption. For example, one circuit might have high processing power and high energy consumption, while a second circuit might have low processing power and low energy consumption. Thus, the performance of the controller (107) can be controlled by selecting one of the available circuits for operation during the execution of a specific command.

[0024] In some cases, the controller (107) has multiple parallel processors / circuits that can be used in parallel to increase computing power. However, using an increasing number of parallel processors / circuits increases peak power consumption and / or the total power consumption for performing a particular task.

[0025] When the memory device (103) receives a command (111) via the communication interface (105), the controller (107) typically performs calculations in connection with data access to the volatile memory (106) and / or the non-volatile memory (109).

[0026] The total computing power of the main memory device (103) for the execution of the instruction (111) can be measured as the time required to complete operations relating to the instruction (111) in the main memory device (103), including operations performed by the controller (107) and operations performed by the volatile main memory (106) and / or the non-volatile main memory (109).

[0027] The total energy power of the working memory device (103) for the execution of the instruction (111) can be measured as the total energy consumption for the completion of the operations in the working memory device (103) associated with the instruction (111), including the operations performed by the control (107) and the operations performed by the volatile working memory (106) and / or the non-volatile working memory (109).

[0028] The total thermal power of the working memory device (103) for the execution of the instruction (111) can be measured as the temperature fluctuations caused by the completion of operations related to the instruction (111) in the working memory device (103), including operations performed by the controller (107) and operations performed by the volatile working memory (106) and / or the non-volatile working memory (109).

[0029] When executing some computationally intensive instructions, the total time required to complete an instruction (111) is limited by the processing power of the controller (107). In such a situation, the controller (107) can be operated in a high-performance mode (e.g., using a high clock speed, a high-performance circuit, and / or multiple parallel processing circuits) to improve the overall processing power of the main memory device (103).

[0030] When executing some data-access-intensive instructions, the total time required to complete an instruction is limited by the data access performance of the main memory (109 and / or 106). In such a situation, the controller (107) can be operated in a low-power mode (e.g., using a low clock speed, a low-power circuit, and / or fewer or no parallel processing circuits) to improve the overall performance / thermal efficiency of the main memory device (103).

[0031] In Fig. 1. The operations performed by the controller (107) are controlled by the firmware (104), which is initially stored in a section of the non-volatile memory (109) and can then be loaded into the volatile memory (106) for execution. Alternatively, the function of the firmware (104) can be implemented using a hardware circuit (e.g., with an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA)).

[0032] For example, the selection of a power mode of the controller (107) for the execution of the command (111) can be implemented using the firmware (104) and / or a hardware circuit in the controller (107).

[0033] For example, an operating parameter value can be used to configure the controller (107) in a specific performance mode. The operating parameter value could be, for example, a clock speed, the identification of a circuit to be selected from several circuits with the same function but different performance compromises, a degree of parallel processing, etc. The operating parameter value can be associated with a workload level in a configuration file to determine a performance mode of the controller (107) for the given command (111).

[0034] Fig. Figure 2 illustrates a configuration file (113) for setting an operating parameter of a memory device (103) according to one embodiment. For example, the configuration file (113) can be stored in the memory device (103) of Fig. 1 can be stored (e.g. as part of the firmware (104)) to configure the operation of the controller (107).

[0035] The configuration file (113) from Fig. 2 identifies a set of values ​​(131, 133, ..., 135) of an operating parameter of the controller (107) for a corresponding set of workload levels (121, 123, ..., 125).

[0036] If the workload level of the controller (107) for the command (111) is estimated to be at a threshold level (e.g. 121, 123, ..., or 125) in the configuration file (113), the corresponding value (e.g. 131, 133, ..., 135) of the operating parameter can be looked up in the configuration file (113) to configure the power mode of the controller (107) for the command (111).

[0037] Preferably, the workload levels (e.g., 121, 123, ..., or 125) of the controller (107) are load estimates relative to, or normalized by, the performance of the main memory (109 or 106). For example, the workload levels (e.g., 121, 123, ..., or 125) can be the estimated number of operations of the controller (107), normalized by the estimated time for data access in main memory (109 or 106).

[0038] For example, if the workload level of the controller (107) is above the threshold level A (121), the operating parameter value (131) is used to operate the controller (107) at full capacity.

[0039] For example, if the operating capacity level of the controller (107) is between threshold level A (121) and threshold level B (123), the operating parameter value (133) is used to operate the controller (107) at a reduced capacity level to improve energy / thermal performance without affecting the overall performance of the working storage device (103), compared to operating at full capacity using the operating parameter value (131).

[0040] The command (111) received at the communication interface (105) typically specifies a type of operation and a data set to be worked with, as in Fig. Figure 3 illustrates the workload level of the controller. This can be estimated based on the type of operations (e.g., read, write, delete) as well as on the characteristics of the data set, such as the size of the data set, whether the data set is on the same memory chip, and whether the data set is on a continuous address block.

[0041] Fig. Figure 3 illustrates an instruction (111) issued from a working memory device (103). Fig. 1 can be analyzed to set one of its operating parameters (e.g., using the configuration file from Fig. 2).

[0042] The in Fig. The illustrated command (111) includes a command opcode (141) and data (143). The command opcode (141) specifies the type of operation, e.g., a read operation or a write operation. The data (143) specifies a data record to be processed (e.g., via addresses). The time required by memory (e.g., 109 and / or 106) to complete the command (111) typically depends on the type of operation, such as reading, writing, deleting, etc.

[0043] The time required by the main memory (e.g., 109 and / or 106) to complete the instruction (111) may also depend on properties of the data (143), such as the size of the data set, whether the data set is located in a continuous address block, whether the data set is located in the same or in different memory chips that can be accessed in parallel, etc.

[0044] Similarly, the number of operations to be performed by the controller (107) can be estimated based on the command op code (141) and / or the characteristics of the data set identified by the data (143) of the command (111).

[0045] From the estimated time required of the working memory (e.g. 109 and / or 106) of the working memory device (103) to complete the instruction (111) and the estimated number of calculations to be performed by the controller (107), a normalized workload level can be determined, which can be compared with the threshold values ​​(e.g. 121, 123, ..., 125) in the configuration file (113) to select an operating parameter value (e.g. 131, 133, ..., or 135) that is used to configure the power mode of the controller (107) during the execution of the instruction (111).

[0046] In some cases, the operation of the memory device (103) may be limited by its thermal performance in the current operating environment. For example, the memory device (103) may include a temperature sensor. If the temperature of the memory device (103) exceeds a threshold, the memory device (103) may be operated at a reduced power level to reduce the heat generated by the memory device (103). For example, the controller (107) may extend the memory access over a longer period (e.g.,by introducing idle cycles between data access cycles when using the memory (109 / 106), whereby the memory (109) is operated at a reduced clock speed; thereby increasing the estimated time for the execution of the instruction (111); and the computing power level of the controller (107) can be reduced accordingly to reduce energy consumption and / or peak energy consumption in order to reduce the effect on the temperature of the main memory device (103).

[0047] In general, a host can communicate the command (111) to the memory device (103) via a communication channel using a predefined protocol. The host can be a computer with one or more central processing units (CPUs) to which computer peripheral devices, such as the memory device (103), can be connected via a connection such as a computer bus (e.g., Peripheral Component Interconnect (PCI), PCI eXtended (PCI-X), PCI Express (PCIe)), a communication interface, and / or a computer network.

[0048] The memory device (103) can be used to store data for the host in non-volatile memory (109). Examples of computer memory devices in general are hard disk drives (HDDs), solid-state drives (SSDs), flash memory, dynamic random-access memory, magnetic tapes, network-connected data storage devices, etc. The communication interface (105) of the memory device (103) implements communication with the host via a communication channel. For example, the communication channel between the host (101) and the data storage device (103) can be a Peripheral Component Interconnect Express (PCI Express or PCIe) bus; and the host (101) and the data storage device (103) communicate with each other using the NVMe protocol (Non-Volatile Memory Host Controller Interface Specification (NVMHCI), also known as NVM Express (NVMe)).

[0049] In some implementations, the communication channel between the host and the memory device (103) includes a computer network, such as a local area network, a wireless local area network, a wireless personal network, a cellular communication network, an always-connected high-speed wireless broadband communication link (e.g., a current or future generation of mobile network connection); and the host and the memory device (103) may be configured to communicate with each other using storage management and utilization commands similar to those of the NVMe protocol.

[0050] The controller (107) of the working memory device (103) executes firmware (104) to perform operations in response to commands (e.g., 111) from the host. Firmware, in general, is a type of computer program that enables the control, monitoring, and data manipulation of technical computer devices. In Fig. 1. The firmware (104) controls the operations of the controller (107) during the operation of the working memory device (103), such as estimating the workload level of the controller (107) for the given instruction (111), selecting an operating parameter value (e.g. 131, 133, ..., 135) and configuring the power mode of the controller (107) according to the selected operating parameter value (e.g. 131, 133, ..., 135).

[0051] The memory device (103) typically includes non-volatile memory (109), such as magnetic material deposited on rigid disks and / or memory cells in an integrated circuit. The memory (109) is non-volatile in that no power supply is required to retain the data / information stored in the non-volatile memory (109), and this data / information can be retrieved after the non-volatile memory (109) has been powered off and on again. The memory cells can be implemented using various memory / data storage technologies, such as…NAND gate-based flash memory, phase-change memory (PCM), magnetic memory (MRAM), resistive random access memory and 3D XPoint, so that the data storage medium (109) is non-volatile and can retain data stored in it for days, months and / or years without an energy supply.

[0052] The memory device (103) can include volatile memory (106) (e.g., dynamic random-access memory (DRAM)) for storing runtime data and instructions used by the controller (107) to improve the computing performance of the controller (107) and / or to provide buffers for data transferred between the host (101) and the non-volatile memory (109). The memory (106) is volatile in that it requires energy to retain the data / information stored in it, and this data / information is lost immediately or rapidly when the power supply is interrupted.

[0053] The volatile memory (106) typically has a lower latency than the non-volatile memory (109), but it quickly loses its data when the power supply is interrupted. Therefore, it is advantageous to use the volatile memory (106) to temporarily store instructions and data that the controller (107) uses in its current computing task to improve performance. In some cases, the volatile DRAM is replaced by volatile static random-access memory (SRAM), which consumes less power than DRAM in some applications. If the non-volatile memory (109) requires data access performance (e.g.,if the volatile memory (106) has a latency and read / write speed comparable to that of the volatile memory (106), the volatile memory (106) can be eliminated; and the controller (107) can perform calculations by working on the non-volatile memory (109) for instructions and data instead of the volatile memory (106).

[0054] For example, crosspoint data storage and memory devices (e.g., 3D XPoint memory) exhibit data access performance comparable to that of volatile memory (106). A crosspoint memory device uses transistorless memory elements, each of which has a memory cell and a selector stacked in a column. Memory element columns are connected by two layers of wire at right angles to each other, one layer above the memory element columns and the other layer below them. Each memory element can be individually selected at a crosspoint of a wire on each of the two layers. Crosspoint memory devices are fast and non-volatile and can be used as a unified memory pool for processing and storage.

[0055] In some cases, the controller (107) has an internal processor cache with data access performance that is better than that of the volatile memory (106) and / or the non-volatile memory (109). Therefore, it is preferable to temporarily store parts of instructions and data used in the current computational task in the controller's (107) internal processor cache during the controller's (107) computational operations. In some cases, the controller (107) has multiple processors, each with its own internal processor cache. In some cases, the volatile memory (106) is implemented on the chip for the controller (107) (e.g., as cache memory).

[0056] Optionally, the controller (107) performs data-intensive in-memory processing using data and / or instructions organized in the memory device (103). For example, in response to a request from the host (101), the controller (107) performs real-time analysis of a data set stored in the memory device (103) and communicates a reduced data set to the host (101) in response. For example, in some applications, the memory device (103) is connected to real-time sensors to store sensor inputs; and the processors of the controller (107) are configured to perform machine learning and / or pattern recognition based on the sensor inputs to support an artificial intelligence (AI) system that is implemented at least partially via the memory device (103) and / or the host (101).

[0057] In some implementations, during the manufacturing of computer chips, the controller processors (107) are integrated into the main memory (e.g., 106 or 109) to enable processing in main memory and thus overcome the von Neumann bottleneck. This bottleneck limits computing performance by restricting throughput due to latency in data movements between a processor and main memory that are configured separately according to the von Neumann architecture. Integrating processing and main memory increases processing speed and main memory transfer rate while reducing latency and power consumption.

[0058] The memory device (103) can be used in various computing systems, such as a cloud computing system, an edge computing system, a fog computing system, and / or a standalone computer. In a cloud computing system, remote computer servers are connected in a network to store, manage, and process data. An edge computing system optimizes cloud computing by performing data processing at the edge of the computer network, close to the data source, thereby reducing data communication with a central server and / or data storage. A fog computing system uses one or more end-user devices or near-user edge devices to store data, thus reducing or eliminating the need to store the data in a central data warehouse.

[0059] At least some embodiments of the inventions disclosed herein can be implemented using computer instructions executed by the controller (107), such as the firmware (104). In some cases, hardware circuits can be used to implement at least some of the functions of the firmware (104). The firmware (104) can initially be stored in the non-volatile memory (109) or another non-volatile device and loaded into the volatile memory (106) and / or the processor's internal cache memory for execution by the controller (107).

[0060] For example, the firmware (104) can be configured to implement the techniques described herein for adjusting the power level of the memory device (103). However, the techniques discussed herein are not limited to use in the memory device (103) from Fig. 1. For example, the memory device can be a solid-state drive, a removable memory card, an embedded general-purpose flash memory chip with more or fewer components than those in Fig. 1 illustrated working memory device (103).

[0061] Fig. Figure 4 shows a method for operating a working memory device according to one embodiment. For example, the method can be derived from Fig. 4 in the working memory device (103) Fig. 1 using a configuration file (113) from Fig. 2 in response to one in Fig. The 3 illustrated command (111) will be implemented.

[0062] The procedure from Fig. 4 includes: Receiving (161) an instruction (111) into a memory device (103); Determining (163) a workload of the instruction (111) based on operations to be performed by a controller (107) of the memory device (103) during the execution of the instruction (111) with respect to a set of data (143) associated with the instruction (111); Determining (165) a performance point (e.g., represented by an operating parameter value (131, 133, ..., or 135)) of the memory device (103) based on the workload of the instruction (111) in order to balance energy consumption and speed during the processing of the instruction (111); and operating (167) the working memory device (103) at the operating performance point (e.g. using the operating parameter value (131, 133, ..., or 135)) in response to the instruction (111).

[0063] Fig. Figure 5 shows a detailed method for operating a working memory device according to one embodiment. For example, the method can be derived from Fig. 4 in the working memory device (103) Fig. 1 using a configuration file (113) from Fig. 2 in response to one in Fig. The 3 illustrated command (111) will be implemented.

[0064] The procedure from Fig. 5 includes: Receiving (181) a command (111) at a communication interface (105) of a memory device (103) specifying a request to access memory (e.g., 109 or 106) in the device (103) for a record (e.g., identified at least partially by addresses of the record in memory); Determining (183) an estimated time for accessing the memory for the record identified by the command (111); Determining (185) an estimated number of operations to be performed by a controller (107) of the memory device (103) for the command (111); Determining (187) a power level (e.g., represented by an operating parameter value (131, 133, ...)or 135)) of the controller (107) based on planning the performance of the estimated quantity of operations within the estimated time span; and configuring (189) the controller (107) to operate at the performance level during the execution of the command (111) (e.g. according to an operating parameter value (131, 133, ... or 135)).

[0065] For example, the procedure includes determining a workload level of the controller (107) during the execution of the instruction (111) based on the estimated time spent accessing the non-volatile memory (109) of the memory device (103) during the execution of the instruction (111) and the estimated amount of computations performed by the controller (107) during the execution of the instruction (111).

[0066] For example, the workload level of the controller (107) can be normalized with respect to the estimated time period used for accessing the non-volatile memory (109) of the memory device (103) during the execution of the instruction (111), so that the workload level is proportional to the estimated amount of computations performed by the controller (107) during the execution of the instruction (111) and inversely proportional to the estimated time.

[0067] For example, the computational power level can be reduced based on the normalized workload level from a maximum control power level (107).

[0068] Preferably, the time required to execute the instruction with the reduced computing power level is essentially the same as the time required to execute the instruction with the maximum power level, so that a reduction in the power level of the controller (107) does not adversely affect the performance of the main memory device (103) as a whole.

[0069] Preferably, the computing power level is reduced to an optimized point such that the time required to execute the instruction at the optimized computing power level is shorter than the time required to execute the instruction at any power level lower than the computing power level optimized for the instruction.

[0070] When the instruction is executed at the reduced computing power level of the controller, the total and / or peak energy consumption of the working memory device is lower than when the instruction is executed at the maximum power level.

[0071] The computing power level of the controller (107) can be set via the clock speed of the controller (107), a level of parallel processing, the selection of one of several circuits that have the same function but different compromises between computing power and energy / heating power, etc.

[0072] For example, the controller (107) can be operated at a maximum clock speed, which can be reduced to a reduced clock speed in order to operate with the reduced computing power level with improved energy / heat performance.

[0073] For example, the reduced clock speed can be selected based on the normalized workload level according to a configuration file (113) located in Fig. 2 is illustrated.

[0074] In some implementations, the controller (107) is implemented on a silicon chip that is separate from the silicon chip(s) for the non-volatile memory (109). The silicon chips of the memory device (103) are sealed within the same integrated circuit package of the memory device (103). The controller (107) and the non-volatile memory (109) can operate with different clock signals.

[0075] In some implementations, a temperature sensor is provided in the memory device (103) to determine the temperature of the memory device at the time of instruction. The temperature measurement represents a thermal constraint and can be used to estimate the time required to access the non-volatile memory during instruction execution without overheating the memory device (103) beyond a threshold.

[0076] Preferably, the workload level is determined as a function of the estimated lengths of the time span for accessing the non-volatile memory (109) for a data record identified by the instruction (111) and an estimated number of calculations to be performed by the controller (107) during the execution of the instruction (111), based at least partially on one of the following: the positions of a data record to be stored in or retrieved from the non-volatile memory (109); whether the data record is located on a contiguous address block; whether the data record is located in the same memory chip; and / or the size of the data record.

[0077] A non-transitory computer data storage medium can be used to store instructions for the firmware (104). When the instructions are executed by the controller (107) of the computer memory device (103), the instructions cause the controller (107) to execute any of the procedures discussed above.

[0078] For the sake of simplicity, this description may include various functions and processes that are executed or caused by computer instructions. However, those skilled in the art will recognize that such expressions mean that the functions result from the execution of the computer instructions by one or more controllers or processors, such as a microprocessor. Alternatively, or in combination, the functions and processes can be implemented using special circuits with or without software instructions, for example, application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs). Embodiments can be implemented with hard-wired circuits without software instructions or in combination with software instructions.Thus, the techniques are not limited to a specific combination of hardware circuits and software, nor to a specific source of instructions executed by the data processing system.

[0079] While some embodiments can be implemented in fully functional computers and computer systems, various embodiments can be distributed as a computer product in a variety of forms and can be used regardless of the specific type of machine or computer-readable media used to actually carry out the distribution.

[0080] At least some of the disclosed aspects can be implemented, at least partially, in software. That is, the techniques can be executed in a computer system or other data processing system in response to its processor, such as a microprocessor or microcontroller, which executes sequences of instructions contained in a working memory, such as ROM, volatile RAM, non-volatile memory, cache, or a remote data storage device.

[0081] Routines executed to implement the embodiments can be implemented as part of an operating system or a specific application, component, program, object, module, or sequence of instructions, referred to as "computer programs." Computer programs typically comprise one or more instructions that are stored at different times in various memory and data storage devices of a computer and that, when read and executed by one or more processors in a computer, cause the computer to perform operations necessary to execute elements related to the various aspects.

[0082] A physical, non-transient computer data storage medium can be used to store software and data that, when executed by a data processing system, cause the system to perform various procedures. The executable software and data can be stored in various locations, such as ROM, volatile RAM, non-volatile memory, and / or cache. Portions of this software and / or data can be stored in any one of these data storage devices. Furthermore, the data and instructions can be obtained from centralized servers or peer-to-peer networks. Different portions of the data and instructions can be obtained from different centralized servers and / or peer-to-peer networks at different times and in different communication sessions, or even within the same communication session.The data and instructions can be obtained in their entirety before the applications are executed. Alternatively, parts of the data and instructions can be obtained dynamically and on schedule as needed for execution. Therefore, it is not necessary for the data and instructions to be completely available on a machine-readable medium at any given time.

[0083] Examples of computer-readable data storage media include writable and non-writable media such as volatile and non-volatile memory devices, read-only memory (ROM), random access memory (RAM), flash memory devices, floppy disks and other removable media, magnetic disk storage media, and optical data storage media (e.g., Compact Disc Read-Only Memory (CD-ROM), Digital Versatile Discs (DVD), etc.). Instructions can be implemented in a transitory medium, such as electrical, optical, acoustic, or other forms of transmitted signals, like carrier waves, infrared signals, digital signals, etc. A transitory medium is typically used to transmit instructions but cannot store them.

[0084] In various embodiments, hard-wired circuits can be used in combination with software instructions to implement the techniques. Thus, the techniques are not limited to a specific combination of hardware circuits and software, nor to a specific source for the instructions executed by the data processing system.

[0085] Although some of the drawings illustrate a series of operations in a specific sequence, operations that are not dependent on the sequence can be rearranged, and other operations can be combined or removed. While some rearrangements or other groupings are specifically mentioned, others are obvious to a person skilled in the art and therefore do not constitute an exhaustive list of alternatives. Furthermore, it is understood that the stages could be implemented in hardware, firmware, software, or any combination thereof.

Claims

[1] Working memory device (103), comprising: a non-volatile memory (109); a communication interface (105) for receiving a command (111) for accessing the non-volatile memory (109) of the memory device (103); and a controller (107) configured to do the following: Determining a workload level (121, 123, 125) by the command (111) to be executed by the controller (107) executing the command (111), based on the determination of a command type to be executed by the controller (107), wherein the command (111) specifies the command type; Selecting a computational power level (131, 133, 135) of the controller (107) according to the workload level (121, 123, 125); and Setting the controller (107) to the computing power level (131, 133, 135) during the execution of the command (111). [2] Working memory device (103) according to claim 1, wherein the computing power level (131, 133, 135) includes a clock speed according to which the controller (107) performs operations; and the controller (107) is located in a first silicon chip; and the non-volatile working memory (109) is located in one or more second silicon chips. [3] Memory device (103) according to claim 2, wherein the first silicon chip and the one or more second silicon chips are configured within the same integrated circuit housing of the memory device (103). [4] Working memory device (103) according to claim 2, wherein the control (107) and the non-volatile working memory (109) operate with different clock signals. [5] Memory device (103) according to claim 1, wherein the workload level (121, 123, 125) is normalized with respect to an estimated time used for accessing the non-volatile memory (109) during the execution of the instruction (111). [6] Working memory device (103) according to claim 5, wherein the workload level (121, 123, 125) is proportional to an estimated number of calculations to be performed by the controller (107) during the execution of the instruction (111) and inversely proportional to the estimated time used to access the non-volatile working memory (109) during the execution of the instruction (111). [7] Working memory device (103) according to claim 6, wherein the computing power level (131, 133, 135) is reduced from a maximum power level of the controller (107); and [8] Working memory device (103) according to claim 7, wherein a time interval for the execution of the instruction (111) at the computational power level (131, 133, 135) is essentially the same as a time interval for the execution of the instruction (111) at the maximum power level. [9] Working memory device (103) according to claim 8, wherein a time interval for the execution of the instruction (111) with the computational power level (131, 133, 135) is shorter than a time interval for the execution of the instruction (111) with a power level that is lower than the computational power level (131, 133, 135). [10] Working memory device (103) according to claim 8, wherein the working memory device (103) consumes less energy for the execution of the instruction (111) with the computing power level (131, 133, 135) of the controller (107) than with the maximum power level. [11] Memory device (103) according to claim 8, wherein the memory device (103) consumes less peak energy during the execution of the instruction (111) at the computing power level (131, 133, 135) of the controller (107) than at the maximum power level; and the computing power level (131, 133, 135) corresponds to the operation of the controller (107) at a first clock speed; and the maximum power level corresponds to the operation of the controller (107) at a second clock speed that is higher than the first clock speed. [12] Working memory device (103) according to claim 7, further comprising: a temperature sensor to determine the temperature of the working memory device (103) at the time of the command (111); where the estimated time used to access non-volatile memory (109) during the execution of instruction (111) is estimated based on the temperature. [13] Working memory device (103) according to claim 1, wherein the working memory device (103) is one of the following: a solid-state drive; a replaceable memory card; and an embedded universal flash memory chip. [14] Method implemented in a working memory device (103), the method comprising: Receiving a command (111) to access a non-volatile memory (109) of the memory device (103); and in response to order (111): Determining a workload level (121, 123, 125) by the command (111) to be executed, a controller (107) executing the command (111), based on the determination of a feature of a data set identified by the command (111) and based on an operation to be performed by the controller (107); Selecting a computational power level (131, 133, 135) of the controller (107) according to the workload level (121, 123, 125); and Setting the controller (107) to the computing power level (131, 133, 135) during the execution of the command (111). [15] Method according to claim 14, wherein workload level (121, 123, 125) is determined based on the following: an estimated time used to access non-volatile memory (109) during the execution of the instruction (111); and an estimated number of calculations that the controller (107) performs during the execution of the command (111); wherein the workload level (121, 123, 125) is determined based on an instruction type and the instruction data (111); and where the workload level (121, 123, 125) is at least partially based on one of the following: Positions of a data set to be stored in or retrieved from the non-volatile memory (109); a size of the data set; and whether the data record is located on a continuous address block or not.

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