SEMICONDUCTOR DEVICE

Abstract

A semiconductor device (100) having a transistor section (70) and a diode section (80), the semiconductor device (100) comprising: a gate metal layer (50) provided over an upper surface of a semiconductor substrate (10); an emitter electrode (52) provided over the upper surface of the semiconductor substrate (10); an emitter region (12) of the first conductivity type provided on the upper surface side of the semiconductor substrate (10) in the transistor section (70); a gate trench portion (40) provided on the upper surface side of the semiconductor substrate (10) in the transistor portion (70), electrically connected to the gate metal layer (50) and in contact with the emitter region (12); an emitter trench portion (60) provided on the upper surface side of the semiconductor substrate (10) in the diode portion (80) and electrically connected to the emitter electrode (52); a dummy trench portion (30) provided on the upper surface side of the semiconductor substrate (10), electrically connected to the gate metal layer (50) and not in contact with the emitter region (12); and a boundary region (81) formed in a region where the transistor portion (70) and the diode portion (80) are adjacent to each other and provided so as to prevent interference between the transistor portion (70) and the diode portion (80), wherein the dummy trench portion is provided in a non-boundary region (83) of the transistor portion or the diode portion.

Description

Background1. Technical area

[0001] The present invention relates to a semiconductor device. 2. State of the art

[0002] In the prior art, a semiconductor device including a transistor section and a diode section is known (see, for example, Patent Documents 1 and 4 to 7). A semiconductor device including a current detection section is also known (see, for example, Patent Documents 2 and 3). Patent document 1: WO 2015 / 068 203 A1 Patent Document 2: Japanese Patent Application Publication JP 2015 - 179 705 A Patent Document 3: Japanese Patent Application Publication JP H10 - 107 282 A Patent document 4: US 2009 / 0 001 411 A1 Patent document 5: JP 2013 - 021 104 A Patent document 6: DE 11 2011 105 319 T5 Patent document 7: US 2017 / 0 236 908 A1

[0003] In the semiconductor device, it is required to improve an element breakdown strength by reducing the influence of noise or reducing the current concentration. General Revelation

[0004] A first aspect of the present invention provides a semiconductor device according to claim 1. A second aspect of the present invention provides a semiconductor device according to claim 2. A third aspect of the present invention provides a semiconductor device according to claim 3. A fourth aspect of the present invention provides a semiconductor device according to claim 4. A fifth aspect of the present invention provides a semiconductor device according to claim 5. A sixth aspect of the present invention provides a semiconductor device according to claim 6. A seventh aspect of the present invention provides a semiconductor device according to claim 7. An eighth aspect of the present invention provides a semiconductor device according to claim 8.

[0005] The semiconductor device may further include a boundary region formed in a region where the transistor portion and the diode portion are adjacent, and provided to prevent interference between the transistor portion and the diode portion. The dummy trench portion may be disposed in the boundary region.

[0006] The dummy trench portion may also be provided in a non-boundary region of the transistor portion or the diode portion.

[0007] The semiconductor device may further include a boundary region formed in a region where the transistor portion and the diode portion are adjacent, and provided to prevent interference between the transistor portion and the diode portion. The dummy trench portion may be provided in a non-boundary region of the transistor portion or the diode portion.

[0008] The transistor portion may have an edge adjacent region adjacent to an edge termination region. The dummy trench portion may be provided in the edge adjacent region.

[0009] If a number of gate trench sections is denoted as G and a number of blind trench sections as D, a relationship 0.01 <D / (D+G)<0,2 erfüllt sein.

[0010] The gate trench portion, the emitter trench portion, and the dummy trench portion may be aligned in a preset alignment direction. A width of the diode portion in the alignment direction may be larger than a width of the transistor portion in the alignment direction.

[0011] The semiconductor device may further include a surface lifetime limiter incorporated in a non-boundary region of at least the diode portion on the upper surface side of the semiconductor substrate, and a first conductivity type cathode region in the diode portion on a lower surface side of the semiconductor substrate. The cathode region may extend further toward the transistor portion than the surface lifetime limiter.

[0012] The semiconductor device may further comprise, on the upper side surface of the semiconductor substrate in the transistor portion, a first conductivity type accumulation region having a higher concentration than the emitter region. The accumulation region may not be provided in a mesa portion adjacent to the dummy trench portion.

[0013] The semiconductor device may further include a first conductivity type drift region provided in the semiconductor substrate. A mesa portion adjacent to the dummy trench portion may include a second conductivity type contact region provided on the upper surface side of the semiconductor substrate and a second conductivity type base region provided between the drift region and the contact region. The contact region may have a higher doping concentration than the base region.

[0014] A film thickness of a dummy insulation film of the dummy trench portion may be smaller than a gate insulation film of the gate trench portion and an emitter insulation film of the emitter trench portion.

[0015] A trench depth of the blind trench portion may be greater than a trench depth of the gate trench portion and a trench depth of the emitter trench portion.

[0016] The semiconductor device may include a current sensing portion. The gate trench portion, the emitter trench portion, and the dummy trench portion may each be aligned in a preset alignment direction on the upper surface side of the semiconductor substrate. A gate-emitter ratio obtained by dividing a number of gate trench portions included in a unit length in the alignment direction by a number of emitter trench portions may be larger in the current sensing portion than in the transistor portion.

[0017] A second aspect of the present invention provides a semiconductor device having a transistor portion and a current detection portion. The semiconductor device may include a gate wire portion provided over an upper surface of the semiconductor substrate. The semiconductor device may include an emitter electrode provided over the upper surface of the semiconductor substrate. The semiconductor device may include a plurality of trench portions aligned in a preset alignment direction on the upper surface side of the semiconductor substrate. The trench portions may include a gate trench portion electrically connected to the gate wire portion. The trench portions may include an emitter trench portion electrically connected to the emitter electrode.A gate-emitter ratio obtained by dividing a number of the gate trench portions included in a unit length of the alignment direction by the number of the emitter trench portions may be larger in the current portion than in the transistor portion.

[0018] Both the gate trench section and the emitter trench section may be arranged in the transistor section. In the current sensing section, the gate trench section may be arranged and the emitter trench section may not be arranged.

[0019] The semiconductor device may include a first conductivity type drift region provided in the semiconductor substrate. The semiconductor device may include a first conductivity type emitter region provided on the upper surface side of the semiconductor substrate and having a higher doping concentration than the drift region. The semiconductor device may include a first conductivity type accumulation region provided below the emitter region in the semiconductor substrate and having a higher doping concentration than the drift region.In a plane parallel to the upper surface of the semiconductor substrate, an area ratio obtained by dividing an area of ​​the accumulation region included in the current detection section by an area of ​​the emitter region may be smaller than an area ratio obtained by dividing an area of ​​the accumulation region included in the transistor section by an area of ​​the emitter region.

[0020] The transistor section may be provided with both the emitter region and the accumulation region. The current detection section may be provided with the emitter region and not with the accumulation region.

[0021] The gate wire portion may have an opening portion formed to penetrate the gate wire portion from an upper surface to a lower surface. At least a part of the current detection portion may be disposed in a region overlapping with the opening portion.

[0022] The gate wire portion may include a gate metal layer formed of metal and a gate runner formed of a semiconductor with added impurities. The opening portion may be provided in the gate runner.

[0023] The semiconductor device may include a first well region provided to surround the transistor portion in a plane parallel to the upper surface of the semiconductor substrate and formed to be deeper than a range from the upper surface of the semiconductor substrate to a lower end of the trench portion. The semiconductor device may include a second well region provided to surround the current sensing portion in the plane parallel to the upper surface of the semiconductor substrate and formed to be deeper than the range from the upper surface of the semiconductor substrate to the lower end of the trench portion.A shortest distance between the emitter region and the second well region provided in the current sensing section may be larger in the alignment direction than a shortest distance between the emitter region and the first well region provided in the transistor section in the alignment direction.

[0024] A shortest distance between the emitter region and the second well region provided in the current sensing section may be larger in a direction perpendicular to the alignment direction than a shortest distance between the emitter region and the first well region provided in the transistor section in the direction perpendicular to the alignment direction.

[0025] Meanwhile, the summary of the present invention does not necessarily describe all necessary features of the present invention. The present invention may also be a sub-combination of the features described above. Brief description of the drawings Fig. 1A is an example of a plan view showing a semiconductor device 100 according to a first embodiment. Fig. 1B is an example of a cross-sectional view of the semiconductor device 100 according to the first embodiment taken along a line a-a'. Fig. 2A is an example of a plan view showing the semiconductor device 100 according to a second embodiment. Fig. 2B is an example of a cross-sectional view of the semiconductor device 100 according to the second embodiment taken along a line b-b'. Fig. 3 is a modified example of the semiconductor device 100. Fig. 4 is a plan view of a semiconductor device 500 according to a comparative example. Fig. 5 shows an example of an overall chip diagram of the semiconductor device 500. Fig. 6 shows an example of an overall chip diagram of the semiconductor device 100. Fig. Figure 7A is a graph showing a current density distribution. Fig. 7B is a graph showing turn-off waveforms of the semiconductor device 100 and the semiconductor device 500. Fig. Figure 8A shows a conduction current density distribution of a full gate semiconductor device. Fig. 8B shows a conduction current density distribution of a semiconductor device having the emitter trench portions E. Fig. 8C shows a conduction current density distribution of a semiconductor device having the emitter trench portions E. Fig. 8D shows a conduction current density distribution of a semiconductor device having the emitter trench portions E. Fig. 9 shows an example of a configuration of the semiconductor device 100 according to a third embodiment. Fig. 10 shows an example of a configuration of the semiconductor device 100 according to a fourth embodiment. Fig. 11 shows an example of a configuration of the semiconductor device 100 according to a fifth embodiment. Fig. 12 is an example of a plan view showing a semiconductor device 200 according to a sixth embodiment. Fig. 13 shows an example of a cross-sectional view of a transistor section 70. Fig. 14 shows an example of a cross-sectional view of a current detecting section 210. Fig. 15 is an enlarged plan view near an outdoor area 104-2. Fig. 16 is an enlarged plan view near an opening portion 212. Fig. 17 is a plan view showing distances of a second well region 218 and an emitter array region 216. Fig. 18 shows a distance X1s. Fig. 19 shows a distance Y1s. Fig. 20 shows a distance X1t in the transistor section 70. Fig. 21 shows another configuration example of an area A of Fig. 16. Fig. 22 shows a distance Y1t in the transistor section 70. Description of exemplary embodiments

[0026] Embodiments of the present invention are described below. The embodiments do not limit the invention according to the claims. Furthermore, not all feature combinations described in the embodiments are necessarily essential for solvents of the invention.

[0027] As used herein, one side in a direction parallel to a depth direction of a semiconductor substrate is referred to as "top" and the other side as "bottom." One of two main surfaces of a substrate, layer, or other member is referred to as an upper surface, and the other surface is referred to as a lower surface. The "top," "bottom," "surface," and "back" directions are not limited to a direction of gravity or a mounting direction of a semiconductor device on a substrate, and the like.

[0028] As used herein, a technical matter can be described using orthogonal coordinate axes: X-axis, Y-axis, and Z-axis. As used herein, a plane parallel to a top surface of the semiconductor substrate is referred to as an XY plane, and a depth direction of the semiconductor substrate is defined as the Z-axis. Meanwhile, a case where the semiconductor substrate is viewed from the Z-axis direction is referred to as "viewed from above" as used herein.

[0029] In each embodiment, an example is shown in which a first conductivity type is N-type and a second conductivity type is P-type; however, the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layers, regions, and the like are reversed in each embodiment.

[0030] As used herein, layers and regions with "n" or "p" added to their respective head end indicate that the majority carriers of the respective layers and regions are electrons or holes. "+" and "-" appended to "n" and "p" mean that the doping concentrations are higher or lower, respectively, than those of layers and regions without "+" and "-".

[0031] Fig. 1A shows an example of a configuration of a semiconductor device 100 according to a first embodiment. The semiconductor device 100 of the present example is a semiconductor chip including a transistor section 70 and a diode section 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT).

[0032] The transistor section 70 is a region including emitter regions 12 and gate trench sections 40. The transistor section 70 of the present example is a region in which a collector region provided on a lower surface side of a semiconductor substrate 10 is projected onto an upper surface of the semiconductor substrate 10, but is not limited thereto. The collector region has a second conductivity type. The collector region of the present example is, for example, a P+ type. The transistor section 70 includes transistors such as IGBTs.

[0033] The diode portion 80 includes diodes such as a freewheeling diode (FWD) provided near the transistor portion 70 on the upper surface of the semiconductor substrate 10. The diode portion 80 of the present example is a region where a cathode region 82 is projected onto the upper surface of the semiconductor substrate 10, and is a region excluding the transistor portion 70, but is not limited thereto.

[0034] In Fig. 1A shows a region around a chip end portion, which is an edge side of the semiconductor device 100, and the other regions are not shown. In the present example, for simplicity, an edge on a negative side in the X-axis direction is described. However, the other edges of the semiconductor device 100 are also similar.

[0035] The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a nitride semiconductor substrate such as a gallium nitride substrate, or the like. The semiconductor substrate 10 of the present example is a silicon substrate.

[0036] The semiconductor device 100 of the present example includes gate trench portions 40, dummy trench portions 30, emitter trench portions 60, a well region 11, emitter regions 12, base regions 14, and contact regions 15 on the upper surface side of the semiconductor substrate 10. The overall chip diagram 100 of the present example also includes an emitter electrode 52 and a gate metal layer 50 provided over the upper surface of the semiconductor device 10.

[0037] The emitter electrode 52 and the gate metal layer 50 are formed from materials containing metal. For example, at least a portion of the emitter electrode 52 may be formed from aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. At least a portion of the gate metal layer 50 may be formed from aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The emitter electrode 52 and the gate metal layer 50 may include a barrier metal formed from titanium or a titanium compound in a layer underlying the portion formed from aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided insulated from each other.

[0038] The emitter electrode 52 and the gate metal layer 50 are provided over the semiconductor substrate 10 with an interlayer dielectric film disposed therebetween. Fig. In Figure 1A, the interlayer dielectric film is omitted. The interlayer dielectric film is provided with a contact hole 49, contact holes 54, and contact holes 56 penetrating it.

[0039] The contact hole 49 is formed to connect the gate metal layer 50 and a gate slider 48. A plug made of tungsten or the like may be formed in the contact hole 49.

[0040] The gate runner 48 is formed to connect the gate metal layer 50 and the gate trench portion 40 of the transistor portion 70. As an example, the gate runner 48 is connected to a gate wiring portion in the gate trench portion 40 and a dummy wiring portion in the dummy trench portion 30 on the upper surface side of the semiconductor substrate 10. The gate runner 48 is not connected to an emitter wiring portion in the emitter trench portion 60. For example, the gate runner 48 is formed of impurity-doped polysilicon. The gate metal layer 50 and the gate runner 48 are examples of the gate wire portion.

[0041] The gate runner 48 of the present example is provided from below the contact hole 49 to a tip end portion of the gate trench portion 40. An interlayer dielectric film such as an oxide film is provided between the gate runner 48 and the upper surface of the semiconductor substrate 10. At the tip end portion of the gate trench portion 40, the gate conductive portion is exposed to the upper surface of the semiconductor substrate 10. The gate trench portion 40 is in contact with the gate runner 48 on the exposed part of the gate conductive portion.

[0042] The contact hole 56 is formed to connect the emitter electrode 52 and the emitter line portion in the emitter trench portion 60. A plug formed of tungsten or the like may be provided in the contact hole 56.

[0043] A connecting portion 25 is provided between the emitter electrode 52 and the emitter line portion. The connecting portion 25 is formed of a conductive material such as impurity-doped polysilicon. The connecting portion 25 is provided above the upper surface of the semiconductor substrate 10, with an interlayer dielectric film such as an oxide film interposed therebetween.

[0044] The gate trench portions 40 are aligned at predetermined intervals in a preset alignment direction (in the present example, the Y-axis direction). The gate trench portion 40 of the present example may include two extension parts 41 extending in an extension direction (in the present example, the X-axis direction) parallel to the top surface of the semiconductor substrate 10 and perpendicular to the alignment direction, and a connecting part 43 connecting the two extension parts 41. The gate trench portion 40 of the present example is electrically connected to the gate metal layer 50. Furthermore, the gate trench portion 40 is in contact with the emitter region 12.

[0045] At least a portion of the connecting part 43 is preferably formed in a curved shape. End portions of the two extension parts 41 of the gate trench portion 40 are connected to reduce the electric field concentration at the end portions of the extension parts 41. The gate runner 48 may be connected to the gate line portion at the connecting part 43 of the gate trench portion 40.

[0046] The dummy trench portions 30 are aligned at predetermined intervals in a preset alignment direction (Y-axis direction in the present example) like the gate trench portions 40. The dummy trench portion 30 of the present example may have a U-shape on the upper surface side of the semiconductor substrate 10, like the gate trench portion 40. That is, the dummy trench portion 30 may include two extension parts 31 extending in one extension direction and a connecting part 33 connecting the two extension parts 31. The dummy trench portion 30 is electrically connected to the gate metal layer 50. However, the dummy trench portion 30 differs from the gate trench portion 40 in that it does not contact the emitter region 12.For example, the semiconductor device 100 may adjust the capacitance between the gate and the emitter by adjusting a ratio of the gate trench portions 40 and the dummy trench portions 30.

[0047] The emitter trench portions 60 are aligned at predetermined intervals in a preset alignment direction (Y-axis direction in the present example) like the gate trench portions 40. The emitter trench portion 60 of the present example may have a U-shape on the upper surface side of the semiconductor substrate 10, like the gate trench portion 40. That is, the emitter trench portion 60 may include two extension parts 61 extending in one extension direction and a connecting part 63 connecting the two extension parts 61. The trench portion 60 is electrically connected to the emitter electrode 52. For example, the emitter trench portion 60 is provided in the diode portion 80, so that it is difficult to deflect the potential around the emitter trench portion 60.

[0048] The emitter electrode 52 is provided over the gate trench portions 40, the dummy trench portions 30, the emitter trench portions 60, the well region 11, the emitter regions 12, the base regions 14, and the contact regions 15.

[0049] The well region 11 is a second conductivity type region provided on the upper surface side of the semiconductor substrate 10 with respect to a drift region 18 described later. The well region 11 is, for example, of a P+ type. The well region 11 is provided within a preset range from an end portion of an active area of ​​a side on which the gate metal layer 50 is provided. A diffusion depth of the well region 11 may be greater than the depths of the gate trench portion 40, the dummy trench portion 30, and the emitter trench portion 60. Partial regions of the gate trench portion 40, the dummy trench portion 30, and the emitter trench portion 60 on the gate metal layer 50 side are provided in the well region 11.The bottom surfaces of the ends of the gate trench portion 40, the dummy trench portion 30 and the emitter trench portion 60 in the extension direction may be covered by the well region 11.

[0050] The contact hole 54 is formed over each of the emitter region 12 and the contact region 15 in the transistor section 70. Furthermore, the contact hole 54 is formed over the base region 14 in the diode section 80. In this way, the interlayer dielectric film is formed with one or more contact holes 54. One or more contact holes 54 may be formed with openings extending in the extension direction. In the first embodiment, the contact region 15 is provided on the upper surface of the boundary region 81. However, like the diode section 80, the base region 14 may be provided on the upper surface of the boundary region 81. This is not limited to the first embodiment and applies to the second to fifth embodiments described later.

[0051] The boundary region 81 is provided in a region where the transistor section 70 and the diode section 80 are adjacent to each other. As used herein, the boundary region 81 is provided in a region where the transistor section 70 and the diode section 80 are adjacent to each other to prevent interference between them. Specifically, the boundary region 81 has a device structure different from a device structure (so-called MOS structure) of the transistor section 70 and a device structure of the diode, such as a freewheeling diode, of the diode section 80.Therefore, the boundary region 81 has a device structure different from a device structure of the transistor section 70 and a device structure of the diode section 80, and may be set as a region positioned between a device structure in which a channel of the transistor section 70 is formed and a device structure of the diode of the diode section 80 in the alignment direction of the trench sections.

[0052] The device structure of the boundary region 81, which differs from a device structure of the transistor section 70 and a device structure of the diode section 80, refers, for example, to a region having a device structure that differs from the transistor section 70 and the diode section 80 with respect to the emitter region 12, the contact region 15, the accumulation region 16, the trench section, the depth of the trench section, and / or a lifetime limiter, a buffer region 20, a cathode region 82, and a collector region 22, which will be described later. As a difference in the structure of the trench section, a deviation from any periodic structure (repeating structure) of the trench section of the transistor section 70 and the trench section of the diode section 80 can be exemplified.As the example, the device structure different from a device structure of the transistor section 70 and a device structure of the diode section 80 is not only focused on a single region (for example, between the single trench) of the transistor section 70 or the diode section 80, and may be a region different from a pattern of the periodic structure (repeating structure) of the transistor section 70 or the diode section 80 even if it is focused on the periodic structure.

[0053] The boundary region 81 may also be in a range from 10 µm to 100 µm or from 50 µm to 100 µm. For example, a base point of the length of the boundary region 81 may be the gate trench portion 40 in which a channel of the transistor portion 70 is formed, and a range from the gate trench portion 40 to a point of 10 µm to 100 µm toward the diode portion 80 may be defined as the boundary region 81.

[0054] A thickness of the semiconductor substrate 10 may be determined depending on a withstand voltage of the semiconductor device 100, and a width of the boundary region 81 in the Y-axis direction may be determined depending on the thickness of the semiconductor substrate 10. Specifically, a configuration may be made such that the higher the withstand voltage of the semiconductor device 100, the wider the width of the boundary region 81 in the Y-axis direction. Furthermore, the width of the boundary region 81 in the Y-axis direction may be determined depending on a flow aspect and an amount of carriers in the semiconductor substrate 10. Specifically, a configuration may be made such that the more carriers are available to flow between the transistor section 70 and the diode section 80 per unit time, the wider the width of the boundary region 81 in the Y-axis direction.It may also be configured such that the width of the boundary region 81 in the Y-axis direction is larger as the amount of carriers in the semiconductor substrate 10 is larger.

[0055] The boundary region 81 may include a plurality of mesa portions. More preferably, the boundary region 81 may include four to ten mesa portions. For example, a base point of the mesa portion of the boundary region 81 may be the gate trench portion 40 in which a channel of the transistor portion 70 is formed, and four to ten mesa portions from the gate trench portion 40 to the diode portion 80 may be set as the boundary region 81. A width of one mesa portion in the Y-axis direction may be approximately 10 μm. A length of the four mesa portions with the three trench portions arranged therebetween in the Y-axis direction may be 50 μm, or a length of the five mesa portions with the four trench portions arranged therebetween in the Y-axis direction may be 50 μm.In addition, a length of the eight mesa sections with the seven trench sections arranged therebetween in the Y-axis direction may be 100 µm, or a length of the ten mesa sections with the nine trench sections arranged therebetween in the Y-axis direction may be 100 µm.

[0056] The boundary region 81 having a structure different from a non-boundary region 83 of the transistor section 70 or the diode section 80 is provided so that it is possible to reduce current interference between the boundary region and the transistor section 70 or the diode section 80. For example, as the width of the boundary region 81 increases in the Y-axis direction, it is possible to more effectively reduce current interference.

[0057] In the first embodiment, the boundary region 81 is provided in the diode section 80. Furthermore, in the first embodiment, the boundary region 81 is a region without the emitter region 12 between the gate trench section 40 and the emitter trench section 60. Since the boundary region 81 has no emitter region 12, it is difficult to snap the semiconductor device 100 into place. The boundary region 81 refers to a region between a region where the gate trench sections 40 of the transistor section 70 are arranged at predetermined intervals in the Y-axis direction and a region where the emitter trench sections 60 of the diode section 80 are arranged at predetermined intervals in the Y-axis direction.

[0058] The non-boundary region 83 is a region except for the boundary region 81 in the transistor section 70 or the diode section 80. In the first embodiment, since the boundary region 81 is provided in the diode section 80, a region except for the boundary region 81 of the diode section 80 is referred to as the non-boundary region 83. In the first embodiment, the non-boundary region 83 is a region having the emitter trench portions 60 in a region different from the boundary region 81. Thus, the non-boundary region 83 includes a region where the emitter trench portions 60 are arranged at predetermined intervals, of the region where the cathode region 82 is projected onto the upper surface of the semiconductor substrate 10. In this case, since the transistor section 70 is not provided with the boundary region 81, the transistor section 70 is entirely a non-boundary region.

[0059] The dummy trench portion 30 is provided in the boundary region 81. However, the dummy trench portion 30 may also be provided in the non-boundary region 83. The dummy trench portion 30 may be provided only in the non-boundary region 83. The boundary region 81 may also be provided with the gate trench portion 40 or the emitter trench portion 60. Meanwhile, one half or more or all of the trench portions positioned within the boundary region 81 may be the dummy trench portions 30.

[0060] A first mesa portion 91, a second mesa portion 92, and a third mesa portion 93 are mesa portions provided near each of the trench portions in the Y-axis direction in a plane parallel to the upper surface of the semiconductor substrate 10. The mesa portion is a part of the semiconductor substrate 10 positioned between the two adjacent trench portions and may be a part extending from the upper surface of the semiconductor substrate 10 to the deepest bottom of each of the trench portions. An extension part of each of the trench portions may be formed as a trench portion. That is, a region positioned between the two extension parts may be formed as the mesa portion.

[0061] The first mesa portion 91 is provided near the gate trench portion 40 and / or the emitter trench portion 60 in the transistor portion 70. Furthermore, the first mesa portion 91 of the present example is provided in the boundary region 81, also near the transistor portion 70. The first mesa portion 91 includes the well region 11, the emitter region 12, the base region 14, and the contact region 15 on the upper surface side of the semiconductor substrate 10. In the first mesa portion 91, the emitter region 12 and the contact region 15 are provided alternately in the extension direction.

[0062] The second mesa portion 92 is a mesa portion provided in the boundary region 81. The second mesa portion 92 includes the well region 11, the base region 14, and the contact region 15 on the upper surface side of the semiconductor substrate 10. In the first embodiment, the second mesa portion 92 does not have the emitter region 12, but may have the emitter region 12. In the first embodiment, the second mesa portion 92 also has the contact region 15, but may not have the contact region 15.

[0063] The third mesa portion 93 is provided in a region positioned between the emitter trench portions 60 adjacent to each other in the diode portion 80. The third mesa portion 93 includes the well region 11 and the base region 14 on the upper surface side of the semiconductor substrate 10.

[0064] The base region 14 is a second conductivity type region provided on the upper surface side of the semiconductor substrate 10. The base region 14 is, for example, of the P-type. The base region 14 may be provided at both end portions of the first mesa portion 91 and the second mesa portion 92 in the X-axis direction on the upper surface side of the semiconductor substrate 10. As shown in Fig. However, as shown in Figure 1B, the base region 14 is provided in the sectional view over a substantially entire area of ​​the active region. Fig. 1A only one end portion of the base region 14 in the X-axis direction.

[0065] The emitter region 12 is provided in contact with the gate trench portion 40 on one side of the upper surface of the first mesa portion 91. The emitter region 12 may be provided in the Y-axis direction from one trench portion of two trench portions extending in the X-axis direction with the first mesa portion 91 therebetween to the other trench portion. The emitter region 12 is also provided below the contact hole 54. The emitter region 12 of the present example is of a first conductivity type. The emitter region 12 is, for example, of the N+ type.

[0066] The contact region 15 is a second conductivity-type region with a higher doping concentration than that of the base region 14. The contact region 15 of the present example is, for example, of the P+ type. The contact region 15 of the present example is provided on the upper surface side of the first mesa portion 91. The contact region 15 may be provided in the Y-axis direction from one trench portion of two trench portions extending in the X-axis direction with the first mesa portion 91 therebetween to the other trench portion. The contact region 15 may or may not be in contact with the gate trench portion 40. The contact region 15 may or may not also be in contact with the emitter trench portion 60. The contact region 15 of the present example is in contact with the dummy trench portion 30 and the gate trench portion 40. The contact region 15 is also provided below the contact hole 54.

[0067] The contact region 15 may also be provided on a top surface side of the second mesa portion 92. An area of ​​the contact region 15 provided on the top surface side of a second mesa portion 92 is larger than an area of ​​the contact region 15 provided on the top surface side of a first mesa portion 91. The contact region 15 provided on the top surface side of a second mesa portion 92 may be provided over an entire area located between the base regions 14 provided at both end portions of the second mesa portion 92 in the X-axis direction.

[0068] The cathode region 82 is a first conductivity type region provided on the lower surface side of the semiconductor substrate 10 in the diode section 80. The cathode region 82 of the present example is of N+ type, for example. A region where the cathode region 82 is provided is shown by the dashed line when viewed from above.

[0069] Fig. 1B is an example of a cross-sectional view taken along a line aa' in Fig. 1A. The cross section aa' is a YZ plane passing through the emitter region 12, the base region 14, and the contact region 15 in the transistor section 70 and the diode section 80. The semiconductor device 100 of the present example includes the semiconductor substrate 10, an interlayer dielectric film 38, the emitter electrode 52, and a collector electrode 24. The emitter electrode 52 is provided on the upper surface of the semiconductor substrate 10 and an upper surface of the interlayer dielectric film 38.

[0070] The drift region 18 is a first conductivity-type region provided in the semiconductor substrate 10. The drift region 18 of the present example is, for example, of the N- type. The drift region 18 may be a remaining region of the semiconductor substrate 10 in which the other doping regions are not formed. That is, a doping concentration of the drift region 18 may be a doping concentration of the semiconductor substrate 10.

[0071] The buffer region 20 is a first conductivity type region provided below the drift region 18. The buffer region 20 of the present example is, for example, of N- type. A doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may serve as a field stop layer configured to prevent a depletion layer extending from the lower surface side of the base region 14 from reaching the second conductivity type collector region 22 and the first conductivity type cathode region 82.

[0072] The collector region 22 is a second conductivity type region provided on the lower surface side of the semiconductor substrate 10 in the transistor section 70. The collector region 22 is, for example, of the P+ type. The collector region 22 of the present example is provided below the buffer region 20.

[0073] The cathode region 82 is provided below the buffer region 20 in the diode section 80. A boundary R is a boundary between the collector region 22 and the cathode region 82. The boundary R may coincide with or be different from a boundary between the transistor section 70 and the diode section 80.

[0074] The collector electrode 24 is formed on a lower surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as metal.

[0075] The accumulation region 16 is a first conductivity type region provided above the drift region 18 in the first mesa portion 91 and the second mesa portion 92. The accumulation region 16 of the present example is of N- type, for example. The accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. A doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. The accumulation region 16 is provided so that it is possible to increase a carrier injection amplification (IE) effect, thereby reducing an on-state voltage of the transistor portion 70. Meanwhile, the accumulation region 16 may be provided in the third mesa portion 93.

[0076] The base region 14 is a second conductivity type region provided above the accumulation region 16 in the first mesa section 91, the second mesa section 92, and the third mesa section 93. The base region 14 is provided in contact with the gate trench section 40. The base region 14 in the third mesa section 93 is a so-called anode region.

[0077] The emitter region 12 is provided between the base region 14 and a top surface 21 in the first mesa section 91. The emitter region 12 is provided in contact with the gate trench section 40. A doping concentration of the emitter region 12 is higher than the doping concentration of the drift region 18. An example of a dopant of the emitter region 12 is arsenic (As). Meanwhile, the emitter region 12 may or may not be provided in the second mesa section 92.

[0078] The contact region 15 is provided above the accumulation region 16 in the first mesa section 91 and the second mesa section 92. The contact region 15 is provided in contact with the gate trench section 40 and the dummy trench section 30 in the first mesa section 91 and the second mesa section 92.

[0079] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the upper surface 21 side. Each of the trench portions is provided from the upper surface 21 to the drift region 18. In the region where the emitter region 12, the base region 14, the contact region 15, and / or the accumulation region 16 are provided, each of the trench portions reaches the drift region 18 through the regions. The configuration "the trench portion passes through the impurity region" is not limited to a configuration in which the impurity region is formed and then the trench portion is formed. A configuration in which the trench portions are formed and then the impurity region is formed between the trench portions is also included in the configuration "the trench portion passes through the impurity region."

[0080] The gate trench portion 40 includes a gate trench, a gate insulating film 42, and a gate wiring portion 44 formed on the upper surface 21 side. The gate insulating film 42 is formed to cover an inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding a semiconductor of the inner wall of the gate trench. The gate wiring portion 44 is formed further inside than the gate insulating film 42 within the gate trench. The gate insulating film 42 insulates the gate wiring portion 44 and the semiconductor substrate 10 from each other. The gate wiring portion 44 is made of a conductive material such as polysilicon. The gate trench portion 40 is covered by the interlayer dielectric film 38 on the upper surface 21 side.

[0081] The gate wiring portion 44 includes a region facing the base region 14, which is adjacent to the first mesa portion 91 side, with the gate insulation film 42 interposed therebetween, in a depth direction of the semiconductor substrate 10. When a preset voltage is applied to the gate wiring portion 44, a channel, which is an inversion layer of electrons, is formed in a surface layer of an interface of the base region 14 that is in contact with the gate trench.

[0082] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 includes a dummy trench, a dummy insulation film 32, and a dummy wiring portion 34 formed on the upper surface 21 side. The dummy insulation film 32 is formed to cover an inner wall of the dummy trench. The dummy wiring portion 34 is formed further inside than the dummy insulation film 32 within the dummy trench. The dummy insulation film 32 insulates the dummy wiring portion 34 and the semiconductor substrate 10 from each other. The dummy trench portion 30 is covered by the interlayer dielectric film 38 on the upper surface 21 side.

[0083] The emitter trench portion 60 may have the same structure as the gate trench portion 40 and the dummy trench portion 30. The emitter trench portion 60 includes an emitter trench, an emitter insulating film 62, and an emitter line portion 64 formed on the upper surface 21 side. The emitter insulating film 62 is formed to cover an inner wall of the emitter trench. The emitter line portion 64 is formed further inside than the emitter insulating film 62 within the emitter trench. The emitter insulating film 62 insulates the emitter line portion 64 and the semiconductor substrate 10 from each other. The emitter trench portion 60 is covered by the interlayer dielectric film 38 on the upper surface 21 side.

[0084] The interlayer dielectric film 38 is provided over the upper surface of the semiconductor substrate 10. The interlayer dielectric film 38 has one or more contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. Another contact hole 49 and the contact hole 54 may also be formed to penetrate the interlayer dielectric film 38. The emitter electrode 52 is provided over the interlayer dielectric film 38.

[0085] The semiconductor device 100 of the present example is configured to adjust the capacitance between the gate and the emitter by adjusting a ratio of the gate trench portions 40 and the dummy trench portions 30. The semiconductor device 100 can increase the capacitance between the gate and the emitter by increasing a proportion of the dummy trench portions 30 and decrease the capacitance between the gate and the emitter by decreasing the proportion of the dummy trench portions 30. When a number of the gate trench portions is denoted as G and a number of the dummy trench portions as D, a relationship of 0.01 <D / (D+G)<0,2 erfüllt sein.

[0086] Meanwhile, the number of gate trench portions 40 refers to a number of the extension parts 41. That is, even in a case where the plurality of extension parts 41 are connected by the connecting part 43 and thus one gate trench portion 40 is formed, the number of the plurality of extension parts 41 is actually the number of gate trench portions 40. Therefore, the number of gate trench portions 40 agrees with the number of gate trench portions 40 in the cross section a-a' as shown in Fig. 1B.

[0087] Also, a number of the blind trench portions 30 is the same. That is, even in a case where the plurality of extension parts 31 are connected by the connecting part 33 and thus a blind trench portion 30 is formed, the number of the plurality of extension parts 31 is actually the number of the blind trench portions 30. Therefore, the number of the blind trench portions 30 agrees with the number of the blind trench portions 30 in the cross section a-a' as shown in Fig. 1B.

[0088] Fig. 2A is an example of a plan view showing the semiconductor device 100 according to a second embodiment. Fig. Figure 2B shows an example of a cross-sectional view along a line bb' in Fig. 2A. The semiconductor device 100 of the second embodiment differs from the semiconductor device 100 according to the first embodiment in that the boundary region 81 is provided in the transistor section 70. In the semiconductor device 100 of the second embodiment, since the boundary region 81 is provided in the transistor section 70, a region excluding the boundary region 81 in the transistor section 70 is referred to as a non-boundary region 83. Meanwhile, since the diode section 80 is not provided with the boundary region 81, the diode section 80 is entirely a non-boundary region.

[0089] In the second embodiment, the non-boundary region 83 is a region different from the boundary region 81 and including the gate trench portion 40 and the emitter trench portion 60. The non-boundary region 83 includes a region, where the gate trench portions 40 and the emitter trench portions 60 are arranged at predetermined intervals, of the region where the collector region 22 is projected onto the upper surface of the semiconductor substrate 10.

[0090] The dummy trench portion 30 is provided in the boundary region 81. However, the dummy trench portion 30 may also be provided in the non-boundary region 83. The dummy trench portion 30 may be provided only in the non-boundary region. The boundary region 81 may also be provided with the gate trench portion 40 and the emitter trench portion 60.

[0091] The configuration in which the boundary region 81 is provided in the transistor section 70 means that the cathode region 82 is relatively shorter and the collector region 22 is relatively longer. For this reason, electrons emitted from the emitter region 12 can be easily introduced into the collector region 22, making it possible to lower the forward voltage.

[0092] Meanwhile, the boundary region 81 may be provided above the transistor portion 70 and the diode portion 80. In this case, the transistor portion 70 and the diode portion 80 are each provided with the boundary region 81 except for the non-boundary region 83.

[0093] Fig. 3 is a modified example of the semiconductor device 100. In the semiconductor device 100 of the present modified example, the contact hole 54 is not provided over at least a part of the second mesa portion 92 adjacent to the dummy trench portion 30 in the boundary region 81. In the semiconductor device 100 of the present modified example, the contact hole 54 is not provided over all of the dummy trench portions 30 adjacent to the second mesa portions 92 in the boundary region 81. That is, the second mesa portion adjacent to the dummy trench portion 30 is not electrically connected to the emitter electrode. Meanwhile, the configuration in which the contact hole 54 is not provided over part or all of the mesa portions in the boundary region 81 can be applied to the first and second embodiments and the third to fifth embodiments described later.

[0094] Fig. 4 is a plan view of a semiconductor device 500 according to a comparative example. The semiconductor device 500 of the present comparative example differs from the semiconductor device 100 of the first embodiment in that the dummy trench portion 30 is not provided. The semiconductor device 500 includes a transistor portion 570 and a diode portion 580.

[0095] The semiconductor device 500 has the emitter trench portion 60 on a boundary side of the diode portion 580 with the transistor portion 570. That is, the semiconductor device 500 of the present comparative example is not provided with the dummy trench portion 30 in the boundary region 81. That is, since the trench portions except the gate trench portion 40 are not connected to the gate metal layer 50, the capacitance between the gate and the emitter is reduced compared to the semiconductor device 100 according to the first embodiment.

[0096] Here, when noise occurs in the semiconductor device 500 while the semiconductor device 500 is performing a FWD operation, a potential difference of a threshold voltage Vth or higher is generated, so that the transistor section 570 may be mistakenly turned on. The lower the capacitance between the gate and the emitter, the greater the influence of the noise on the semiconductor device 500. If the transistor section 570 is mistakenly turned on, a short-circuit current flows, so that a short-circuit mode is entered during a reverse recovery operation, so that the semiconductor device 500 may be destroyed.

[0097] On the other hand, since the semiconductor device 100 includes the dummy trench portions 30, the capacitance between the gate and the emitter increases. Therefore, even when noise occurs in the semiconductor device 100, it is difficult to mistakenly turn on the transistor portion 70. In this way, the configuration in which the dummy trench portions 30 are provided corresponds to a configuration in which a noise suppression capacitor is provided. This reduces the influence of noise on the semiconductor device 100.

[0098] Fig. 5 shows an example of an overall chip diagram of the semiconductor device 500 according to the comparative example. The semiconductor device 500 of the present comparative example includes a plurality of transistor sections 570 and a plurality of diode sections 580.

[0099] In the semiconductor device 500 of the present comparative example, a width Wd of the diode section 580 in the Y-axis direction is smaller than a width Wt of the transistor section 570 in the Y-axis direction. Furthermore, in the present comparative example, a width of the transistor section 570 in the X-axis direction is equal to a width of the diode section 580 in the X-axis direction. A total area of ​​the plurality of diode sections 580 is smaller than a total area of ​​the plurality of transistor sections 570.

[0100] During a switching operation in the semiconductor device 500, the current on the transistor section 570 side may gradually be concentrated on the diode section 580 side. In this case, heat is generated locally, and the semiconductor device 500 may be destroyed. While the current flows smoothly during a turn-off operation, the current tends to flow in this manner and concentrates toward the cathode region over time. In the semiconductor device 500, heat generation due to current concentration is notable because the width Wd of the diode section 580 in the Y-axis direction is smaller than the width Wt of the transistor section 570 in the Y-axis direction. In particular, when the switching operation is performed with a high current density, the semiconductor device 500 may be destroyed.

[0101] Fig. 6 shows an example of an overall chip diagram of the semiconductor device 100. The semiconductor device 100 of the present example includes a plurality of transistor sections 70 and a plurality of diode sections 80. The semiconductor device 100 includes an edge termination region 102 and an outer region 104 at outer sides of the active region in which the transistor sections 70 and the diode sections 80 are provided.

[0102] The edge termination region 102 reduces the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination region 102 includes, for example, a guard ring, a field plate, a RESURF, and a combination thereof.

[0103] The outer region 104 is provided near the transistor sections 70 and the diode sections 80. The outer region 104 includes, for example, a gate pad, a sensing section, and a temperature sensing section.

[0104] The semiconductor device 100 of the present example includes the fifteen transistor sections 70 and the twelve diode sections 80. In the semiconductor device 100 of the present example, a width Wd of the diode section 80 in the Y-axis direction is greater than or equal to a width Wt of the transistor section 70 in the Y-axis direction, and is preferably greater than the width Wt in the Y-axis direction. For example, the width Wd of the diode section 80 in the Y-axis direction may be 500 µm or more, 1000 µm or more, or 1500 µm or more. In the present example, moreover, a width of the transistor section 70 in the X-axis direction is equal to a width of the diode section 80 in the X-axis direction. In the semiconductor device 100 of the present example, a total area of ​​the diode sections 80 is greater than or equal to a total area of ​​the transistor sections 70, and is preferably larger than the total area of ​​the transistor sections 70.

[0105] In the semiconductor device 100 of the present example, since the width Wd of the diode portion 80 in the Y-axis direction is greater than or equal to the width Wt of the transistor portion 70 in the Y-axis direction, the current flowing in the transistor portion 70 also flows in the cathode region 82 of the diode portion 80, making it possible to reduce the current concentration. Therefore, the current concentration is reduced, making it difficult to destroy the semiconductor device 100 of the present example.

[0106] The total area of ​​the diode sections 80 may be 1.2 times, 1.5 times, or 2.0 times larger than the total area of ​​the transistor sections 70. A ratio of the total area of ​​the transistor sections 70 to the total area of ​​the diode sections 80 is set from the standpoint of a trade-off between conduction loss and current concentration of the semiconductor device 100. That is, as the total area of ​​the transistor sections 70 increases, conduction loss tends to decrease. Conversely, as the total area of ​​the diode sections 80 increases, current concentration tends to decrease.

[0107] When the semiconductor device 100 includes the diode portions 80 with a total area equal to or greater than the total area of ​​the transistor portions 70, the capacitance between the gate and the emitter is reduced compared to a case where the total area of ​​the diode portions 80 is smaller than the total area of ​​the transistor portions 70. However, in the semiconductor device 100 of the present example, the dummy trench portion 30 is provided in the boundary region 81, so that the capacitance between the gate and the emitter can be suppressed.

[0108] Meanwhile, in a case where the semiconductor device 100 has a fixed size of a semiconductor chip, the number of the transistor sections 70 and the diode sections 80 may be reduced, and at the same time, the total area of ​​the diode sections 80 may be set to be greater than or equal to the total area of ​​the transistor sections 70. This reduces the current loss by forming an interface region between the transistor section 70 and the diode section 80, that is, by reducing the boundary region 81 for preventing interference between the transistor section 70 and the diode section 80.

[0109] The semiconductor device 100 of the present example has more transistor sections 70 than diode sections 80 in the Y-axis direction. Therefore, the transistor sections 70 are arranged at both ends in the Y-axis direction. The transistor sections 70 are provided at both ends in the Y-axis direction, so current concentration hardly occurs in the diode section 80.

[0110] For example, the semiconductor device 100 of the present example includes the five transistor sections 70 and the four diode sections 80 in the Y-axis direction. However, the number of the transistor sections 70 and the diode sections 80 in the Y-axis direction is not limited thereto. For example, the numbers of the transistor sections 70 and the diode sections 80 may be four and three, three and two, or two and one. Also, the numbers of the transistor sections 70 and the diode sections 80 may be six and five, seven and six, or eight and seven. Meanwhile, the numbers of the transistor sections 70 and the diode sections 80 in the Y-axis direction may be the same.

[0111] The semiconductor device 100 also includes three rows of transistor sections 70 and diode sections 80 in the X-axis direction. However, the number of rows of transistor sections 70 and diode sections 80 in the X-axis direction is not limited thereto. For example, the number of rows of transistor sections 70 and diode sections 80 in the X-axis direction may be one row, two rows, four rows, or five rows or more.

[0112] Fig. Figure 7A is a graph showing a current density distribution. A vertical axis indicates the current density [A / cm 2 ] and a horizontal axis indicates any position along the Y-axis.

[0113] A distribution D1 indicates the current density distribution when using the semiconductor device 100. In the semiconductor device 100 of the present example, the ratio of the total area of ​​the transistor sections 70 to the total area of ​​the diode sections 80 is 20:40. That is, the total area of ​​the diode sections 80 corresponds to approximately 66% of a total area of ​​the transistor sections 70 and the diode sections 80.

[0114] A distribution D2 indicates the current density distribution when using the semiconductor device 100. In the semiconductor device 100 of the present example, the ratio of the total area of ​​the transistor sections 70 to the total area of ​​the diode sections 80 is 20:20. That is, the total area of ​​the diode sections 80 is 50% of the total area of ​​the transistor sections 70 and the diode sections 80.

[0115] A distribution D3 indicates the current density distribution when using the semiconductor device 500. In the semiconductor device 500 of the present example, the ratio of the total area of ​​the transistor sections 570 to the total area of ​​the diode sections 580 is 20:6. That is, the total area of ​​the diode sections 580 is approximately 23% of the total area of ​​the transistor sections 570 and the diode sections 580.

[0116] Comparing distribution D1 with distribution D3, a maximum current density value decreases with increasing proportion of diode sections 80. That is, semiconductor device 100 can reduce the maximum current density value by setting the total area of ​​diode sections 80 greater than or equal to the total area of ​​transistor sections 70.

[0117] Fig. 7B is a graph showing turn-off waveforms of the semiconductor device 100 and the semiconductor device 500. The graph shows changes in the collector current Ic [A / cm 2 ] and the voltage Vce between the collector and the emitter over time. The collector current Ic of the semiconductor device 100 is higher than the collector current Ic of the semiconductor device 500. That is, the semiconductor device 100 can implement the switching operation with a higher current density than the semiconductor device 500 because the width of the diode section 80 is set larger than the width of the transistor section 70.

[0118] Fig. 8A to 8D are views for comparing the conduction current density distributions when the ratio of the gate trench portions G and the emitter trench portions E is changed. A vertical axis indicates the conduction current density [A / cm 2], and a horizontal axis indicates positions in the Y-axis direction near the transistor portion and the diode portion. The gate trench portion G is a trench portion electrically connected to the gate metal layer 50 and provided in contact with the emitter region 12. The emitter trench portion E is a trench portion electrically connected to the emitter electrode 52.

[0119] Fig. 8A shows a conduction current density distribution of a full-gate semiconductor device. In the semiconductor device of the present example, all the trench portions are gate trench portions G. That is, in the semiconductor device of the present example, all the trench portions are electrically connected to the gate metal layer 50.

[0120] Fig. 8B shows a conduction current density distribution of a semiconductor device having emitter trench portions E. In the semiconductor device of the present example, the ratio of the gate trench portions G to the emitter trench portions E is 2:1. That is, in the semiconductor device of the present example, the number of gate trench portions G is greater than the number of emitter trench portions E.

[0121] Fig. 8C shows a conduction current density distribution of a semiconductor device having the emitter trench portions E. In the semiconductor device 500 of the present example, the ratio of the gate trench portions G to the emitter trench portions E is 1:1. That is, in the semiconductor device of the present example, the number of gate trench portions G is equal to the number of emitter trench portions E.

[0122] Fig. 8D shows a conduction current density distribution of the semiconductor device having the emitter trench portions E. In the semiconductor device 500 of the present example, the ratio of the gate trench portions G to the emitter trench portions E is 1:2. That is, in the semiconductor device of the present example, the number of gate trench portions G is smaller than the number of emitter trench portions E.

[0123] Referring to the conduction current density distributions of Fig. 8A to 8D, when the proportion of the emitter trench portions E is increased compared to the gate trench portions G, the conduction current density distribution tends to be increased. For example, the conduction current density distribution of Fig. 8A, compared to the other examples, tend to be localized in a specific area. As the proportion of emitter trench sections E is increased, the channel area is also reduced, so the maximum conduction current value tends to increase.

[0124] Here, an example of a method for designing the semiconductor device 100 in which the influence of noise is reduced while suppressing current concentration is described. In the full-gate semiconductor device, all the trench portions are electrically connected to the gate metal layer 50 so that the potential around the trench portions can be deflected. For this reason, the semiconductor device preferably includes both the gate trench portion G and the emitter trench portion E. As the proportion of the emitter trench portions E is increased compared to the gate trench portions G, the maximum value of the conduction current density distribution decreases as shown in Fig. 8A to 8D tend to.

[0125] By increasing the ratio of the total area of ​​the diode portions 80 to the total area of ​​the transistor portions 70, it is possible to suppress the breakdown of the semiconductor device 100 while suppressing the maximum value of the conduction current density distribution. Specifically, in the first embodiment, the boundary region 81 is provided in the diode portion 80. The boundary region 81 is provided in the diode portion 80 such that the cathode region 82 becomes relatively longer and the collector region 22 becomes relatively shorter. For this reason, the electrons emitted from the emitter region 12 can be easily introduced into the collector region 22, making it possible to effectively reduce the maximum value of the current density.

[0126] On the other hand, if the ratio of the total area of ​​the diode sections 80 to the total area of ​​the transistor sections 70 is increased, the capacitance between the gate and the emitter is reduced. Therefore, the semiconductor device 100 is provided with the dummy trench section 30 in the boundary region 81, so that it is possible to ensure the capacitance between the gate and the emitter while reducing the current concentration by increasing the number of diode sections 80. This makes it possible to implement the semiconductor device 100 in which the influence of noise is reduced while suppressing element breakdown due to current concentration.

[0127] Meanwhile, the above-described dummy trench portion 30 may be provided so as to extend in the X-axis direction to the edge termination region 102 of the transistor portion 70 adjacent to the edge termination region 102, without being limited to the boundary region 81 where the transistor portion 70 and the diode portion 80 are adjacent to each other. That is, the side of the edge termination region 102 of the transistor portion 70 adjacent to the edge termination region 102 may be provided with the dummy trench portion 30 that does not contact the emitter region 12. The side of the edge termination region 102 of the transistor portion 70 on which the dummy trench portion 30 is provided is shown by the dashed line as the edge adjacent region 84.The edge adjacent region 84 is a region adjacent to the edge termination region 102 on a positive side or a negative side of the transistor section 70 in the Y-axis direction. This makes it possible to suppress the concentration of carriers while ensuring the capacitance between the gate and the emitter by forming an ineffective region that does not function as a transistor on the edge termination region 102 side of the transistor section 70. Therefore, the number of dummy trench portions 30 to be inserted in the edge adjacent region 84 may be larger than the number of dummy trench portions 30 to be inserted in the boundary region 81. Furthermore, the dummy trench portion 30 may be provided only in the edge adjacent region 84.When the dummy trench portion 30 is provided in the edge adjacent region 84, the width Wt of the transistor portion 70 in the Y-axis direction and the width Wd of the diode portion 80 in the Y-axis direction are not limited.

[0128] Fig. 9 shows an example of a configuration of the semiconductor device 100 according to a third embodiment. The semiconductor device 100 of the present example differs from the semiconductor device 100 according to the first embodiment in that it includes a surface lifetime limiter 95 and a subsurface lifetime limiter 96.

[0129] The surface lifetime limiter 95 and the subsurface lifetime limiter 96 are used to adjust the lifetime of carriers. The surface lifetime limiter 95 and the subsurface lifetime limiter 96 are formed by injecting ions from the upper surface side or the lower surface side of the semiconductor substrate 10 by injecting helium.

[0130] The surface lifetime limiter 95 is provided on the upper surface side of the semiconductor substrate 10. For example, the surface lifetime limiter 95 of the third embodiment is provided in the diode section 80. The surface lifetime limiter 95 of the present example is provided so as to extend from the non-boundary region 83 to at least a part of the boundary region 81. The surface lifetime limiter 95 can reduce the carrier lifetime on the anode region side of the diode section 80, thereby reducing the tail current to reduce the reverse recovery loss Err.

[0131] The surface lifetime limiter 95 may or may not be provided in the transistor portion 70. That is, the surface lifetime limiter 95 of the present example is provided with an extension from the non-boundary region 83 to a part of the boundary region 81, but may be provided with an extension to the boundary R, ​​or may be provided with an extension to the transistor portion 70 beyond the boundary R. Further, in the present example, the region where the collector region provided on the lower surface side of the semiconductor substrate 10 is projected onto the upper surface side of the semiconductor substrate 10 is set as the transistor portion 70, and the region excluding the transistor portion 70 where the cathode region 82 is projected onto the upper surface of the semiconductor substrate 10 is set as the diode portion 80.However, a region where the surface life limiter 95 is not provided may be set as the transistor section 70, and a region where the surface life limiter 95 is provided may be set as the diode section 80.

[0132] The sub-surface lifetime limiter 96 is provided on the lower surface side of the semiconductor substrate 10. The sub-surface lifetime limiter 96 of the present example is provided in both the transistor section 70 and the diode section 80. A concentration of the sub-surface lifetime limiter 96 may be lower on the transistor section 70 side than on the diode section 80 side. For example, the concentration of the sub-surface lifetime limiter 96 in the boundary region 81 of the diode section 80 is lower than the concentration of the sub-surface lifetime limiter 96 in the non-boundary region 83 of the diode section 80. This allows the current to easily flow through the cathode region 82, so that the current concentration in the transistor section 70 can be easily reduced.

[0133] The cathode region 82 extends further toward the transistor section 70 than the surface lifetime limiter 95. This allows the current to flow easily through the cathode region 82, so that the current concentration in the transistor section 70 can be easily reduced.

[0134] In addition, a concentration of the cathode region 82 on the transistor section 70 side may be higher than on the diode section 80 side. For example, the concentration of the cathode region 82 in the boundary region 81 of the diode section 80 is higher than the concentration of the cathode region 82 in the non-boundary region 83 of the diode section 80. Thereby, the current can continue to flow easily through the cathode region 82, so that the current concentration in the transistor section 70 can be easily reduced.

[0135] Fig. 10 shows an example of a configuration of the semiconductor device 100 according to a fourth embodiment. The semiconductor device 100 of the present example differs from the semiconductor device 100 according to the first embodiment in the structure of the boundary region 81.

[0136] The accumulation region 16 is provided in the transistor section 70. The accumulation region 16 is not provided in the boundary region 81. That is, the accumulation region 16 is not provided in the second mesa section 92 adjacent to the dummy trench section. The second mesa section 92 is provided with the contact region 15. In the semiconductor device 100 of the present example, since the accumulation region 16 is not provided in the second mesa section 92 positioned between the dummy trench sections 30, it is possible to easily extract holes toward the emitter electrode 52 in the boundary region 81.

[0137] Fig. 11 shows an example of a configuration of the semiconductor device 100 according to a fifth embodiment. The semiconductor device 100 of the present example differs from the semiconductor device 100 according to the first embodiment in the structure of the dummy trench portion 30.

[0138] The dummy trench portion 30 has a different shape from the gate trench portion 40 and the emitter trench portion 60. The dummy trench portion 30 of the present example can adjust the capacitance between the gate and the emitter of the semiconductor device 100 by adjusting an insulation film in the trench and a trench depth.

[0139] The film thickness of the dummy insulating film 32 is smaller than that of the gate insulating film 42 and the emitter insulating film 62. This increases the capacitance between the gate and the emitter of the semiconductor device 100. In the present example, the film thickness of the dummy insulating film 32 is made thin without changing the width of the trench formed on the upper surface side of the semiconductor substrate 10. However, the film thickness of the dummy insulating film 32 can be made relatively thin by increasing the width of the trench for providing the gate trench portion 40 and the emitter trench portion 60 and increasing the film thicknesses of the gate insulating film 42 and the emitter insulating film 62.

[0140] A trench depth of the dummy trench portion 30 is larger than a trench depth of the gate trench portion 40 and a trench depth of the emitter trench portion 60. This increases the capacitance between the gate and the emitter of the semiconductor device 100. Meanwhile, in the present example, the trench depth of the dummy trench portion 30 is set large. However, the trench depth of the dummy trench portion 30 can be made relatively large by reducing the depth of the trench for providing the gate trench portion 40 and the emitter trench portion 60.

[0141] In the semiconductor device 100 of the present example, the film thickness of the dummy insulating film 32 is made small and the trench depth of the dummy trench portion 30 is made large, so that the capacitance between the gate and the emitter can be increased. This reduces the influence of noise on the semiconductor device 100. Meanwhile, the semiconductor device 100 can be designed to increase the capacitance between the gate and the emitter by adjusting either the film thickness of the dummy insulating film 32 or the trench depth of the dummy trench portion 30.

[0142] Fig. 12 is an example of a plan view showing a semiconductor device 200 according to a sixth embodiment. The semiconductor device 200 of the present example includes a transistor section 70 and a current detection section 210. A structure of the transistor section 70 may be the same as that of the transistor section 70 according to any one of the embodiments described with reference to Fig. 1A to 11 may be the same as a partial structure of the transistor section 70 according to any aspect or may be different.

[0143] The transistor section 70 of the present example includes the gate trench section 40 and the emitter trench section 60. A mesa section in contact with the gate trench section 40 and a mesa section in contact with the emitter trench section 60 may have the same structures as the first mesa section 91 described with reference to FIG. Fig. 1A to 11. The transistor section 70 may further include the dummy trench section 30 and the second mesa section 92 in contact with the dummy trench section 30.

[0144] The semiconductor device 200 may further include a diode portion 80. In this case, the orientation of the transistor portion 70 and the diode portion 80 may be the same as in the semiconductor device 100 described with reference to Fig. 1A to 11. Also in the present example, the gate trench section 40, the emitter trench section 60, and the blind trench section 30 are each provided with an extension in the X-axis direction and aligned in the Y-axis direction.

[0145] The upper surface of the semiconductor substrate 10 of the present example is provided with a gate pad 208 connected to a gate wire portion 46, a current detection pad 202 connected to the current detection portion 210, an anode pad 204, and a cathode pad 206. The anode pad 204 and the cathode pad 206 are pads to be connected to a temperature detection portion disposed above the upper surface of the semiconductor substrate 10. The temperature detection portion is, for example, a PN diode formed of polysilicon or the like. However, the pads disposed on the upper surface of the semiconductor substrate 10 are not limited thereto.

[0146] As described above, each of the contact pads is arranged in the outer region 104. The current detection section 210 may also be arranged in the outer region 104. At least a part of the current detection section 210 may be arranged between any two contact pads when viewed from above. The current detection section 210 is provided in the outer region 104 so that it is possible to suppress a reduction in the areas of the transistor section 70 and the like.

[0147] In the present example, the gate pad 208 and the current sensing portion 210 and the current sensing pad 202 are arranged on opposite sides of the upper surface of the semiconductor substrate 10. In Fig. 12, an outer region 104-1, in which the gate pad 208 is provided, and an outer region 104-2, in which the current sensing section 210 and the current sensing pad 202 are provided, are arranged so that the transistor section 70 is arranged therebetween in the Y-axis direction. The anode pad 204 and the cathode pad 206 may be arranged in the outer region 104-2. The arrangement of the pads is not limited to the example of Fig. 12. The arrangement of the contact pads may be similar to the semiconductor device 100 described with reference to Fig. 1A to 11.

[0148] The gate wire portion 46 includes the gate metal layer 50 and the gate runner 48. The gate metal layer 50 is arranged to surround the transistor portion 70 (the transistor portion 70 and the diode portion 80 if the diode portion 80 is provided) when viewed from above. The gate runner 48 may be arranged along the gate metal layer 50. The gate runner 48 may be arranged to at least partially overlap under the gate metal layer 50. The gate runner 48 may be arranged to cross the transistor portion 70. The gate runner 48 is connected to the gate trench portion 40 and the dummy trench portion 30 and is configured to transmit the gate voltage.

[0149] The current sensing section 210 is configured to sense the current flowing through the transistor section 70. The current sensing section 210 of the present example includes at least one gate trench section 40 and the first mesa section 91. Also in the current sensing section 210 of the present example, each of the trench sections is provided with an extension in the X-axis direction and is aligned in the Y-axis direction. However, the extension direction and alignment direction of each of the trench sections of the current sensing section 210 may be different from the extension direction and alignment direction of each of the trench sections of the transistor section 70.

[0150] The current sensing section 210 of the present example has a similar structure to the transistor section 70 when viewed from above, so that the current flowing through the transistor section 70 is simulated at a ratio corresponding to a channel area ratio. An area of ​​the current sensing section 210, when viewed from above, is smaller than an area of ​​the transistor section 70. The area of ​​the current sensing section 210 may be smaller than an area of ​​each of the contact pads, such as the gate pad 208, arranged on the upper surface of the semiconductor substrate 10.

[0151] In the present example, a value obtained by dividing the number G of gate trench portions 40 included in a unit length in the alignment direction of the respective trench portions by the number E of emitter trench portions is referred to as the gate-emitter ratio G / E. Meanwhile, when the dummy trench portion 30 is provided, a gate-emitter ratio (G+D) / E obtained by dividing a sum of the number G of gate trench portions 40 and the number D of dummy trench portions 30 by the number E of emitter trench portions 60 can be set as the gate-emitter ratio.

[0152] The gate-emitter ratio of the current sensing section 210 is larger than the gate-emitter ratio of the transistor section 70. That is, in the current sensing section 210, the gate trench sections 40 are arranged at a higher density compared to the transistor section 70. The gate-emitter ratio of the current sensing section 210 can be calculated from the number of all trench sections aligned in the Y-axis direction in the current sensing section 210. The gate-emitter ratio of the transistor section 70 can also be calculated from the number of all trench sections aligned in the Y-axis direction in the transistor section 70.

[0153] Since the current detection section 210 has a smaller area than the transistor section 70, the insulation strength tends to be reduced. In this regard, if the gate-emitter ratio of the current detection section 210 is increased, the insulation film capacitance between the gate and the emitter in the current detection section 210 can be increased. For this reason, it is possible to suppress a voltage rise even when charges are injected into respective electrodes by electrostatic discharge (ESD) and the like. Therefore, it is possible to increase the insulation strength of the current detection section 210. Even in a case where the current detection section 210 is not provided with the emitter trench section 60, it is possible to omit a shield test for the emitter trench section 60 of the current detection section 210.

[0154] Fig. 13 shows an example of a cross-sectional view of the transistor section 70. In Fig. Figure 13 shows a YZ cross-section through the emitter region 12. In the transistor section 70 of the present example, a gate trench section 40 and an emitter trench section 60 are arranged alternately in the Y-axis direction. In this case, the gate-emitter ratio of the transistor section 70 is 1 / 1 = 1.

[0155] Meanwhile, each of the contact holes 54 may be provided with a barrier metal 57. The barrier metal 57 may comprise a titanium film and / or a titanium nitride film. The barrier metal 57 may be provided with a cover of the interlayer dielectric film 38. In addition, the contact hole 54 may be provided with a tungsten plug 58. The barrier metal 57 and the tungsten plug 58 may also be provided in the manner described with reference to Fig. 1A to 11 may be provided.

[0156] Fig. 14 shows an example of a cross-sectional view of the current detecting section 210. In Fig. 14 shows a YZ cross-section passing through the emitter region 12. In the current detection section 210 of the present example, the gate trench sections 40 are sequentially aligned in the Y-axis direction, and the emitter trench section 60 is not provided. That is, all the trench sections in the current detection section 210 of the present example are the gate trench sections 40. In this case, the gate-to-emitter ratio of the current detection section 210 is 1 / 0 and thus an infinite value. Furthermore, in the current detection section 210 of the present example, some emitter trench sections 60 may be provided at both end portions in the alignment direction (in the Y-axis direction) of the trench sections. The gate-emitter ratio of the current sensing section 210 may be twice or more or ten times or more as large as the gate-emitter ratio of the transistor section 70.

[0157] Furthermore, in each of the current detection sections 210 and the transistor sections 70, a value obtained by dividing an area of ​​the accumulation region 16 by an area of ​​the emitter region 12 as viewed from above is referred to as an area ratio of the accumulation region 16. That is, the area ratio of the accumulation region 16 in the current detection section 210 is a value obtained by dividing a total area of ​​the accumulation regions 16 included in the current detection section 210 by a total area of ​​the emitter regions 12 included in the current detection section 210 as viewed from above. Likewise, the area ratio of the accumulation region 16 in the transistor section 70 is a value obtained by dividing a total area of ​​the accumulation regions 16 included in the transistor section 70 by a total area of ​​the emitter regions 12 included in the transistor section 70 as viewed from above.

[0158] The area ratio of the accumulation region 16 in the current detection section 210 is preferably smaller than the area ratio of the accumulation region 16 in the transistor section 70. By reducing the area ratio of the accumulation regions 16 included in the current detection section 210, it is possible to reduce the IE effect in the current detection section 210 and suppress a decrease in the clamping voltage due to accumulation of minority carriers. Therefore, even when the voltage in the transistor section 70 is clamped during the turn-off operation, for example, it is possible to suppress the occurrence of an avalanche in the current detection section 210, thereby suppressing the breakdown of the current detection section 210.When the area ratio of the accumulation regions 16 in the current detection section 210 is reduced, it is possible to prevent a voltage waveform in the current detection section 210 from fluctuating excessively. For this reason, it is possible to suppress an imbalance of operation in the current detection section 210, thereby suppressing the breakdown of the current detection section 210.

[0159] In the example of Fig. 13, the transistor section 70 is provided with both the emitter region 12 and the accumulation region 16. In Fig. 14, the current detection section 210 is provided with the emitter region 12, but not with the accumulation region 16. That is, the area ratio of the accumulation region 16 in the Fig. 14 is zero. The area ratio of the accumulation region 16 in the current detection section 210 may be half or less, or 1 / 10 or less, of the area ratio of the accumulation region 16 in the transistor section 70.

[0160] Fig. 15 is an enlarged plan view near the outer region 104-2. As described above, the gate slider 48 is provided to surround the outer region 104-2. The gate slider 48 of the present example has a crossing part 47 provided to cross the outer region 104-2 when viewed from above. The crossing part 47 of the present example is formed to cross the outer region 104-2 in the Y-axis direction. The crossing part 47 is formed to connect the two gate sliders 48 provided at both ends of the outer region 104-2 in the Y-axis direction. The crossing part 47 may be provided without overlapping the anode pad 204 and the cathode pad 206.

[0161] The gate wire portion 46 has an opening portion 212 formed to penetrate the gate wire portion 46 from an upper surface to a lower surface. In the present example, the crossing part 47 of the gate runners 48 is formed with the opening portion 212. The opening portion 212 is formed to penetrate the polysilicon gate runner 48. In Fig. 15, a portion of the gate runner 48 except for the opening portion 212 is obliquely hatched.

[0162] The current detection section 210 is arranged in a region in which at least a part overlaps the opening section 212 under the gate slider 48. The current detection section 210 may be arranged such that at least a part overlaps a region of the gate slider 48 except for the opening section 212. In the example of Fig. 15, the current detection section 210 is completely arranged to overlap the opening section 212 or the gate slider 48. The current detection section 210 is arranged below the gate slider 48, so that it is possible to easily connect the gate trench section 40 of the current detection section 210 and the gate slider 48.

[0163] In addition, at least a part of the current detection section 210 is exposed through the opening section 212, so that it is easy to connect the current detection section 210 and the current detection pad 202 to each other. At least a part of the current detection pad 202 may be provided in the opening section 212. The current detection pad 202 of the present example may be provided with an extension from a position where it does not overlap the gate slider 48 to the opening section 212 above the gate slider 48. Fig. In Figure 15, a portion of the current sensing pad 202 provided above the gate slider 48 is shown by the dashed line. The current sensing pad 202 and the gate slider 48 are insulated from each other by an interlayer dielectric film or the like. The current sensing pad 202 may be provided to cover the entire opening portion 212.

[0164] Fig. 16 is an enlarged plan view near the opening portion 212. In Fig. 16, the current detection pad 202 is omitted. In the present example, the semiconductor substrate 10 is provided with a first well region 220 and a second well region 218. The first well region 220 and the second well region 218 are P+ type regions provided from the upper surface of the semiconductor substrate 10 to a deeper part than a lower end of the trench portion. The first well region 220 corresponds to the well region 11 of the semiconductor device 100 described with reference to Fig. 1A to 11.

[0165] The first well region 220 is provided to surround the transistor section 70 (the transistor section 70 and the diode section 80 when the diode section 80 is provided) when viewed from above. The second well region 218 is provided to surround the current detection section 210 when viewed from above. In the present example, the second well region 218 is formed as part of the current detection section 210. That is, an outer peripheral end of the second well region 218 when viewed from above coincides with an outer peripheral end of the current detection section 210 when viewed from above.

[0166] The first well region 220 and the second well region 218 are arranged separately from each other. For example, an N-type region such as the drift region 18 may be provided between the first well region 220 and the second well region 218.

[0167] The current detection section 210 of the present example includes an emitter arrangement region 216 and an emitter non-arrangement region 214. The emitter arrangement region 216 is a region in which the emitter regions 12 are periodically arranged when viewed from above. For example, as shown in Fig. 1A and the like, the emitter region 12 and the contact region 15 are arranged alternately in the X-axis direction in the emitter arrangement region 216. The emitter arrangement region 216 may be a region including a center of the current detection section 210 when viewed from above.

[0168] The emitter non-array region 214 is a region where the emitter region 12 is not provided. A P-type region may be exposed on an upper surface of the emitter non-array region 214. The P-type region may have the same doping concentration as the contact region 15, the same doping concentration as the base region 14, or a different doping concentration.

[0169] The emitter non-array region 214 is provided to surround the emitter array region 216 when viewed from above. For example, the emitter array region 216 and the emitter non-array region 214 each have a rectangular outer shape when viewed from above. The emitter non-array region 214 is surrounded by the second well region 218 when viewed from above.

[0170] In the emitter arrangement region 216 and the emitter non-arrangement region 214, the trench portions such as the gate trench portion 40 and each of the mesa portions are arranged. Fig. 16, some of the trench portions are shown with the dashed line. Each of the trench portions is provided with an extension in the X-axis direction. When the emitter arrangement region 216 and the emitter non-array region 214 are arranged adjacent to each other in the X-axis direction, the trench portions may be continuously provided over both the emitter arrangement region 216 and the emitter non-array region 214. The end portions of the gate trench portion 40 in the X-axis direction may be provided within the second well region 218. This makes it possible to reduce the electric field concentration at the end portions of the gate trench portion 40.

[0171] The end portions of the gate trench portion 40 in the X-axis direction are preferably provided at positions where they overlap the gate slider 48. That is, the end portions of the gate trench portion 40 are preferably located outside the opening portion 212. This makes it easy to connect the gate trench portion 40 and the gate slider 48 to each other.

[0172] The emitter arrangement region 216 and the emitter non-array region 214 may be fully exposed through the opening portion 212. Thereby, the emitter arrangement region 216 and the emitter non-array region 214 may be fully connected to the current sensing pad 202.

[0173] In the example of Fig. 16, end portions of the opening portion 212 are disposed above the second well region 218, as viewed from above. In another example, the end portions of the opening portion 212 may be disposed above the emitter non-array region 214.

[0174] Fig. 17 is a plan view illustrating distances of the second well region 218 and the emitter array region 216. In Fig. 17, the structures except for the second well region 218, the emitter arrangement region 216 and the emitter non-arrangement region 214 are omitted.

[0175] In the X-axis direction, a shortest distance between the emitter array region 216 and the second well region 218 is denoted as X1s, and a length of the emitter array region 216 is denoted as X2s. The distance X1s is the shortest distance between the emitter region 12 located at the outermost edge in the X-axis direction in the emitter array region 216 and the second well region 218. The length X2s is a maximum distance in the X-axis direction between the emitter regions 12 located at both ends in the X-axis direction in the emitter array region 216.

[0176] In the Y-axis direction, a shortest distance between the emitter array region 216 and the second well region 218 is denoted as Y1s, and a length of the emitter array region 216 is denoted as Y2s. The distance Y1s is the shortest distance between the emitter region 12 located at the outermost edge in the emitter array region 216 in the Y-axis direction and the second well region 218. The length Y2s is a maximum distance between the emitter regions 12 located at both ends in the emitter array region 216 in the Y-axis direction.

[0177] The current detection section 210 of the present example has a larger gate-emitter ratio than the transistor section 70. For this reason, compared to a case where the current detection section has the same gate-emitter ratio as the transistor section 70, it is possible to ensure an equivalent channel area even if the area of ​​the emitter arrangement region 216 is reduced. Since it is possible to reduce the area of ​​the emitter arrangement region 216, it is possible to increase the distances X1s and Y1s between the second well region 218 and the emitter region 12 and easily separate the current flowing through the current detection section 210 and the current flowing through another region.

[0178] For example, the distance X1s can be 10% or more, or 20% or more, of the length X2s. The distance Y1s can be 10% or more, 20% or more, or 30% or more of the width Y2s.

[0179] Fig. 18 shows the distance X1s. Fig. 18 is a plan view showing an outline of an area A in Fig. 17. Region A is a region including the emitter array region 216, the emitter non-array region 214, and the second well region 218 arranged side by side in the X-axis direction.

[0180] As described above, the distance X1s is the shortest distance between the emitter region 12, which is located on the outermost side in the X-axis direction, and the second well region 218. The contact region 15 and / or the base region 14 may be provided between the emitter region 12 and the second well region 218. In Fig. 18, the base region 14 is disposed over half or more of a region between the outermost emitter region 12 and the second well region 218 in the X-axis direction. In another example, the contact region 15 may be disposed over half or more of the region between the outermost emitter region 12 and the second well region 218 in the X-axis direction. Meanwhile, the base region 14 or the contact region 15 may be disposed over the entire region between the outermost emitter region 12 and the second well region 218 in the X-axis direction.

[0181] Fig. 19 shows the distance Y1s. Fig. 19 is a plan view showing an outline of an area B in Fig. 18. Region B is a region including the emitter array region 216, the emitter non-array region 214, and the second well region 218 arranged side by side in the Y-axis direction.

[0182] As described above, the distance Y1s is the shortest distance between the emitter region 12, which is located on the outermost side in the Y-axis direction, and the second well region 218. The contact region 15 and / or the base region 14 may be provided between the emitter region 12 and the second well region 218. However, as shown in Fig. 16, in which some of the trench portions are shown with the dashed line, the gate trench portion 40 or the emitter trench portion 60 extending in the X-axis direction may be provided within a range of the pitch Y1s of the present example.

[0183] Fig. 20 shows a distance X1t in the transistor section 70. Fig. 20 is a partial plan view of the transistor section 70. The distance X1t is the shortest distance in the X-axis direction between the outermost emitter region 12 in the X-axis direction and the first well region 220 in the transistor section 70.

[0184] The distance X1s in the current detecting section 210, which is Fig. 18 may be larger than the distance X1t in the transistor section 70. As described above, when the distance X1s in the current detection section 210 is increased, it is possible to easily separate the current flowing through the current detection section 210 from the current flowing through another region. The distance X1s may be twice or larger, or five times or larger, than the distance X1t.

[0185] Fig. 21 shows another configuration example of area A of Fig. 20. In Fig. 21, a length of the base region 14 in the X-axis direction, which is in contact with the second well region 218 of the current sensing section 210, is denoted as Xb, and a distance between the outermost emitter region 12 and the base region 14 is denoted as Xc. Furthermore, in the present example, the distance X1s in the current sensing section 210 is greater than the distance X1t in the transistor section 70.

[0186] In the example of Fig. 18, the length Xb of the base region in contact with the second well region 218 of the current sensing section 210 is greater than a length of the base region in contact with the first well region 220 of the transistor section 70. That is, the base region 14 of the current sensing section 210 is designed longer than the base region of the transistor section 70, so that the distance X1s between the second well region 218 and the outermost emitter region 12 is increased.

[0187] In the present example, the distance Xc between the outermost emitter region 12 and the base region 14 in contact with the second well region 218 is made larger than the distance between the outermost emitter region 12 in the transistor section 70 and the base region 14 in contact with the first well region 218. Thereby, the distance X1s in the current sensing section 210 can be made larger than the distance X1t in the transistor section 70.

[0188] Meanwhile, in the current sensing section 210, the contact region 15 may be provided between the outermost emitter region 12 and the base region 14 in contact with the first well region 218. That is, the distance Xc is a length of the contact region 15 located between the outermost emitter region 12 and the base region 14 in contact with the first well region 218. The length Xc of the outermost contact region 15 in the X-axis direction in the current sensing section 210 may be greater than the length of the outermost contact region 15 in the X-axis direction in the transistor section 70.

[0189] Fig. 22 shows a distance Y1t in the transistor section 70. Fig. 22 is a partial plan view of the transistor section 70. The distance Y1t is a shortest distance in the Y-axis direction between the outermost emitter region 12 in the Y-axis direction in the transistor section 70 and the first well region 220. Meanwhile, as in Fig. 19, the gate trench portion 40 or the emitter trench portion 60 extending in the X-axis direction may be provided within a range of the pitch Y1t of the present example.

[0190] The distance Y1s in the current detecting section 210, which is Fig.19 may be larger than the distance Y1t in the transistor section 70. As described above, when the distance Y1s is increased in the current detection section 210, it is possible to easily separate the current flowing through the current detection section 210 from the current flowing through another region. The distance Y1s may be twice or more or five times or more as large as the distance Y1t.

[0191] Meanwhile, the current detection section 210 of the semiconductor device 200 may be provided with the subsurface lifetime limiter 96, like the transistor section 70. Furthermore, the current detection section 210 may be provided with the surface lifetime limiter. For example, if the transistor section 70 is provided with the surface lifetime limiter 95, the current detection section 210 is also provided with the surface lifetime limiter 95.

[0192] Although the present invention has been described with reference to the embodiments, the technical scope of the present invention is not limited to the scope described in the embodiments. It will be apparent to those skilled in the art that the embodiments can be modified or improved in various ways. It is also clear from the claims that the modifications or improvements can also fall within the technical scope of the present invention.

[0193] The description and drawings also disclose aspects described in each of the following points. (Point 1)

[0194] A semiconductor device having a transistor portion and a diode portion may include a boundary region formed in a region where the transistor portion and the diode portion are adjacent to each other and provided so as to prevent interference between the transistor portion and the diode portion.

[0195] The transistor section and the diode section may include a plurality of trench sections aligned in a preset alignment direction.

[0196] The diode section may have a cathode region of the first conductivity type on a surface side opposite a surface side of the semiconductor substrate.

[0197] A width of the diode portion in the alignment direction may be larger than a width of the transistor portion in the alignment direction.

[0198] The cathode region may be provided with an extension to the boundary region in the alignment direction. (Point 2)

[0199] In point 1, the width of the diode section in the alignment direction can be greater than or equal to 1500 µm. (Point 3)

[0200] In item 1 or 2, the semiconductor device may have a plurality of transistor sections and a plurality of diode sections.

[0201] A total area of ​​the plurality of diode sections may be larger than a total area of ​​the plurality of transistor sections. (Point 4)

[0202] In any one of items 1 to 3, the semiconductor device may further comprise: a gate metal layer provided over an upper surface of the semiconductor substrate, an emitter electrode provided above the upper surface of the semiconductor substrate, an emitter region of the first conductivity type provided on the upper surface side of the semiconductor substrate in the transistor section, Gate trench portions provided on the upper surface side of the semiconductor substrate in the transistor portion, electrically connected to the gate metal layer, and in contact with the emitter region, and Emitter trench portions provided on the upper surface side of the semiconductor substrate in the diode portion and electrically connected to the emitter electrode.

[0203] The emitter trench sections may also be arranged in the transistor section at predetermined intervals between the gate trench sections. (Point 5)

[0204] In item 4, the semiconductor device may further include a dummy trench portion provided on the upper surface side of the semiconductor substrate, electrically connected to the gate metal layer, and not in contact with the emitter region. (Point 6)

[0205] In any one of items 1 to 5, the boundary region may be a region having a device structure different from a device structure of the transistor section and a device structure of the diode section. (Point 7)

[0206] In any one of items 1 to 6, the semiconductor device may further comprise: an interlayer dielectric film provided over the upper surface side of the semiconductor substrate, and Contact holes provided in the interlayer dielectric film between the trench portions in the transistor portion and the diode portion, wherein an emitter electrode is embedded in the contact holes.

[0207] The interlayer dielectric film between the trench portions in the boundary region may not be formed with the contact hole. (Point 8)

[0208] In any of items 1 to 7, the diode section may have the limiting region and a non-limiting region.

[0209] A concentration of the cathode region in the boundary region of the diode section may be higher than a concentration of the cathode region in the non-boundary region of the diode section. (Point 9)

[0210] In any one of items 1 to 8, the semiconductor device may further comprise a subsurface lifetime limiter provided on a side opposite to the upper surface side of the semiconductor substrate.

[0211] The diode section may have the limit region and a non-limit region.

[0212] A concentration of the subsurface lifetime limiter in the boundary region of the diode section may be lower than a concentration of subsurface lifetime limiter in the non-boundary region of the diode section. (Point 10)

[0213] In any one of items 1 to 9, the semiconductor device may further comprise a surface lifetime limiter incorporated in a non-boundary region of at least the diode portion on the upper surface side of the semiconductor substrate. The cathode region may extend further toward the transistor portion than the surface lifetime limiter.

[0214] The operations, procedures, steps, and stages of each process performed by an apparatus, system, program, and method shown in the claims, specification, and drawings may be performed in any order, as long as the order is not explicitly indicated by "before," "previously," or the like, and as long as the output of a previous process is not used in a later process. Even if the process flow is described in the claims, specification, and drawings using terms such as "first" or "next," this does not necessarily mean that the process must be performed in that order. List of reference symbols 10 Semiconductor substrate 11 Bath area 12 Emitter area 14 Basic area 15 Contact area 16 Accumulation area 18 Drift area 20 Buffer area 21 upper surface 22 Collector area 23 lower surface 24 Collector electrode 25 connecting section 30 blind trench section 31 Extension part 32 Blind insulation film 33 connecting section 34 blind line section 38 dielectric interlayer film 40 Gate trench section 41 Extension part 42 Gate insulation film 43 Connecting part 44 Gate line section 46 Gate wire section 47 Crossing section 48 gate runners 49 contact hole 50 Gate metal layer 52 Emitter electrode 54 contact hole 56 contact hole 57 barrier metal 58 tungsten plugs 60 emitter trench section 61 extension part 62 Emitter insulation film 63 connecting part 64 Emitter line section 70 transistor section 80 diode section 81 Border area 82 Cathode area 83 Non-border area 84 Border Neighbor Area 91 first mesa section 92 second mesa section 93 third mesa section 95 surface life limiter 96 subsurface life limiter 100 semiconductor devices 102 Edge finishing area 104 Outdoor area 200 semiconductor devices 202 Current detection contact point 204 Anode contact point 206 Cathode contact point 208 Gate contact point 210 Current detection section 212 opening section 214 Emitter non-arrangement region 216 Emitter arrangement area 218 second tub area 220 first tub area 500 semiconductor devices 570 transistor section 580 diode section

Claims

[1] A semiconductor device (100) having a transistor portion (70) and a diode portion (80), the semiconductor device (100) comprising: a gate metal layer (50) provided over an upper surface of a semiconductor substrate (10); an emitter electrode (52) provided over the upper surface of the semiconductor substrate (10); an emitter region (12) of the first conductivity type provided on the upper surface side of the semiconductor substrate (10) in the transistor section (70); a gate trench portion (40) provided on the upper surface side of the semiconductor substrate (10) in the transistor portion (70), electrically connected to the gate metal layer (50) and in contact with the emitter region (12); an emitter trench portion (60) provided on the upper surface side of the semiconductor substrate (10) in the diode portion (80) and electrically connected to the emitter electrode (52); a dummy trench portion (30) provided on the upper surface side of the semiconductor substrate (10), electrically connected to the gate metal layer (50) and not in contact with the emitter region (12); and a boundary region (81) formed in a region where the transistor portion (70) and the diode portion (80) are adjacent to each other and provided so as to prevent interference between the transistor portion (70) and the diode portion (80), wherein the dummy trench portion is provided in a non-boundary region (83) of the transistor portion or the diode portion. [2] A semiconductor device (100) having a transistor portion (70) and a diode portion (80), the semiconductor device (100) comprising: a gate metal layer (50) provided over an upper surface of a semiconductor substrate (10); an emitter electrode (52) provided over the upper surface of the semiconductor substrate (10); an emitter region (12) of the first conductivity type provided on the upper surface side of the semiconductor substrate (10) in the transistor section (70); a gate trench portion (40) provided on the upper surface side of the semiconductor substrate (10) in the transistor portion (70), electrically connected to the gate metal layer (50) and in contact with the emitter region (12); an emitter trench portion (60) provided on the upper surface side of the semiconductor substrate (10) in the diode portion (80) and electrically connected to the emitter electrode (52); and a dummy trench portion (30) provided on the upper surface side of the semiconductor substrate (10), electrically connected to the gate metal layer (50) and not in contact with the emitter region (12), wherein: the transistor section (70) has an edge adjacent region (84) adjacent to an edge termination region (102), and the blind trench section (30) is provided in the edge adjacent area (84). [3] A semiconductor device (100) having a transistor portion (70) and a diode portion (80), the semiconductor device (100) comprising: a gate metal layer (50) provided over an upper surface of a semiconductor substrate (10); an emitter electrode (52) provided over the upper surface of the semiconductor substrate (10); an emitter region (12) of the first conductivity type provided on the upper surface side of the semiconductor substrate (10) in the transistor section (70); a gate trench portion (40) provided on the upper surface side of the semiconductor substrate (10) in the transistor portion (70), electrically connected to the gate metal layer (50) and in contact with the emitter region (12); an emitter trench portion (60) provided on the upper surface side of the semiconductor substrate (10) in the diode portion (80) and electrically connected to the emitter electrode (52); and a dummy trench portion (30) provided on the upper surface side of the semiconductor substrate (10), electrically connected to the gate metal layer (50) and not in contact with the emitter region (12), wherein: the semiconductor device (100) has a plurality of gate trench portions (40) and a plurality of dummy trench portions (30); and then, if a number of the gate trench sections (40) is denoted by G and a number of the blind trench sections (30) is denoted by D, a relationship 0.01 <D / (D+G)<0,2 is fulfilled. [4] A semiconductor device (100) having a transistor section (70) and a diode section (80), the semiconductor device (100) comprising: a gate metal layer (50) provided over an upper surface of a semiconductor substrate (10); an emitter electrode (52) provided over the upper surface of the semiconductor substrate (10); an emitter region (12) of the first conductivity type provided on the upper surface side of the semiconductor substrate (10) in the transistor section (70); a gate trench portion (40) provided on the upper surface side of the semiconductor substrate (10) in the transistor portion (70), electrically connected to the gate metal layer (50) and in contact with the emitter region (12); an emitter trench portion (60) provided on the upper surface side of the semiconductor substrate (10) in the diode portion (80) and electrically connected to the emitter electrode (52); a dummy trench portion (30) provided on the upper surface side of the semiconductor substrate (10), electrically connected to the gate metal layer (50) and not in contact with the emitter region (12); and an accumulation region (16) of the first conductivity type, which has a higher concentration than the emitter region (12), on the side of the upper surface of the semiconductor substrate (10) in the transistor section (70), wherein the accumulation region (16) is not provided in a mesa portion adjacent to the blind trench portion (30). [5] A semiconductor device (100) having a transistor section (70) and a diode section (80), the semiconductor device (100) comprising: a gate metal layer (50) provided over an upper surface of a semiconductor substrate (10); an emitter electrode (52) provided over the upper surface of the semiconductor substrate (10); an emitter region (12) of the first conductivity type provided on the upper surface side of the semiconductor substrate (10) in the transistor section (70); a gate trench portion (40) provided on the upper surface side of the semiconductor substrate (10) in the transistor portion (70), electrically connected to the gate metal layer (50) and in contact with the emitter region (12); an emitter trench portion (60) provided on the upper surface side of the semiconductor substrate (10) in the diode portion (80) and electrically connected to the emitter electrode (52); a dummy trench portion (30) provided on the upper surface side of the semiconductor substrate (10), electrically connected to the gate metal layer (50) and not in contact with the emitter region (12); and a drift region (18) of the first conductivity type provided in the semiconductor substrate (10), wherein: a mesa section adjacent to the blind trench section (30) comprises: a contact region (15) of the second conductivity type provided on the upper surface side of the semiconductor substrate (10); and a base region (14) of the second conductivity type provided between the drift region (18) and the contact region (15), and the contact region (15) has a higher doping concentration than the base region (14). [6] A semiconductor device (100) having a transistor portion (70) and a diode portion (80), the semiconductor device (100) comprising: a gate metal layer (50) provided over an upper surface of a semiconductor substrate (10); an emitter electrode (52) provided over the upper surface of the semiconductor substrate (10); an emitter region (12) of the first conductivity type provided on the upper surface side of the semiconductor substrate (10) in the transistor section (70); a gate trench portion (40) provided on the upper surface side of the semiconductor substrate (10) in the transistor portion (70), electrically connected to the gate metal layer (50) and in contact with the emitter region (12); an emitter trench portion (60) provided on the upper surface side of the semiconductor substrate (10) in the diode portion (80) and electrically connected to the emitter electrode (52); a blind trench portion (30) provided on the upper surface side of the semiconductor substrate (10), electrically connected to the gate metal layer (50) and not in contact with the emitter region (12), wherein a film thickness of a dummy insulation film (32) of the dummy trench portion (30) is smaller than that of a gate insulation film (42) of the gate trench portion (40) and an emitter insulation film (62) of the emitter trench portion (60). [7] A semiconductor device (100) having a transistor section (70) and a diode section (80), the semiconductor device (100) comprising: a gate metal layer (50) provided over an upper surface of a semiconductor substrate (10); an emitter electrode (52) provided over the upper surface of the semiconductor substrate (10); an emitter region (12) of the first conductivity type provided on the upper surface side of the semiconductor substrate (10) in the transistor section (70); a gate trench portion (40) provided on the upper surface side of the semiconductor substrate (10) in the transistor portion (70), electrically connected to the gate metal layer (50) and in contact with the emitter region (12); an emitter trench portion (60) provided on the upper surface side of the semiconductor substrate (10) in the diode portion (80) and electrically connected to the emitter electrode (52); a blind trench portion (30) provided on the upper surface side of the semiconductor substrate (10), electrically connected to the gate metal layer (50) and not in contact with the emitter region (12), wherein a trench depth of the blind trench section (30) is greater than a trench depth of the gate trench section (40) and a trench depth of the emitter trench section (60). [8] A semiconductor device (100) having a transistor section (70) and a diode section (80), the semiconductor device (100) comprising: a gate metal layer (50) provided over an upper surface of a semiconductor substrate (10); an emitter electrode (52) provided over the upper surface of the semiconductor substrate (10); an emitter region (12) of the first conductivity type provided on the upper surface side of the semiconductor substrate (10) in the transistor section (70); a gate trench portion (40) provided on the upper surface side of the semiconductor substrate (10) in the transistor portion (70), electrically connected to the gate metal layer (50) and in contact with the emitter region (12); an emitter trench portion (60) provided on the upper surface side of the semiconductor substrate (10) in the diode portion (80) and electrically connected to the emitter electrode (52); a dummy trench portion (30) provided on the upper surface side of the semiconductor substrate (10), electrically connected to the gate metal layer (50) and not in contact with the emitter region (12); and a current detection section (210), wherein: the gate trench portion (40), the emitter trench portion (60) and the dummy trench portion (30) are each aligned in a preset alignment direction on the side of the upper surface of the semiconductor substrate (10), and a gate-emitter ratio obtained by dividing a number of gate trench portions (40) included in a unit length in the alignment direction by a number of emitter trench portions (60) is larger in the current detection portion (210) than in the transistor portion (70). [9] A semiconductor device (100) according to any one of claims 2 to 8, further comprising a boundary region (81) formed in a region where the transistor portion (70) and the diode portion (80) are adjacent to each other, and provided so as to prevent interference between the transistor portion (70) and the diode portion (80), wherein the blind trench section (30) is arranged in the boundary region (81). [10] The semiconductor device (100) according to claim 9, wherein the dummy trench portion (30) is also provided in a non-boundary region (83) of the transistor portion (70) or the diode portion (80). [11] The semiconductor device (100) according to claim 9 or 10, wherein the gate trench portion (40), the emitter trench portion (60) and the dummy trench portion (30) are aligned in a preset alignment direction, and a width of the diode portion (80) in the alignment direction is greater than a width of the transistor portion (70) in the alignment direction. [12] A semiconductor device (100) according to any one of claims 9 to 11, further comprising: a surface lifetime limiter (95) introduced into a non-boundary region (83) of at least the diode section (80) on the side of the upper surface of the semiconductor substrate (10); and a cathode region (82) of the first conductivity type provided in the diode section (80) on one side of the lower surface of the semiconductor substrate (10), wherein the cathode region (82) extends further toward the transistor section (70) than the surface lifetime limiter (95). [13] A semiconductor device (100) according to any one of claims 1 to 6, comprising the transistor section (70) and a current detection section (210), the semiconductor device (100) comprising: a gate wire portion (46) provided over an upper surface of a semiconductor substrate; and a plurality of trench sections aligned in a preset alignment direction on the side of the upper surface of the semiconductor substrate (10), wherein the plurality of trench sections comprise the gate trench section (40) electrically connected to the gate wire section (46) and the emitter trench section (60) electrically connected to the emitter electrode (52), and a gate-emitter ratio obtained by dividing a number of gate trench portions (40) included in a unit length in the alignment direction by a number of emitter trench portions (60) is larger in the current detection portion (210) than in the transistor portion (70). [14] A semiconductor device according to claim 13, wherein both the gate trench section (40) and the emitter trench section (60) are arranged in the transistor section (70) and the gate trench section (40) is arranged in the current detection section (210) and the emitter trench section (60) is not arranged in the current detection section (210). [15] A semiconductor device according to claim 13 or 14, further comprising: a drift region (18) of the first conductivity type provided in the semiconductor substrate (10); wherein the emitter region (12) has a doping concentration which is higher than that of the drift region (18); and an accumulation region (16) of the first conductivity type provided below the emitter region (12) in the semiconductor substrate (10) and having a doping concentration higher than that of the drift region (18), wherein, in a plane parallel to the upper surface of the semiconductor substrate (10), an area ratio obtained by dividing an area of ​​the accumulation region (16) included in the current detection section (210) by an area of ​​the emitter region (12) is smaller than an area ratio obtained by dividing an area of ​​the accumulation region (16) included in the transistor section (70) by an area of ​​the emitter region (12). [16] A semiconductor device according to claim 15, wherein the transistor section (70) is provided with both the emitter region (12) and the accumulation region (16) and the current detection section (210) is provided with the emitter region (12) and is not provided with the accumulation region (16). [17] A semiconductor device according to any one of claims 13 to 16, wherein the gate wire portion (46) has an opening portion formed to penetrate the gate wire portion (46) from an upper surface to a lower surface, and at least a part of the current detection section (210) is arranged in a region overlapping the opening section. [18] A semiconductor device according to claim 17, wherein the gate wire portion (46) comprises a gate metal layer formed of metal and a gate runner formed of semiconductor with added impurities, and the opening section is provided in the gate runner. [19] A semiconductor device according to claim 13 or 14, further comprising: a drift region (18) of the first conductivity type provided in the semiconductor substrate (10); wherein the emitter region (12) has a doping concentration which is higher than that of the drift region (18); a first well region (220) provided to surround the transistor portion (70) in a plane parallel to the upper surface of the semiconductor substrate (10) and formed to be deeper than a range from the upper surface of the semiconductor substrate (10) to a lower end of the trench portions; and a second well region (218) provided to partially overlap with the current detection portion (210) in the plane parallel to the upper surface of the semiconductor substrate (10) and formed to be deeper than the range from the upper surface of the semiconductor substrate (10) to the lower end of the trench portions, wherein a shortest distance between the emitter region (12) and the second well region (218) provided in the current detection section (210) in the alignment direction is greater than a shortest distance between the emitter region (12) and the first well region (220) provided in the transistor section (70) in the alignment direction. [20] A semiconductor device according to claim 13 or 14, further comprising: a drift region (18) of the first conductivity type provided in the semiconductor substrate (10); wherein the emitter region (12) has a doping concentration which is higher than that of the drift region (18); a first well region (220) provided to surround the transistor portion (70) in a plane parallel to the upper surface of the semiconductor substrate (10) and formed to be deeper than a range from the upper surface of the semiconductor substrate (10) to a lower end of the trench portions; and a second well region (218) provided to partially overlap with the current detection portion (210) in the plane parallel to the upper surface of the semiconductor substrate (10) and formed to be deeper than the range from the upper surface of the semiconductor substrate (10) to the lower end of the trench portions, wherein a shortest distance between the emitter region (12) and the second well region (218) provided in the current detection section (210) in a direction perpendicular to the alignment direction is greater than a shortest distance between the emitter region (12) and the first well region (220) provided in the transistor section (70) in the direction perpendicular to the alignment direction.

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