Semiconductor device

Abstract

Semiconductor device, exhibiting: - a semiconductor substrate (1); - an oxide layer (4) which is provided on an upper surface of the semiconductor substrate (1); - a protective ring (3) which is provided on the oxide layer (4); and - an organic insulating layer (6) which directly contacts the oxide layer (4) in a termination region (7) between the guard ring (3) and an outer edge section of the semiconductor substrate (1), where: - a groove (8) is provided on the upper surface of the semiconductor substrate (1) in the termination region (7), - the oxide layer (4) is provided within the groove (8) and - the groove (8) is embedded in the organic insulating layer (6).

Description

Area

[0001] The present disclosure relates to a semiconductor device which must exhibit moisture resistance. background

[0002] In a semiconductor device, an oxide layer is deposited on the top surface of a semiconductor substrate, and a polyimide is deposited on the oxide layer. However, due to weak adhesion between the oxide layer and the polyimide, moisture penetrates from the polyimide-oxide layer interface into a termination region over time under continuous exposure. This causes an electric field concentration problem between a guard ring in an outermost edge region and a channel stopper. To address this, it has been proposed to extend the termination region to improve moisture resistance (see, for example, PTL 1). Citation list for patent literature

[0003] [PTL 1] JP 2015- 220 334 A

[0004] Document US 2009 / 0309193A1 discloses a mesa semiconductor device in which conventionally occurring dielectric strength degradation and leakage currents are avoided through the use of a cost-effective material. This well-known mesa semiconductor device is designed to offer high dielectric strength and high reliability. A stable protective film of a thermal oxide layer forms on the inner wall of the mesa pit of the mesa semiconductor device to cover and protect the PN junction. An insulating film with negative electrical charges fills the space in the mesa pit covered by the thermal oxide layer, thus preventing the formation of an electron accumulation layer at the interface between an n-type semiconductor layer and the thermal oxide layer.The structure described above weakens the influence of positive electrical charges in the thermal oxide layer and ensures the expansion of a depletion layer into the n-semiconductor layer at the interface with the thermal oxide layer.

[0005] Publication JP 2007-246 807 A describes a method for producing a laminated layer intended to improve the adhesion between a transparent substrate or functional layer made of an organic compound and a functional layer with silicon oxide as its main component. In a laminated layer obtained by applying a silicon oxide-containing functional layer to a surface made of an organic compound, a liquid organosilicon compound is applied at ambient temperature and pressure to the surface of the organic compound between the functional layer and the organic compound. The organosilicon compound is then irradiated with light or a high-energy active species (490 kJ / mol) to form an adhesive layer. This improves the adhesion between the functional layer and the organic compound. Summary Technical Problem

[0006] When a termination region is expanded, the effective current-flowing region becomes narrower, and loss characteristics worsen due to the increased current density, leading to a larger chip size. An increase in chip size is extremely problematic, especially for an expensive material like SiC, whose chip cost per unit area is extremely high.

[0007] It is an object of the present invention, which was implemented to solve the problem described above, to provide a semiconductor device that achieves an improvement in moisture resistance without forming a longer termination region. Solution to the problem

[0008] A semiconductor device according to the present disclosure comprises: a semiconductor substrate; an oxide layer provided on an upper surface of the semiconductor substrate; a guarding ring provided on the upper surface of the semiconductor substrate; and an organic insulating layer that directly contacts the oxide layer in a termination region between the guarding ring and an outer edge section of the semiconductor substrate, wherein a groove is provided on the upper surface of the semiconductor substrate in the termination region, and wherein the groove is embedded in the organic insulating layer. Advantageous effects of the invention

[0009] In the present invention, at least one groove is provided on an upper surface of the semiconductor substrate in the termination region. Moisture entering from an edge of the organic insulating layer and penetrating along the grooves is thus lengthened, increasing the creepage distance for the moisture to reach the protective ring in the outermost edge region. Additionally, the grooves are embedded in the organic insulating layer, thereby improving adhesion between the organic insulating layer and the oxide layer. This can prevent moisture penetration from the edge of the organic insulating layer, thus improving moisture resistance. Furthermore, the termination region can be designed to be shorter, which can lead to a smaller chip size and cost reduction. Brief description of the characters Fig. Figure 1 is a top view illustrating a semiconductor device according to embodiment 1. Fig. Figure 2 is a cross-sectional view along line AB in Fig. 1. Fig. Figure 3 is a cross-sectional view illustrating a semiconductor device according to embodiment 2. Description of the embodiments

[0010] A semiconductor device according to the embodiments of the present disclosure is described with reference to the figures. The same components are identified by the same reference numerals, and their repeated description is omitted. Design 1

[0011] Fig. Figure 1 is a top view illustrating a semiconductor device according to embodiment 1. A central section of a semiconductor substrate 1 is an effective region 2 through which a current flows. A transistor or diode is provided in the effective region 2. A plurality of guard rings 3 are provided on a top surface of the semiconductor substrate 1 such that they surround the effective region 2.

[0012] Fig. Figure 2 is a cross-sectional view along line AB in Fig. 1. An oxide layer 4 is provided on the top surface of the semiconductor substrate 1. The semiconductor substrate 1 is a silicon substrate, and the oxide layer 4 is a silicon oxide layer. Guard rings 3 are selectively provided on the oxide layer 4. An insulating guard layer 5 is selectively provided so that it covers the guard rings 3. The semiconductor device 1 is singulated into chips in a wafer state, and the singulated portion becomes an outer edge portion of the semiconductor substrate 1.

[0013] An organic insulating layer 6 is selectively deposited on the oxide layer 4 and the insulating protective layer 5. The organic insulating layer 6 is, for example, a polyimide. The organic insulating layer 6 directly contacts the oxide layer 4 in a termination region 7 between the protective ring 3 at the outermost edge and the outer edge section of the semiconductor substrate 1. The organic insulating layer 6 does not reach the outer edge section of the semiconductor substrate 1.

[0014] In the present embodiment, at least one groove 8 is provided on the upper surface of the semiconductor substrate 1 in the termination region 7. Moisture entering from an edge of the organic insulating layer 6 and penetrating along the grooves 8 increases the creepage distance for the moisture to reach the protective ring 3 at the outermost edge. Furthermore, the grooves 8 are embedded in the organic insulating layer 6, thus improving adhesion between the organic insulating layer 6 and the oxide layer 4. This can prevent moisture from penetrating from the edge of the organic insulating layer 6, thereby improving moisture resistance. Additionally, the termination region 7 can be designed to be shorter, which can lead to a smaller chip size and cost reduction. Design 2

[0015] Fig.Figure 3 is a cross-sectional view illustrating a semiconductor device according to embodiment 2. A plurality of adhesive layers 9 are selectively provided between the oxide layer 4 and the organic insulating layer 6 in the termination region 7. The adhesion between the adhesive layers 9 and the organic insulating layer 6 is higher than the adhesion between the organic insulating layer 6 and the oxide layer 4. The provision of these adhesive layers 9 improves the adhesion between the organic insulating layer 6 and the oxide layer 4. Furthermore, the adhesive layers 9 make an interface where moisture can penetrate convex, thus increasing the creepage distance for moisture to reach the protective ring 3 at the outermost edge region.As a result, it is possible to further improve moisture resistance.

[0016] Part of the adhesive layers 9 protrudes from the organic insulating layer 6 outwards from the semiconductor substrate 1. This increases the strength when stress is applied in the direction outside the semiconductor substrate 1, making the adhesive layers 9 less likely to detach.

[0017] As a result, a multitude of adhesive layers 9 are provided, creating an interface where moisture penetrates in a concave and convex manner. Accordingly, the creepage distance for moisture to reach the protective ring 3 at the outermost edge region is longer, thus improving moisture resistance. Therefore, the termination region 7 can be designed to be shorter, which can lead to a smaller chip size and cost reduction.

[0018] The adhesive layers 9 are tetraethoxysilane (TEOS) layers applied by CVD. Some concavities and convexities, into which the polyamide of the organic insulating layer 6 penetrates, exist on the surface of the TEOS layers. Consequently, the adhesion between the adhesive layers 9 and the organic insulating layer 6 with some of these concavities and convexities is higher than that of a thermal oxide layer or the like.

[0019] Furthermore, the adhesive layers 9 are preferably made of SinSiN, which is the same material as the insulating protective layer 5. This makes it possible to form the adhesive layers 9 without the addition of a process.

[0020] The semiconductor substrate 1 is not limited to a silicon substrate, but can instead be a wide-bandgap semiconductor with a wider bandgap than silicon. The wide-bandgap semiconductor could be, for example, silicon carbide, a gallium nitride-based material, or diamond. The present disclosure is particularly effective for a wide-bandgap semiconductor device designed to exhibit a high electric field strength at the interface.

[0021] A semiconductor device constructed from a wide-bandgap semiconductor exhibits high voltage withstand capability and high permissible current density, and can therefore be miniaturized. The use of such a miniaturized semiconductor device enables the miniaturization and high integration of the semiconductor module in which the device is embedded. Furthermore, the semiconductor device exhibits high thermal resistance; a cooling fin of a heat sink can be miniaturized, and a water-cooled component can be air-cooled, leading to further miniaturization of the semiconductor module. Since the semiconductor device also exhibits low power loss and high efficiency, a highly efficient semiconductor module can be achieved. Reference symbol list 1 Semiconductor substrate; 3 Protective rings; 4 Oxide layer; 5 insulating protective layer; 6 organic insulating layer; 7. Completion region; 8 grooves; 9 Adhesive layer

Claims

Semiconductor device comprising: - a semiconductor substrate (1); - an oxide layer (4) provided on an upper surface of the semiconductor substrate (1); - a guarding ring (3) provided on the oxide layer (4); and - an organic insulating layer (6) directly contacting the oxide layer (4) in a termination region (7) between the guarding ring (3) and an outer edge section of the semiconductor substrate (1), wherein: - a groove (8) is provided on the upper surface of the semiconductor substrate (1) in the termination region (7), - the oxide layer (4) is provided within the groove (8), and - the groove (8) is embedded in the organic insulating layer (6). Semiconductor device according to claim 1, further comprising an adhesive layer (9) which is provided between the oxide layer (4) and the organic insulating layer (6) in the termination region (7), wherein: - the adhesion between the adhesive layer (9) and the organic insulating layer (6) is higher than the adhesion between the organic insulating layer (6) and the oxide layer (4), and - the adhesion between the adhesive layer (9) and the oxide layer (4) is higher than the adhesion between the organic insulating layer (6) and the oxide layer (4). Semiconductor device according to claim 2, wherein a part of the adhesive layer (9) protrudes from the organic insulating layer (6) towards the outside of the semiconductor substrate (1). Semiconductor device according to claim 2 or 3, wherein a plurality of the adhesive layers (9) is provided. Semiconductor device according to one of claims 2 to 4, wherein the adhesive layer (9) is a tetraethoxysilane layer. Semiconductor device according to one of claims 2 to 4, further comprising an insulating protective layer (5) which covers the protective ring (3), wherein the adhesive layer (9) is made of the same material as the insulating protective layer (5). Semiconductor device according to one of the preceding claims, wherein the organic insulating layer (6) is a polyimide. Semiconductor device according to one of the preceding claims, wherein the semiconductor substrate (1) is formed from a semiconductor with a wide band gap.

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